《逻辑与计算机设计基础》(原书第五版)课后习题答案-chapter04_solutions-5th

A 111
X
DDBB =AAXX+BBXX
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5
4-14.
Problem Solutions – Chapter 4 For part a) results, replace codes in table below with state name, e.g., 00 with A.
3
10/1 2
11/0 00/1
Format: XY/Z
4-11.
DA B
DB=X A
SA = B
SB = X A
Present staRteA = B Input RB =NXext sAtate
Output
PresenAt state B
A
B
0
0
0 00 0
0 00 1
0 01 1
0 11 0
0 10 01 10101 00 11 01001 10 01 100 11 0 1 0 1
NeNxetxsttasteate
AA BB CC
100
01 00 00
00 00 00
1 0 1
0 1
0 0 0
0 0
0 1 1
0 0
10 00 11
01 00 11
1 0 0
1 0
1 1 1
0 0
0 0 0
Z D E F DEF
To enter state A on reset, flip-flop A should have its set input S connected to Reset and flip-flops B-F should have their reset inputs R connected to Reset.
Q(t)
0 0 0 0 1 1 1 1
Inputs
X
Y
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
c) // Serial odd parity generator: Verilog Process Description // problem 4-19 c, 5th edition module serial_odd_parity_generator (CLK, RESET, X, Y, Z);
1 10 0
1 10 1 1 11 1
1
1
Input X
X 0
01 10 01 10 01 10 01
1
Next sAtate B Output Y
AB
0
1
0 01 0
0 10 1
1 11 0
1 00 0
0 00 1
0 11 0 1 10 1
1
1
Y 0
01 11 10 01
10
00 01
1
1/1
0/0
input CLK, RESET, X, Y; output Z; reg state, next_state;
parameter state0 = 1'b0, state1 = 1'b1; reg Z;
// state register: implements positive edge-triggered // state storage with asynchronous reset. always @(posedge CLK or posedge RESET) begin
0
0
0 00
0 0
001
wk.baidu.com
0
11
1 10
1 10
1 11
11
0
1
10
0
1
1 0
1
01
0
00
1
11
0
10
1
1
Nextt state state AB
A 0B 0
1
0
0 00 1
1 00 0
0 11 0
0 1
1
0 0
1
1 11 1
1 01 1
01
DA
B
1
A1 1
1
X
DDAA = AAXX+BBXX
DB
B
1
d) Using equations for the circuit rather than a schematic:
DA CX
DB AX
DD AX B X AX B X
DE EX F X EX F X
DC BX DX E X BX DX E X DF CX DX FX CX DX FX
0
1
1/0
0/1
0/1
1/0
2
3
0/0
1/1
Format: X/Y
4
4-12.
a)
Problem Solutions – Chapter 4
Vdd
Vdd
b)
X
Reset
D
A
C A
D
B
Clock
C
B
Y
4-13.*
PresPernetsent state
state
Input
Input
A
B
X
A 0B
0X
Input
1 0 011 0 1
1
1
1
0
Output
0 1 000 1 0
0
0
0
1
Next State 01 00 00 01 11 00 01 11 10 10 00
4-10.
00/0 11/1
01/0 10/1 11/0 0
00/0 01/1 10/0 11/1 01/0
00/1 1
01/1, 10/0
AB
10 00 00 00 10 00 01 01 11 01 10 10 11 01 11 11
d) This machine is a Mealy machine.
Problem Solutions – Chapter 4
Output
Z
0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0
Present state Present state
Q
0Q
0
00
0 1
0
10
10
11
1
1
1
Inputs Inputs
XY
0 X0 Y
01
1 1
0 01
0
0 00 1
0 11 0
1 10 1
1 01 0
01
10
11
Next state Next state
Q
0Q
1
1 0
0
11
01
00
11
0
0
1
Output Output
S
0S
0
0 0
0
10
10
10
11
1
1
1
00/0, 11/0
01/1, 10/1
0
1
00/1, 11/1
01/0, 10/0
Format: XY /S
3
Problem Solutions – Chapter 4
4-9.
Present State 00 01 00 00 01 11 00 01 11 10 10
if (RESET) state <= state0;
8
.
4-16.
Problem Solutions – Chapter 4
9
4-17.
Problem Solutions – Chapter 4
10
Problem Solutions – Chapter 4
4-18.*
Format: XY /Z (x = unspecif ied) Format: XY/Z (x = unspecified)
endcase end endmodule
Output
Z
0 X 1 X 1 X 0 X
11
4-19.
Problem Solutions – Chapter 4
Format: XY/Z (x = unspecified)
00/1 x1/x
0
10/1 x1/x
00/0 1
10/0
Present state
AB
Input Y
Next state
AB
Output Z
S0 - 00 S1 - 01 S2 - 10 S3 - 11
00
0
01
1
00
1
10
1
01
0
01
0
01
1
10
0
10
0
01
0
10
1
00
0
11
0
01
0
S0
1
0
0
1
1
S3
0
0 S1 0
11
1
10
0
1
1
1
S2 0
1/1
d) This machine is a Moore machine.
1 1
11 11 00
00 11 10
1 1
0
1 1
1
1 1
0
01 11 10
011
111
111
011
X=0
000
100
11 0
011
001
010
101
111
X=1
001
100
010
101
000
011
111
11 0
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AA BB CC
000
00 00 00
00 00 01
0 0 000
0 0 011
1 1 100
00 11 01
00 11 01
0 0 111
1 1 000
1 1 001
11 00 01
11 01 00
111 011 101 11 01 11
110
110
111
4-18. 1 1
InInppuutt
XX
if (RESET) state <= state0;
else state <= next_state;
end
// next state function: implements next state as function // of X, Y and state always @(X, Y or state) begin
CHAPTER 4 4-1.
Problem Solutions – Chapter 4 © 2016 Pearson Education, Inc.
4-2. 4-3. 4-4.
1
4-5.
Problem Solutions – Chapter 4
Y
DA
Clock C
DB
Z
Clock C
Present state
S0 - 00 S1 - 01 S2 - 10 S3 - 11 Format: XY/Z (X = unspecified)
X1/0, 1X/0
S0 00/0
01/1 1X/0
S1
00 /1
01/0
S2 00/0
1X/0
01/1 S3
00/1, 1X/0
4-7.*
PPresenntt ssttaattee
6
Problem Solutions – Chapter 4
d)
A
X1
X1
X2
X2
A
X1 X2
C X1
A X1 X2
A X1 X2 D X1 X2
D X1 X2
D X1 X2
D X1 X2
C X1
A
X1
X2
A
X1
B
X1
S
C
X2 D
X2
B
D X1
C
B
D
X1
7
4-15.
Problem Solutions – Chapter 4
case (state) state0: next_state = ({X,Y} == 2'b10) ? state1: state0; state1: next_state = Y ? state0 : state1;
endcase end
// output function: implements output as function // of X, Y, and state always @(X or Y or state) begin
4-6.
X Y
DA
Clock C
D
BX
Z
Clock C
2
Present state
AB
00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11
Inputs
XY
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Next state
11 1
00 0
1 0
0 1 1
1 0 1
1
0
OuNtpeuxtt state
ZQ(t+1)
0 X
0 0 1
10
X1
1 X
0 1 0
0
X
c) // Serial 2s complementer: Verilog Process Description // problem 4-18 c, 5th edition module serial_2s_complementer(CLK, RESET, X, Y, Z);
case (state) state0: case ({X,Y}) 2'b00: Z = 1'b0; 2'b10: Z = 1'b1; default: Z = 1'bx; endcase state1: case ({X,Y}) 2'b00: Z = 1'b1; 2'b10: Z = 1'b0; default: Z = 1'bx; endcase
input CLK, RESET, X, Y; output Z; reg state, next_state; parameter state0 = 1'b0, state1 = 1'b1;
reg Z;
// state register: implements positive edge-triggered // state storage with asynchronous reset. always @(posedge CLK or posedge RESET) begin
x1/x
00/0
00/1
x1/x
10/0
0
1
10/1
Present state
Q(t)
0 0 0 0 1 1 1 1
Next InpPurtessent state stateInputs
X
YQ(t)
Q(t+1X) Y
0 0
0 1
0 0 0
1
00
1
11
0 0
0 1
1 1 1
1
0
1
1
0 0
0 0 1
0 1 0