解读XILINX的7系列28nm FPGA封装策略
FPGA可编程逻辑器件芯片XCZU28DR-2FFVG1517E中文规格书
7Series FPGAs Package FilesAbout ASCII Package FilesThe ASCII files for each package include a comma-separated-values (CSV) version and a text version optimized for a browser or text editor. Each of the files consists of the following:•Device/Package name (FPGA Family—Device—Package), date and time of creation•Eight columns containing data for each pin:°Pin—Pin location on the package.°Pin Name—The name of the assigned pin.°Memory Byte Group—Memory byte group between 0 and 3. For more information on the memory byte group, see the 7Series FPGAs Memory Interface Solutions UserGuide (UG586).°Bank—Bank number.°V CCAUX Group—Number corresponding to the V CCAUX_IO power supply for the given pin. V CCAUX is shown for packages with only one V CCAUX group.°Super Logic Region—Number corresponding to the super logic region (SLR) in the devices implemented with stacked silicon interconnect (SSI) technology.°I/O Type—CONFIG, HR, HP, or GT (GTP, GTX, GTH) depending on theI/O type. For more information on the I/O type, see the 7Series FPGAs SelectIOResources User Guide (UG471).°No-Connect—This list of devices is used for migration between devices that have the same package size and are not connected at that specific pin.•Total number of pins in the package.•The package file links for the ruggedized packages have the same pinouts are as the equivalent BGA packages.°RS pinouts use the SBG/SBV files (Artix®-7 devices)°RB pinouts use the FBG/FBV files (Artix-7 devices)°RF pinouts use the FFG/FFV files (Kintex®-7 and Virtex®-7 devices)Table 2-1:Spartan-7 FPGAs Package/Device Pinout FilesDevice CPGA196CSGA225CSGA324FTGB196FGGA484FGGA676XC7S6 XA7S6CPGA196ProductionCSGA225ProductionFTGB196ProductionXC7S15 XA7S15CPGA196ProductionCSGA225ProductionFTGB196ProductionXC7S25 XA7S25CSGA225ProductionCSGA324ProductionFTGB196ProductionXC7S50 XA7S50CSGA324ProductionFTGB196ProductionFGGA484ProductionXC7S75 XA7S75FGGA484ProductionFGGA676ProductionXC7S100 XA7S100FGGA484ProductionFGGA676ProductionTo download all available Virtex-7 FPGAs package/device/pinout files click here:Note:Only the available files listed in Table2-4 and Table2-5 are linked and consolidated in the above ZIP file.Table 2-4:Virtex-7T FPGAs Package/Device Pinout FilesDevice FF1157/FFG1157FF1761/FFG1761FL1925/FLG1925FH1761/FHG1761RF1157RF1761 XC7V585T FFG1157FFG1761XC7V2000T FLG1925FHG1761XQ7V585T RF1157RF1761 Table 2-5:Virtex-7XT FPGAs Package/Device Pinout FilesDeviceFF1157FFG1157FFV1157RF1157FF1158FFG1158FFV1158RF1158FF1761FFG1761FFV1761RF1761FF1926FFG1926FF1927FFG1927FFV1927FF1928FFG1928FF1930FFG1930RF1930FL1926FLG1926FL1928FLG1928FL1930FLG1930XC7VX330T FFG1157FFG1761XC7VX415T FFG1157FFG1158FFG1927XC7VX485T FFG1157FFG1158FFG1761FFG1927FFG1930XC7VX550T FFG1158FFG1927XC7VX690T FFG1157FFG1158FFG1761FFG1926FFG1927FFG1930XC7VX980T FFG1926FFG1928FFG1930XC7VX1140T FLG1926FLG1928FLG1930 XQ7VX330T RF1157RF1761XQ7VX485T RF1761RF1930XQ7VX690T RF1157RF1158RF1761RF1930XQ7VX980T RF1930CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50T CPG236 Package (only)—XA7A15T, XA7A35T, and XA7A50TCPG236 Packages (only)—XA7A15T, XA7A35T, and XA7A50T Pinout DiagramFigure 3-42:CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50T I/O BanksFigure 3-43:CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50T CPG236 Packages (only)—XA7A15T, XA7A35T, and XA7A50T Memory GroupingsFigure 3-44:CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50T CPG236 Packages (only)—XA7A15T, XA7A35T, and XA7A50T Power and GND Placement。
Xilinx-FPGA配置的一些细节
Xilinx-FPGA配置的一些细节Xilinx FPGA配置的一些细节2010年07月03日星期六 14:260 参考资料(1) Xilinx: Development System Reference Guide. dev.pdf, v10.1在Xilinx的doc目录下有。
(2) Xilinx: Virtex FPGA Series Configuration and Readback. XAPP138 (v2.8) March 11, 2005在Xilinx网站上有，链接/bvdocs/appnotes/xap p138.pdf(3)Xilinx: Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode.XAPP502 (v1.5) December 3, 2007在Xilinx网站上有，链接/bvdocs/appnotes/xap p502.pdf注：此外xapp139和xapp151也是和配置相关的。
(4)Xilinx: Virtex-4 Configuration Guide. UG071 (v1.5) January 12, 2007(5) Tell me about the .BIT file format.链接：/FAQ_Pages/0026_Tell_me_about_bit_files.htm1 Xilinx配置过程主要讲一下Startup Sequence。
Startup Sequence由8个状态组成.除了7是固定的之外，其它几个的顺序是用户可设置的，而且Wait for DCM和DCI是可选的。
其中默认顺序如下：这些在ISE生成bit文件时通过属性页设定。
这几个状态的具体含义如下：Release_DONE : DONE信号变高GWE : 使能CLB和IOB，FPGA的RAMs和FFs可以改变状态GTS : 激活用户IO，之前都是高阻。
xilinx的7系芯片选型手册
XC7K480T XCE7K480T 74,650 477,760 597,200 6,788 955 34,380 8 400 192 1,920 1 1 1 32 -1, -2 -2L, -3 -1, -2, -2L
Footprint Compatible Footprint Compatible
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Virtex®-7 FPGAs
Optimized for Highest System Performance and Capacity (1.0V) Part Number XC7V585T XC7V2000T XC7VX330T XC7VX415T XC7VX485T XC7VX550T XC7VX690T — XCE7VX330T XCE7VX415T XCE7VX485T XCE7VX550T XCE7VX690T EasyPath™ Cost Reduction Solutions (1) XCE7V585T Slices 91,050 305,400 51,000 64,400 75,900 86,600 108,300 Logic Logic Cells 582,720 1,954,560 326,400 412,160 485,760 554,240 693,120 Resources CLB Flip-Flops 728,400 2,443,200 408,000 515,200 607,200 692,800 866,400 Maximum Distributed RAM (Kb) 6,938 21,550 4,388 6,525 8,175 8,725 10,888 Memory Block RAM/FIFO w/ ECC (36 Kb each) 795 1,292 750 880 1,030 1,180 1,470 Resources Total Block RAM (Kb) 28,620 46,512 27,000 31,680 37,080 42,480 52,920 Clocking CMTs (1 MMCM + 1 PLL) 18 24 14 12 14 20 20 Maximum Single-Ended I/O 850 1,200 700 600 700 600 1,000 I/O Resources Maximum Differential I/O Pairs 408 576 336 288 336 288 480 DSP Slices 1,260 2,160 1,120 2,160 2,800 2,880 3,600 3 4 — — 4 — — PCIe® Gen2(2) PCIe Gen3 — — 2 2 — 2 3 Integrated IP Analog Mixed Signal (AMS) / XADC 1 1 1 1 1 1 1 Configuration AES / HMAC Blocks 1 1 1 1 1 1 1 Resources 36 36 — — 56 — — GTX Transceivers (12.5 Gb/s Max Rate) (3) — — 28 48 — 80 80 GTH Transceivers (13.1 Gb/s Max Rate) (4) GTZ Transceivers ( 28.05 Gb/s Max Rate) — — — — — — — Commercial -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 Speed Grades -2L, -3 -2L, -2G -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 Extended (5) Industrial -1, -2 -1 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 (6) Dimensions (mm) Available User I/O: 3.3V HR I/O, 1.8V HP I/Os (GTX, GTH) Package 35 x 35 0, 600 (20, 0) 0, 600 (0, 20) 0, 600 (0, 20) 0, 600 (20, 0) 0, 600 (0, 20) FFG1157 / FFV1157(7) (7) Footprint 42.5 x 42.5 100, 750 (36, 0) 50, 650 (0, 28) 0, 700 (28, 0) 0, 850 (0, 36) FFG1761 / FFV1761 FHG1761 45 x 45 0, 850 (36, 0) Compatible FLG1925 45 x 45 0, 1200 (16, 0) 35 x 35 0, 350 (0, 48) 0, 350 (48, 0) 0, 350 (0, 48) 0, 350 (0, 48) FFG1158 / FFV1158(7) Footprint FFG1926 45 x 45 0, 720 (0, 64) FLG1926 45 x 45 Compatible (7) 45 x 45 0, 600 (0, 48) 0, 600 (56, 0) 0, 600 (0, 80) 0, 600 (0, 80) FFG1927 / FFV1927 Footprint FFG1928 45 x 45 FLG1928 45 x 45 Compatible Footprint FFG1930 45 x 45 0, 700 (24, 0) 0, 1000 (0, 24) FLG1930 45 x 45 Compatible FLG1155 35 x 35 FLG1931 45 x 45 FLG1932 45 x 45
Xilinx 7系列开发板性能比较
Xilinx 7-系列FPGA 和All Programmable SoC 能为航空航天与军用、医疗、科学、石油天然气、金融、通信以及生命科学等应用提供节能型高性能处理解决方案。
FPGA 架构固有的平行结构和定制架构适合高吞吐量数据处理和软件加速。
这些器件以28nm 芯片工艺为基础，集成HKMG 技术以更低的功耗将系统性能实现最大化。
所有Xilinx 器件都具有很长的产品生命周期，可降低淘汰风险。
这些因素的综合使基于Xilinx 器件的HPC 平台能以单芯片提供高达2 TFLOPS 的高处理性能，且功耗远低于GPU 和多核DSP。
Xilinx 高性能计算(HPC) 平台以最原始的计算性能和最低成本，借助Xilinx 固有的可靠性实现快速原型设计。
利用Xilinx 计算加速解决方案信心十足地将概念设计推向市场。
Vivado HLS 提供多种采用单精度或双精度C/C++ 开发的快速原型设计流程软件应用。
这些应用可被编译成高效的硬件实现方案，并可编程到Xilinx 28nm 器件中。
Vivado HLS 包含于Vivado Design Suite: System Edition。
使用C/C++ 和OpenCL 完成基于软件的系统实现Xilinx 目前正与早期的客户合作开发一个全新系统级的异构并行编程环境，在一个全面的基于Eclipse 的开发环境中利用C / C + +和开放计算语言(OpenCL®) 等抽象化计划。
该开发环境提供面向市场的库，可通过Xilinx All Programmable 器件显著提高异构系统（已验证）的生产力，并可助力需要实现并行架构的系统架构师、软件应用开发人员、和嵌入式设计人员提升系统性能、降低BOM 成本和总功率，开发时间符合ASSP、DSP、和GPU。
浅谈现代集成电路28nm芯片制造工艺A(前端FEOL)
浅谈现代集成电路28nm芯片制造工艺A(前端FEOL) 全球90%以上集成电路都是CMOS工艺制造的，经历了半个多世纪发展进化，芯片集成度从一个芯片包含几十个器件进化到几十亿个器件。
从上世纪60年代MOS器件采用铝栅工艺，70年代采用了硅栅工艺，铝线互连，进化到现代集成电路采用高K金属栅、超低k介质多层铜线互连，以及FD-SOI和FinFET立体结构。
制造工艺也越来越复杂。
下面就纳米级体硅平面型CMOS集成电路工艺流程，展现芯片先进制程不断丰富现代集成电路制造工艺。
1）现将几种先进制程工艺简介如下：50多年发展，集成电路制造过程工艺越来越复杂，先进制程不断完善。
首先为了抑制短沟道效应，提高栅极对沟道的控制能力，提高栅极电容，栅氧化层厚度不断减薄。
对于厚度大于4nm的栅氧化层，SiO2是理想的绝缘体，不会形成栅漏电流。
当纯二氧化硅厚度小于3nm时，衬底的电子以量子形式穿过栅介质进入栅极，形成栅极漏电流。
（量子隧穿）栅极漏电导致功耗增加，IC 发热且阈值电压飘移，可靠性降低。
为提高介质绝缘特性，当特征尺寸达到0.18μm时采用氮氧化硅代替二氧化硅。
特征尺寸进入90nm节点，单纯缩小厚度不能满足器件性能的要求了，于是采用提高氮氧化硅含氮量以增加介电常数k，但SiON厚度低于14Å会严重遂穿，栅极漏电剧增。
45nm节点之后氮氧化硅已经不能满足mos器件正常工作的要求，开始使用高k介质HfO2代替SiON来改善栅极漏电问题，同时采用金属栅解决费米能级钉扎和多晶硅栅耗尽问题。
尽管在0.35μm技术节点开始采用掺杂多晶硅与金属硅化物（WSi）鈷（镍）多晶硅化物栅叠层代替多晶硅栅，降低了多晶硅栅的电阻。
但金属栅电阻要比金属硅化物还要小。
高k金属栅HKMG.采用高k介质材料替代SiO2。
二氧化硅k=3.9,氮氧化硅k=4~7，高K介质(HfO2和,HfSiON）=15~25。
同样等效氧化层厚度时，高k材料的物理厚度是SiO2的3~6倍。
FPGA的7系列与6系列的比较
7 Series FPGAs MigrationMethodology Guide UG429 (v1.1) October 15, 2014Revision HistoryThe following table shows the revision history for this document.Date Version Revision10/15/14 1.1Added paragraph on clocking components to the end of the Clocking Considerationssection in Chapter 2.Updated description of FIFO18E1/FIFO36E1 in Chapter 2.03/17/11 1.0Initial Xilinx release.Table of ContentsRevision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Chapter1:Targeting/Retargeting Considerations for 7Series Devices HDL Coding Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Use of DSP and Other Arithmetic Intensive Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9RAM Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Use of Synthesis and Physical Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Software Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Use of LUTs as Route-Thrus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Chapter2:Virtex-6 FPGA Retargeting Considerations7Series Device Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Use of Existing Soft IP, EDIF, or NGC Netlists. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Driving Non-Clock Loads with Global Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Other Primitive Retargeting Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Using Unimacros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23I/O Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Xilinx Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Chapter1 Targeting/Retargeting Considerations for 7Series DevicesThis chapter covers topics associated with prior FPGA design implementations that are not technology specific. The concepts in this chapter should be considered when eitherevaluating existing design source from prior FPGA or ASIC targets or when developing new code for use in the 7series devices.HDL Coding ConsiderationsUse of Control SignalsThe use of control signals (signals that control synchronous elements such as clock, set, reset, and clock enable) can impact device density, utilization, and performance. This is true in almost any FPGA technology. However, the difference in the topology of the 7seriesdevices should be considered in selecting and using control signals. These considerations are necessary to achieve the best device utilization and performance.Avoid Use of Both a Set and a Reset on a Register or LatchAs with the Virtex®-6 and Spartan®-6 architectures, 7series devices do not have a REV pin.As a result, flip-flops cannot natively implement both a set signal and a reset signal without the use of additional logic. Thus, when using both a synchronous set and reset, anadditional signal is added to the datapath, which might affect area and timing depending on placement, fanout, and timing considerations. In some cases, that additional signal can be absorbed without increasing logic levels and, in that case, has little net effect on thedesign. However, for an asynchronous set and reset, the effect on resource utilization and timing is more significant and should be avoided.Registers that contain both asynchronous reset and asynchronous set signals and/or with an asynchronous control signal with a dynamic value can be implemented. The resulting circuit might consume more resources than desired and might have more significant effect on timing and verification than originally thought.This configuration can be described in RTL or be instantiated with an FDCPE in HDL, EDIF, or NGC formats. This simple coding example consists of Verilog code describing asynchronous set and reset resulting in additional resources and timing paths:always @(posedge reset, posedge set, posedge clk)if (reset)a_reg <= 1'b0;else if (set)a_reg <= 1'b1;elsea_reg <= A;This second coding example consists of VHDL code describing an asynchronous control signal with a dynamic value resulting in additional resources and timing paths: process (clk, initc) beginif initc='1' thendata_reg <= init_signal;elsif (clk'event and clk='1') thendata_reg <= data_in;end if;end process;When the software encounters these configurations, it issues a warning message describing the issue and lists the corresponding registers. When using Xilinx Synthesis Technology (XST) for synthesis, this warning is issued:WARNING:Xst:3001 - This design contains one or more registers or latches with an active asynchronous set and asynchronous reset. While this circuit can be built, it creates a sub-optimal implementation in terms of area, power and performance. For a more optimal implementation Xilinx highly recommends one of these:1) Remove either the set or reset from all registers and latches ifnot needed for required functionality2) Modify the code in order to produce a synchronous set and/or reset(both is preferred)3) Use the -async_to_sync option to transform the asynchronousset/reset to synchronous operation (timing simulation highlyrecommended when using this option)Please refer to search string "Virtex7 asynchronous set/reset"for more details.List of register instances with asynchronous set and reset:My_async_reg in unit <async_set_and_reset_module_or_entity>If a third-party synthesis is used, a similar warning might also be seen. If the design contains a netlist or instantiated FDCPE component, this message might be seen in Map:WARNING: MapLib:1182 - One or more latches or registers which have both an active asynchronous set and reset have been found in the design. To get this samefunctionality in the virtex7 architecture a sub-optimal circuit must be created in terms of area, power and performance. Therefore it is highly suggested to either remove one set or reset or make the function synchronous in order to obtain a more optimal implementation in this architecture.List of register instances with set and reset:My_async_regIf any of these warnings are encountered, it is suggested to evaluate the code for changes that can eliminate the need for describing both a asynchronous set and reset condition.Register InitializationMany engineers use the inherent initialization of registers and latches in the FPGA via the global set/reset (GSR) signal by implicitly specifying initialization of an inferred register, thus creating a more robust and sometimes smaller circuit. With initialization, a different start-up state from reset state is allowed, which in some cases (such as a state machine with certain states that must be run at start-up but perhaps not on a subsequent reset) it consumes less logic than an uninitialized state yields. Initialization also allows for the RTL description to more closely and accurately behave as the actual FPGA, creating a more accurate representation of the circuit. For this reason it is suggested to use register initialization on any inferred register, SRL, or RAM when possible.In this code example, the reg register is initialized with the value of 1:signal reg: std_logic := '1';...process (clk) beginif (clk'event and clk='1') thenif (rst='1') thenreg <= '0';elsereg <= val;end if;end if;end process;In the coding example, the use of initialization eliminates the need to specify a set condition for the sole purpose of creating an initial condition of a logic one. Even if the initial condition matches the reset condition, it is still suggested to specify register initialization to allow the simulation start-up state to more accurately reflect the initial condition of the FPGA without requiring a reset condition.Limit Use of Active-Low Control SignalsIt is not recommended to use inferred or instantiated components with active-Low control signals due to the combination of:•The 7series device’s coarse slice composition (8 registers per slice).•The absence of a programmable inversion element on the slice control signals in the 7series device.•Hierarchical design methods that do not allow optimization across hierarchical boundaries, such as the use of KEEP_HIERARCHY, partitions, partial reconfiguration, or bottom-up synthesis.In certain situations, device utilization can increase due to the use of a LUT as an inverter and the additional restrictions of register packing sometimes caused by active-Low control signals.Timing can also be affected by the use of active-Low control signals. Active-High control signals should be used wherever possible in the HDL code or instantiated components. When a control signal’s polarity cannot be controlled within the design (such as when it is driven by an external, non-programmable source), the signal in the top-level hierarchy of the code should be inverted, and active-High control signals driven by the inverter to get the same polarity (functionality) should be described. When described in this manner, the inverter can be absorbed into the I/O logic, without using any additional logic or routing, resulting in better utilization, performance, and power.Limit Use of Low Fanout Control SignalsThe number of unique control signals in the design should be limited to those necessary for design functionality and operation. Low fanout, unique control signals can result in underutilized slices in terms of registers, SRLs, and LUT RAM. These control signals can have negative impacts on placement and timing. In general, a set, reset, or clock enable should not be implemented in the code unless it is required for the active functionality of the design.Unnecessary Use of Sets or ResetsUnnecessary sets and resets in the code can prevent the inference of SRLs, RAMs (LUT RAMs or block RAMs), and other logic structures that are otherwise possible. To get the most efficiency out of the architecture, sets and resets should only be coded when they are necessary for the active functionality of the design.Sets and resets should not be coded when they are not required. For example, a reset is not required when it is only used for initialization of the register, because register initialization occurs automatically upon completion of configuration.Another example where a reset is not required is when a circuit remains idle for long periods. A simple reset on the input registers eventually flushes out the data on the rest of the circuit.A third example is with inner registers when the reset is held for multiple clock cycles. In this case, the inner registers are flushed during reset, so the reset is not necessary on all registers. By reducing the use of unnecessary sets or resets, greater device utilization, better placement, improved performance, and reduced power can be achieved.Sets for Multipliers or Adders/Subtractors in DSP48E1 Slice Registers7series DSP48E1 slice registers contain only resets and not sets. The 7series DSP blocks can perform many different functions, including multiplication, addition/subtraction, comparators, counters, and general logic. To allow the flexibility of use of this additionalresource in the design, a set condition cannot exist in the function for it to properly map to this resource. Thus, unless necessary, a set (value equals logic 1 upon an applied signal) should not be coded around multipliers, adders, counters, or other logic that can be implemented within a DSP48E1 slice.Use of Synchronous Sets/ResetsIf a set or reset is necessary for the proper operation of the circuit, a synchronous reset should always be coded. Synchronous sets/resets have improved timing characteristics and stability and can also result in smaller, better utilization within the FPGA. Synchronous sets/resets can result in less logic (fewer LUTs), fewer restrictions on packing, and, often, faster circuits. The registers within blocks like the DSP48E1andRAMB36E1/RAMB18E1 cannot implement an asynchronous set and reset. Thus they cannot be used with functional equivalency if an asynchronous set or reset exists in the RTL code. With synchronous resets, far more flexibility is provided to the sharing of registers within a slice. Each slice has a shared reset and registers with incompatible synchronous resets can be remapped to the datapath, allowing them to be placed into the same slice. Asynchronous resets cannot be remapped and retain the same functionality. Thus two registers with different asynchronous resets or a register with an asynchronous reset and one without cannot be mapped into the same slice. This not only affects device density but also can have negative effects on performance and power because placement can become suboptimal and require more routing delay and capacitance.If you do not want to recode existing asynchronous resets to synchronous resets, the asynchronous resets can be treated as synchronous resets by using the Asynchronous To Synchronous switch, if available, in the synthesis tool. Use of this switch though adds the risk that the RTL hardware description might not act exactly like the implemented design under all reset conditions. Thus extra care and effort might be needed during circuit verification if the switch is used.If XST is the synthesis tool, the Asynchronous To Synchronous switch is available in the ISE® software Project Navigator Properties for XST, or the -async_to_sync switch can be used as a synthesis option when used by the command line. This option is not as effective as recoding to use a synchronous set/reset in terms of reducing resources and improving performance. However, it does allow for additional register packing and optimizations, which is not possible otherwise, resulting in a smaller and sometimes faster circuit compared to not using this option at all.Use of Clock EnablesHigh fanout clock enables should not be manually split or replicated but coded as a single clock enable. If replication becomes necessary for timing or other reasons, it should be controlled within the synthesis tool. This allows for greater flexibility to control replication many times, giving a better trade-off balance between additional resources and power for improved performance. Also as placement and other factors change, the replication requirements might also change. Having control of this from the synthesis andimplementation tools means that the original code does not need to be modified and reverified for such changes.Another benefit to retaining high-fanout clock enables to a single net is it allows for simpler remapping to other dedicated resources like a BUFGCE or BUFHCE. These can realize the same functionality with the added benefit of an even greater reduction in both power and consumption of routing resources.Use of DSP and Other Arithmetic Intensive CodeMany DSP designs are well suited for the 7series architecture. To obtain best use of the architecture, the underlying features and capabilities need to be understood so that design entry code can take advantage of these resources.The DSP48E1 blocks use a signed arithmetic implementation. It is suggested to code using signed values in the HDL source to best match the resource capabilities and, in general, get the most efficient mapping. If unsigned bus values are used in the code, the synthesis tools should still be able to use this resource but might not get the full bit precision of the component due to the unsigned-to-signed conversion. The multiplier within the 7series DSP48E1 slice has an input bit precision of 18bits by 25bits signed data. Thus the bit precision for unsigned data is 17bits by 24bits. For Verilog code, data is considered unsigned unless otherwise declared in the code.If the target design is expected to contain a large number of adders, it is suggested to evaluate the design to make greater use of the DSP48E1 slice pre- and post-adders. For example, with FIR filters, the adder cascade can be used to build a systolic filter rather than using multiple successive add functions (adder trees). If the filter is symmetric, you can evaluate using the dedicated pre-adder to further consolidate the function into both fewer LUTs and flip-flops and also fewer DSP slices as well (in most cases, half the resources).If adder trees are necessary, the 6-input LUT architecture can efficiently create ternary addition (A+B+C=D) using the same amount of resources as a simple 2-input addition. This can help save and conserve carry logic resources, when needed. In many cases, there is no need to use these techniques. By knowing these capabilities, the proper trade-offs can be acknowledged up front and accounted for in the RTL code to allow for a smoother and more efficient implementation from the start.In most cases, DSP resources should be inferred. If XST is used for synthesis, it is suggested to consult the “XST Hardware Description Language (HDL) Coding Techniques” chapter of UG627, XST User Guide. It is also suggested to read UG479, 7 Series FPGAs DSP48E1 Slice User Guide, for the features and capabilities of the DSP48E1 slice and how to best leverage this resource for one’s design needs.RAM ConsiderationsTo maximize the use of block RAMs and LUTs in the 7series architecture, certain considerations must be understood when retargeting block RAM and LUT RAM by inference, instantiated primitive, Unimacro, or CORE Generator™ software. If theCORE Generator tool is used for RAM generation, the IP should be regenerated for the7series device, or the RAM should be recoded for proper synthesis inference.Either method often gives good results for utilization and performance. However, it is recommended to infer memory where possible to improve understanding of the code, simulation, and future portability of the code.Instantiating RAMsThe recommendations in this section are for cases in which RAM primitives are instantiated in the design or when it is not possible to regenerate CORE Generator software IP for7series devices. These suggestions should also be implemented by code that infers RAM, especially when using synthesis attributes to guide which RAM resources are used (such as syn_ramstyle for Synplicity or RAM_STYLE for XST). The suggestions are divided by RAM depth, the most important factor in determining which RAM resource to use.Depths Less Than 128 BitsDue to the large LUTs and deep LUT RAMs in 7series FPGAs, the criteria for choosing between a block RAM and LUT RAM might have changed from previous FPGA generations. In general, a LUT RAM should be used for all memories that consist of 64 bits or less, unless there is a shortage of logic resources (LUTs) and/or SLICEMs for the target device.Using LUT RAMs for memory depths of 64 bits or less, regardless of data width, is more efficient in terms of resources, performance, and power. For depths greater than 64 bits but less than or equal to 128 bits, the decision on the best resource to use depends on these factors:1.The availability of extra block RAMs. If not available, LUT RAM should be used.2.The latency requirements. If asynchronous read capability is needed, LUT RAMs must beused.3.The data width. Widths greater than 16 bits should use block RAM, if available.4.The necessary performance requirements. Registered LUT RAMs generally have shorterclock-to-out timing and fewer placement restrictions than block RAMs. If the design already contains instantiated LUT RAMs with depths greater than 16 bits, the deeper primitive (for example, RAM32X1S or RAM64X1S) should be used.RAM16X1S components, used in conjunction with MUXF5 components or other logic, are not properly retargeted to automatically use the greater depth LUT. In such cases, the code should be modified to properly use the deeper primitives.Depths Greater Than 128 BitsIn most cases, depths greater than 128 bits should target block RAM. There are two types of block RAM in the 7series devices: an 18Kb RAM (RAMB18E1) and a 36Kb RAM(RAMB36E1). The choice between these RAMs is generally dictated by the desired width and depth. Table 1-1 shows the RAMB18 and RAMB36 width/depth combinations in True Dual-Port (TDP) or Simple Dual-Port (SDP) configurations.Assess Additional RAM FeaturesGood design practices include determining whether any dedicated RAM features should be used when starting a new design project. Some features to consider are:•FIFO: The 7series device block RAM contains dedicated logic to implementsynchronous (same clock) or dual-clock FIFO buffers with features such as first word fall-through and programmable threshold almost empty and almost full flags. Designs containing FIFOs created from soft logic should consider using this dedicated logic to improve device utilization, power, and performance as well as ease the overall design of these components.Table 1-1:Guide for Block RAM Primitive Selection Based on Memory Width, Depth, and Type (True-Dual Port vs. Simple-Dual Port)Memory Width (Bits)RAMB18 TDPRAMB18 SDPRAMB36 TDPRAMB36 SDP512 Depth 18bits or less 36bits or less 19bits to36bits 37bits to72bits 1K Depth 18bits or less 18bits or less 19bits to 36bits 19bits to 36bits 2K Depth 9bits or less 9bits or less 10bits to 18bits 10bits to 18bits 4K Depth 4bits or less 4bits or less 5bits to 9bits 5bits to 9bits 8K Depth 2bits or less2bits or less3bits to 4bits3bits to 4bits16K Depth 1bit 1bit 2bits 2bits 32K Depth N/A N/A 1bit 1bit 64K DepthN/AN/A1bit (1)1bit (1)Notes:1.Requires two RAMB36 components configured in cascade mode.•ECC Logic: The 7series block RAM also contains dedicated logic for RAM content error detection and correction. This feature should be considered for designs requiring such data error correction.•Output Registers: Use of the output register can significantly improve performance (clock to out) of the block RAM, while also improving power and device utilization. If a design is ported into the 7series architecture from a prior architecture, the codeshould be re-examined to see if the output register can be incorporated into thedesign.•Byte Wide Write Enables: 7series devices have byte-wide write enables. This feature can be beneficial to the block RAM access and utilization for the device. In some cases, more efficient use of block RAMs and other resources can be seen with the use of this feature.•Enable/Reset Priority. 7series FPGAs can change the priority of enables versus resets, allowing for greater consistency of output register control to that of slices and I/O registers.More information can be obtained from the 7Series FPGAs Memory Resources User Guide. Use of Synthesis and Physical ConstraintsMany times, synthesis attributes, constraints, and directives are embedded in the code or synthesis constraints file to create a desired result in a prior implementation or architecture. It is suggested to comment out or remove these elements because they might lead to an inferior result and not be the best choice in future implementations.Any LOCs, RLOCs, BEL constraints, or other physical constraints, embedded in the code, netlist, or UCF file of the existing design should be removed before retargeting to a 7series FPGA. An optimal placement for an older architecture is likely not optimal in a 7series FPGA due to differences in the functional blocks, device floorplan, and timing. In some cases, errors can occur due to layout and coordinate differences. However, even if no errors occur, timing, density, and power can be suboptimal unless the physical constraints are modified, removed or updated for the new architecture.Specification of Timing ConstraintsFirst, synthesis timing constraints should be specified that relate realistic timing objectives. The synthesis software can apply area-saving algorithms where performance objectives can still be met in areas with excess timing slack. Timing optimization algorithms can be applied in areas with tight timing slack. Without timing constraints, the synthesis tools must optimize all parts of the design for timing, often at the expense of area. This can also lead to optimization (logic level reduction) in areas that do not need it at the expense of paths that could be further optimized. Timing constraints allow focus on the areas of design that need it and relaxation on those that do not.Implementation timing constraints should also be applied that reflect both the desired I/O and clock timing but also the timing exceptions, such as multicycle paths and false paths or timing ignores (TIGs). Applying realistic and complete timing constraints can often result not only in improved results but also shorten timing closure and debug as well as reduce run time and memory requirements as well. It is not recommended to over constrain the design because it can lead to longer run times, more memory, and, in some cases, worse results than a precisely constrained design. Time spent to create a good UCF file can save far greater time in the overall timing closure process.Software OptionsSoftware algorithms for the 7series FPGAs are designed to deliver a balance between device area (and thus cost), power, and performance. Options in the ISE tools allow designers to improve device area at the cost of performance or improve performance at the cost of device area. There are also options to reduce power that can often result in trade-offs in performance, area, and/or software run time. Options in the software can be specified to achieve design goals when the default balanced approach does not. It is not suggested though to use these options until first it is determined that the design goals can be met with the default algorithms. For this reason, it is suggested that the first design runs are done with the default options used for the software. Then after analysis of those results, specific options can be used to help tune the algorithms to gain the results needed.Use of LUTs as Route-ThrusWhen analyzing 7series FPGA LUT utilization, the use of LUTs as route-thrus must be considered. LUT route-thrus in the Map report are created when access is needed to internal slice logic or registers when no other input path is available into the slice, most commonly when the bypass inputs (AX, BX, CX, or DX) are not available. A LUT route-thru uses a single input to the LUT to obtain access into the slice. A few situations can cause this: 1. A flip-flop, RAM, or other non-LUT source drives a flip-flop (where bypass lines areoccupied, generally because four registers already exist in the slice).2. A flip-flop, RAM, or other non-LUT source drives the MUXF7/MUXF8 data inputs withinthe slice.3. A flip-flop, RAM, or other non-LUT source drives a select or data line of CARRY4 (selectline of MUXCY and/or DI of XORCY).7series devices have eight registers within a slice, beneficial for both performance and area. For many high-speed, highly pipelined designs, these additional registers can allow for maximum performance without the cost of additional logic. They also allow for improved LUT combinations to utilize the dual output structure of the 6-input LUT without。
浅析Xilinx 7系列Multiboot
浅析Xilinx 7系列Multiboot在远程更新的时候，有时候需要双镜像来保护设计的稳定性。
在进行更新设计的时候，只更新一个镜像，另一个镜像在部署之前就测试过没问题并不再更新。
当更新出错时，通过不被更新的镜像进行一些操作，可以将更新失败的数据重新写入Flash。
这样即使更新出错，也能保证设计至少可以被远程恢复。
Xilinx的双镜像方案成为Multiboot。
本文对Xilinx 7系列的MulTIboot做一些简单介绍。
MulTIboot直接操作的是两个镜像，但实际上可以用于多个镜像。
为了便于描述，MulTIboot 中的两个镜像分别成为G镜像（Golden）和M镜像（MulTIboot）。
远程更新的方案，有一些是通过FPGA来读写Flash的，例如Xilinx平台下需要自己实现的Flash读写控制器，Altera平台下的ASML IP。
当无法提供JTAG等其他连接时，Flash 的更新就只有FPGA一种方案。
当写入Flash的操作出现错误，或者Flash中部分地址中的数据出现错误，导致无法正确写入或者存储的数据出现错误，这样会导致FPGA无法加载成功。
当FPGA无法加载成功或者工作不正常的时候，Flash的读写操作也就无法得到保证。
此时也就不能重新通过远程更新方案来重新读写Flash，纠正之前的错误。
所以可以看到，如果Flash直接由FPGA控制，当远程更新出现错误时，很可能导致远程更新彻底失效，只能安排现场更新来修复。
对应方案就是使用双镜像（多镜像），更新的时候只更新M镜像，更新后直接使用M镜像。
当出现M镜像更新出现错误的时候，则启动G镜像。
通过G镜像中的设计来重新更新Flash中M镜像部分的数据。
由于G镜像从来没有被更新过，这样出现错误的概率也就非常小。
这样即使M镜像出现错误，可以通过G镜像来完成一些工作（例如Flash读写操作），由此来保证设计一直可以使用。
从这个分析可以看出，双镜像的方案，需要完成两个任务。
Xilinx展望7系列：FPGA给力高密度和高收发
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Xilinx Kintex-7系列FPGA高速采集卡中文资料
Xilinx Kintex-7系列FPGA高速采集卡中文资料基于Xilinx Kintex-7 FPGA，XC7K160/325/410T FBV676可选，DDR3 256MB/512MB可选。
NOR FLASH 256Mb，可根据开发需求自搭配，成本可控；工业级FMC连接器，支持高速ADC和DAC等FMC标准模块；PCI Express 标准，提供PCIe x2高速数据传输接口，单通道通信速率可高达5GBaud； Serial Rapid I/O，提供SRIO x2高速数据传输接口，单通道通信速率可高达5GBaud；SFP+光纤接口，传输速率可高达10Gbit/s；集成千兆网及I2C等常见接口，拓展能力强；提供板卡原理图和丰富的开发例程，入门简单。
图 1 Xilinx Kintex-7 FPGA基本参数图 2 TL-K7FMC采集卡正面图图 3 TL-K7FMC采集卡侧视图1图 4 TL-K7FMC采集卡侧视图2图 5 TL-K7FMC采集卡侧视图3图 6 TL-K7FMC采集卡侧视图4TL-K7FMC采集卡是一款广州创龙基于Xilinx Kintex-7系列FPGA自主研发的FMC数据采集卡，可配套广州创龙TMS320C6655、TMS320C6657、TMS320C6678开发板使用。
TL-K7FMC采集卡完全支持PCI Express 标准，串行高速输入输出SRIO总线通过HDMI接口提供稳定、可靠的高速传输能力，为产品的快速成型提供极大的便利。
TL-K7FMC采集卡的FMC接口不仅简化了I/O接口模块设计，提供高速的接口通信能力，而且提高了模块的利用率，标准化设计使产品有更好的通用性。
1 典型运用领域高速数据采集系统音视频数据处理系统图像处理设备软件无线电设备通信系统高精度仪器仪表高端数控系统 2 软硬件参数硬件参数ASP-134488-01400PINArrayEEPROMAT24C02SPIFLASHCDCM61002RESETDDR3Kintex-7Xilinx 7 seriesSerial Rapid IO x2PCIE GEN2 x4Kintex-XADCSFP+28nm Technology Low Cost FPGAOSC25MHzUART图 7 TL-K7FMC采集卡硬件框图JTAGPHYLED710-1100-304848PIN图 8 TL-K7FMC硬件资源图解1图 9 TL-K7FMC硬件资源图解2表1CPU RAM ROM EEPROM 网络 Xilinx Kintex-7 FPGA，XC7K160/325/410T FBV676 256MByte/512MByte DDR3 256MBit NOR FLASH 2KBit 10/100/1000M ETHERNET光纤接口 LED 3x 可编程指示灯 1x 复位按键按键 2x 用户可编程按键 1x SRIO TX，1x SRIO RX，2通道，单通道最高速率5GBaud，HDMI座 1x PCIe 4x(Gen2)，2通道，单通道最高通信速率5GBaud 2x 48pin欧式连接器，GPIO拓展拓展IO 1x I2C，HDMI座 1x PMOD 1x XADC 1x FMC，400pin 仿真器接口启动方式串口电源开关电源接口 1x 14pin JTAG接口，间距 1x 2bit启动方式选择拨码开关 1x UART，Micro USB接口，提供4针TTL电平测试端口 1x 电源拨码开关 1x 12V 2A直流输入DC005电源接口，外径，内径 1x SFP+ 1x 供电指示灯软件参数表 2 Vivado版本号 3 开发资料提供采集卡原理图、入门教程、丰富的Demo程序；提供与DSP通信教程，完美解决DSP+FPGA异构平台通信开发瓶颈；提供完整的软件开发包，以及配套的开发文档。
FPGA从Xilinx 的7系列学起(7)
FPGA从Xilinx 的7系列学起（7）2.4 BlockRAM的级联7系列BlockRAM存储器可以把两个相邻RAM使用专用的布线资源级联到一起。
这个对于工程师的重要性在于仅仅级联两块RAM的时候，可以考虑节省不少的资源。
从上面说讲述中，可以看出来，很显然不可以直接级联两个以上的的RAM。
但是如果你是使用Spartan-6系列，那用户就不能考虑使用这个级联功能，因为他们并没有该功能。
如果你想使用更大规模的RAM存储空间，那么你就借助IP核的工具来实现这一点。
IP的工具将增加一些输入的逻辑和一些输出的多路复用器，将更多的RAM 级联到一起。
这个和上面说的两个BlockRAM进行级联不太一样，上面的不需要额外的逻辑资源，但是IP核工具就需要额外的CLB资源。
使用IP工具，你可以构建128K, 256K，512K甚至更大的存储空间，越大消耗的额外的CLB资源就更多。
2.5 内部集成的ECC功能BlockRAM内部集成错误检测和纠正单元，可以做64位ECC的校验，这个时候72位的bit位都需要被使用。
可以纠正所有的单bit的错误，这个错误修正是在数据的输出端口进行的，而不是在内部的存储阵列里面进行的；能够检测但是不能纠正双bit的错误；能够指示出错误地址。
当用户需要时，可以故意插入一些错误，进行相关的测试。
这个对使用外部高速存储器控制器的用户来说，会很有帮助。
2.6 字节写模式7系列和Virtex-6一样支持的字节使用的方式。
这个对使用嵌入式设置的工程师来说非常重要，在WRITE_FIRST模式下，进行字节操作的时候，当没有整字节操作完成时，输出口会显示为不确定值。
这个真实的反映了新的memory的内容。
那么用户进行设计的时候就需要时刻关注这个存储空间的内容，当用户进行读操作的时候，只有当READ信号有效的时候才可以进行读。
关于XILINX系列FPGA芯片的架构性能剖析
关于XILINX系列FPGA芯片的架构性能剖析XILINX公司拥有多种不同系列的FPGA芯片，随着微电子技术的发展，芯片的结构与功能也发生了相应的变化。
本文参考了XILINX系列芯片的相关资料，结合微电子电路相关知识，重点针对Virtex系列芯片，从其基本结构、CLB （可配置逻辑块）、IOB （输入输出模块）、可编程内连等方面进行了详细的分析研究。
最后通过比较的方式给出了各系列芯片间芯片结构以及性能上的差异。
1Virtex系列芯片基本概况Virtex系列芯片的基本电路框图结构如图1 所示。
它主要由可配置逻辑块（Configurable Logic Blocks，CLB）组成的规则阵列构成内部核心部分;周围是输入输出模块（Input/Output B locks，IOB）;在管芯的四个角上有4个时钟锁相环;遍及整个芯片分布着4个通用低摆率的全局时钟分配网络;在CLB与IOB之间，有两列RAM块，分别位于左右对称的两侧，这一系列的芯片可以把配置数据存在其内部的静态存储单元中，通过这种方式可以实现无限循环次数的重复编程，存储在静态存储单元中的值控制着可配置存储单元及内连资源，这些值在上电时加载到静态存储单元中，如果需要改变系统功能时可重新对其进行配置，同时，它还提供了基于函数发生器的单端口与双端口的分布式RAM。
Virtex系列芯片最多可容纳的逻辑门数为1000000门，系统时钟频率可达200MHz;它采用5层金属板的CMOS工艺。
2Virtex系列芯片详细分析1）输入输出逻辑块（IOB）它提供了包装引脚与内部逻辑之间的接口界面。
Virtex系列芯片的IOB的电路结构如图2所示。
图2中，三个IO寄存器既可作为D型触发器也作为边沿敏感的琐存器，它们共用同一个时钟，共用同一个置位/复位信号，但各自有独立的时钟以始能信号。
对每一个寄存器，输入数据可配置成同步置位、同步复位、异步预置位、异步清零，具体配置可以通过软件。
迈入28nm阵营,Xilinx 7系列FPGA打造完整可编程产品组合
统一架 构 、将整体 功耗 降低一 半且具 言 ，Ａｒ － Ｐ ．ｍｍ焊球间距的低成本 ｔ ７Ｆ ＧＡ的 功耗 比 Ｓ ａ ａ － 片级封装和 １０ ｉ ｘ ｐ ｒ ｎ６ ｔ
Ｃ 有业界最 高容量 （ 多达 ２ ０万个逻 辑 Ｆ Ｇ 减 少 了 一 半 ， 成 本 降 低 了 Ｐ Ｂ制造封装 。 ０ ＰＡ
Ｅ ｃｕ 一 ｓ■ ｔ ｖ 一 ｅ ’ ｅ ｎ ｒ 一 ｘ ｔ ｉ ｖ ｌ ｅ ｉ 。 ｅｗ
迈入 ２ ｎ 阵营 ，Ｘｌ ｘ７系列 Ｆ Ｇ ８ｍ ｉ ｉ ｎ Ｐ Ａ打 造 完整可编程产 品组合 ■ 记者 ：韩霜
Ｐ Ｓ 在赛灵思公司看来 ，当今的全球经 可编 程解 决方 案 ，而 此前 只有 Ａ ＳＰ 低 功耗 、最 低 成本 的 Ｆ ＧＡ，采用小 济形势为可编程芯片发展提供了天时地 和 Ａ Ｉ 能 做 到 这 一 点 。 Ｓ Ｃ才
ｐ ｒ 一 Ｐ Ａ速度 快 ａ 争取更大的市场份额，往往意味着竞争 构 的 基 础 上 ，推 出 了三 款 全 新 统 一 元不 等 ，比 Ｓ ａｔｎ６Ｆ Ｇ 者要 跑步 前 进。如今 在 Ｆ Ｇ Ｐ Ａ领 域，
２ｎ ８ ｍ开始成为厂商们的竞争高地。
赛灵 思公司此次推 出的全新 ７系 （ 逻辑结构 、Ｂｏ ｋＲ ｌｃ ＡＭ、时钟技术 、
工艺 ，与其代工厂伙伴合作 ，协助定义 万 个逻辑 单元 ，在 降低一 半功耗 的情 １ Ｖ的新 一代车 载信息娱 乐系统 的小 ２ 新工艺以达到 Ｆ Ｇ Ｐ Ａ性能的要求。 同时， 况 下实现 了系统 性能 翻番。赛灵思 制 型 、低功 耗要求 ，还能满足 军用航 空 还采用创新型架构增强技术 ，以降低逻 定 了 Ｅ ｓ Ｐ ｔ ＷＡＰＣ要求 。 ． ａ ｙ ａｈ成本降低计划 ，可确保 电子和通信设备严格 的 Ｓ
xilinx fpga封装命名规则
xilinx fpga封装命名规则【1.FPGA封装概述】FPGA（现场可编程门阵列）是一种高度集成的硬件平台，用户可以根据需求配置和编程来实现不同的功能。
在FPGA中，封装起着关键作用，它将芯片的引脚连接到外部电路，便于与其他器件交互。
了解和掌握FPGA封装的命名规则，对于FPGA设计和工程师至关重要。
【2.Xilinx FPGA封装命名规则的含义】Xilinx作为全球领先的FPGA供应商，其封装命名规则具有一定的代表性和权威性。
该命名规则主要包括以下几个方面：1.封装类型：如BGA、QFP、TQFP等，表示封装的形状和引脚数。
2.制造商：如Xilinx，表示FPGA芯片的供应商。
3.系列：如7系列、10系列等，表示FPGA芯片的代际。
4.型号：如xc2064、xc5v系列等，表示具体芯片型号。
5.速度等级：如-2、-3、-4等，表示芯片的传输速度。
6.电源电压：如1.8V、3.3V等，表示芯片的工作电压。
【3.Xilinx FPGA封装命名规则的具体解析】以xc2064为例，解析其命名规则：- x：表示Xilinx公司。
- c：表示芯片系列，此处为7系列。
- 2064：表示该芯片具有2064个可用I/O引脚。
【4.命名规则在FPGA设计中的应用实例】在实际FPGA设计中，命名规则可以帮助工程师快速了解芯片的性能、引脚数量、工作电压等信息，从而选择合适的封装。
以下是一个应用实例：假设某项目需要使用具有较多I/O引脚的FPGA芯片，工程师可以通过查找xilinx FPGA封装命名规则中带有多位数的产品，如xc2064、xc2560等，来选取合适的芯片。
【5.总结与建议】掌握Xilinx FPGA封装命名规则，有助于工程师更高效地进行FPGA设计。
在实际应用中，建议工程师熟悉各类封装的特点和适用场景，以便根据项目需求选择合适的芯片。
XILINX FPGA选型详解
SLICEM中的函数生成器(LUTs)可以实现为同步RAM资源，
也称为分布式RAM。一个SLICEM中的多个LUT可以以 各种方式组合在一起，以存储每个SLICEM最多512位的 大量数据。多个切片可以组合起来创建更大的内存。
Maximum Distributed
RAM
Block RAM/FIFO w/ECC
存储的资源介绍可以参考：UG57CMT： 一个CMT包含一个混合模式时钟管理器 （MMCM）和两个锁相环；MMCM是用于 大范围频率的频率合成的主要块，并作为 外部或内部时钟的抖动滤波器，以及 deskew时钟和其他功能的广泛范围。PLL 的主要目的是为PHY I/Os提供时钟，但也 可以用于以有限的方式对设备中的其他资 源进行时钟。
基于SRAM的FPGA
这类产品是基于SRAM结构的可再配置型器件，通电时要将配 置数据读入片内SRAM中，配置完成就可进入工作状态。断电 后SRAM中的配置数据丢失，FPGA内部逻辑关机也随之消失， 这种基于SRAM的FPGA可反复使用。
01
反熔丝FPGA
采用反熔丝编程技术的FPGA内部具有反熔丝阵 列开关结构，其逻辑功能的定义由专用编程器根 据设计实现所给出的数据文件，对其内部反熔丝 真累进行烧录，从而使器件实现相应的逻辑功能。 这种器件的缺点是只能一次性编程，有点是具有 高抗干扰性和低功耗，适合于要求高可靠性、高 保密性的定型产品。
• Spartan7系列是7系列中拥有最低的价格、最低的功耗、最小的尺寸以及最低的设计难度，一些低端应用中极为合适 • Artix7系列是7系列中相对Spartan7系列则增加了串行收发器和DSP功能，其逻辑容量也更大，适合逻辑一些稍微复杂
的中低端应用
• Kintex7系列是7系列中在所有系列中拥有最佳的性价比，无论是硬核数量还是逻辑容量，都能满足中低端、以及部 分高端应用需求
xilinx fpga封装命名规则
xilinx fpga封装命名规则（原创版）目录1.Xilinx FPGA 芯片的命名规则2.芯片命名规则中的各部分含义3.命名规则的查询方法4.举例说明正文Xilinx FPGA 芯片的命名规则相对复杂，它包含了多个部分，每个部分都有其特定的含义。
首先，Xilinx FPGA 芯片的命名规则中，"XC"代表的是 FPGA 芯片的系列，比如 XC3S、XC4VLX 等，这个系列数字是对 FPGA 性能和功能的一种区分。
接下来的数字代表的是 FPGA 芯片的具体型号，比如"300"、"400"等，这个数字越大，代表的 FPGA 芯片的性能和功能也越强大。
其次，Xilinx FPGA 芯片的命名规则中，"-5"和"-7"等数字代表的是FPGA 芯片的性能等级。
比如，XC3S500 代表的是高性能的 XC3S 系列FPGA 芯片，而 XC3S700 代表的是更高性能的 XC3S 系列 FPGA 芯片。
再次，Xilinx FPGA 芯片的命名规则中，"FGG"和"FFG"等字母代表的是 FPGA 芯片的封装形式。
比如，XC3S500FGG676 代表的是 676 引脚的FPGA 芯片，采用 FBGA 封装，而 XC3S500FFG676 代表的是 676 引脚的FPGA 芯片，采用 QFP 封装。
最后，Xilinx FPGA 芯片的命名规则中，字母"C"代表的是 FPGA 芯片的商用等级，也就是表示这款 FPGA 芯片是商业级的，适用于一般的商业应用。
如果想要查询 Xilinx FPGA 芯片的命名规则，可以查阅 Xilinx 公司的官方文档，比如《Xilinx FPGA 用户手册》等。
在这些文档中，你可以找到详细的命名规则及其含义。
举个例子，XC3S500FGG676 这个命名，可以解读为：这是 XC3S 系列的 FPGA 芯片，具体型号为 500，性能等级为 -5，封装形式为 FBGA，引脚数为 676，商用等级为 C。
Xilinx全新7系列杀向功耗性能比新时代
Xilinx全新7系列杀向功耗性能比新时代“在我们全力降低功耗为新市场提供技术组合之际,7系列的推出表示赛灵思和FPGA行业全面进入新阶段。
除了让每代新产品都能根据摩尔定律发展满足自身及客户对容量和性能的要求之外,我们还继续致力于针对新用户和新市场的特定需求推出设计平台,为更广泛的用户群提供可编程逻辑。
”赛灵思总裁兼首席执行官MosheGavrielov说。
赛灵思全球高级副总裁汤立人指出“全新7系列FPGA(多达200万个逻辑单元)不仅在帮助客户降低功耗和成本方面取得了新的突破,而且还不影响容量的增加和性能的提升,从而进一步扩展了可编程逻辑的应用领域。
新系列产品采用针对低功耗高性能精心优化的28nm工艺技术,不仅能实现出色的生产率,解决ASIC和ASSP等其他方法开发成本过高、过于复杂且不够灵活的问题,使FPGA平台能够满足日益多样化的设计群体的需求。
”28nm系列产品进一步扩展了赛灵思随40nm Virtex-6和45nmSpartan-6 FPGA系列(现已投入量产)同步推出的目标设计平台战略。
该目标设计平台战略将FPGA、ISE设计套件软件工具和IP、开发套件以及目标参考设计整合在一起,使客户能够充分利用现有的设计投资,降低整体成本,满足不断发展的市场需求。
赛灵思在该新一代产品中迈出了关键性的一步,显着扩大了可用IP和设计生态系统,确保客户即便在向28nm产品转型过程中也能集中精力做好产品差异化工作。
业界最低功耗的28nm FPGA系列新型FPGA系列产品使开发人员能在多种系统(包括功耗不到2W的便携式超声波设备、供电电压为12V 的车载信息娱乐系统,以及低成本LTE基带和毫微微蜂窝基站等)中实施可编程解决方案,而此前只有ASSP和ASIC才能做到这一点。
赛灵思采用了专为实现低静态功耗精心优化的独特HKMG(高介电层/金属闸)工艺,相对于其他28nm高性能工艺而言能将静态功耗降低一半。
然后,赛灵思再采用创新型架构增强技术,以降低逻辑和I/O的静态功耗。
Xilinx FPGA高速资源合理利用的一种思路
电子技术与软件工程Electronic Technology & Software Engineering网络通信技术Network Com m unication TechnologyXilinx F P G A高速资源合理利用的一种思路杨见1陈伟1许杰2陈少林2(1.四川九洲空管科技有限责任公司四川省绵阳市621000 2.空装驻綿阳地区某军事代表室四川省綿阳市621000 )摘要：本文主要结合实际工程案例，遵照X ilin x高速收发器使用规则，对如何充分利用其硬件资源进行高速应用设计，提出一种 相对于常规设计思路更为合理的方式。
关键词：FPG A;高速资源；X ilin x高速收发器随着CML(CurrentModeLogic)、CDR、8b l0b 编码/64b66b 编码技术、预加重/去加重、时钟补偿等技术的出现，能够极大地 减小时钟抖动、收发时钟频偏、信号衰减和线路噪声对接收性能的 影响，从而使高速串行传输方式得到极为广泛的应用，而其接口信 号线数量少、应用成本低等优点，更是让开发人员相比并行数据传 输接口而言，更愿意选择高速串行传输方式。
Xilinx FPGA集成了 可实现不同线速率的高速串行收发器硬核资源，开发人员只需要进 行简单的配置即可实现高速串行应用。
基于成本考虑，在工程应用 中，开发人员依然遵循通过调用尽量少的资源去完成足够多的功能 这一准则展开设计。
本文就针对这一点对Xilinx FPGA高速串行资 源的利用提出一种设计思路进行分析并验证。
1设计需求QUAD116搭建4条常规的10G高速链路与目标设备三通信，QUAD115搭建3条10G高速链路与目标设备二通信，以及一条 千兆网链路与目标设备一通信。
链路设计要求如图1所示。
2设计思路Xilinx 7系列G T X每四个Channel组合成一个QUAD，每个 Q UAD有两组参考时钟输入，一个QPLL，4个CPLL，CPLL输出 时钟频率最高3.125Ghz，通信链路线速率最高6.25Gbps，QPLL输出时钟频率则在5.93Ghz〜12.5G h z范围内。
Xilinx Notes
7 Series FPGAs Overview参考ds180_7Series_Overview.pdf。
1.General Description7系列包括Artix 7、Kintex 7和Virtex 7。
其中Artix 7面向较低端应用，功耗低，价格低，封装小；Kintex 7面向中端应用，性价比更高，性能约比Artix 7提高2倍；Virtex 7面向高端应用。
采用28nm工艺。
2.Summary of 7 Series FPGA Features●Real 6-input look-up table(LUT) technology configurable as distributed memory.●SelectIO technology with support for DDR3 interfaces up to 1866Mb/s.●600Mb/s to 6.6Gb/s up to 28.05Gb/s.●包括一个用户可配置的ADC（双12位，1MSPS的ADC），芯片内部集成热和电源传感器。
●DSP slices with 25×18 multiplier, 48-bit accumulator, and pre-adder.●Powerful clock management tiles(CMT), combining phase-locked loop(PLL) andmixed-mode clock manager(MMCM) blocks for high precision and low jitter.●支持PCIe的endpoint和root port，支持gen3。
● 1.0V核电压，当需要达到更低的功耗时，可配置0.9V核电压。
3.CLBs, Slices, and LUTs7系列的FPGA可将任意一个查找表配置为6输入查找表（64bit ROM），或配置为2个5输入查找表（32bit ROM）。
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解读XILINX的7系列28nm FPGA封装策略
买椟还珠的故事，大家一定不陌生。
如果把芯片内部最值钱和最有技术含量的那个硅片比喻为珍珠的话，芯片外面的封装，包括管脚，就可以比喻为椟了。
搞芯片的，无不以能设计出皇冠上的那颗明珠而自豪，如果有人说自己是搞封装的，多半会被人觉得是芯片行业的非主流。
然而，有个叫戈登摩尔的人，搞出来一个摩尔定律，明确提出，同样的珍珠，价格，每隔18个月减半。
（本文由OpenHW 的Kevin原创，转载请注明）。
芯片的来源，归根到底，是取之不竭的沙子，而封装，管脚这些东西，可是要实实在在地消耗铜，金，稀有金属等资源。
因此，封装的成本降低的速度，远远小于摩尔定律的速度。
这样，如果椟的价格不变的话，珍珠的价格总有一天会比椟还便宜，没办法，再贵的价格，被2除了n次，都会很便宜。
封装也有贵的和便宜的之分。
管脚越多越贵，对散热要求越高越贵。
因此，想要做到封装也便宜，功耗小是基本要求。