Closed-Form Expressions for the Maximum Transient Noise Voltage Caused by an IC Switching Current on

Closed-Form Expressions for the Maximum Transient Noise V oltage Caused by an IC Switching Current on a Power Distribution NetworkJingook Kim,Member,IEEE,Liang Li,Songping Wu,Student Member,IEEE,Hanfeng Wang,Yuzo Takita, Hayato Takeuchi,Kenji Araki,Senior Member,IEEE,Jun Fan,Senior Member,IEEE,and James L.Drewniak,Fellow,IEEEAbstract—Closed-form expressions for transient power distri-bution network(PDN)noise caused by an IC switching current are derived for a PDN structure comprised of traces with decou-pling capacitors.Criteria for identifying a dominant decoupling capacitor for an impulse switching current are also proposed.The derived PDN noise expressions are validated with measurements of currents at both local and bulk capacitors,the PDN impedance, and the total voltage noise in an operating consumer device.Index Terms—Current measurement,design guideline,dynamic noise,power distribution network(PDN),switching current,target impedance,transient noise.I.I NTRODUCTIONM ODERN integrated circuits(ICs)operate with an inter-nal clock frequency of more than several gigahertz and core power currents of up to tens of amperes.The switching currentflowing from power to ground through the core logic and buffers results in significant drop and ripple in the sup-ply voltage,seriously affecting power integrity(PI)and signal integrity(SI),as well as causing electromagnetic interference (EMI)problems[1]–[3].For EMI and SI concerns,not only the magnitude of the voltage ripple or drop but also its time-domain waveform determines the spectral components of electromag-netic emissions,crosstalk,and jitter.For PI,engineering best practices hold that the maximumfluctuation of the power level seen by an IC is most critical,since too much voltagefluctua-tion can give rise to serious functionality issues such as logicManuscript received October30,2011;revised February17,2012;accepted April4,2012.Date of publication April30,2012;date of current version October 17,2012.This work was jointly supported by the National Science Foundation under Grant0855878,and the year of2011Research Fund of the Ulsan National Institute of Science and Technology,Korea.J.Kim is with the School of Electrical and Computer Engineering,Ulsan National Institute of Science and Technology,Ulsan689-798,Korea(e-mail: jingook@unist.ac.kr).L.Li,H.Wang,J.Fan,and J.L.Drewniak are with the Electromagnetic Compatibility Laboratory,Missouri University of Science and Technology, Rolla,MO65409USA(e-mail:llh9b@;hw3h6@; jfan@;drewniak@).S.Wu was with the Electromagnetic Compatibility Laboratory,Missouri University of Science and Technology,Rolla,MO65409USA.He is now with Cisco Systems,San Jose,CA95134USA(e-mail:swhv7@).Y.Takita,H.Takeuchi,and K.Araki are with the Sony Corpora-tion,Tokyo108-0075,Japan(e-mail:Yuzou.Takita@;Hayato. Takeuchi@;Kenji.Araki@).Color versions of one or more of thefigures in this paper are available online at .Digital Object Identifier10.1109/TEMC.2012.2194786malfunction and timing jitter in signals.Many reports in the literature have focused on predicting and minimizing the worst case voltage drop[4],[5].The average noise within a clock cycle is also important,in addition to the peak noise,because the power-supply noise affects timing,system performance,and core logic failures[6],[7].Currently,one of the important design objectives of a power distribution network(PDN)is to supply enough charge quickly for IC switching so that the maximum voltage drop seen by the IC is smaller than the specified allow-able limit,which is usually defined as a percentage of the supply voltage.A very convenient guideline for PDN design is target impedance[8]–[10],because the performance of a PDN is typ-ically analyzed in the frequency domain,especially in the early design stages.If the IC current consumption can be estimated from IC models such as SPICE or IBIS,the voltage drop at the IC is assumed as a product of the current with the input impedance of the PDN in the frequency domain.The target impedance is defined as the input impedance that results in the maximum al-lowable voltage drop.Then,the objective of the PDN design is to achieve an input impedance lower than the target impedance, which supposedly ensures a voltage drop lower than the limit. The target impedance is commonly defined asZ target=((Power Supply V oltage)×(allowed ripple%))current.(1) This definition,which is very straightforward and intuitive,is just extended to the entire frequency range of interest as a con-stant value.However,the actual impedance of a PDN at the IC is not a constant,but a strong function of frequency.The parasitic inductances existing in the PDN structures such as traces,par-allel planes,and vias make the low-impedance objective more difficult to achieve at higher frequencies[11],[12].In other words,the target impedance of(1)is highly constrained at high frequencies,which could result in an overdesign.Also,both the voltage ripple and the switching current is a time-domain concept,whereas the target impedance is a frequency-domain concept.In[12],the Fourier transform was used to calculate the worst noise from the designed PDN impedance and com-pared with the target noise ing the frequency-domain PDN model in retrieving the time-domain noise voltage re-quires computational steps such as an inverse Fourier transform or pole-zerofitting methods[13].However,a simpler intuitive0018-9375/$31.00©2012IEEErelationship between the PDN impedance and the actual noise voltage would be more useful in the early design stages.An improved concept for target impedance was proposed in[14]to correlate the PDN impedance with the IC switching current waveforms and the allowable voltage drop waveforms in the time domain.The target impedance was directly derived from the transient noise response induced by a single current impulse.The previous approach was applicable only in the high-frequency range for the design of a local decoupling capacitor. To extend and generalize the improved target impedance con-cept over the entire frequency range,a more rigorous formula-tion is required for a PDN structure with multiple decoupling capacitors.Establishing PDN design specifications such as the target impedance is the reverse problem of the PDN noise analysis. In the noise analysis problem,the maximum noise voltage on the PDN induced by the IC switching current can be estimated by simulation or calculation using an appropriate PDN model and the switching current.Conversely,specifications for PDN design are obtained from a knowledge or approximation of the IC switching current and a maximally allowable PDN noise limit.To develop specifications,a simple representation of the maximum PDN noise caused by IC switching currents in the time domain is necessary.In this paper,closed-form expressions for the maximum PDN noise resulting from a switching current impulse of an IC in a given PDN model are developed along with useful criteria identifying the dominant decoupling capacitor for the current impulse.The maximum PDN voltage ripple can then be quickly estimated using the proposed expressions,as shown in Fig.1. The waveform of an IC switching current is approximated by a triangular shape.The proposed PDN noise expressions are then validated from measurements in an operating handheld con-sumer device,where the PDN utilizes power traces instead of power planes due to the high design density of such products. Full measurements of current at both local and bulk capacitors, PDN impedance,and the total voltage noise have been per-formed on an IC power trace.The closed-form expressions for the PDN noise caused by an impulse current can be applied to develop more rigorous PDN design methodology,such as an im-proved target impedance,which is desirable for a cost-effective solution in consumer electronic devices.II.C RITERIA FOR C LOSED-F ORM S OLUTIONS OF THES ECOND-O RDER D IFFERENTIAL E QUATION FOR T RANSIENTC URRENT AND PDN N OISE V OLTAGEUsing power traces is fairly common in compact consumer electronic devices for various reasons.As shown in Fig.2(a), several capacitors such as large capacitance value and package size bulk capacitors,as well as small local ones,are employed to lower the impedance value in different frequency ranges.Bulk capacitor works well from approximately1kHz to1MHz.A high-frequency ceramic local capacitor is effective from approx-imately1MHz to several hundred MHz.A local capacitor is closer to an IC but has smaller capacitance value than a bulk one,which provides hierarchical charge reservoirs,as shownin Fig.1.Fast estimation of maximum PDN voltage ripple at an IC using the closed-form expressions proposedherein.Fig.2.(a)Trace-type PDN net with decoupling capacitors in a compact con-sumer electronic device,and(b)its cascaded LC circuit model,and(c)the impedance seen at the IC.The elements dominating a particular bandwidth are indicated on the curve.Fig.2(b).In the small hand-held product,the length of power net between the local and bulk capacitors is likely to be much shorter than a wavelength of even the fastest IC switching currents.The trace net between capacitors is then electrically short and can be modeled as one-stage LC circuit.The traces between an IC and decoupling capacitors are then modeled just as series re-sistances and inductances,because the capacitance of the trace is negligible compared to the value of decoupling capacitors.Thus,the PDN structure of the trace net with decoupling ca-pacitors can be modeled as cascaded LC circuits,as shown in Fig.2(b).The inductance comes from the interconnections (such as bond wires,BGA balls,package/printed circuit board (PCB)traces,and vias)and the equivalent series inductance of the capacitor package.The resistance is dominated by the con-tact resistance of the IC pins,interconnects,and the equivalent series resistance of the capacitor.The ultimate charge reservoir for all switching is the voltage regulator module(VRM)such as a dc–dc buck converter,which is located at the end of the power net.The VRM can also be modeled as a large value inductor in series with an ideal battery at frequencies higher than the dc–dc switching frequency[15].On-chip and on-package decoupling capacitors,which are not shown in Fig.2,may also be used. The impedance seen from the IC side is dominated by inductive and capacitive response in the impedance curves with alternating poles and zeros,as depicted in Fig.2(c).The hierarchical charge reservoir of decoupling capacitors results in separated multiple poles and zeros in the impedance curve.The ratio of the values of the bulk and local capacitors is usually more than10in order to separate the multiple resonance frequencies and lowers the PDN impedance in wide frequency ranges.The resistances con-tribute to the IR drop at dc and the Q-factors of the resonances. The rigorous expressions for the transient currents and noise voltages at the PDN in Fig.2(b)are given as solutions of the fourth-order differential equation,which are very complicated and not practical to use.The objective of this paper is to ob-tain practical closed-form expressions for transient currents and noise voltages at the PDN,which can be used to develop design guidelines in practice.Therefore,the expressions are approx-imated for practical use within reasonable assumptions.The first assumption is short-circuit approximation of a capacitor at the next downstream branch.For example,when an IC tran-sient switching current i1(t)with a triangular shape is drawn, as shown in Fig.3(a),it is divided into i C1(t)and i2(t)at the first node N1for the capacitor C1.In analyzing the current sep-aration at the N1node,the capacitor at the next downstream branch C2is approximated as a short circuit.The short-circuit approximation of the downstream capacitor C2has little effect on the currents amounts of the i C1(t)and i2(t),as long as the ratio of the C1and C2is sufficiently large.The validation of this approximation will be discussed soon.With the approxi-mation,the transient currents i C1(t)and i2(t)resulting from the current i1(t)are then calculated as closed-form solutions of the second-order differential equation.The resultant i2(t)is then drawn from the downstream section.The i2(t)is drawn from i C2(t)and i3(t)combined at the node N2,as shown in Fig.3(b). The i C2(t)and i3(t)should be solved with maintaining the C2 capacitor,because the C2is not a downstream capacitor for the N2node and its effect is not negligible.The i C2(t)and i3(t)are then also solved as the solutions of the second-order differen-tial equation,as shown in Fig.3(b).Through this hierarchical solving procedure,all the transient currents at every node are solved analytically in closed-form solutions of the second-order differential equations.As mentioned,however,this transient an-alytical procedure works only when the capacitors at the next downstream branches can be approximated as a shortcircuit.Fig.3.Hierarchical procedure for calculating every current at a PDN in closed-form solutions of the second-order differential equation.(a)Bulk capacitor was shorted in analyzing currents at thefirst section,(b)Currents at the next downstream section are calculated from the currents calculated in(a),with maintaining the bulk capacitor.The short-circuit approximation to achieve the practical closed-form solutions is valid when the ratio of the values of the bulk and local capacitors is sufficiently large satisfying a certain criterion.Tofind the criterion,the PDN branch impedances for two cases with and without the short-circuit approximation of the C2capacitor are compared in Fig.4.The C2capacitor is shorted in Fig.4(b).The impedance of the C1branch is denoted as Z1,and the impedance of all other downstream branches af-ter the N1node is denoted as Z2and Z 2for Fig.4(a)and(b), respectively.The Fourier transform I1(f)of the current i1(t)is then divided at the N1node by the ratio of Z1and Z2,and that of Z1and Z 2,respectively.The Fourier transform of the current flowing after the N1node are given asI2(f)=Z1Z1+Z2I1(f),I 2(f)=Z1Z1+Z 2I1(f)(2)where I2(f)and I 2(f)are the Fourier transform of the currents, i2(t)and i 2(t),in Fig.4(a)and(b),respectively.If|Z2−Z 2|<<|Z1|,thenI 2(f)=Z1Z1+Z2−(Z2−Z 2)I1(f)≈Z1Z1+Z2I1(f)=I2(f)(3) which means that the I 2(f)is approximately equal to I2(f)in the condition.As a rule of thumb,assuming that a maximally10%error is allowable,the criterion for the condition of|Z2−Z 2|<<|Z1| is conveniently defined as|Z2−Z 2|<110|Z1|.(4) The|Z2−Z 2|is derived as|Z 2−Z2|=(R3+R VRM+jω(L3+L VRM))2(R 3+jωL 3)(jωC2R 3+1−ω2C2L 3)<(R 3+jωL 3)(jωC2R 3+1−ω2C2L 3)(5)Fig.4.Assessment of a criterion for the closed-form solutions of each currentwith circuit models and responses of (a)original branch impedances and (b)branch impedances with the bulk capacitor shorted.The dominant elements in a particular bandwidth are indicated.where R3=R C 2+R 3+R VRM ,L 3=L C 2+L 3+L VRM ,and ω=2πf .The |Z 1|and the upper boundary of |Z 2−Z2|in (5)are depicted together according to the frequency in Fig.5.Thepeak value of |Z2−Z 2|occurs at the frequency of f 0=1/(2π L 3C 2).The values of |Z 2−Z2|and |Z 1|at f 0are obtained as|Z 2−Z 2|f =f 0<L 3C 2+1R 23L 23C 22and|Z 1|f =f 0≈L 3C 2C 1.(6)The criterion of (4)at f 0is then simplified asZ 2−Z 2Z 1 f =f 0<110i .e .,C 2C 1>10 1+1R 23L 3C 2.(7)Both of the |Z 2−Z2|and |Z 1|in the frequencies higher than f 0has the capacitive impedance determined by C 2and C 1,asFig.5.Comparison between magnitudes of the (Z 2–Z 2)and Z 1.shown in Fig.5,and the criterion of (4)in those frequency range is given asZ 2−Z 2Z 1f >f 0<110i .e .,C 2C 1>10.(8)The condition (7)includes (8).Thus,if only condition (7)issatisfied,the |Z 2−Z2|is smaller than a tenth of |Z 1|at every frequency,and the I 2(f )is approximately equal to I 2(f )at every frequency with less than 10%error by (3).Consequently,the current i 2(t )can be approximated as i 2(t ),if the criteria (7)is satisfied.Equations (7)and (8)basically define the ratio of two hierar-chical capacitors C 1and C 2,which means the bulk decoupling capacitance should be larger more than ten times the local decou-pling capacitance.If the ratio of the values of two hierarchical capacitors does not satisfy the criterion,then the proposed hi-erarchical analysis including the short-circuit approximation of the next downstream capacitor is not applicable.In that case,a circuit simulator can be utilized to find transient current and voltages instead of using the analytical solutions,because the solutions are too complicated to be practical.However,as men-tioned,the criterion is usually satisfied in common PDN designs,since the multiple resonance frequencies caused by each capaci-tor should be sufficiently separated to lower the PDN impedance in wide frequency ranges.Therefore,the current at all branches in a practical trace PDN can be solved analytically in simple closed-form solutions of the second-order differential equation,which could be useful in developing design guidelines.The practical case where the ratio of values of the bulk and local capacitors is sufficiently large is just focused and considered herein.On the other hand,if two adjacent capacitors are both local decoupling capacitors in close proximity to each other with sim-ilar capacitance values,then the resonance frequencies caused by each capacitor are also similar.The two local capacitors are then in parallel and can be considered as an equivalent local capacitor.III.C LOSED-F ORM E XPRESSIONS FOR M AXIMUM PDN N OISE V OLTAGE I NDUCED BY A T RIANGULAR C URRENT I MPULSE The transient current and voltage noise are solved analytically in time domain,and simple expressions for maximum voltage noises are derived in this section.Assume the IC switching current i1(t)can be modeled as a triangular impulse asi1(t)=I peakT r(tu(t)−2(t−T r)u(t−T r)+(t−2T r)u(t−2T r))(9)where I peak and T r represent the peak value and rise time of the triangular current,respectively,and the u(t)represents the Heaviside step function.The currents i C1(t)and i2(t)at the node N1containing the local capacitor branch as shown in Fig.3(a)are then approxi-mately solved asi C1(t)=I peakT rL 2(L C1+L 2)·1ω1⎛⎜⎝sinω1te−α1t u(t)−2sinω1(t−T r)e−α1(t−T r)u(t−T r)+sinω1(t−2T r)e−α1(t−2T r)u(t−2T r)⎞⎟⎠(10)i2(t)=I peakT r(tu(t)−2(t−t r)u(t−t r)+(t−2t r)u(t−2t r))−I peakT rL 2(L C1+L 2)·1ω1⎛⎜⎝sinω1te−α1t u(t)−2sinω1(t−T r)e−α1(t−T r)u(t−T r)+sinω1(t−2T r)e−α1(t−2T r)u(t−2T r)⎞⎟⎠(11)whereω1andα1represent the oscillation frequency and the attenuation constant,which are given asω1≈1/(L C1+L 2)C1andα1=(R C1+R 2)/2(L C1+L 2)in ω1>>α1;L 2=L2+[L C2||(L3+L VRM)]and R 2=R2+ [R C2||(R3+R VRM)].The resistances have very little effects on the expression of i C1(t)and i2(t),except for the attenuation constant of the sine functions,when it is assumed that the impedance seen from the IC is dominated by inductive and capacitive impedance curves, except for the resonance peaks.Equations(10)and(11)are simplified in practical conditions of the impulse current,and the simple expressions for maximum transient voltage noise are obtained in the following sections.A.Maximum Voltage Noise Induced by an Impulse Current With Fast Rise TimeThefirst practical condition is the case when the rise time of current T r is much faster than the LC oscillation period as2ω1T r<0.25π,i.e.,T rT p1<0.063(12)where T p1is the oscillation period given as T p1=2π/ω1.Fig.6.(a)Division of the IC current with fast rise time at the local decouplingcapacitor branch.(b)Three components in the PDN noise voltage caused by theIC current with fast rise time.In condition(12),sinω1t≈ω1t at t≤2T r in10%error,andthe i2(t)and i C1(t)in(10)and(11)are approximated asi C1(t≤2T r)≈I peakT rL 2L C1+L 2·tu(t)−2(t−T r)u(t−T r)+(t−2T r)u(t−2T r)andi2(t≤2T r)≈I peakT rL C1L C1+L 2·tu(t)−2(t−T r)u(t−T r)+(t−2T r)u(t−2T r).(13)Because the L C1is much smaller than L 2in usual PDN de-signs,the i C1(t)should be much larger than i2(t),as depicted inFig.6(a),which means a fast impulse current is predominantlyprovided by the local decoupling capacitor.The voltage drop at the location of IC induced by the currentsis then calculated as−v(t≤2T r)=(R1i1(t)+R C1i C1(t))+L1di1(t)dt+L C1di C1(t)dt+1C1i C1(t)dt=I peakT rR1+R C1L 2L C1+L 2×tu(t)−2(t−T r)u(t−T r)+(t−2T r)u(t−2T r)+I peakT rL1+L C1L 2L C1+L 2(u(t)−2u(t−T r)+u(t−2T r)) +I peakT rL 2L C1+L 212C1t2u(t)−2(t−T r)2u(t−T r)+(t−2T r)2u(t−2T r).(14) Thefirst term in(14)has the same shape as the IC current.The second and third terms are proportional to the derivativeand the integration of the IC current,respectively.Each term represents the noise component caused by the resistance,induc-tances,and capacitance.The characteristic shapes of each noise term are summarized in Fig.6(b),and the total voltage drop is the summation of the three noise components.The maximum drop of the transient voltage noise is the most critical parameter in PI,since the possibility of logic malfunction and the maximum jitter at output buffers in IC predominantly depend on the maximum voltage ripple.Since the voltage drop,–v (t ),is uniformly increasing from t =0to t =T r ,the maximum voltage drop can occurs at T r ≤t ≤2T r .First,the voltage drops at the rise time T r and at the twice the rise time 2T r are given as−v (T r )=I peak R 1+R C 1L 2L C 1+L 2+I peakT r L 1+L C 1L 2L C 1+L 2+I peakL 2L C 1+L 2T r 2C 1(15)−v (2T r )=I peakL 2L C 1+L 2T rC 1.(16)If there is a maximum voltage drop at T r <t <2T r ,thederivative of –v (t )should be equal to zero at the maximum drop.The value of a possible maximum voltage drop and the time when it occurs,t peak ,is then obtained as−v (t peak )=I peak C 12T r R 1+R C 1L 2L C 1+L 2 2L C 1+L 2L 2−I peak T r L 1+L C 1L 2L C 1+L 2+I peak T rC 1L 2L C 1+L 2(17)where t peak=2T r −L C 1+L 2L 2R 1+R C 1L 2L C 1+L 2C 1.(18)Because t peak >T r ,i.e.,T r >L C 1+L 2L2R 1+R C 1L 2L C 1+L 2C 1,the upper boundary of the −v (t peak )can be found as−v (t peak )<I peak2R 1+R C 1L 2L C 1+L 2−I peakT r L 1+L C 1L 2L C 1+L 2+I peak T r C 1L 2L C 1+L 2=12(−v (T r ))−3I peak 2T rL 1+L C 1L 2L C 1+L 2+34(−v (2T r )).(19)Hence,any maximum voltage drop at T r <t <2T r ,−v (t peak ),is smaller than 1.25·max (−v (T r ),−v (2T r )).The voltage drop at t ≥2T r does not exceed (−v (2T r ))either,and the max-imum voltage drop at overall time induced by a single triangular current can be summarized as−v max ≈I peak ·max (−v (T r ),−v (2T r ))=I peak·max ⎛⎜⎜⎝R1+1T r L 1+L C 1L2L C 1+L 2 +L 2L C 1+L 2T r 2C 1,L 2L C 1+L 2T r C 1⎞⎟⎟⎠(20)where R 1=R 1+R C 1L2L C 1+L 2,L 2=L 2+L C 2||(L 3+L VRM ).L 2is usually much larger than the L C 1in a practical PDN design,and (20)is then further simplified as−v max ≈I peak·max R 1+R C 1+1T r (L 1+L C 1)+T r 2C 1,T rC 1.(21)B.Local Capacitor Branch Neglected for an Impulse CurrentWith Slow Rise TimeExpressions (20)and (21)for the maximum voltage drop are applicable to the case when the rise time of the triangular impulse current is much faster than the oscillation period T p 1.On the contrary,if the rise time of an impulse current is much slower than the oscillation period,then the C 1capacitor branch can be just neglected.The condition for neglecting the local decoupling capacitor is quantitatively identified herein.The second term in i 2(t )of (11)is the summation of sine functions.Because −1≤sin ω1t ≤1,the summation of the sine functions cannot be larger than 4.So the second term in i 2(t )is bounded below a limit asI peakT r L 2L C 1+L 2·1ω1⎛⎜⎝sin ω1te −α1t u (t )−2sin ω1(t −T r )e −α1(t −T r )u (t −T r )+sin ω1(t −2T r )e −α1(t −2T r )u (t −2T r )⎞⎟⎠≤4I peakT r ω1·L 2(L C 1+L 2).(22)Therefore,if1T r ω1<140,i.e.,T r T p 1>6.4(23)then (22)is bounded below Ip e a k 10·L2(L C 1+L 2),which is smaller than 10%of the peak in the first term of i 2(t ).The second term in the i 2(t )can then be ignored in criterion (23),and the i 2(t )is just approximated to only its first term asi 2(t )≈I peakT r(tu (t )−2(t −T r )u (t −T r )+(t −2T r )u (t −2T r ))which is the same as the current before the C 1capacitor branch,i 1(t ).In summary,if the rise time of an triangular impulse current is much slower than the oscillation period T p 1,as T r /T p 1>6.4,then very little portion of the current is provide by the C 1capacitor,and the voltage ripple can be analyzed at the next downstream LC sections with just ignoring the C 1capacitor branch,as shown in Fig.7.It physically represents that theFig.7.Local capacitor branch neglected for an impulse current with slow risetime.charge for a slow impulse current is predominantly provided by a far and large capacitor,rather than by a close and small capacitor.C.Expressions Summary for Maximum Voltage Drop The maximum transient voltage drop induced by a triangu-lar impulse current can be represented with simple expressions by identifying the criteria described earlier.First,the condition for solutions of the second-order differential equation should be confirmed by comparing the values of two hierarchical capac-itors C 1and C 2.If C 2is much larger than C 1with satisfying criterion (7),all currents at every branch can be expressed in closed forms.The second process is identifying whether the capacitor C 1is dominant or negligible for the impulse current.When the rise time of the current is much faster than the oscil-lation at C 1capacitor by criterion (12),the fast impulse current is predominantly provided by C 1rather than by the other down-stream PDN structure,as shown in Fig.8(a).This case is denoted as Criterion 1herein.The maximum voltage drop can then be calculated using (20)or (21).On the contrary,when the rise time of the current is much slower than the oscillation period by criterion (23),the C 1branch is negligible and the major portion of the impulse current is di-rectly provided by the downstream PDN structure.Once C 1is neglected,the similar process determining whether C 2is dom-inant or negligible for the impulse current is performed by re-placing the T p 1and ω1with T p 2and ω2in criteria (12)and (23),respectively.T p 2and ω2represent the period and frequency of the oscillation at C 2capacitor given asT p 2=2π/ω2and ω2=1(L C 2+L 3+L VRM )C 2.(24)If C 1is negligible and C 2is a dominant capacitor for the impulse current,which is denoted as Criterion 2,the impulse current is predominantly provided by C 2,as shown in Fig.8(b).The voltage drop is then calculated as −v (t )=(R 1+R 2)i 1(t )+R C 2i C 2(t )+(L 1+L 2)di 1(t )dt +L C 2di C 2(t )dt +1C 2i C 2(t )dtwhich is similar to that for the dominant local decouplingcapacitor.Fig.8.Expressions for the maximum noise when the IC current is predom-inantly provided by (a)the local capacitor (Criterion 1),(b)the bulk capacitor(Criterion 2),and (c)the VRM (Criterion 3).The maximum voltage drop is also similarly given as−v max ≈I peak max ⎛⎜⎜⎝R1+1T r L 1+L 2+L C 2L3L C 2+L 3 +L 3L C 2+L 3T r 2C 2,L3L C 2+L 3T r C 2⎞⎟⎟⎠(25)where R 1=R 1+R 2+R C 2L 3L C 2+L 3and L 3=L 3+L VRM .L 3is also usually much larger than the L C 2in a practical PDN design,and (25)is further simplified as−v max ≈I peak max ⎛⎜⎝R 1+R 2+R C 2+1T r×(L 1+L 2+L C 2)+T r 2C 2,T r C 2⎞⎟⎠.(26)For the last case of Criterion 3,if the both C 1and C 2branches are negligible,most of the impulse current is directly provided by the VRM,as shown in Fig.8(c).In this case,the maxi-mum voltage drop always occurs at t =T r ,because there is no capacitive noise.It is simply given as−v max ≈I peak (R 1+R 2+R 3+R VRM )+I peakT r(L 1+L 2+L 3+L VRM ).(27)。