Fly Reliability Test Standard V10.0

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Semiconductor Reliability Training

Request for product termination
NPR: new product request DAC: design approval certificate PQC: product qualification certificate
9
Accelerated life test
➢ Why accelerated ?
It is used to reduce necessary learning time to understand:
• How and why device failure, to identify design and process weak points in order to what/how to improve • When device expected to failure
Reliabilit yTraining
Plan
➢ This short course is intended to give you some basics in Reliability ➢ Contents
➢ Introduction to Reliability ➢ Accelerated Life Test • Preconditioning • Moisture resistance test • Mechanical robustness test • Die oriented test --- HTRB • HTS --- IMC formation risk • Solderability vs. whisker test ➢ Potential package failure & Risk assessment validation ➢ Reliability qualification practice (example: Green molding compound qualification)

B101EW04 V0 spec_10.1寸AU屏

1 of 31B101EW03 V0 document version : 0.1( ) Preliminary Specifications (V ) Final SpecificationsModule 10.1” SD+ 16:10 TFT-LCD Model Name B101EW04 V0Note ()LED Backlight without driving circuit designCustomerDateNormal 02/15/2011Checked & Approved byDate Note: This Specification is subject to change without notice.Approved by DateIvan Wu02/15/2011Prepared byJay Lin 02/15/2011NBBU Marketing Division / AU Optronics corporation2 of 31B101EW03 V0 document version : 0.1 Contents1. Handling Precautions........................................................................................................4 2. General Description . (5)2.1 General Specification......................................................................................................................................5 2.2 Optical Characteristics...................................................................................................................................6 3. Functional Block Diagram ...............................................................................................11 The following diagram shows the functional block of the 10.1 inches wide Color TFT/LCD 40 Pin (One ch/connector Module).....................................................................................11 4. Absolute Maximum Ratings (12)4.1 Absolute Ratings of TFT LCD Module.........................................................................................................12 4.2 Absolute Ratings of Environment................................................................................................................12 5. Electrical characteristics. (13)5.1 TFT LCD Module............................................................................................................................................13 5.2 Backlight Unit ................................................................................................................................................15 6. Signal Characteristic. (16)6.1 Pixel Format Image........................................................................................................................................16 6.2 The input data format....................................................................................................................................17 6.3 Integration Interface Requirement...............................................................................................................18 6.4 Interface Timing.............................................................................................................................................20 6.5 Power Sequence............................................................................................................................................21 6.5.1 Panel Power Sequence..............................................................................................................................21 7. Panel Reliability Test (22)7.1 Vibration Test.................................................................................................................................................22 7.2 Shock Test......................................................................................................................................................22 7.3 Reliability Test ...............................................................................................................................................22 8. Mechanical Characteristics. (23)8.1 LCM Outline Dimension................................................................................................................................23 9. Shipping and Package.. (25)9.1 Shipping Label Format..................................................................................................................................25 9.2 Carton Package .............................................................................................................................................26 9.3 Shipping package of palletizing sequence.................................................................................................27 10. Appendix . (28)10.1 EDID description (28)3 of 31B101EW03 V0 document version : 0.1Record of RevisionVersion and Date Page Old descriptionNew DescriptionRemark 0.1 2010/10/28 All First Edition for Customer4 of 31B101EW03 V0 document version : 0.11. Handling Precautions1) Since front polarizer is easily damaged, pay attention not to scratch it.2) Be sure to turn off power supply when inserting or disconnecting from input connector. 3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots.4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.6) Since CMOS LSI is used in this module, take care of static electricity and insure human earth when handling.7) Do not open nor modify the Module Assembly.8) Do not press the reflector sheet at the back of the module to any directions.9) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the Interface Connector of the TFT Module.11) After installation of the TFT Module into an enclosure (Notebook PC Bezel, for example), do not twist nor bend the TFT Module even momentary. At designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the TFT Module from outside. Otherwise the TFT Module may be damaged. 12) S mall amount of materials having no flammability grade is used in the LCD module. The LCD module should be supplied by power complied with requirements of Limited Power Source (IEC60950 or UL1950), or be applied exemption. 13) D isconnecting power supply before handling LCD modules, it can prevent electric shock, DO NOT TOUCH the electrode parts, cables, connectors and LED circuit part of TFT module that a LED light bar build in as a light source of back light unit. It can prevent electrostatic breakdown.5 of 31B101EW03 V0 document version : 0.12. General DescriptionB101EW03 V0 is a Color Active Matrix Liquid Crystal Display composed of a TFT LCD panel, a driver circuit, and LED backlight system. The screen format is intended to support 1280(H) x 800(V) screen and 262k colors (RGB 6-bits data driver) with LED backlight driving circuit. All input signals are LVDS interface compatible.B101EW03 V0 is designed for a display unit of notebook style personal computer and industrial machine.2.1 General SpecificationThe following items are characteristics summary on the table at 25 ℃ condition:ItemsUnit SpecificationsScreen Diagonal [mm] 255.85(10.07W”) Active Area [mm] 216.96(H) x 135.6(V) Pixels H x V 1280x3(RGB) x 800 Pixel Pitch [mm] 0.1695(H) x 0.1695(V) Pixel Arrangement R.G.B. Vertical Stripe Display ModeNormally BlackWhite LuminanceNote: I LED is LED current [cd/m 2] 400 typ, 320minLuminance Uniformity (5P) 1.25 max Contrast Ratio 600 min Response Time[ms] 25 typ Nominal Input Voltage VDD [Volt] +3.3 typ.Power Consumption[Watt]Typ Max - 3.1W @ Black patternWeight[Grams] 190g max. Physical Size[mm] LWT Max 229.96 149.6 5.56 Typical 229.46 149.1 Min 228.96 148.6 3.39Electrical Interface 1 channel LVDS6 of 31B101EW03 V0 document version : 0.1 Glass Thickness [mm] 0.3 Surface Treatment GlareSupport Color262K colors ( RGB 6-bit +FRC)Temperature Range OperatingStorage (Non-Operating) [oC] [o C]0 to +50 -20 to +60RoHS ComplianceRoHS Compliance2.2 Optical CharacteristicsThe optical characteristics are measured under stable conditions at 25℃ (Room Temperature) :ItemSymbolConditions Min. Typ. Max. Unit NoteWhite LuminanceILED=18.5mA5 points average320 400 - cd/m 21, 4, 5θR θL Horizontal (Right) CR = 10 (Left) 80 80 - - - - degreeViewing AngleψH ψL Vertical (Upper) CR = 10 (Lower)80 80 - - - - 4, 9Luminance Uniformity δ5P 5 Points - - 1.25 1, 3, 4 Luminance Uniformity δ13P 13 Points- - 1.60 2, 3, 4 Contrast Ratio CR 600 - - 4, 6 Cross talk % 4 4, 7T r Rising - - - T f Falling - - - Response TimeT RTRising + Falling-25-msec4, 8Rx 0.542 0.582 0.622 RedRy 0.303 0.343 0.383 Gx 0.294 0.334 0.374 Green Gy 0.540 0.580 0.620Bx 0.107 0.147 0.187 Blue By 0.089 0.129 0.169 Wx 0.273 0.313 0.353 Color / Chromaticity CoodinatesWhiteWy 0.289 0.329 0.369 NTSC%CIE 1931-45-47 of 31B101EW03 V0 document version : 0.1Note 1: 5 points position (Ref: Active area)Note 2: 13 points position (Ref: Active area)Note 3: The luminance uniformity of 5 or13 points is defined by dividing the maximum luminance values by the minimum test point luminanceδW13 = Maximum Brightness of thirteen pointsMinimum Brightness of thirteen points Maximum Brightness of five pointsδW5 = Minimum Brightness of five points8 of 31B101EW03 V0 document version : 0.1Note 4: Measurement methodThe LCD module should be stabilized at given temperature for 30 minutes to avoid abrupt temperature change during measuring. In order to stabilize the luminance, the measurement should be executed after lighting Backlight for 30 minutes in a stable, windless and dark room, and it should be measured in the center of screen.Note 5： Definition of Average Luminance of White (Y L ):Measure the luminance of gray level 63 at 5 points ，Y L = [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5 L (x) is corresponding to the luminance of the point X at Figure in Note (1).Note 6： Definition of contrast ratio:Contrast ratio is calculated with the following formula.Contrast ratio (CR)=Brightness on the “White” state Brightness on the “Black” state9 of 31B101EW03 V0 document version : 0.1 Note 7： Definition of Cross Talk (CT)CT = | Y B – Y A | / Y A × 100 (%) WhereY A = Luminance of measured location without gray level 0 pattern (cd/m 2) Y B = Luminance of measured location with gray level 0 pattern (cd/m 2)Note 8: Definition of response time:The output signals of BM-7 or equivalent are measured when the input signals are changed from “Black” to “White” (falling time) and from “White” to “Black” (rising time), respectively. The response time interval between the10% and 90% of amplitudes. Refer to figure as below.10 of 31B101EW03 V0 document version : 0.1Note 9. Definition of viewing angleViewing angle is the measurement of contrast ratio ≧10, at the screen center, over a 180° horizontal and180° vertical range (off-normal viewing angles). The 180° viewing angle range is broken down as follows; 90° (θ) horizontal left and right and 90° (Φ) vertical, high (up) and low (down). The measurement direction is typically perpendicular to the display surface with the screen rotated about its center to develop the desired measurement viewing angle.11 of 31B101EW03 V0 document version : 0.1 3. Functional Block DiagramThe following diagram shows the functional block of the 10.1 inches wide Color TFT/LCD 40 Pin (One ch/connector Module). TBD12 of 31B101EW03 V0 document version : 0.1 4. Absolute Maximum RatingsAn absolute maximum rating of the module is as following:4.1 Absolute Ratings of TFT LCD ModuleItemSymbol Min Max Unit Conditions Logic/LCD Drive VoltageVin-0.3+4.0[Volt]Note 1,213 of 31B101EW03 V0 document version : 0.1 5. Electrical characteristics 5.1 TFT LCD Module5.1.1 Power SpecificationInput power specifications are as follows;SymbleParameterMinTypMaxUnit sNoteVDD Logic/LCD Drive Voltage 3.0 3.3 3.6 [Volt]PDD VDD Power - -1.0[Watt ]Note 1/2 IDD IDD Current - 257.6 303.03 [mA]Note 1/2 IRush Inrush Current - -1500 [mA] Note 3VDDrpAllowableLogic/LCD Drive Ripple Voltage--100[mV] p-pNote 1 : Maximum Measurement Condition ：Black Pattern Note 2：Typical Measurement Condition: Mosaic Pattern Note 3：Measure ConditionVin rising time0V3.3V14 of 31B101EW01 V2 document version : 2.1 5.1.2 Signal Electrical CharacteristicsInput signals shall be low or High-impedance state when VDD is off.It is recommended to refer the specifications of SN75LVDS82DGG (Texas Instruments) in detail.Signal electrical characteristics are as follows;Parameter ConditionMin MaxUnit V th Differential Input High Threshold (Vcm=+1.2V) 100[mV] V tl Differential Input Low Threshold (Vcm=+1.2V) -100 -[mV] V ID Differential Input Voltage100 600 [mV] V cmDifferential InputCommon Mode Voltage1.1251.375[V]Note: LVDS Signal Waveform15 of 31B101EW01 V2 document version : 2.1 5.2 Backlight Unit5.2.1 LED characteristicsParameter Symbol Min Typ Max Units Condition- - 2.1 [Watt] (Ta=25℃), Note 1Type I , V in =12VBacklight Power ConsumptionPLEDLED Life-Time N/A 12,000--Hour (Ta=25℃), Note 2I F =18.5 mANote 1: Calculator value for reference P LED = V F (Normal Distribution) * I F (Normal Distribution) / Efficiency Note 2: The LED life-time define as the estimated time to 50% degradation of initial luminousNote 3: This panel will support lower duty ratio at PWM conditional frequency. The PWM frequency constrainbetween 100 Hz to 300 Hz and a same typical 200Hz. The duty ratio support from 5% to 100%.5.2.2 Backlight input signal characteristicsParameter Symbol Min Typ Max Units Remark6.0 12.0 21.0 [Volt] Type I, Note 1LED Power Supply VLED 4.5 5 5.5 [Volt] Type II, Note 1LED Enable Input High Level 2.5 - 5.5 [Volt] LED Enable Input Low LevelVLED_EN- - 0.8 [Volt] PWM Logic Input High Level2.5 - 5.5 [Volt] PWM Logic Input Low LevelVPWM_EN-- 0.8 [Volt] PWM Input Frequency FPWM 100 - 1K HzPWM Duty Ratio Duty 1 -- 100 % PWM Frequency <5K HzPWM Duty RatioDuty15--100%PWM Frequency ≧500 HzNote 1: Type I and II is an independent of design parameter. It should be separated from system design.6. Signal Characteristic6.1 Pixel Format ImageFollowing figure shows the relationship of the input signals and LCD pixel format.6.2 The input data formatSignal Name DescriptionR5 R4 R3 R2 R1 R0 Red Data 5 (MSB)Red Data 4Red Data 3Red Data 2Red Data 1Red Data 0 (LSB)Red-pixel DataRed-pixel DataEach red pixel's brightness data consists ofthese 6 bits pixel data.G5 G4 G3 G2 G1 G0 Green Data 5 (MSB)Green Data 4Green Data 3Green Data 2Green Data 1Green Data 0 (LSB)Green-pixel DataGreen-pixel DataEach green pixel's brightness data consists ofthese 6 bits pixel data.B5 B4 B3 B2 B1 B0 Blue Data 5 (MSB)Blue Data 4Blue Data 3Blue Data 2Blue Data 1Blue Data 0 (LSB)Blue-pixel DataBlue-pixel DataEach blue pixel's brightness data consists ofthese 6 bits pixel data.RxCLKIN Data Clock The typical frequency is 54.2MHZ.The signal isused to strobe the pixel data and DE signals. Allpixel data shall be valid at the falling edge whenthe DE signal is high.DE Display Timing This signal is strobed at the falling edge ofRxCLKIN. When the signal is high, the pixeldata shall be valid to be displayed.VS Vertical Sync The signal is synchronized to RxCLKIN .HS Horizontal Sync The signal is synchronized to RxCLKIN .Note: Output signals from any system shall be low or High-impedance state when VDD is off.6.3 Integration Interface Requirement6.3.1 Connector DescriptionPhysical interface is described as for the connector on module.These connectors are capable of accommodating the following signals and will be following components.Connector Name / Designation For Signal ConnectorManufacturer TycoType / Part Number Tyco 2069716-3(I-PEX 20455-040E-12 compatibleMating Housing/Part Number IPEX 20453-040T-11 or compatible6.3.2 Pin AssignmentLVDS is a differential signal technology for LCD interface and high speed data transfer device.Pin Signal Description1 NC No connect2 Vdd Logic supply, +3.3V3 Vdd Logic supply, +3.3V4 NC No connect, Aging for AUO5 Sclk I2C series input clock6 Sdat I2C data I/O7 NC No connect8 Rin0- Receiver signal of LVDS CH0(-)9 Rin0+ Receiver signal of LVDS CH0(+)10 GND Ground11 Rin1- Receiver signal of LVDS CH1(-)12 Rin1+ Receiver signal of LVDS CH1(+)13 GND Ground14 Rin2- Receiver signal of LVDS CH2(-)15 Rin2+ Receiver signal of LVDS CH2(+)16 GND Ground17 Rclk- Receiver signal of LVDS Clock (-)18 Rclk+ Receiver signal of LVDS Clock (+)19 GND Ground20 Rin3- Receiver signal of LVDS CH3(-)21 Rin3+ Receiver signal of LVDS CH3(+)22 GND Ground23 NC No connect24 NC No connect25 GND Ground26 NC No connect27 Color(EN) Color Enhancement enable (1=on, 0=off)28 CABC(EN) Content BL control enable (1=on, 0=off)29 LED_PWM(I) PWM signal to TCON30 LED_PWM(O) PWM signal from TCON31 NC No connect32 LED_Cat_1 LED cathode33 LED_Cat_2 LED cathode34 LED_Cat_3 LED cathode35 LED_Cat_4 LED cathode36 LED_Cat_5 LED cathode37 LED_Cat_6 LED cathode38 NC No connect39 LED_Anode LED Anode40 LED_Anode LED AnodeLVDS is a differential signal technology for LCD interface and high speed data transfer device.6.4 Interface Timing6.4.1 Timing CharacteristicsBasically, interface timings should match the 1280 x 720 /60Hz manufacturing guide line timing.Parameter SymbolMin. Typ. Max. Unit Frame Rate - - 60 Hz Clock frequency 1/ T Clock - 68.9 80 MHzPeriod T V 808 816 1023 Active T VD 800 800 800 Vertical SectionBlanking T VB 8 16 223 T Line Period T H 1310 1408 2047 Active T HD 1280 1280 1280 Horizontal SectionBlankingT HB30128767T ClockNote : DE mode only6.4.2 Timing diagram6.5 Power Sequence6.5.1 Panel Power SequenceVDD power and LED on/off sequence is as follows. Interface signals are also shown in the chart. Signals from any system shall be Hi-Z state or low level when VDD is off..Note 1：If T4<200ms，the display garbage may occur. We suggest T4>200ms to avoid the display garbage.Note 2：If T1 or T2 <0.5 ms, the inrush current may cause the damage of fuse. If the T1 or T12 <0.5ms, the inrush current I2 t is under typical melt of fuse Spec., there’s no above mentioned problem.7. Panel Reliability Test7.1 Vibration TestTest Spec:Test method: Non-OperationAcceleration: 1.5 GFrequency: 10 - 500Hz RandomSweep: 30 Minutes each Axis (X, Y, Z)7.2 Shock TestTest Spec:Test method: Non-OperationAcceleration: 220 G , Half sine waveActive time: 2 msPulse: X,Y,Z .one time for each side7.3 Reliability TestItems Required Condition Note TemperatureHumidity BiasTa= 40℃, 90%RH, 300hHigh TemperatureOperationTa= 50℃, Dry, 300hLow TemperatureOperationTa= 0℃, 300hHigh TemperatureStorageTa= 60℃, 35%RH, 300hLow TemperatureStorageTa= -20℃, 50%RH, 250hThermal ShockTestTa=-20℃to 60℃, Duration at 30 min, 100 cyclesESD Contact : ±8 KVAir : ±15 KVNote 1Note1: According to EN 61000-4-2 , ESD class B: Some performance degradation allowed. No data lost . Self-recoverable. No hardware failures.Remark: MTBF (Excluding the LED): 30,000 hours with a confidence level 90%23 of 31B101EW01 V2document version : 2.124 of 31B101EW01 V2 document version : 2.1Back View9. Shipping and Package 9.1 Shipping Label FormatLabel location9.2 Carton Package9.3 Shipping package of palletizing sequence10. Appendix10.1 EDID descriptionAddress FUNCTION Value Value Value Note HEX HEX BIN DEC00 Header 00 00000000 001 FF 11111111 25502 FF 11111111 25503 FF 11111111 25504 FF 11111111 25505 FF 11111111 25506 FF 11111111 25507 00 00000000 008 EISA Manuf. Code LSB 06 00000110 609 Compressed ASCII AF 10101111 1750A Product Code D4 11010100 2120B hex, LSB first 40 01000000 640C 32-bit ser # 00 00000000 00D 00 00000000 00E 00 00000000 00F 00 00000000 010 Week of manufacture 01 00000001 111 Year of manufacture 14 00010100 2012 EDID Structure Ver. 01 00000001 113 EDID revision # 03 00000011 314 Video input def. (digital I/P, non-TMDS, CRGB) 80 10000000 12815 Max H image size (rounded to cm) 17 00010111 2316 Max V image size (rounded to cm) 0F 00001111 1517 Display Gamma (=(gamma*100)-100) 78 01111000 12018 Feature support (no DPMS, Active OFF, RGB,tmg Blk#1) 0A 00001010 1019 Red/green low bits (Lower 2:2:2:2 bits) 61 01100001 97 1A Blue/white low bits (Lower 2:2:2:2 bits) 75 01110101 117 1B Red x (Upper 8 bits) 95 10010101 149 1C Red y/ highER 8 bits 55 01010101 85 1D Green x 54 01010100 84 1E Green y 8C 10001100 140 1F Blue x 27 00100111 3920 Blue y 22 00100010 3421 White x 50 01010000 8022 White y 54 01010100 8423 Established timing 1 00 00000000 024 Established timing 2 00 00000000 026 Standard timing #1 01 00000001 127 01 00000001 128 Standard timing #2 01 00000001 129 01 00000001 1 2A Standard timing #3 01 00000001 1 2B 01 00000001 1 2C Standard timing #4 01 00000001 1 2D 01 00000001 1 2E Standard timing #5 01 00000001 1 2F 01 00000001 130 Standard timing #6 01 00000001 131 01 00000001 132 Standard timing #7 01 00000001 133 01 00000001 134 Standard timing #8 01 00000001 135 01 00000001 136 Pixel Clock/10000 LSB 12 00010010 1837 Pixel Clock/10000 USB 1B 00011011 2738 Horz active Lower 8bits 00 00000000 039 Horz blanking Lower 8bits 94 10010100 148 3A HorzAct:HorzBlnk Upper 4:4 bits 50 01010000 80 3B Vertical Active Lower 8bits 20 00100000 32 3C Vertical Blanking Lower 8bits 08 00001000 8 3D Vert Act : Vertical Blanking (upper 4:4 bit) 30 00110000 48 3E HorzSync. Offset 8 00001000 8 3F HorzSync.Width A 00001010 1040 VertSync.Offset : VertSync.Width 31 00110001 4941 Horz&Vert Sync Offset/Width Upper 2bits 00 00000000 042 Horizontal Image Size Lower 8bits E5 11100101 22943 Vertical Image Size Lower 8bits 95 10010101 14944 Horizontal & Vertical Image Size (upper 4:4 bits) 00 00000000 045 Horizontal Border (zero for internal LCD) 00 00000000 046 Vertical Border (zero for internal LCD) 00 00000000 047Signal (non-intr, norm, no stero, sep sync, negpol) 18 00011000 2448 Detailed timing/monitor 00 00000000 049 descriptor #2 00 00000000 0 4A 00 00000000 0 4B 0F 00001111 15 4C 00 00000000 0 4D 00 00000000 0 4E 00 00000000 0 4F 00 00000000 050 00 00000000 051 00 00000000 052 00 00000000 053 00 00000000 054 00 00000000 055 00 00000000 056 00 00000000 057 00 00000000 058 00 00000000 059 20 00100000 325A Detailed timing/monitor 00 00000000 05B descriptor #3 00 00000000 05C 00 00000000 05D FE 11111110 2545E 00 00000000 05F Manufacture 41 01000001 65 A60 Manufacture 55 01010101 85 U61 Manufacture 4F 01001111 79 O62 0A 00001010 1063 20 00100000 3264 20 00100000 3265 20 00100000 3266 20 00100000 3267 20 00100000 3268 20 00100000 3269 20 00100000 326A 20 00100000 326B 20 00100000 326C Detailed timing/monitor 00 00000000 06D descriptor #4 00 00000000 06E 00 00000000 06F FE 11111110 25470 00 00000000 071 Manufacture P/N 42 01000010 66 B72 Manufacture P/N 31 00110001 49 173 Manufacture P/N 30 00110000 48 074 Manufacture P/N 31 00110001 49 175 Manufacture P/N 45 01000101 69 E76 Manufacture P/N 57 01010111 87 W77 Manufacture P/N 30 00110000 48 078 Manufacture P/N 34 00110100 52 479 Manufacture P/N 20 00100000 3231 of 31AU OPTRONICS CORPORATIONProduct SpecificationB101EW01 V2 document version : 2.1 7B Manufacture P/N30 00110000 48 0 7C 20 00100000 32 7D0A 00001010 10 7E Extension Flag 00 00000000 0 7FChecksum430100001167SUM5888。

Internship Training Report

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Contact pushor Contact blade
Dut socket
TESTER
Loadboard
Handler
TEST HEAD
Interface
Handler 必須與 tester 相結合(此動作叫 mount 機)及接上interfacer才能測試, 動作為handler 的手臂將DUT放入socket 此時 contact pushor下壓, 使 DUT的腳正確與 socket 接觸後, 送出 start 訊號, 透過 interface 給 tester, 測完後, tester 送回 binning 及EOT 訊號; handler做分類動作。客戶產品的尺寸及腳數不同, handler 提供不同的模具 (kits)供使用, 如下請參閱:
Finished Goods Inventory
Assembly
Program
Materials Fab
sort
Die Bank
Assembly
Final Test
Bin Inventory
Program Development
Probe Die Splits
ASET
Final Test Burn In Lead Scan
PMU Connectio n High Speed Current Comparators
Sense
+ I High compare 0.0V Force + I Low compare Measure VREF 0.001nA VOLTAGE CURRENT VOLTAGE CURRENT
Iout Comparators
F1
K1 DUT

MAX232 5V 双通道 RS-232 驱动接收器说明书

FEATURES●Output voltage levels are compatible with input levelsof CMOS and TTL integrated circuits●Meets All EIA/TIA-232E and V.28/V.24 Specifications ●Supply voltage range from 4.5 to 5.5V●Low input current: 1.0µA at 25°C●Output current 24mA●Tolerable value of static potential not less than 2kV ●Available in DIP-16 PackageAPPLICATIONS●Portable Computers●Battery-Powered RS-232 Systems●Interface Translation●Low-Power Modems●TerminalsDIP-16ORDERING INFORMATIONDevice Package MAX232EN DIP-16 * Refer to the ordering information for the details.DESCRIPTIONThe MAX232 is a dual driver/receiver of RS-232 standard with a single supply voltage and bipolar output voltage of the transmitter formed by a built-In voltage multiplying generator on four 1.0µF external capacitors, designed for use in state-of-the-art high performance computing systems, high-speed electronic devices with high reliability of information exchange between remote objects.Input voltage levels are compatible with standard CMOS and TTL levels.ABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL MIN. MAX. UNIT Supply Voltage V CC-0.3 6.0 V Transmitter High Output Voltage V+V CC-0.3 14 V Transmitter Low Output Voltage V--14 0.3 V Transmitter Input Voltage V TIN-0.3 V++0.3 V Receiver Input Voltage V RIN-30 30 V Voltage Applied to Transmitter Output V TOUT V--0.3 V++0.3 V Voltage Applied to Receiver Output V ROUT-0.3 V CC+0.3 V Storage Temperature Range T STG-65 150 °CHTC1RECOMMENDED OPERATING CONDITIONSPARAMETER SYMBOL MIN. MAX. UNIT Supply Voltage V CC 4.5 5.5 V Transmitter Input Voltage V TIN0 V CC VReceiver Input Voltage V RIN-30 30VOutput Current of Transmitter Short Circuit I SC- ±60 mA Ambient Temperature Range T A-40 +85 °CORDERING INFORMATIONPackage Oder No. Package Marking Compliance Supplied AsDIP-16 MAX232EN MAX232E RoHS, Green TubeHTC2PIN CONFIGURATIONC1+V+C1-C2+C2-V-T2OUT R2INVCCGNDT1OUTR1INR1OUTT1INT2INR2OUT DIP-16 PKGPIN DESCRIPTIONPin No. Pin Name Pin Description1 C1+ Terminal for Positive Charge-Pump C1 Capacitor2 V+ Positive Voltage Generated by the Charge-Pump3 C1- Terminal for Negative Charge-Pump C1 Capacitor4 C2+ Terminal for Positive Charge-Pump C2 Capacitor5 C2- Terminal for Negative Charge-Pump C2 Capacitor6 V- Negative Voltage Generated by the Charge-Pump7 T2OUT RS-232 Driver Output (Levels RS-232)8 R2IN RS-232 Receiver Input (Levels RS-232)9 R2OUT RS-232 Receiver Output (Levels TTL/CMOS)10 T2IN RS-232 Driver Input (Levels TTL/CMOS)11 T1IN RS-232 Driver Input (Levels TTL/CMOS)12 R1OUT RS-232 Receiver Output (Levels TTL/CMOS)13 R1IN RS-232 Receiver Input (Levels RS-232)14 T1OUT RS-232 Driver Output (Levels RS-232)15 GND Ground16 VCC Supply Voltage InputHTC3TYPICAL APPLICATION CIRCUITFUNCTION TABLEINPUT (RIN, TIN)OUTPUT (ROUT, TOUT)L (Low Level) H (High Level)H (High Level) L (Low Level)HTC 4ELECTRICAL CHARACTERISTICS(Limits in standard typeface are for T A=25°C, and the limits in boldface type apply over full operating temperature range.) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNITSupply Current I CC V CC = 5.5VV IL = 0V- -10.014.0mAReceiver ParametersHysteresis Voltage V h V CC = 5.0V 0.20.2-0.91.0VOn (Operation) Voltage V on V O≤ 0.1V, I OL≤ 20µA - - 2.42.3VOff (Dropout) Voltage V off V O≥ V CC - 0.1VI OH≤ -20µA0.80.9- - VOutput Low Voltage V OL I L = 3.2mA, V CC = 4.5V,V IH = 2.4V- -0.30.4VOutput High Voltage V OH I OH = -1.0mA, V CC = 4.5V,V IL = 0.8V3.63.5- - VInput Resistance R I V CC = 5.0V 3.03.0-7.07.0kΩTransmitter ParametersOutput Low Voltage V OL V CC = 4.5V, V IH = 2.0V,R L = 3.0kΩ- --5.2-5.0VOutput High Voltage V OH V CC = 4.5V, V IL = 0.8V,R L = 3.0kΩ5.25.0- - VInput Low Current I IL V CC = 5.5V, V IL = 0V - --1.0-10.0µAInput High Current I IH V CC = 5.5V, V IH = V CC- -1.010.0µASpeed Of Output Front Charge SR V CC = 5.0V, C L = 50 - 1000pF,R L = 3.0 - 7.0kΩ3.02.7-3027V/µsOutput Resistance R O V CC = V+ = V- = 0VV O = ±2V350300- - ΩShort Circuit Output Current I SC V CC = 5.5VV O = 0VV I = V CC- --50-60mAV I = 0 - -5060Speed Of Information Transmission STV CC = 4.5V, C L = 1000pF,R L = 3.0kΩ, t W = 7µs (forextreme, t W = 8µs)140120- - kbit/sDynamic ParametersSignal Propagation Delay Time When Switching On (Off)t PHLR(t PLHR)V CC = 4.5V, C L = 150pF,V IL = 0V, V IH = 3.0V,t LH = t HL≤ 10ns- -9.710.0µsSignal Propagation Delay Time When Switching On (Off)t PHLT(t PLHT)V CC = 4.5V, C L = 2500pF,V IL = 0V, V IH = 3.0V,R L = 3kΩ, t LH = t HL≤ 10ns- -5.06.0µsHTC5TIMING DIAGRAM0VV OHV OLFigure 1. t PHL and t PLH waveforms of Receiver0VV OHV OLFigure 2. t PHL and t PLH waveforms of Transmitter6HTCFigure 3. t SLH and t SHL waveforms of Transmitter7HTCREVISION NOTICEThe description in this data s heet is subject to change without any notice to describe its electrical characteristics properly.8HTC。

按键寿命测试

WORK INSTRUCTIONS TITLE 按鍵寿命试验Revision HistoryDoc. Rev. 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Description New Release Update all Update Item 6 Update all Add Item 6.1, 6.3.1 Update Item 3, 5.3, 6.1, 6.3 Update Title & Item 1, 5, 6.3 Update Item 6.3.1 Update Item 6.3.1, 6.3.2 Update Item 6.3.1, 6.3.2 Page All All P 2~3 All P3 All All P3 P3 P 3,4 Effective Date Dec. 07, 94 Nov. 14, 95 Mar. 25, 98 Sep. 01, 98 Jul. 05, 99 May. 30, 02 Jul. 01, 03 Jun. 30, 05 Sep. 14, 05 Oct. 14, 06Distribution ListDepartment Sourcing – QA ADM (Administration) DC (Document Control) ISMD (International Sales & Market Development) PCT (Procurement) PMGT (Program Mgt) PUR (Purchasing) R&D Shipping Sourcing Others : QA-LAB HK DG Department Comp-LAB DEE DEM IE PA/GA PE PMC PME PQC PRE PROD DG 1 1 Department QA QA- Training SMD IE SMD PROD SQM SQM (SI) Store TE SCM KPO R&D SZ DG 111111ApprovalLocation of Issued Dept: Sign Prepared by: Checked by (If): Approved by: HK / DG / SZ Name Jeanne He Ryan Fan W.B. Lee Title QA Sr. Technician QA Engineer QA Manager Date (M/D/Y)Revision Status1 6 11 16 21 26 31 36 [10.0] [ ] [ ] [ ] [ ] [ ] [ ] [ ] 2 7 12 17 22 27 32 37 [10.0] [ ] [ ] [ ] [ ] [ ] [ ] [ ] 3 8 13 18 23 28 33 38(Page [Page Rev.])Stamp5 10 15 20 25 30 35 40 [ [ [ [ [ [ [ [ ] ] ] ] ] ] ] ][10.0] [ ] [ ] [ ] [ ] [ ] [ ] [ ]4 9 14 19 24 29 34 39[10.0] [ ] [ ] [ ] [ ] [ ] [ ] [ ]REF. NO.WQA9022PAGE REV.10.0PAGE1 of 4WORK INSTRUCTIONS TITLE 按鍵寿命试验1. 目的 1.1 1.2 制定规范的操作指引,提供试验人员进行按鍵寿命试验. 模拟用户日常使用电话的情形, 试验在不同部位的按鍵寿命情況 .2.范围适用于所有电话机成品 (除客户特殊要求外) 以及物料 .3.参考文件 3.1 WQA9151-- Reliability Test Items for North American Vtech and AT&T Brand Products. WQA9152-- Reliability Test Items for Vtech Europe Products.3.2 定义无.4.5.责任 5.1 5.2 试验申请者提供试验功能正常的样品,并填写试验申请单. 实验室负责人负责完成所有的可靠性测试, 并以 E - Mail 形式将试验结果通知 Project Leader 和申请者 , 试验完毕后发出的正式的报告 , 并将样品退还申请人. 对于 Failure 的项目 , 实验室负责人要在當天内通知相关负责人员 , 并协助分析 Fail 的原因 . 相关部门在必要时提供改善行动 , 并且送改善后的 Sample 到实验室 , 重做测试,以确认改善行动是否有效.5.35.46.程序 6.1 冲头的调校及安装(按鍵壽命測試 )REF. NO.WQA9022PAGE REV.10.0PAGE2 of 4WORK INSTRUCTIONS TITLE 按鍵寿命试验6.1.1 逐一调校冲头上的弹簧行程,用弹力计测量,使之符合按压距离 3.0±0.2mm 时压力为 450~600g. 弹力计 450~600g 3mm 6.1.2 将调校好的冲头正确地安装在冲压机上调校螺丝冲头6.1.3 6.2測試頻率: 50~70 次 / 1 分鐘检查样品机的所有按键外观装配应良好和功能正常 ,然后将样品机正确地安装在冲压机的支架上. 做按鍵寿命试验 , VTECH 标准要求如下 : 6.3.1 机械寿命次数种類數字按鍵每次使用經常使用經常使用偶然使用較少使用 6.3.2 具体例子 “0 ~ 9” 數字鍵開 / 關机鍵 ;Menu 鍵免提按鍵; 音量按鍵; “*” 及 “#” 鍵; ITAD 鍵; Delete 鍵 Radio 鍵 PAGE, Memory dial, Mute, Hold, Redial, Flash, Conference, Intercom" 鍵 “PROGRAM” 鍵要求次數美洲机歐洲机 100,000 200,000 75,000 100,000 50,000 30,000 10,000 5,000 50,000 30,000 10,000 5,0006.3试验过程中需每一万次停下來檢查一次 ,如有问题需详细记录 .REF. NO.WQA9022PAGE REV.10.0PAGE3 of 4WORK INSTRUCTIONS TITLE 按鍵寿命试验6.3.3 试验过程中检查细节功能, 卡鍵, 触点导电层烂或脱落, Keypad 烂或裂等.试验项目 Keypad7.试验要求 7.1 7.2 試驗中和試驗后按鍵功能正常. 試驗中和試驗后按鍵有任何的机械損坏都是不可以接受的.REF. NO.WQA9022PAGE REV.10.0PAGE4 of 4。

副本V系列信赖性测试标准

Prepare 50 ℃ DI water,put the test specimen in the bath for 3 hrs,then check the film condition.
ASTM D1654、ASTM B117-97； 35℃，5％ NaCl， spray 96hr， with adhesion test and cosmetic check.
test environment: temperature 20± 2℃,humidity 55± 5% tape speed:1 second 50mm,60second 3000mm. fixed load:RCA system 175gf,3 second ON/1 second OFF. Special paper tape:broad #60 cloth. Leave test samples under 25° for 24 hrs. Make the cross-cut scratch C the paint surface by cutter. Stick a specified tape (3M Scotch 610) on the scratched area completely (release all air out). Within 90± 30s of application,remove the type by seizing the free end and rapidly(not jerked) back upon itself at as close to an angle of 180° possible, moer as than 3 times.
Use a fluorescent UV/condensation Apparatus to test a specimen for 100 hrs and then check the film condition.Please refer to ASTM D4587,TABLE1,NO:4.

R7731A PWM 控制器商品说明书

R7731A-10 August 2011General DescriptionThe R7731A is a high-performance, low cost, low start-up current and current mode PWM controller with burst triple mode to support green mode power saving operation. The R7731A integrates functions of soft start, Under Voltage LockOut (UVLO), Leading Edge Blanking (LEB), Over Temperature Protection (OTP) and internal slope compensation. It provides the users a superior AC/DC power application of higher efficiency, low external component counts and lower cost solution.To protect the external power MOSFET from being damaged by supply over voltage, the R7731A output driver is clamped at 12V. Furthermore, R7731A features fruitful protections like Over Load Protection (OLP) and Over Voltage Protection (OVP) to eliminate the external protection circuits and provide reliable operation. R7731A is available in SOT-23-6 and DIP-8 packages.Burst Triple Mode PWM Flyback ControllerFeaturesz Very Low Start-up Current (<30μA)z 10/14V UVLOz Soft Start Function z Current Mode Controlz Jittering Switching Frequency z Internal Leading Edge Blanking z Built-in Slope Compensationz Burst Triple Mode PWM for Green-Mode z Cycle-by-Cycle Current Limit z Feedback Open Protection z Over Voltage Protectionz Over Temperature Protection z Over Load Protectionz Soft Driving for Reducing EMI z Driver Capability ±200mA z High Noise ImmunityzOpto-Coupler Short ProtectionzRoHS Compliant and Halogen FreeApplicationsz Adaptor and Battery Charger z ATX Standby Power z Set-Top Box (STB)z DVD and CD(R)z TV/Monitor Standby Power zPC PeripheralsOrdering InformationR7731AG : Green (Halogen Free and Pb Free)Note :Richtek products are :` RoHS compliant and compatible with the current require-ments of IPC/JEDEC J-STD-020.` Suitable for use in SnPb or Pb-free soldering processes.Marking InformationIDP= : Product Code W : Date CodeR7731AGN : Product Number YMDNN : Date CodeR7731AGERichTek R7731A GNYMDNNPin Configurations(TOP VIEW)SOT-23-6DIP-8GATE VDD NC CSRTNCCOMP GND VO+VO-* : See Application InformationR7731A-10 August 2011Function Block DiagramVDDRTGATEGNDAbsolute Maximum Ratings(Note 1)z Supply Input Voltage, V DD-------------------------------------------------------------------------------------------------−0.3V to 30V z GATE Pin----------------------------------------------------------------------------------------------------------------------−0.3V to 20V z RT, COMP, CS Pin----------------------------------------------------------------------------------------------------------−0.3V to 6.5V z I DD-------------------------------------------------------------------------------------------------------------------------------10mAz Power Dissipation, P D @ T A = 25°CSOT-23-6----------------------------------------------------------------------------------------------------------------------0.4WDIP-8---------------------------------------------------------------------------------------------------------------------------0.714Wz Package Thermal Resistance (Note 2)SOT-23-6, θJA-----------------------------------------------------------------------------------------------------------------250°C/WDIP-8, θJA----------------------------------------------------------------------------------------------------------------------140°C/Wz Junction T emperature-------------------------------------------------------------------------------------------------------150°Cz Lead Temperature (Soldering, 10 sec.)---------------------------------------------------------------------------------260°Cz Storage T emperature Range----------------------------------------------------------------------------------------------−65°C to 150°C z ESD Susceptibility (Note 3)HBM (Human Body Mode)------------------------------------------------------------------------------------------------4kVMM (Machine Mode)--------------------------------------------------------------------------------------------------------250V Recommended Operating Conditions (Note 4)z Supply Input Voltage, V DD-------------------------------------------------------------------------------------------------12V to 25Vz Operating Frequency-------------------------------------------------------------------------------------------------------50k to 130kHz z Junction T emperature Range----------------------------------------------------------------------------------------------−40°C to 125°C z Ambient T emperature Range----------------------------------------------------------------------------------------------−40°C to 85°CElectrical CharacteristicsTo be continuedNote 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective single layer thermal conductivity test board of JEDEC 51-3 thermal measurement standard.Note 3. Devices are ESD sensitive. Handling precaution is recommended.Note 4. The device is not guaranteed to function outside its operating conditions.Note 5. Guaranteed by design.R7731A-10 August D MAX vs. Temperature7071727374757677787980-40-2020406080100120Temperature (°C)D M A X (%)Typical Operating CharacteristicsV TH vs. Temperature9101112131415-40-25-105203550658095110125Temperature (°C)V D D (V )I DD_ST vs. Temperature10121416182022242628-40-1510356085110135Temperature (°C)I D D _S T (µA)I DD_OP vs. Temperature1.251.301.351.401.451.501.55-40-1510356085110135Temperature (°C)I D D _O P (m A )f OSC vs. Temperature57585960616263-40-1510356085110135Temperature (°C)f O S C (k H z )V COMP vs. Temperature5.405.445.485.525.565.60-40-2020406080100120Temperature (°C)V C O M PR7731A-10 August 2011V CLAMP vs. V DD78910111213111213141516171819202122V DD (V)V C L A M P (V)V GATE_OFF vs. V DD400425450475500525550575600111213141516171819202122V DD (V)V G A T E _O F F (m V)I SUPPLY vs. Temperature0.300.350.400.450.50-40-2020406080100120Temperature (°C)I S U P P L Y (m A)I SUPPLY vs. V DD0.4080.4100.4120.4140.4160.4180.4200.4220.4240.426111213141516171819202122V DD (V)I S U P P L Y (m A)V CLAMP vs. Temperature10.010.511.011.512.012.513.0-40-1510356085110135Temperature (°C)V C L A M P (V)GATE vs. Temperature50100150200250300350-40-25-105203550658095110125Temperature (°C)G A T E (n s )V CSTH vs. Temperature0.8000.8150.8300.8450.8600.8750.890-40-25-105203550658095110125Temperature (°C)V C S T H (V )R7731A-10 August 2011Application InformationUVLOUnder Voltage LockOut (UVLO) block is to ensure V DD has reached proper operation voltage before we enable the whole IC blocks. To provide better temperature coefficient and precise UVLO threshold voltage, the reference voltage of hysteresis voltage (10V / 14V) is from band-gap block directly. By this way, R7731A can operate more reliable in different environments.The maximum start-up current (30μA) is only for leakage current of IC at UVLO(on)-0.1V. The external al-capacitor on VDD may have 5 to 6μA extra leakage current. So designed start-up current of the system should exceed 36μA or more and IC can start up normally. In addition,designed start-up current of system should be less than 380μA, and IC can work normally at hiccup mode.Jittering OscillatorFor better EMI performance, R7731A will operate the system with ±6% frequency deviation around setting frequency.To guarantee precise frequency, it is trimmed to 5%tolerance. It also generates slope compensation saw-tooth,75% maximum duty cycle pulse and overload protection slope. By adjusting resistor of RT pin according to the following formula :Figure 1. CompetitorV CSV OUTV CS(500mV/Div)V OUT (2V/Div))(k R 6500(kHz)f T OSCΩ=It can typically operate between 50kHz to 130kHz. Note that RT pin can 't be short or open otherwise oscillator will not operate.Built-in Slope CompensationTo reduce component counts, slope compensation is implemented by internal built-in saw-tooth. Since it 's built-in, it 's compromised between loop gain and sub-harmonic reduction. In general design, it can cancel sub-harmonic to 90Vac.Leading Edge Blanking (LEB)MOSFET C OSS , secondary rectifier reverse recovery current and gate driver sourcing current comprise initial current spike. The spike will seriously disturb current mode operation especially at light load and high line. R7731A provides built-in 420ns LEB to guarantee proper operation in diverse design.Noise ImmunityCurrent mode controller is very sensitive to noise. R7731A takes the advantages of Richtek long term experience in designing high noise immunity current mode circuit and layout. Also, we amplify current sense signal to compare with feedback signal instead of dividing feedback signal.All the effort is to provide clean and reliable current mode operation.Soft-StartDuring initial power on, especially at high line, current spike is kind of unlimited by current limit. Therefore,besides cycle-by-cycle current limiting, R7731A still provides soft-start function. It effectively suppresses the start-up current spike. As shown in the Figure 1 and Figure 2, the start-up V CS is about 0.3V lower than competitor. The typical soft-start duration is 4ms (R T =100k Ω). Again, this will provide more reliable operation and possibility to use smaller current rating power MOSFET .Gate DriverA totem pole gate driver is fine tuned to meet both EMI and efficiency requirement in low power application. An internal pull low circuit is activated after pretty low V DD to prevent external MOSFET from accidentally turning on during UVLO.Burst Triple ModeTo fulfill green mode requirement, there are 3 operation modes in R7731A. Please also refer to Figure 3 for details.`PWM ModeFor most of load condition, the circuit will run at traditional PWM current mode.`Burst ModeDuring light load, switching loss will dominate the power efficien cy calculation. This mode is to cut switching loss. As shown in Figure 3, when the output load gets light, feedback signal drops and touches V BURL (Typical value is 1.75V). Clock signal will be blanked and system ceases to switching. After V OUT drops and feedback signal goes back to V BURH (1.8V, typically), switching will be resumed. Burst mode so far is widely used in low power application because it 's simple, reliable and will not have any patent infringement issue.`VDD Holdup ModeWhen the V DD drops down to V DD turn off threshold voltage, the system will be shut down. During shut down period, controller does nothing to any load change and might cause V OUT down. To avoid this, when V DD drops to a setting threshold, 11V, the hysteresis comparator will bypass PWM and burst mode loop and force switching at a very lo w level to supply energy to VDD pin. The designed value is 11.25V with 0.5V hysteresis band.Furthermore, VDD holdup mode is only designed to prevent V DD from touching turn off threshold voltage under light load or load transient moment. Relative to burst mode, switching loss will increase on the system at VDD holdup mode, so it is highly recommended that the system should avoid operating at this mode during light load or no load condition, normally.Figure 3. Burst Triple ModeFigure 2. R7731AV CSV OUTV CS(500mV/Div)V OUT (2V/Div)V V V V V V VR7731A-10 August 2011ProtectionR7731A provides fruitful protection functions that intend to protect system from being damaged. All the protection functions can be listed as below :`Cycle-by-Cycle Current LimitThis is a basic but very useful function and it can be implemented easily in current mode controller.`Over Load ProtectionLong time cycle-by-cycle current limit will lead to system thermal stress. To further protect system, system will be shut down after about 4096 clock cycles. it 's about 60ms delay in 67kHz operation. After shutdown, system will resume and behave as hiccup. By proper start-up resistor design, thermal will be averaged to an acceptable level over the ON/OFF cycle of IC. This will last until fault is removed. #It's highly recommended to add a resistor in parallel with the opto-coupler. T o provide sufficient bias current to make TL-431 regulate properly,1.2k Ω resistor is suggested.`Brownout ProtectionDuring heavy load, this will trigger 60ms protection and shut down the system. If it 's in light load condition,system will be shut down after V DD is running low and triggers UVLO.` OVPOutput voltage can be roughly sensed by VDD pin.If the sensed voltage reaches 27V threshold, system will be shut down after 20μs deglitch delay.`Feedback Open and Opto-Coupler ShortThis will trigger OVP or 60ms delay protection. It depends on which one occurs first.`OTPInternal OTP function will protect the controller itself from suffering thermal stress and permanent damage. It stops the system from switching until the temperature is under threshold level. Meanwhile, if V DD reaches V DD turn off threshold voltage, system will hiccup till over temperature condition is gone.Figure 4. R-C Filter on CS PinNegative Voltage Spike on Each PinNegative voltage (< −0.3V) on each pin will cause substrate injection. It leads to controller damage or circuit false trigger. Generally, it happens at CS pin due to negative spike because of improper layout or inductive current sense resistor. Therefore, it is highly recommended to add a R-C filter to avoid CS pin damage, as shown in Figure 4. Proper layout and careful circuit design should be done to guarantee yield rate in mass production.Auxiliary Ground (c)ICGround (d)MOSFET Ground (b)Figure 5. PCB Layout GuideLayout ConsiderationA proper PCB layout can abate unknown noise interference and EMI issue in the switching power supply. Please refer to the guidelines when you want to design PCB layout for switching power supply:The current path (1) from bulk capacitor, transformer,MOSFET, Rcs return to bulk capacitor is a huge high frequency current loop. It must be as short as possible to decrease noise coupling and kept a space to other low voltage traces, such as IC control circuit paths, especially.Besides, the path (2) from RCD snubber circuit to MOSFET is also a high switching loop, too. So keep it as small as possible.It is good for reducing noise, output ripple and EMI issue to separate ground traces of bulk capacitor (a), MOSFET (b), auxiliary winding (c) and IC control circuit (d). Finally,connect them together on bulk capacitor ground (a). The areas of these ground traces should be kept large.Placing bypass capacitor for abating noise on IC is highly recommended. The bypass capacitor should be placed as close to controller as possible.To minimize reflected trace inductance and EMI minimize the area of the loop connecting the secondary winding,the output diode, and the output filter capacitor. In addition,provide sufficient copper area at the anode and cathode terminal of the diode for heatsinking. Provide a larger area at the quiet cathode terminal. A large anode area can increase high-frequency radiated EMI.R7731A-10 August 2011Outline DimensionA1HSOT-23-6 Surface Mount PackageRichtek Technology CorporationHeadquarter5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C.Tel: (8863)5526789 Fax: (8863)5526611Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.Richtek Technology CorporationTaipei Office (Marketing)5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C.Tel: (8862)86672399 Fax: (8862)86672377Email:*********************8-Lead DIP Plastic Package。

羽毛绒浊度测量不确定度评定

36羽毛绒浊度测量不确定度评定高婧，赖淦珠（南京海关纺织工业产品检测中心，江苏无锡 214021）摘要：为反映实验室羽毛羽绒浊度检测结果的可靠程度，文章在GB/T 10288-2016《羽绒羽毛检验方法》基础上，对羽毛羽绒浊度测量过程中不确定度的影响因素进行了分析，并对各分量分别进行了评定，计算出了羽毛羽绒浊度的合成标准不确定度和扩展不确定度。

分析表明：测量重复性是影响浊度不确定度的最重要分量，检测人员目光的稳定性是保证检测结果准确性的关键所在。

关键词：羽毛绒；浊度；不确定度评估中图分类号：G712 文献标识码：A d oi:10.3969/j.issn.1673-0968.2021.03.0091 前言测量不确定度的评定是实验室检测结果报告的重要组成部分，其评定能力反映了实验室的技术水平。

不确定度的大小直接反映了检测结果质量的高低，客观反映了检测结果的可靠性。

浊度是反映羽毛羽绒清洁程度的重要指标。

GB/T 10288-2016《羽绒羽毛检验方法》标准浊度A法是采用目测法，由于该方法是由人眼对测试结果进行评级，存在测试精度低、测试数据易受人员波动性大的问题，为了提高实验室在浊度测试的精确度，本文分析了羽毛羽绒浊度测定过程中不确定度来源，并对各分量分别进行了评定。

2 羽毛绒浊度测量不确定度评估2.1 羽毛绒浊度测试2.1.1 测试方法及原理试验依据：GB/T10288-2016《羽绒羽毛检验方法》中5.5浊度 A法（目测法）。

环境条件：在光源为600lx-1000lx的日光或人工光源下进行观察。

2.1.2 试验仪器2.1.2.1水平振荡器：频率为（150±2）次/ min，振幅为（40±2）mm。

2.1.2.2 标准筛： 150目2.1.2.3玻璃浊度计：带刻度玻璃管或有机玻璃管，内径（32±1）mm，高度1000mm，底部有双十字线塑料片或陶瓷片。

2.1.2.4 三角烧杯：250ml2.1.2.5 蒸馏水或去离子水，符合GB/T6682规定的三级水。

Qualmark快速环境加速测试系统说明书

INTRODUCING . . .•Entry Level Rapid Testing System provides combined Environment Accelerated Testing:–Rapid Thermal changes from +200° C to -100° C–Six Degree of Freedom Repetitive Shock Vibration •Portable for easy movement between departments •Easy to use with preset programs & remote monitoring•xLF2 Vibration Table with PSD Management Standard FeaturesWork Space19.0”w x 16.0”d x 10.0”h(482 x 406 x 254mm)Outer Dimensions32.8”w x 43.5”d x 56.1”h(833 x 1105 x 1425mm)Table Size16.0”w x 12.0”d(406 x 304mm)Table Capacity50 lbs (23 kg)Actuators 2 Lubricant-free Actuators Acceleration 4 – 40 gRMS typicalTemp Range+200°C to -100°CThermal Ramp Range Up to 40°C / minPower Requirements208VAC / 40A / 1Φ 50/60Hz208VAC / 25A / 3Φ 50/60HzAir Requirements 20 scfm at 80 psi*Patent PendingPortable Rapid Testing SystemThousands of companies embrace combined environment accelerated testing that includes vibration (typically on an ED Shaker) and thermal testing, to rapidly improve the reliability of their electronic product designs. Conducting this practice early is most beneficial, as reliability can most easily be improved early in the development process. Qualmark’s new Portable Rapid Testing System takes this to a whole new level. HawQ preys on and exposes failure points, and screams through thermal testing in a fraction of the time of traditional thermal chambers. This leading edge system allows you to conduct rapid testing with thermal change rates of 40°C/min from -100 to +200°C! By maxi-mizing the thermal cycles performed in 24 hours, you slash your testing time! Time is money, and HawQ will help you save it! But not just that, HawQ also delivers Six Degree of Freedom vibration at the simple push of a button. By utilizing the ultimate combined environment of rapid thermal changes plus vibration, your designs will fly through reliabil-ity testing. "Through this process, we have improvedfirst-pass success during subsequent MIL-STD-1540 qualification testing, reduced the number of problems once in production, and improved... performance. These results are vitally important to our profit bottom line, plus they improve customer and insurance provider confidence in our ability to introduce new technology successfully." [White Paper by Brian Kosinski & Dennis Cronin, Space Systems/Loral]HawQ is a cost effective, portable solution that is available for purchase or lease to utilize in, or near, product development groups. The Portable Rapid Testing System provides an easy to use solution with Ethernet/WiFi options to allow for remote monitoring by development teams, and is a quiet, vibration-isolated system for virtually all develop-ment teams, R&D, Reliability, and University Labs.®E s t a b l i s h e d1981Center of ExcellenceThe strategic focus ofQualmark's Center of Excel-lence (COE) is to reduce customer warranty costs that are attributable to product failures by deploying and supporting a Accelerated Reliability Testing program.The COE team gathersinformation about the product from customer design experts and applies decades of experience and specialized knowledge in Accelerated Stress Testing to deliversolutions that will significantly reduce existing warranty costs and proactively mitigatewarranty costs in new designs.Contact the COE TODAY to request training for optimum HALT utilization.***********************New System Includes:•One (1) year warranty•Operations & Maintenance manual •Multi-pane Viewing Window•LN2 Cooling System (Cylinders provided separately)•PC or Monitor (optional)•System Manager Software (optional)•System start-up by QM certified service engineer (optional)•System and software orientation (optional)•Thermal AlarmsFeatures and Benefits*Patent PendingVibration Features Table Top16.0” x 12.0” (406 x 304mm)Table Top Hardware12 threaded 3/8-16 holes on 4” centers;M10-1.5 thread optionalActuators 2 pneumatic, impulse-type, lubricant-free actuators VibrationSix degree of freedom, random, Omni Axial™ broadband excitation Table Product Capacity50 lbs. (23 kg) Vibration Range 5-40 gRMSThermal Features Heating SystemOpen-element nichrome type Cooling System LN2 - insulated solenoid valveTemperature Range +200°C to -100°C ( +392°F to -148°F)Thermal Ramp Range Heating: up to 35°C / min (average)Cooling: up to 40°C / min (average)Internal Features Interior Dimension 19.0”w x 15.0”d x 10.0”h (482 x 381 x 254mm)Interior Volume 1.65 cu/ftInternal Construction Stainless Steel Exterior FeaturesExterior Dimensions 28.0”w x 33.0”d x 60.0”h (711 x 838 x 1524mm)External Construction Painted steel constructionDoor1 lifting door, opens approximately 100° Window(1) 15” x 5” (381 x 127mm) multi-pane window in the door Access Ports (2) 2” ports, one on each sideSoundNominally <72dBA measured at 1 meter10390 E 48th Street, Denver, CO 80238-2620 USAPhone +1.888.425.8669© 2013 Qualmark, All Rights Reserved. Printed In U.S.A Doc ID: 920-0366Options & Accessories•QDaq Data Acquisition •Spectrum Analyzer •PC with HawQ Manager Software•HawQ Manager Software •Basic Fixture Kit •PCA Fixture Clamps •O2 Sensor •Dewar Kit•Multiple Dewar KitTouch-screen PLCOver-temp Shutdown Easy On/O /Pause Buttons。

HT7550-1_PDF_C18333_2017-09-19

D V
a
´ V
O U T
Note: Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at VIN= VOUT+2V with a fixed load.
Thermal Information
Symbol θJA Parameter Thermal Resistance (Junction to Ambient) (Assume no ambient airflow, no heat sink) Package SOT23-5 SOT89 TO92 SOT23-5 PD Power Dissipation SOT89 TO92 Max. 500 200 200 0.20 0.50 0.50 Unit °C/W °C/W °C/W W W W
HT7527-1, +2.7V Output Type
Ta=25°C Symbol VIN VOUT IOUT ∆VOUT VDIF ISS
D V D T D V
IN O U T
Parameter Input Voltage Output Voltage Output Currenage (Note) Quiescent Current
Operating Temperature ................................... −40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ″AbsolutemAximum Ratings″ may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditionsmAy affect device reliability.

HumaStar 100 Assay Panel Quick Reference Guide

≤190 mg/dl; ≤5.0 mmol/l
1 Linear 120 500 - 25,000 U/l S
NaCl, (DIL)
–X–
m: 4,620 - 11,500 U/l; 77 - 195 µkat/l f: 3,930 - 10,800 U/l; 65 - 180 µkat/l
1 Linear 120 5 - 2000 U/l
S; HEP NaCl, (DIL)
XX–
m: ≤ 190 U/l; ≤ 3.20 µkat/l f: ≤ 170 U/L; ≤ 2.85 µkat/l
1 Linear 120 5 - 2000 U/l
S; Li-HEP NaCl, (DIL)
– – – CK-MB <24 U/l; <0.4 µkat/l Control
2/7
HumaStar 100 Assay Panel Quick Reference Guide
R APO A1/B Standard
1 Linear 120 1 - 70 U/l
S
NaCl, X X
(DIL)
1 Linear 120 1.5 - 8.0 g/dl
S; EDTA; NaCl,
HEP
(DIL)
XXX
1 Linear 120 10 - 2000 U/l
S; HEP NaCl, (DIL)
30 - 90 U/l; 0.5 - 1.5 µkat/l
≤200 IU/ml; ≤200kIU/l
m: 115 - 190 mg/dl; 1.15 - 1.90 g/l f: 115 - 220 mg/dl; 1.15 - 2.20 g/l
m: 60 - 138 mg/dl; 0.60 - 1.38 g/l f: 52 - 129 mg/dl; 0.52 - 1.29 g/l

1.3寸OLED手册

CONTENTREVISION RECORD (3)1 OVERVIEW (4)2 FEATURES (4)3 MECHANICAL DATA (4)4 MECHANICAL DRAWING (5)5 MODULE INTERFACE (6)6 FUNCTION BLOCK DIAGRAM (8)6.1 F UNCTION B LOCK D IAGRAM (8)6.2 P ANEL L AYOUT D IAGRAM (8)7 ABSOLUTE MAXIMUM RATINGS (9)8 ELECTRICAL CHARACTERISTICS (9)8.1 DC E LECTRICAL C HARACTERISTICS (9)8.2 E LECTRO-OPTICAL C HARACTERISTICS (10)8.3 AC E LECTRICAL C HARACTERISTICS (11)9 FUNCTIONAL SPECIFICATION AND APPLICATION CIRCUIT (18)9.1 R ESET T IMING (18)9.2 A PPLICATION C IRCUIT (19)9.3 E XTERNAL DC-DC APPLICATION CIRCUIT (25)9.4 D ISPLAY C ONTROL I NSTRUCTION (26)9.5 R ECOMMENDED S OFTWARE I NITIALIZATION (26)10 PACKAGE SPECIFICATION (27)11 RELIABILITY (28)11.1 R ELIABILITY T EST (28)11.2 L IFETIME (28)11.3 F AILURE C HECK S TANDARD (28)12 ILLUSTRATION OF OLED PRODUCT NAME (29)13 OUTGOING QUALITY CONTROL SPECIFICATIONS (30)13.1 S AMPLING M ETHOD (30)13.2 I NSPECTION C ONDITIONS (30)13.3 Q UALITY A SSURANCE Z ONES (30)13.4 I NSPECTION S TANDARD (31)14 PRECAUTIONS FOR OPERATION AND STORAGE (34)14.1 P RECAUTIONS FOR O PERATION (34)14.2 S OLDERING (34)14.3 P RECAUTIONS FOR S TORAGE (34)14.4 W ARRANTY PERIOD (34)4Mechanical Drawing9.4Display Control InstructionRefer to SH1106G IC Specification.9.5Recommended Software InitializationTBD10Package SpecificationTBDStain removable by soft cloth or air blow is acceptable.(1)Crack, deep scratch, deep hole and deep pressure mark onthe TCP/FPC are not acceptable.(2)Terminal lead twisted or broken is not allowable.(3)Copper exposed is not allowed by naked eye inspection.14Precautions for operation and Storage14.1Precautions for Operation(1)Since OLED panel is made of glass, do not apply any mechanical shock or impact or excessiveforce to it when installing the OLED module. Any strong mechanical impact due to falling droppingetc. may cause damage (breakage or cracking).(2)The polarizer on the OLED surface is made of soft material and is easily scratched. Please takemost care when handing. When the surface of the polarizer of OLED Module is contaminated,please wipe it off gently by using moisten soft cloth with isopropyl alcohol, do not use water,ketone or aromatics. If there is saliva or water on the OLED surface, please wipe it off immediately.(3)When handling OLED module, please be sure that the body and the tools are properly grounded.And do not touch I/O pins with bare hands or contaminate I/O pins, it will cause disconnection ordefective insulation of terminals.(4)Do not attempt to disassemble or process the OLED module.(5)OLED module should be used under recommended operating conditions shown in the specification.Since the higher voltage leads to the shorter lifetime, be sure to use the specified operating voltage.(6)Foggy dew, moisture condensation or water droplets deposited on surface and contact terminals willcause polarizer stain or damage, the deteriorated display quality and electrochemical reaction thenleads to shorter life time and permanent damage to the module probably. Please pay attention to theenvironmental temperature and humidity.(7)An afterimage is created by the difference in brightness between unused dot and the fixed dot,according to the decrease of brightness of the emitting time. Therefore, to avoid having anafterimage, the full set should be thoroughly used instead of using a fixed dot. When the fixed dotemits, an afterimage can be created.(8)Flicker could be come out at full on display. And it disappears when frame frequency increase, butbrightness decreases too.14.2Soldering(1)Soldering should be performed only on the I/O terminals.(2)Use soldering irons with proper grounding and no leakage.℃.(3)Iron: no higher than 300 and 3~4 sec during soldering14.3Precautions for Storage(1)Please store OLED module in a dark place. Avoid exposure to sunlight, the light of fluorescent lampor any ultraviolet ray.(2)Keep the environment temperature between 10℃ and 35℃and the relative humidity less than60%. Avoid high temperature and high humidity.(3)Keep the OLED modules stored in the container when shipped from supplier before using them isrecommended.(4)Do not leave any article on the OLED module surface for an extended period of time.14.4Warranty periodVisionox Display Co., Ltd. warrants for a period of 12 months from the shipping date when stored orused under normal condition.。

74f161a, 74f163a同步预置二进制计数器用户手册说明书

74F161A, 74F163A Synchronous Presettable Binary Counter 74F161A74F163A74F161A, 74F163A Synchronous Presettable Binary CounterUnit Loading/Fan Out74F161A IEEE/IEC74F161A 74F163A IEEE/IEC74F163APin NamesDescriptionU.L. HIGH / LOWInput I Output I Count Enable Parallel Input 1.0 / 1.0 20µA / -0.6mA Count Enable Trickle Input1.0 /2.020µA / -1.2mA Clock Pulse Input (Active Rising Edge)1.0 / 1.020µA / -0.6 mA MR (74F161A)Asynchronous Master Reset Input (Active LOW) 1.0 / 1.020µA / -0.6 mA SR (74F163A)Synchronous Reset Input (Active LOW) 1.0 /2.020µA / -1.2 mA Parallel Data Inputs1.0 / 1.0 20µA / -0.6 mA Parallel Enable Input (Active LOW) 1.0 /2.020µA / -1.2mAFlip-Flop Outputs 50 / 33.3-1mA / 20mA74F161A, 74F163A Synchronous Presettable Binary Counter74F161A, 74F163A Synchronous Presettable Binary Counter74F161A, 74F163A Synchronous Presettable Binary CounterAbsolute Maximum RatingsStresses exceeding the absolute maximum ratings may damage the device. The device may not function or beoperable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.Note:2.Either voltage limit or current limit is sufficient to protect inputs.Recommended Operating ConditionsThe Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.Symbol ParameterRatingT STG Storage Temperature–65°C to +150°C T A Ambient Temperature Under Bias –55°C to +125°C T J Junction Temperature Under Bias –55°C to +150°C V CC V CC Pin Potential to Ground Pin –0.5V to +7.0V V IN Input Voltage (2) –0.5V to +7.0V I IN Input Current (2)–30mA to +5.0mAV OVoltage Applied to Output in HIGH State (with V CC = 0V)Standard Output 3-STATE Output–0.5V to V CC –0.5V to +5.5VCurrent Applied to Output in LOW State (Max.) twice the rated I OL (mA)ESD Last Passing Voltage (Min.)4000VSymbol ParameterRatingT A Free Air Ambient Temperature 0°C to +70°C V CCSupply Voltage+4.5V to +5.5VDC Electrical CharacteristicsSymbol Parameter V CC Conditions Min.Typ.Max.Units V IH Input HIGH Voltage Recognized as a HIGH Signal 2.0V V IL Input LOW Voltage Recognized as a LOW Signal0.8V V CD Input Clamp Diode Voltage Min.I IN= –18mA–1.2VV OH Output HIGHVoltage 10% V CC Min. 2.5V 5% V CC 2.7V OL Output LOWVoltage10% V CC Min.I OL= 20mA0.5VI IH Input HIGH Current Max.V IN= 2.7V 5.0µA I BVI Input HIGH CurrentBreakdown TestMax.V IN= 7.0V7.0µAI CEX Output HIGH LeakageCurrentMax.V OUT = V CC50µAV ID Input Leakage Test0.0I ID= 1.9µA, All Other PinsGrounded4.75VI OD Output Leakage CircuitCurrent 0.0V IOD= 150mV, All Other PinsGrounded3.75µAI IL Input LOW Current Max.V IN= 0.5V (CEP, CP, MR, P0–P3)–0.6mAV IN= 0.5V (CET, PE, SR)–1.2I OS Output Short-CircuitCurrentMax.V OUT= 0.0V–60–150mAI CC Power Supply Voltage Max.3755mA74F161A, 74F163A Synchronous Presettable Binary Counter74F161A, 74F163A Synchronous Presettable Binary CounterAC Electrical CharacteristicsAC Operating RequirementsSymbolParameterT A = +25°C,V CC = +5.0V,C L = 50pFT A = –55°C to +125°C,V CC = +5.0V,C L = 50pF T A = 0°C to 70°C,V CC = +5.0V,C L = 50pFUnitsMin.Typ.Max.Min.Max.Min.Max. f MAX Maximum Count Frequency 100MHz t PLH Propagation Delay,CP to Q n (PE Input HIGH) 3.5 5.57.5 3.59.0 3.58.5nst PHL 3.57.510.0 3.511.5 3.511.0t PLH Propagation Delay,CP to Q n (PE Input LOW) 4.0 6.08.5 4.010.0 4.09.5ns t PHL 4.0 6.08.5 4.010.0 4.09.5tPLH Propagation Delay,CP to TC5.010.014.0 5.016.5 5.015.0ns t PHL 5.010.014.0 5.015.5 5.015.0t PLH Propagation Delay,CET to TC2.5 4.57.5 2.59.0 2.58.5ns t PHL 2.5 4.57.5 2.59.0 2.58.5t PHL Propagation Delay,MR to Q n (74F161A) 5.59.012.0 5.514.0 5.513.0ns t PHLPropagation Delay,MR to TC (74F161A)4.58.010.54.512.54.511.5ns SymbolParameterT A = +25°C,V CC = +5.0VT A = –55°C to +125°C,V CC = +5.0V T A = 0°C to 70°C,V CC = +5.0V UnitsMin.Max.Min.Max.Min.Max.t S (H)Setup Time, HIGH or LOW,P n to CP5.0 5.5 5.0ns t S (L) 5.0 5.5 5.0t H (H)Hold Time, HIGH or LOW,P n to CP2.0 2.5 2.0ns t H (L) 2.0 2.5 2.0t S (H)Setup Time, HIGH or LOW,PE or SR to CP11.013.511.5ns t S (L)8.510.59.5t H (H)Hold Time, HIGH or LOW,PE or SR to CP2.03.6 2.0ns t H (L)000t S (H)Setup Time, HIGH or LOW,CEP or CET to CP 11.013.011.5ns t S (L) 5.0 6.0 5.0t H (H)Hold Time, HIGH or LOW,CEP or CET to CP 000ns t H (L)000t W (H)Clock Pulse Width (Load), HIGH or LOW5.0 5.0 5.0ns t W (L) 5.0 5.0 5.0t W (H)Clock Pulse Width (Count), HIGH or LOW4.05.0 4.0ns t W (L)6.08.07.0t W (L)MR Pulse Width, LOW (74F161A)5.0 5.0 5.0ns t RECRecovery Time, MR to CP (74F161A)6.06.06.0nsFigure 2. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" NarrowPackage Number M16A74F161A, 74F163A Synchronous Presettable Binary Counter74F161A, 74F163A Rev. 1.0.211The Power Franchise™TinyBoost。

MAX7377 用户手册说明书

General DescriptionThe MAX7377 dual-speed silicon oscillator with reset is a replacement for ceramic resonators, crystals, crystal oscillator modules, and discrete reset circuits. The device provides the primary and secondary clock source for microcontrollers in 3V, 3.3V, and 5V applications. The MAX7377 features a factory-programmed high-speed oscillator, a 32.768kHz oscillator, and a clock selec-tor input. The clock output can be switched at any time between the high-speed clock and the 32.768kHz clock for low-power operation. Switchover is synchronized inter-nally to provide glitch-free clock switching.Unlike typical crystal and ceramic resonator oscillator circuits, the MAX7377 is resistant to vibration and EMI. The high-output-drive current and absence of high-impedance nodes make the oscillator less susceptible to dirty or humid operating conditions. With a wide operating temperature range as standard, the MAX7377 is a good choice for demanding home appliance and industrial environments.The MAX7377 is available in factory-programmed fre-quencies from 32.768kHz to 10MHz. See Table 1 for standard frequencies and contact the factory for custom frequencies.The MAX7377 is available in a 5-pin SOT23 package. Refer to the MAX7383 data sheet for frequencies ≥10MHz. The MAX7377 standard operating temperature range is -40°C to +125°C. See the Applications Information sec-tion for the extended operating temperature range.Applications●White Goods ●Consumer Products ●Appliances and Controls●Handheld Products●Portable Equipment ●Microcontroller Systems Features● 2.7V to 5.5V Operation●Accurate High-Speed 600kHz to 10MHz Oscillator ●Accurate Low-Speed 32kHz Oscillator●Glitch-Free Switch Between High Speed and LowSpeed at Any Time ●±10mA Clock-Output Drive Capability ●2% Initial Accuracy●±50ppm/°C Temperature Coefficient ●50% Duty Cycle●5ns Output Rise and Fall Time●Low Jitter: 160ps (P-P) at 8MHz (No PLL) ●3mA Fast-Mode Operating Current (8MHz) ●13μA Slow-Mode Operating Current (32kHz) ●-40°C to +125°C Temperature RangeTypical Application Circuit appears at end of data sheet.19-3474; Rev 4; 1/21The first two letters are AX. See Table 1 at the end of the data sheet for the two-letter code.PART TEMP RANGE PIN-PACKAGE PKG CODE MAX7377AX_ _-T-40°C to +125°C5 SOT23-5U5-2Silicon Oscillator with Low-Power Frequency SwitchingMAX7377Evaluation Kit Available DesignResourcesTools and ModelsSupportOne Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2021 Analog Devices, Inc. All rights reserved.© 2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.Click here to ask an associate for production status of specific part numbers.Pin ConfigurationOrdering InformationV CC to GND .............................................................-0.3V to +6V All Other Pins to GND ................................-0.3V to (V CC + 0.3V)CLOCK Current ................................................................±10mA Continuous Power Dissipation (T A = +70°C) 5-Pin SOT23(derate 7.1mW/°C above +70°C) ...................571mW (U5 - 2)Operating Temperature Range...........................-40°C to +135°C Junction Temperature .......................................................+150°C Storage Temperature Range ..............................-60°C to +150°C Lead Temperature (soldering, 10s )..................................+300°C(V CC = 2.7V to 5.5V, T A = -40°C to +125°C, unless otherwise noted. Typical values are at V CC = 5V and T A = +25°C.) (Note 1)Note 1: All parameters are tested at T A = +25°C. Specifications over temperature are guaranteed by design.Note 2: The frequency is determined by part number selection. See Table 1.Note 3: Guaranteed by design. Not production tested.Note 4: Guaranteed by design. Part will function outside tested range.PARAMETERSYMBOL CONDITIONSMIN TYPMAX UNITS Operating Supply Voltage V CC 2.75.5V Operating Supply Current I CC f CLOCK = 8MHz, no load 35mA f CLOCK = 32.768kHz, no load 1325µA Operating Supply Voltage Ramp V RAMP (Note 4)101000µs LOGIC INPUT (SPEED)Input High Voltage V IH 0.7 x V CCV Input Low Voltage V IL 0.3 x V CCV Input Current I IN2µACLOCK OUTPUT Output High Voltage V OH V CC = 4.5V, I SOURCE = 9mA V CC - 0.4V V CC = 2.7V, I SOURCE = 2.5mA V CC - 0.4Output Low VoltageV OL V CC = 4.5V, I SINK = 20mA 0.4V V CC = 2.7V, I SINK = 10mA 0.4Initial Fast CLOCK Frequency Accuracyf FCLOCKV CC = 5V, T A = +25°C (Note 2)-2+2% V CC = 2.7V to 5.5V, T A = +25°C -4+4Fast CLOCK Frequency Temperature Sensitivity (Note 3)±50±325ppm/°C Initial Slow CLOCK Frequency Accuracyf SCLOCKV CC = 5V, T A = +25°C (Note 2)32.44032.76833.096kHz V CC = 2.7V to 5.5V, T A = +25°C 31.78533.751Slow CLOCK Frequency Temperature Sensitivity (Note 3)±50±325ppm/o C CLOCK Output Duty Cycle 435057%CLOCK Output Jitter Observation of 8MHz output for 20s using a 500MHz oscilloscope160ps P-P CLOCK Output Rise Time t R 10% to 90%5ns CLOCK Output Fall Time t F90% to 10%5ns Startup DelayV CC rising from 0 to 5V in 1µs 100µs CLOCK Output EnableV CC rising2.49 2.572.70V Output Undervoltage LockoutHysteresisV THYS 45mVFrequency SwitchingAbsolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Electrical Characteristics(V CC = 5V, T A = +25°C, unless otherwise noted.)DUTY CYCLE vs. TEMPERATURETEMPERATURE (ºC)D U T Y C Y C L E (%)120954570-520-304647484950515253545545-55DUTY CYCLE vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)D U T Y C Y C LE (%)5.24.94.646474849505152535455454.35.5DUTY CYCLE vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)D U T Y C Y C L E (%)5.24.94.646474849505152535455454.35.5SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (ºC)S U P P L Y C U R R E N T (m A )120954570-520-3010.511.011.512.012.513.013.514.010.0-55SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (ºC)S U P P L Y C U R R E N T (m A )120954570-520-300.60.70.80.91.01.11.21.31.41.50.5-55SUPPLY CURRENT vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (A )5.24.94.60510152025304.3 5.5DUTY CYCLE vs. TEMPERATURETEMPERATURE (ºC)D U T Y C Y C L E (%)120954570-520-304647484950515253545545-55SUPPLY CURRENT vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (m A )5.24.94.60.60.70.80.91.01.11.21.31.41.50.54.35.5FREQUENCY vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)F R E Q U E N C Y (k H z ) 5.24.94.630.531.031.532.032.533.033.534.034.535.030.04.35.5Frequency SwitchingTypical Operating Characteristics(V CC = 5V, T A = +25°C, unless otherwise noted.)FREQUENCY vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)F R E Q U E N C Y (M H z ) 5.24.94.63.923.943.963.984.004.024.044.064.084.103.904.35.5FREQUENCY vs. TEMPERATURETEMPERATURE (ºC)F R E Q U E N C Y (k H z )120954570-520-3032.132.232.332.432.532.632.732.832.933.032.0-55FREQUENCY vs. TEMPERATURETEMPERATURE (ºC)F R E Q U E NC Y(M H z )120954570-520-303.923.943.963.984.004.024.044.064.084.103.90-5540ns/divCLOCK CLOCK OUTPUT WAVEFORM (C L = 10pF)40ns/divCLOCK CLOCK OUTPUT WAVEFORM (C L = 50pF)f = 4MHz, C L = 50pF40ns/divCLOCKCLOCK OUTPUT WAVEFORM (C L = 100pF)20µs/div MAX7377 toc16HIGH-SPEED TO LOW-SPEEDTRANSITION400ns/divMAX7377 toc17HIGH-SPEED TO LOW-SPEED TRANSITION (EXPANDED SCALE)Frequency SwitchingTypical Operating Characteristics (continued)(V CC = 5V, T A = +25°C, unless otherwise noted.)Detailed DescriptionThe MAX7377 is a dual-speed clock generator for micro-controllers (μCs) and UARTs in 3V, 3.3V, and 5V applica -tions (Figure 1). The MAX7377 is a replacement for two crystal oscillator modules, crystals, or ceramic resonators. The high-speed clock frequency is factory trimmed to specific values. A variety of popular standard frequencies are available. The low-speed clock frequency is fixed at 32.768kHz (Table 1). No external components are required for setting or adjusting the frequency.Supply VoltageThe MAX7377 has been designed for use in systems with nominal supply voltages of 3V, 3.3V, or 5V and is speci-fied for operation with supply voltages in the 2.7V to 5.5V range. See the Absolute Maximum Ratings section for limit values of power-supply and pin voltages.OscillatorThe clock output is a push-pull configuration and is capable of driving a ground-connected 500Ω or a positive- supply-connected 250Ω load to within 400mV of either supply rail. The clock output remains stable over the full operating voltage range and does not generate short out-put cycles when switching between high- and low-speed modes. A typical startup characteristic is shown in the Typical Operating Characteristics .Clock-Speed Select InputThe MAX7377 uses a logic input pin, SPEED, to set clock speed. Take this pin low to select slow clock speed (nomi-nally 32.768kHz) or high to select full clock speed. The SPEED input can be strapped to V CC or to GND to select fast or slow clock speed, or connected to a logic output (such as a processor port) used to change clock speed on the fly. If the SPEED input is connected to a processorPIN NAME FUNCTION1CLOCK Push-Pull Clock Output 2GND Ground3SPEED Clock-Speed Select Input. Drive SPEED low to select the 32kHz fixed frequency. Drive SPEED high to select factory-trimmed frequency.4V CC Positive Supply Voltage. Bypass V CC to GND with a 0.1µF capacitor.5E.C.Externally Connected. Must be externally connected to V CC.20µs/div MAX7377 toc18LOW-SPEED TO HIGH-SPEEDTRANSITIONCLOCKSPEED400ns/divMAX7377 toc19LOW-SPEED TO HIGH-SPEED TRANSISTION (EXPANDED SCALE)Frequency SwitchingTypical Operating Characteristics (continued)Pin Descriptionport that powers up in the input condition, connect a pullup or pulldown resistor to the SPEED input to set the clock to the preferred speed on power-up. The leakage current through the resistor into the SPEED input is very low, so a resistor value as high as 500kΩ may be used.Applications InformationInterfacing to a Microcontroller Clock InputThe MAX7377 clock output is a push-pull, CMOS, logic output that directly drives any microprocessor (μP) or μC clock input. There are no impedance-matching issues when using the MAX7377. The MAX7377 is not sensi-tive to its position on the board and does not need to be placed right next to the μP . Refer to the microcontroller data sheet for clock-input compatibility with external clock signals. The MAX7377 requires no biasing components or load capacitance. When using the MAX7377 to retrofit a crystal oscillator, remove all biasing components from the oscillator input.Output JitterThe MAX7377’s jitter performance is given in the Electrical Characteristics table as a peak-to-peak value obtained by observing the output of the MAX7377 for 20s with a 500MHz oscilloscope. Jitter values are approximately proportional to the period of the output frequency of the device. Thus, a 4MHz part has approximately twice the jit-ter value of an 8MHz part. The jitter performance of clock sources degrades in the presence of mechanical and electrical interference. The MAX7377 is relatively immune to vibration, shock, and EMI influences, and thus provides a considerably more robust clock source than crystal or ceramic resonator-based oscillator circuits.Initial Power-Up and OperationAn internal power-up reset disables the oscillator until V CC has risen above 2.57V. The clock then starts up within 30μs (typ) at the frequency determined by the SPEED pin.Extended Temperature OperationThe MAX7377 was tested to +135°C during product characterization and shown to function normally at this temperature (see the Typical Operating Characteristics ). However, production test and qualification is only per-formed from -40°C to +125°C at this time. Contact the factory if operation outside this range is required.Power-Supply ConsiderationsThe MAX7377 operates with a 2.7V and 5.5V power-supply voltage. Good power-supply decoupling is needed to maintain the power-supply rejection performance of the MAX7377. Bypass V CC to GND with a 0.1μF surface-mount ceramic capacitor. Mount the bypass capacitor as close to the device as possible. If possible, mount the MAX7377 close to the microcontroller’s decoupling capacitor so that additional decoupling is not required. A larger value bypass capacitor is recommended if the MAX7377 is to operate with a large capacitive load. Use a bypass capacitor value of at least 1000 times that of the output load capacitance.Figure 1. Functional DiagramFrequency SwitchingNote: For all other reset threshold options, contact factory.Table 2. Standard Part NumbersTable 1. Standard FrequenciesSUFFIXSTANDARD FREQUENCY (MHz)MG 1OK 1.8432QT 3.39545QW3.6864RD 4RH4.1943TP8PARTPIN-PACKAGE FREQUENCY (Hz)TOP MARK MAX7377AXMG 5 SOT231M AENE MAX7377AXOK 5 SOT23 1.8432M AEND MAX7377AXQT 5 SOT23 3.39545M AEMY MAX7377AXQW 5 SOT23 3.6864M AEMZ MAX7377AXRD 5 SOT234M AFBJ MAX7377AXRH 5 SOT23 4.1943M AENB MAX7377AXTP5 SOT238MAENCPACKAGE TYPE PACKAGE CODE OUTLINE ND PATTERN NO.5 SOT23U5-221-005790-0174Frequency SwitchingTypical Application CircuitChip InformationPROCESS: BiCMOSPackage InformationFor the latest package outline information and land patterns (foot-prints), go to /packages . Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.REVISION NUMBERREVISION DATE DESCRIPTIONPAGES CHANGED34/14No /V OPNs; removed Automotive reference from Applications section 141/21Revised Package Information table.7Frequency SwitchingRevision HistoryInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.。

原子荧光法测定矿泉水中硒的方法验证与确认

分析检测原子荧光法测定矿泉水中硒的方法验证与确认张敏娟，王珺，李媛（陕西省产品质量监督检验研究院，陕西西安 710048）摘要：由于方法验证过程受人员、环境、设备、试剂和设施等多方面因素的影响，这些因素可能对测试结果的准确性和可靠性产生影响，因此检测机构在采用新方法前须对该方法进行验证。

矿泉水中硒含量的测定采用《食品安全国家标准饮用天然矿泉水检验方法》（GB 8538—2022），本文从检出限、定量限、精密度和正确度等方面对该方法进行验证。

经验证，各指标均满足《环境监测分析方法标准制订技术导则》（HJ 168—2020）等标准要求，表明本实验室具有水中硒氢化物原子荧光法测定的条件和能力。

关键词：方法验证；矿泉水；硒Verification and Confirmation of Atomic Fluorescence Method for Determining Selenium in Mineral WaterZHANG Minjuan, WANG Jun, LI Yuan(Shaanxi Institute of Supervision & Testing on Product Quality, Xi’an 710048, China) Abstract: Since the method verification process is affected by many factors such as personnel, environment, equipment, reagents and facilities, which may affect the accuracy and reliability of the test results, the testing organization must verify the method before adopting the new method. The determination of selenium content in mineral water adopts the GB 8538—2022. This article verifies this method from the aspects of detection limit, quantitative limit, precision, accuracy, etc. After verification, all indicators meet the requirements of the HJ 168—2020 and other standards, indicating that our laboratory has the conditions and ability for the determination of selenium hydride atomic fluorescence in water.Keywords: method validation; mineral water; selenium硒是人体不可或缺的一种重要微量元素，硒元素对人体具有抗癌、抗肿瘤、抗衰老等功效，同时可以增强人体免疫力和抵抗力。

《工业及类似用途除湿机》标准解读

标准评析《工业及类似用途除湿机》标准解读■ 亓新1 刘迎文2（1. 中国家用电器研究院；2. 西安交通大学热流科学与工程教育部重点实验室）摘要：伴随客户需求升级、产品升级，传统工业除湿机正在逐步细分化，但在各种工业除湿机备受青睐的同时，标准检测行业未有匹配的标准能对其水平进行评价，消费群体更难有选购的参考。

T/CAS 436-2020《工业及类似用途除湿机》标准的发布与实施有效地解决了该难题，针对我国现有工业除湿机的特点，对能效限定值进行大幅提升；同时针对不同区域的实际情况，给出了高温、低温、超高温等不同工况条件下除湿能力的测试及评价方法；根据除湿机高湿工况的工作条件，增加可靠性方面的考核，提升除湿机产品安全可靠性设计水平，并对消费者对选购节能产品做出有效的指引。

本文就该标准的背景、构架、各部分内容的制定思路和核心指标等进行了详细论述与解读，以期对正确理解和执行该标准有所帮助。

关键词：标准，节能，高温除湿，工业除湿机DOI编码：10.3969/j.issn.1002-5944.2021.04.025Interpretation of Industrial and Similar Dehumidifier StandardQI Xin1 LIU Ying-wen2（1. China Household Electric Appliance Research Institute; 2. Lab of Thermo-Fluid Science & Engineering of MOE, School of Energy & Power Engineering, Xi'an JiaoTong University）Abstract: With the increase of customers’ demands and upgrading of products, traditional industrial dehumidifiers are gradually refined. However, while all kinds of industrial dehumidifiers become popularized, there are no corresponding evaluation standards in the standard testing industry. And consumers have no basis to choose and buy relevant products. The release and implementation of T/CAS 436-2020, Technical specification for flat evaluation of industrial dehumidifiers, effectively solves the problem. According to the characteristics of existing industrial dehumidifiers in China, the energy efficiency limit value is greatly improved. At the same time, according to the actual situation in different regions, the standard provides test and evaluation methods of dehumidification capacity under different working conditions such as high temperature, low temperature and ultra-high temperature. According to the working conditions of dehumidifiers under high humidity conditions, reliability assessment is added to improve the safety and reliability design of dehumidifiers, and provide effective guidance for consumers while purchasing energy-saving products. This paper discusses and interprets the background, framework, development ideas and core indicators of the standard in order to facilitate correct understanding and implementation of the standard.Keywords: standard, energy saving, high temperature dehumidifier, industrial dehumidifier亓新，刘迎文：《工业及类似用途除湿机》标准解读1 引言工业场所除湿要求的提高、产品的节能升级和技术飞速进步等因素催化了工业除湿机市场及技术的蓬勃发展。

Fujitsu BS2000 OSD VM2000 V10.0虚拟化白皮书说明书

White paperFujitsu BS2000/OSDVM2000 V10.0Virtualization of BS2000/OSD within the Dynamic Data Center.Introduction 2 VM2000: The basis for multiple system environments 2 Classic benefits of VM2000 in a service data center 3 VM2000 added value in high-availability network 4 Functional enhancements in VM2000 V10.0 5 Version overview 6 Performance-Hinweise 7 Summary of VM2000 benefits 7IntroductionA virtual infrastructure like VM2000 reduces IT costs by increasing efficiency, flexibility and responsecapability. It provides IT resource allocation on-the-fly in response to new business requirements andservice requests. Extremely high levels of server utilization are a byproduct.VM2000 supports the simultaneous operation of different, totally segregated system environmentson one server. The CPU power and main memory of one real server can be distributed across up to 15virtual servers. This distribution and the allocation of peripheral devices can be modified dynamically.The configuration of peripherals, including their connections (channels), and other devices can bemodified or extended during live operation.The advantage of using VM2000 as compared with the use of multiple servers is the possibility ofconsolidation with the aim of providing more efficient use of hardware resources, human resourcesand infrastructure.VM2000: The basis for multiple system environmentsCustomers are increasingly faced with the need to handle different system environments simultaneously on one server in order to cope most effectively with the wide variety of IT tasks they have to deal with.The reasons:⏹Optimization of costs⏹Simple and uniform handling and administration⏹Parallel operation of production, development, test and version updates⏹Automation and operational reliability⏹Complex systems, for example for service data centers⏹Availability for backup systems⏹Separation of sensitive applicationsVM2000 runs on the current BS2000/OSD S series and SQ series business servers and supports the current versions of the BS2000/OSD operating system as guest systems.VM2000 can fulfill your requirements flexibly thanks to the following features:Simultaneous operation of many systemsThe maximum number of supported guest systems is 15 .Full separation of guest systemsAccess to memory areas on the other guest systems is protected. Faults in operation on one guest system do not affect the other guest systems, even if these errors cause the system to crash.Flexible assignment of resources to the VMsMemory, devices, CPU power and global store can be assigned to VMs “on the fly”. The granularity of assignment is very small.The Capacity-on-Demand feature is offered: The administrator can switch on extra CPUs for a certain time, so CPU power can be increased to cover a peak load period.Increased reliability and availabilityWhen the guest system used for administration fails, it is automatically restarted. A manual restart of this system can also be initiated. This does not affect the remaining guest systems.When one CPU fails, VM2000 automatically activates the available spare CPU (S140, S145, S155, S170, S180 and S190), and system performance remains unimpaired. The same recovery is done for an involved guest system: a virtual spare CPU will be switched on – the guest system performance remains the same. With this technique, the availability of mono guest systems is equal to the availability level of MP guest systems.necessary address conversion is done by hardware. The devices are assigned directly to the guest system; virtual I/O operation is only necessary for shared pubsets and disks.Performance-hungry guest systems can be prioritized, thus enabling a flexible response to customer requirements. Administration of I/O peripherals is possible for VM2000 as a whole.Full integration of BS2000/OSD guest systems into the automation and high availability concepts of BS2000/OSD⏹HIPLEX-AF for application monitoring⏹HIPLEX-MSCF for clusteringClassic benefits of VM2000 in a service data centerVM2000 allows data center service providers to install one or a small number of high-performance business servers that can run several operating systems for a variety of external customers.This enables detailed capacity planning throughout the organization. Obvious knock-on effects of this include cost savings in relation to operating staff and space requirements for computers. The virtualization of resources such as CPU, main memory and global storage guarantees a high level of efficiency and optimum use of resources.The billing of the consumed CPU power can be done in two different ways:⏹Usage basedVM2000 writes VM-specific accounting records. They show the consumed CPU and the time periods of resource assignment.⏹Service level agreementsA fixed amount of CPU power is agreed with the customer. The amount of CPU power used can be limited using the VM2000 functionMAX-CPU-UTILIZATION.Limitation of the CPU power for a group of VMsA data center can offer type 2 pricing models to customers with more than one guest system on S servers. A two-step assignment of CPU power is possible. In the first step you decide how much power is given to the group and how the consumption of the group is limited. In a second step you decide how to distribute this power within the group. Power not consumed by group members will preferably be offered within the group. Assign a subset of the server to customerCPUs can be combined to form CPU pools. You can arrange which guest systems should run within such a pool.Dedicated CPUsThe data center can offer quasi-native running guest systems to customers with very high performance requirements. The virtual CPUs of such guest systems will be bound in a fixed manner to real CPUs. So the Hypervisor overhead and the indirect overhead will become extremely small for the VM.Very fine CPU-QUOTA and UTILIZATIONThese scheduling parameters can now be specified by decimal numbers. So it is possible to specify CPU assignments for big servers which correspond to one-digit RPF values.VM1VM VM K11 K12VM K3VM K4Client K4 5 % 25 %10 %keine 30 % implizit implizit20 %Limitation of the CPU power (Max-CPU-UTIL)Planned share of total CPU power (CPU-Quota)Client K1Client K2VM VM VM K21 K22 K23CPU-PoolVM-GroupCPU CPU dedi-cated CPUCPUClient K3VM2000 added value in high-availability networkThe general aim of a high-availability BS2000/OSD cluster is to be able to switch to redundant hardware and operating systems in the event of a server or application failure. In the event of a fault, business-critical applications on the failing system are exported together with their resources to the surviving system (less important services on the standby system may have to be delayed).HIPLEX (Highly Integrated System Complex) is Fujitsu’s clustering concept, designed to support an availability cluster comprising several BS2000/OSD business servers. A HIPLEX with VM2000 servers provides the following benefits:System availabilityIf a guest system on which an application is running fails, the entire system environment with the application can be made available without delay on the second business server.Application availabilityIf the application fails, it can quickly continue running on the same server in a backup guest system or it can be switched to a second server. The second system is in this case actively redundant. An example of an application that requires maximum availability would be automatic teller machines (ATM) in different bank branches: The service is available around the clock and the transactions are monitored centrally. Two business s ervers running VM2000 are provided for this purpose at the bank’s head office as well as the BS2000/OSD operating system and the relevant “ATM” application software. The required availability is provided by a HIPLEX with VM2000 running on every server.In the event of errors, operation of the same production application (in A1) is guaranteed on the second business server (B) under VM2000. A guest system (B2) with a basic memory configuration is set up for backup purposes in this instance. If errors occur, the main memory of the backup system is extended dynamically using the resources of the lower-priority guest systems, the production application is moved out to the backup system and can continue working immediately. The data belonging to the production application must be transferred, provided it is not stored on shared data media (shared pubset).Business Server A: S210 with VM2000Business Server B: S210 with VM2000Functional enhancements in VM2000 V10.0VM2000 V10.0 featuring support for the new BS2000/OSD-BC V9.0 functions.VM2000 V10.0 supports⏹on S servers: OSD V8 and OSD V9 as monitor system, OSD V6 to OSD V9 as guest systems,⏹on SQ servers: OSD V8- or OSD V9-based OSD/XC packages as monitor system, OSD V8- to OSD V9-based OSD/XC packages as guest systems. VM2000 V10.0 requires X2000 as of V5.3 on SQ servers.SX servers are supported no longer.The main new functions in VM2000 V10.0 are:Consolidation of HSI linesAfter version V9.0 (S/SX) and V9.5 (SQ only) VM2000 V10.0 is a joint version, which will again support all the current HSI lines (S/SQ). SX servers are officially no longer supported.Support of ETERNUS DX disk systemsEternus DX disk systems are supported to the same extent as EMC Symmetrix disk systems by VM2000 (PAV, Snap & Clones).Save & Restore of the VM2000 configurationThe backup of an existing VM2000 configuration is intended to enable the VM2000 administrator to recover the VM2000 configuration after the restart of the overall VM2000 system, i.e. ending all guest systems and restarting the monitor system, without having to write a suitable procedure file with VM2000 commands or adapt an existing procedure file. It should also be possible to use the backup to restore the VM2000 configuration on a backup server, on which - apart from the monitor system - no further BS2000 guest systems run.The VM2000 administrator can generate a backup with the command SAVE-VM-CONFIGURATION. The VM2000 administrator can trigger the recovery of a VM2000 configuration through the installation of a backup with the command RESTORE-VM-CONFIGURATION.CPU pools also for SQ servers (incl. adaptation of the multiprocessor capacity of the VMs)The maximum multiprocessor capacity of a VM on an SQ server is increased from 16 to 32.The high-availability & LiveMigration functionality for SQ server units is mainly implemented through MARS, X2000 and HA-Addon software. Nevertheless, deliverables are also required in VM2000, which make it possible to use VM2000 in such a HA cluster (e.g. a global view of all VMs in a cluster due to the required global uniqueness of VM names and necessary VM2000-specific tests).Version overview1) : guest systems as of OSD V5.0 (also with VM2000 V8.0)2) : monitor and guest systems as of OSD/XC V4.1 only3) : subsequent also with VM2000 V9.0 possible4) : subsequent also with VM2000 V9.5 possibleVM2000 overheadThe VM2000overhead, which arises for loads with exclusive allocation of the disk peripherals in comparison with native operation, is caused by the CPU requirement of the hypervisors (HPV-ACTIVE), the paths for switching from one BS2000 guest system to the hypervisor, and as a result of the loss in hardware performance because of the sinking effectiveness of the CPU caches due to competing guest systems. The size of the overheads is essentially determined by the number of virtual processors and their relationship to the physical processors as well as by the IO load intensity.The VM2000 overhead was measured using the TPS benchmark on S servers. It contributes more than 10% for a configuration with a quadro VM. If only mono and bi-VMs are operated, the overhead is between 6 and 6.5%, thus making it higher than the overhead measured with VM2000 V9.0 (4.1%). More frequent changes to the hypervisor due to the higher system performance were determined as the cause for the increased overhead.The recommendations previously made for the operation of BS2000 systems under VM2000 should be observed, i.e. the usual guidelines for the load (65-70% for TP operation) should be maintained and the chosen degree of VM multiprocessors should be as low as possible. Summary of VM2000 benefits⏹Parallel operation of several BS2000/OSD systems on one server⏹Support for version upgrades of the operating system, system-specific software and application systems⏹Parallel operation of several different BS2000/OSD operating system versions and Linux systems on one server⏹More flexible resource distribution than is possible on multi-server configurations⏹Provision of backup systems⏹Price advantages compared to several servers (consolidation)E-mail: ***********************.com Website: /bs2000 2012-09-18 EM EN Technical data subject to modification and delivery subject to availability. Any liability that the data and illustrations are complete, actual or correct is excluded. Designations may be trademarks and/or copyrights of the respective manufacturer, the use of which by third parties for their own purposes may infringe the rights of such owner. [Other disclaimers]。

无线蓝牙耳机电子产品可靠性试验标准中英文版模板

RODUCT reliability Test standard产品可靠性试验标准Product Type: True Wireless EarphonesModel:Document No.REVISIONSApprovalsContents1Purpose (1)2Policy (1)3Safety (1)4RESPONSIBILITY (1)5SAMPLING PLAN (1)5.1Total Samples Required (1)5.2Sample grouping (2)5.3Unit Marking: (2)5.3.1Sampling Plan Visual Tests (3)5.3.2Sampling Plan Function Tests (3)5.3.3Sampling Plan Product Reliability Tests (3)5.3.4Sampling Plan Mechanical Validation and Life Tests (4)5.3.5Sampling Plan Packaging Tests (4)5.3.6Sampling Plan Compliance Validation Tests (5)6PROCEDURE (5)6.1Test Definitions and Descriptions for Visual Tests (5)6.1.1External Visual Examination (5)6.1.2Internal Visual Examination (6)6.2Test Definitions and Descriptions for Function Tests (7)6.2.1Manual Listening and Calling Test (7)6.2.2Frequency Response (7)6.2.3Mic Sensitivity Test (8)6.2.4THD Test (8)6.2.5Audio Balance Test (9)6.2.5Audio Balance Test （ANR Off） (9)6.2.6Audio Balance Test （ANR On） (9)6.2.7NC Stability test (9)6.2.8Hiss Noise Test (9)6.2.9ANR Test (9)6.3Test Definitions and Descriptions for Product Reliability Tests (9)6.3.1Continuous Max. Output Power Test (11)6.3.2Non Operational Thermal Shock Test (11)6.3.3Operational Temperature / Humidity Cycle Test (12)6.3.4Non Operational Temperature / Humidity Cycle Test (13)6.3.5Driver Deformation Test (14)6.4Test Definitions and Descriptions for Mechanical Validation and Life Tests (15)6.4.1Cable Flexing Test (15)6.4.2Cable Tensile Strength Test (15)6.4.3Insertion & Extracting Test (16)6.4.4Bluetooth test (16)6.4.5Switch Life Test (18)6.4.6Charging Pin Life Test (18)6.4.7USB Socket Withstand Force Test (19)6.4.8Drop Test (19)6.4.9Vibration Test (19)6.4.10Charge Time Test (21)6.4.11Music Play Time Test (21)6.4.12ESD Test (21)6.4.13Decorative Surface Tests (22)6.4.14Standby Time Test (29)6.4.15RCA Test For Coating Parts (29)6.4.16Free fall repeat Test (29)6.5Test Definitions and Descriptions for Packaging Validation (30)6.5.1Retail Packaging Drop Test (30)6.5.2Shipping Carton Vibration Test (30)6.5.3Shipping Carton Piling Up Test (31)6.5.4Shipping Carton Packaging Storage Test (31)6.5.5Shipping Carton Drop Test (32)6.6Test Definitions and Descriptions for Compliance Validation (33)6.6.1EMC Test (33)6.6.2RoHS Compliance Test (33)6.6.3REACH Compliance Test (33)6.7IPX5 Protection against water Test (34)7ANNEXES (35)1PurposeThis document explains the sequence of testing to be used to verify the Bluetooth headset .本文档诠释了用于验证蓝牙耳机的测试顺序。

LSAT 评分指南说明书

June 2017 LSAT AdministrationThis Interpretive Guide for the June 2017 LSAT was developed to help admission officers, deans, faculty, prelaw advisors, and others who use LSAT scores, to facilitate the law school admission process. This guide does not cover all the technical psychometric information available regarding the LSAT, but it does provide basic information in nontechnical language for those who need to use and interpret these scores.Interpreting LSAT ScoresScores on the Law School Admission Test (LSAT) are reported on a scale from 120 to 180 and can be directly compared across testing administrations and testing years. Why are scores on the 120–180 scale comparable to each other?These scores have the s ame meaning from one administration to the next and from one year to the next as a result of a statistical process called equating.When scores are equated, a given scaled score represents comparable ability regardless of the administration in which it is obtained. The average ability level of test takers (group performance) is higher at some administrations than at other administrations. Nevertheless, for any individual test taker, a given scaled score represents the same degree of ability regardless of when the score is earned. Information about group performance may be useful to some score users. However, score users should never inflate or discount an individual’s score to take into account the administration at which it was earned, since the scores from different test forms have been made comparable through the equating process. An applicant’s LSAT score provides the same information about the applicant’s ability regardless of the ability of others who tested at the same time. For example, an applicant with an LSAT score of 160 might have a higher relative standing among February test takers than among June test takers, but the ability level represented by a score of160i s t he same regardless of when t hat s core is earned. Distribution of June 2017 Test TakersTo guide and monitor their admission processes, many LSAT score users use information about the percentage of test takers who earn each scaled score. This is frequently referred to as distribution data because it provides information about howtest takers are distributed across the score scale. Distribution data based on information available from the June 2016 and June 2017 administrations are presented in Table 1.Table 1 shows percentile ranks for June 2016 test takers compared to June 2017 test takers. The same score would havea different percentile rank within different groups. LSAT score users are likely to be most interested in percentile ranks forthree different reference groups: all test takers, all lawschool applicants, and all applicants to a particular law school. This Interpretive Guide only shows percentile ranks for test takers to date. The monthly applicant reports sent to each law school show the percentile ranks for applicants to all ABA-approved law schools to date and for applicants to that law school. These percentile ranks for the reference group of applicants are different from the percentile ranks for all test takers.Some Things to Note•The test-taker volume for the June 2017 administration was approximately 20 percent higher than reported for the June2016 administration.•The mean LSAT score for the June 2017 administration was 0.27 points higher than the mean LSAT score for the June 2016administration.•Slight differences were noted between the percentile ranks for the two testing periods.Reliability, Measurement Error, Score Bands, and Score DifferencesTo assess the reliability or consistency of LSAT scores, a reliability coefficient is computed for each LSAT form. Reliability coefficients indicate how reproducible a test taker’s performance would be over repeated administrations of the same test form. Reliability coefficients are measured on a scale from0to1.T he larger the v alue of the reliability coefficient, the more reproducible a test taker’s performance should be. Values of at least .9 indicate a very reliable test form.Table 2 shows the reliability coefficient for the June 2017 (Form8LSN127) test form. This and previous LSAT reliability coefficient values have typically been over .9, indicating that the LSAT is a very reliable test.LSAT scores contain a certain amount of measurement error that is assessed with the standard error of measurement for individual scores (SEM I). The SEM I is more useful than the reliability coefficient for interpreting the precision of individual test scores. The SEM I indicates how close a test taker’s observed score is likely to be to his or her true score. (A test taker’s true score is the score that he or she would obtain on a perfectly reliable test—a test with a reliability coefficient of 1.) The LSAT SEM I is very stable and tends to be about 2.6 scaled score points. The actual SEM I value for Form 8LSN127 is 2.63 points (see Table 2). Smaller SEM Ivalues indicate more precise scores.Law School Admission CouncilPO Box 40, Newtown PA 18940-0040P: 215.968.1001Table 1: Score Distributions for the June LSAT AdministrationJune 2017 June 2016 Score%Below%Below180 99.9 99.9179 99.9 99.9178 99.9 99.9177 99.7 99.7176 99.5 99.7175 99.5 99.5174 99.2 99.3173 98.7 98.9172 98.3 98.6171 97.8 98.0170 97.0 96.9169 96.3 96.2168 94.8 94.7167 93.7 93.8166 91.7 92.0165 90.6 90.8164 88.4 88.7163 86.0 86.3162 83.2 83.8161 80.7 81.4160 77.7 78.7159 74.7 75.6158 71.5 72.5157 68.5 69.3156 65.3 65.7155 61.9 63.6154 58.2 60.1153 54.6 56.2152 50.9 52.5151 47.2 48.6150 43.6 44.5149 39.7 42.2148 36.0 38.1147 34.2 34.2146 30.6 32.2145 27.2 28.2144 23.8 24.2143 22.0 22.3142 18.8 18.8141 17.4 17.3140 14.4 15.6139 12.8 12.6138 10.3 11.2137 9.0 10.0136 7.9 7.7135 6.8 6.6134 5.7 5.7133 4.9 5.0132 4.2 4.2131 3.4 3.6130 2.7 2.9129 2.2 2.4128 1.8 2.0127 1.7 1.7126 1.4 1.3125 1.1 1.0124 0.9 0.8123 0.9 0.6122 0.7 0.5121 0.6 0.4120 0.0 0.0Test Takers Mean Std Dev 27,589150.8810.6422,970150.6110.60Score bands, or ranges of scores that contain a test taker’s true scorea certain percentage of the time, can be derived using the SEM I.Score bands are constructed by adding and subtracting a multipleof the SEM I to or from a scaled score. By adding and subtractingone times t he SEM I to or from a score, the score band will containan individual’s true score approximately 68 percent of the time. Byadding and subtracting two times the SEM I to or from a score, thescore band will contain an individual’s true score approximately 95percent of the time.For reporting purposes, LSAC constructs score bands bysubtracting one times the rounded SEM I from the LSAT score toobtain a lower bound value, and adding one times the roundedSEM I to the LSAT score to obtain an upper bound value. LSACadjusts the score bands for LSAT scores lying in the upper andlower regions of the LSAT score scale (i.e., scores close to 120 or180), which makes them asymmetrical.Given that the SEM I for Form 8LSN127 is 2.63 points (which weround to 3 to create score bands), the score band for most LSATscores will be 7 score points. For example, the score band for anLSAT score of 150 will be 147 to 153.LSAT score users are sometimes interested in comparing scoredifferences among test takers. When this is done, users must keepin mind that the SEM for score differences (SEM D)is larger than theSEM associated with individual scores (SEM I). In fact, it isapproximately 1.4 times larger. The interpretation of the SEM D issimilar to the interpretation of the SEM I: the difference betweenscores from two test takers is within one SEM D on either side of thetrue score difference, approximately 68 percent of the time.Table 2 shows the SEM associated with score differences for Form8LSN127. For this form, the SEM D is 3.72 points, which we roundup to 4 points to compare scores. If two test takers have scores of150 and 154, for example, their true score difference will lie in therange of 0 to 8 points (4-point difference, plus or minus therounded 4-point SEM D), approximately 68 percent of the time.Note: This example illustrates that small score differences betweentwo test takers may be due to measurement error and may notrepresent real differences in the abilities of test takers. Thisunderscores the LSAC cautionary policy against putting undueweight on small score differences among test takers. The LSAT isjust one source of information that should be considered whenevaluating an applicant.Table 2: Reliability and Standard Error of Measurementto Date: 2017–2018 Testing YearReliabilityCoefficientStandard Errorof Measurement8LSN127 (June 2017) .94Individual Scores(SEM I)2.63Score Differences(SEM D)3.72© 2017 Law School Admission Council, Inc.。

PF11089克莱斯勒DV规范

D AIMLER C HRYSLER CORPORATION Document No: PF-11089 Performance Standard Date Published: 2005-09-29 Category Code: L-1 Change Level: -EASL Requirement: YesRESTRICTED: NoRADIO PERFORMANCE REQUIREMENTS FORREQ RADIO - AM/FM/6-DVDRET RADIO - LW/MW/FM/6-DVDREL RADIO - LW/MW/FM/DVD1.0 GENERAL1.1 PurposeThis standard constitutes an acceptance specification for AM/FM/6-DVD, LW/MW/FM/6-DVD andLW/MW/FM/DVD radio assemblies equipped with digital IF tuner, RDS/diversity tuner, integrated satellite radio, auxiliary input jack, DVD video, DVD audio, CD, compressed audio (MP3 and WMA), CAN bus communication, RBDS, RDS, remote control via steering wheel control, audio amplifiers, real-time clock display, dual audio outputs and composite video output to support external VES, as well as hands free phone and voice recognition interface. Any exception to this performance standard must be noted in the released documents and approved by Audio & Telematics Components management.1.2 Coverage of this StandardThis standard covers the design, operation, performance, reliability, durability, and quality requirements. This standard is supported by PF-8500, General Requirements, and PS-7000, Outside Designed and Developed Items (ODD Box Items), which describes terms and responsibilities associated with the requirements of this standard. This standard is also supported by PF-11056 unless otherwise specified.1.3 Limitations on UsageThe requirements of this standard supersede the requirements of PF-11056.1.4 Location of Definitions/Abbreviations/AcronymsDefinitions/Abbreviations/Acronyms can be found in Section 10.0 toward the end of this standard.2.0 SPECIAL TEST EQUIPMENTRefer to the Special Test Equipment section of PF-11056.3.0 ENVIRONMENTAL REQUIREMENTSRefer to the Environmental Requirements section of PF-11056 except for items specifically mentioned in this section.4.0 PHYSICAL REQUIREMENTSRefer to the Physical Requirements section of PF-11056 except for items specifically mentioned in thissection.The radio shall provide all displays in English language.The radio shall have a reconfigurable VF display and shall meet the requirements as defined in PF-11056.The radio shall follow the faceplate color, finish and process requirements given in Table 1.TABLE 1: FACEPLATE PAINT AND FINISH REQUIREMENTSPART SUB - PART FINISH PROCESS DAY TIME COLOR ILLUMINATED COLORFT - LMolded and PaintOpaque Black to MatchPN-363-DX9N/A N/A FaceplateCPM – 583 (SPI –SPE3)Pad PrintOpaque White to MatchVP-S7-07WN/A N/A ButtonsCPM – 583 (SPI –SPE3) Molded, Paint and Lazer Etch Transclucent White tomatch VP-S7-07WOpaque Black to MatchPN-363-DX9Blue/Green u’ 0.124 and v’ 0.499 Tol 0.016RMin 1.0 - Nom 1.5 -Max 2.0Knob CPM-526 Molded ColorOpaque Black to MatchPN-310-DX9N/A N/A Lens - Light RingPS-1285 Item 1 Molded Milky White Blue/Green u’ 0.124 and v’ 0.499 Tol 0.016R Min 0.7- Nom 1.2 -Max 1.7 Chrome Ring PP-001-SZ0Molded and Chrome Plating Bright Chrome Chrome Plating PS-8810N/AKnobAssemblyHolderCPM-526 Molded Color Opaque Black to Match PN-310-DX9 N/A N/A CD/DVD OpticsPS-1285 Item 1MoldedClearBlue/Green u’ 0.124 and v’ 0.499 Tol 0.016R Min 0.7- Nom 1.2 -Max 1.7 MoldedTransclucent BlackBlue/GreenMin 44- Nom 76 -Max 108VF-Display LensPS-1285 Item 1Pad PrintOpaque White to Match VP-S7-07WN/A N/A5.0 ELECTRICAL, AND MECHANICAL REQUIREMENTSRefer to the Electrical and Mechanical Requirements section of PF-11056 except for items specifically mentioned in this section.5.1 Tuner and Media RequirementsRefer to Table 2 for market-based configurations specific to the radio part number.TABLE 2: MARKET SUPPORT REQUIREMENTSP/N Bus Description MarketSpeed ECE USA JAPAN ROW 05064111AA REQ - AM/FM/6-DVD 05064112AA 83.3k REQ+RSC - AM/FM/6-DVD/SDARS05064127AA RET - LW/MW/FM/6-DVD05107096AA REL - LW/MW/FM/DVDTABLE 2: MARKET SUPPORT REQUIREMENTSP/N Bus Description MarketSpeed ECE USA JAPAN ROW05107099AA REQ - AM/FM/6-DVD05064113AA 125k REQ+RSC - AM/FM/6-DVD/SDARS05064055AA RET - LW/MW/FM/6-DVD05064053AA REL - LW/MW/FM/DVDThe REQ radio shall support tuner requirements for USA, ROW, and Japan markets as defined in PF-11056The RET radio shall support tuner requirements for ECE market as defined in PF-11056The REL radio shall support tuner requirements for ECE, ROW and Japan markets as defined in PF-11056The radio shall meet requirements for “CD Player/Changer” as defined in PF-11056.The radio shall meet requirements for the "DVD Player/Changer" as defined in PF-11056. In addition, radio shall follow the region coding implementation specified in NTG4 System SRS.The REQ radio with SDAR shall meet requirements for the "Integrated Satellite Radio" as defined in PF-11056.The radio parts with 83.3 kbps CAN bus shall meet requirements for CAN-B body bus as defined in PF-11056.The radio parts with 125 kbps CAN bus shall meet requirements for I-HS body bus as defined in PF-11056.5.2 Connector RequirementsThe radio shall use the 54-Way connector that consists of one 22-Way radio connector, one 10-Way HFM connector, and one 22-Way VES connector as defined below.54-Way Radio Connector Tyco Part Number 1438772-1The radio shall meet the requirements for the "22-Way Radio Connector" as defined in PF-11056.The radio shall meet the requirements for the "10-Way HFM Connector" as defined in PF-11056.The radio shall meet the requirements for the "22-Way VES Connector" as defined in PF-11056, with the following exceptions:- Video Input from VES is not supported.- Video Input from backup camera is not supported.The radio shall meet the requirements for the "RF Connectors" as defined in PF-11056, with the following exceptions:- Satellite Radio Input is supported only for REQ radios with Integrated Satellite Radio option.5.3 DVD Player/Changer RequirementsThe DVD player/changer shall support the following media formats: CDDA, CD-R, CD-RW, MP3, WMA, DVD Video, DVD Audio, DVD-R, DVD-RW, DVD+R, DVD+RW, DVD-ROM, SACD(CD layer), and CDDA+MP3.The following exceptions apply to the DVD Player/Changer requirements of PF-11056.For the DVD changer REQ/RET radio, Fast Forward Time (DVDC FFT) shall be between 5.1 and 5.6 seconds; Fast Rewind Time (DVDC RWT) shall be between 4.8 and 5.3 seconds.For the single DVD player REL radio, Fast Forward Time (DVD FFT) shall be between 5.1 and 5.6 seconds; Fast Rewind Time (DVD RWT) shall be between 4.6 and 5.1 seconds.5.4 Control RequirementsRefer to the control requirements section of PF-11056 except for items specifically mentioned in this section.5.5 DVD Player/Changer Common Mechanical RequirementsRefer to the DVD player/changer common mechanical requirements section of PF-11056 except for items specifically mentioned in this section.5.6 IOD RequirementThe ignition off current draw shall not exceed 0.3 mA.5.7 SDARS RequirementsUpon each ignition cycle as well as when the integrated SDAR module is in full power mode, radio shall check for the connection of the SDARS antenna based on the following two status bits sent by the integrated SDAR module. If the antenna is not connected, radio shall set the fault(s) as defined in the radio DDT.TABLE 3: SDARS FAULT SETTINGS CRITERIAAudio/Data Output Status Antenna ConnectionStatusLow-line NTG4Radio DisplayDTC0 0 Normal Display0 1 Normal Display Set DTC1 0 "ACQUIRING SIGNAL"1 1 "***NO SIGNAL***" Set DTCAudio/Data Output Status:0 = audio/data present at output (OK)1 = loss of audio/data at output Antenna Connection Status:0 = antenna connected1 = antenna disconnected5.8 Fan RequirementsRefer to the fan requirements section of PF-11056 except for items specifically mentioned in this section. The fan shall operate while ignition is on and the radio internal temperature rises to a level requiring fan operation. The fan operation shall be independent of the engine RPM.6.0 FUNCTIONAL REQUIREMENTSThe radio shall meet the functional requirements of the following documents unless a later revision is released by a CN.- Refer to the Functional Requirements section of PF-11056.- Refer to “NTG4 Low Line VF Display Screen Requirements, Version 1.4” for VF Display Layouts. - Refer to “NTG4 Low Radio SRS, Revision 3 (7/26/05)” for radio local behavior requirements. - Refer to “NTG4 System SRS, Version 1.3” for system behavior requirements.- Refer to “DaimlerChrysler Core Radio DSP Personalization Parameters for 2007 Next Telematics Generation 4 Radios, Version 0.1”- Refer to CAN Mailbox for VMM 529. The 83.3k radios shall use CAN-B. The 125k radios shall use CAN-I-HS. All radios shall use the “RADIOwSDARS” messaging. - Refer to Radio DDT 2.01.000- Refer to Process Standard PS-11024.The RET and REL radio shall comply with the antitheft requirements defined in PF-11056 but radio is not required to have an anti-theft LED. Refer to NTG4 System SRS for implementation details.7.0 RELIABILITY/DURABILITY REQUIREMENTSRefer to the Reliability/Durability Requirements section of PF-11056 except for items specifically mentioned in this section.ED, DV, and PV testing shall be performed with a combination of REQ, RET, and REL radios to take advantage of common architecture and components among the three variations. - Variant 1: with SDAR vs. without SDAR;- Variant 2: 6-DVD mechanism vs. 1-DVD mechanism;- Variant 3: low speed CAN bus 83.3 kbps vs. high speed CAN bus 125 kbps.For ED testing, the radio shall follow the test flow described in Table 3.TABLE 4: ED TEST LAYOUTSample SizeLeg A B C DRET-LW/MW/FM/6-DVD (CAN Body- 83.3k) 05064127AARET-LW/MW/FM/6-DVD (CAN Body- 125k) 05064055AA2 1 1 1REL-LW/MW/FM/DVD (CAN Body- 83.3k) 05107096AAREL-LW/MW/FM/DVD (CAN Body- 125k) 05064053AAREQ-AM/FM/6-DVD (CAN Body- 83.3k) 05064111AAREQ-AM/FM/6-DVD (CAN Body- 125k) 05107099AA2 2 2 1 REQ + RSC-AM/FM/6-DVD /SDARS(CAN Body- 83.3k) 05064112AAREQ + RSC-AM/FM/6-DVD /SDARS (CAN Body- 125k) 05064113AATotal Sample Size 4 3 3 21 Burn-In Burn-In Burn-In Burn-In2 FullParametr icsFull Parametrics Extreme Parametrics ExtremeParametrics3 EMC CEOT Media MediaTABLE 4: ED TEST LAYOUTSample SizeLeg A B C DElectrical Temperature Rise TemperatureRise4 FullParametricsFull Parametrics Skip Immunity SkipImmunity5 Parametric Subset ParametricSubset6 Audio Output Timing Speaker DCOffset7 8Notes:1. REQ radio with SDAR and REL radio parts are not available in ED phase for a complete ED testing.2. REQ radio with SDAR shall at least run the following leg as a partial ED testing (two samples).Test 1: Burn InTest 2: Full ParametricsTest 3: Media Temperature Rise (radio in SDAR mode)Test 4: Vibration (At the end of each axis, run functional test in CD/DVD mode, and check the media for damage)Test 5: Parametric SubsetTest 6: Audio Output Timing (SDAR mode)3. REL radio shall at least run the following leg as a partial ED testing (two samples).Test 1: Burn InTest 2: Full ParametricsTest 3: Media Temperature Rise Test 4: Skip ImmunityTest 5: Vibration (At the end of each axis, run functional test in CD/DVD mode, and check the media for damage)Test 6: Parametric SubsetTest 7: Audio Output Timing (DVD mode)For DV and PV testing, the radio shall follow the test flow described in Table 5, Table 6 and Table 7.TABLE 5: DV/PV TEST LAYOUT (PART 1)Sample SizeLeg A B1 B2 C D1 D2 E1RET-LW/MW/FM/6-DVD (CAN Body- 83.3k) 05064127AARET-LW/MW/FM/6-DVD (CAN Body- 125k) 05064055AA3 2REL-LW/MW/FM/DVD (CAN Body- 83.3k) 05107096AA3 2 3 2 1 REL-LW/MW/FM/DVD (CAN Body- 125k) 05064053AA2 3 3 2 1 REQ-AM/FM/6-DVD (CAN Body- 83.3k) 05064111AAREQ-AM/FM/6-DVD (CAN Body- 125k) 05107099AAREQ + RSC-AM/FM/6-DVD /SDARS(CAN Body- 83.3k) 05064112AA2 1 2 3REQ + RSC-AM/FM/6-DVD /SDARS (CAN Body- 125k) 05064113AA5 2 2Total Sample Size 10 4 4 2 12 8 4TABLE 5: DV/PV TEST LAYOUT (PART 1)Sample SizeLeg AB1B2CD1D2E1 RET-LW/MW/FM/6-DVD (CAN Body-83.3k) 05064127AARET-LW/MW/FM/6-DVD (CAN Body- 125k)05064055AA3 2REL-LW/MW/FM/DVD(CAN Body- 83.3k)05107096AA3 2 3 2 1REL-LW/MW/FM/DVD(CAN Body- 125k)05064053AA2 3 3 2 1REQ-AM/FM/6-DVD(CAN Body- 83.3k)05064111AAREQ-AM/FM/6-DVD(CAN Body- 125k)05107099AAREQ + RSC-AM/FM/6-DVD /SDARS(CAN Body- 83.3k)05064112AA2 1 2 3REQ + RSC-AM/FM/6-DVD /SDARS(CAN Body- 125k)05064113AA5 2 2Total Sample Size 10 4 4 2 12 8 4 Test 1 Dimensional Critical InspectionTest2 Burn-In Burn-In Burn-In Burn-In Burn-In Burn-In Burn-InTest 3 ParametricSubset ParametricSubsetParametricSubsetParametricSubsetParametricSubsetMechanicalParametricSubsetFullParametricsTest 4 SSTE ThermalHumidityCycle ThermalHumidityCycleThermalHumidityCycleBSR SMOAE(ME)HTOE(3/4)Test 5 ParametricSubset ParametricSubsetParametricSubsetParametricSubsetParametricSubsetMechanicalParametricSubsetFullParametricsTest 6 LTOE MechanicalShock MechanicalShockMechanicalShockSMOAE(ME)SolarRadiationSoakHTOE(1/4)Test 7 ParametricSubset ParametricSubsetParametricSubsetParametricSubsetMechanicalParametricSubsetPackage Drop ParametricSubsetTest 8 ThermalShock Dust Dust Dust ParametricSubsetTest 9 ParametricSubset ParametricSubsetParametricSubsetParametricSubsetTest 10 Vibration Fan Noise HandlingDropTest 11 ParametricSubset Parametric SubsetTest 12 ChemicalExposure -Cabin Test 13 ParametricSubsetTABLE 6: DV/PV TEST LAYOUT (PART 2)Sample SizeLeg E2 F G H I J K RET-LW/MW/FM/6-DVD (CAN Body-83.3k) 05064127AA1RET-LW/MW/FM/6-DVD (CAN Body-125k) 05064055AA3REL-LW/MW/FM/DVD(CAN Body- 83.3k)05107096AA2 3 1 1 1 3 1REL-LW/MW/FM/DVD(CAN Body- 125k)05064053AA1 2 3 2 2 3 1REQ-AM/FM/6-DVD(CAN Body- 83.3k)05064111AAREQ-AM/FM/6-DVD(CAN Body- 125k)05107099AAREQ + RSC-AM/FM/6-DVD/SDARS(CAN Body- 83.3k)05064112AA3 1REQ + RSC-AM/FM/6-DVD/SDARS(CAN Body- 125k)05064113AA3 5 9 3 3 1Total Sample Size 6 10 14 6 6 12 4 Test 1 Dimensional Critical InspectionTest 2 Burn-In Burn-In Burn-In Burn-In Burn-In Burn-In Burn-InTest 3 ParametricSubsetFullParametricsParametricSubsetFullParametricsFullParametricsParametricSubsetParametricSubsetTest 4 HTOE(3/4) HTHE(3/4) PTCE Fan Noise LightingSubsetLighting EMC/ElectricalTest 5 ParametricSubsetExtremeParametricsParametricSubsetLightingSubsetPTCE(3/4) Faceplate&Media TempRiseParametricSubsetTest 6 HTOE(1/4) HTHE(1/4) PTCE(3/4) FullParametricsCD/DVDImmunity toSkipAudio FeedthroughTest 7 ParametricSubset ParametricSubsetFullParametricsLightingSubsetAudioOutputTimingTest 8 LightingSubset PTCE(1/4) SpeakerDCOffsetTest 9 Fan Noise ParametricSubset Test10 PTCE(1/4)Test 11 ParametricSubset Test12Test13TABLE 7: DV/PV TEST LAYOUT (PART 3)Sample SizeLeg M1M2O1O2 RET-LW/MW/FM/6-DVD (CAN Body-83.3k) 05064127AA1RET-LW/MW/FM/6- 2TABLE 7: DV/PV TEST LAYOUT (PART 3)Sample SizeLeg M1M2O1O2 DVD (CAN Body-125k) 05064055AAREL-LW/MW/FM/DVD(CAN Body- 83.3k)05107096AA2REL-LW/MW/FM/DVD(CAN Body- 125k)05064053AA3 2 3REQ-AM/FM/6-DVD(CAN Body- 83.3k)05064111AA2REQ-AM/FM/6-DVD(CAN Body- 125k)05107099AA3REQ + RSC-AM/FM/6-DVD/SDARS(CAN Body- 83.3k)05064112AA3 3 2REQ + RSC-AM/FM/6-DVD/SDARS(CAN Body- 125k)05064113AA4Total Sample Size 10 10 5 5Test 1 Dimensional Critical InspectionTest 2 Burn-In Burn-In Burn-In Burn-InTest 3 FullParametrics ParametricSubsetParametricSubsetParametricSubsetTest 4 VehicleEnduranceVehicleEnduranceSMOAE(SwitchEndurance)WaterIntrusionTest 5 MechanicalParametricSubset Parametric SubsetTest 6 WaterIntrusionTest 7 ParametricSubsetTest 8Test 9Test 10Test 11Test 12Test 13Dimensional Critical Inspection samples may come from any leg(s).HTOE, HTHE, PTCE tests shall use Parametric Evaluation Technique (PET) analysis.For the 6- DVD changer mechanism, PET analysis shall be performed using 5 homogenous samples of REQ+RSC(CAN Body - 125k) for both HTOE and HTHE tests. In addition, PET analysis shall be performed using 15 homogenous samples of REQ+RSC(CAN Body – 125k) on PTCE tests.For the single DVD mechanism, PET analysis on PTCE tests shall be performed using 10 samples of REL(CAN Body – 83.3k & 125k). PET analysis on HTOE and HTHE tests shall be performed using 5 samples of REL (CAN Body – 83.3k & 125k).Test 10 and 11 in leg C and Test 6, 7 and 8 in leg D2 applies to PV only.8.0 PRODUCT ASSURANCERefer to the Product Assurance section of PF-11056.9.0 TESTING REQUIREMENTSRefer to the Testing Requirements section of PF-11056 except for items specifically mentioned in this section.The radio shall meet all homologation requirements for ECE market as defined in the packaging model.10.0 DEFINITIONS/ABBREVIATIONS/ACRONYMSRefer to the Definitions/Abbreviations/Acronyms section of PF-11056.11.0 GENERAL INFORMATIONThree asterisks “***” after the section/paragraph header denotes single or multiple technical changes to the section/paragraph.Certain important information relative to this standard has been included in separate standards. To assure the parts submitted meet all of DaimlerChrysler requirements, it is mandatory that the requirements in the following standards be met.CS-9800 - Application of this standard, the subscription service, and approved sourcesCS-9003 - Regulated substances and recyclabilityQS-9000 - Quality system requirementsCS-CORROSIONWithin Engineering Standards, the Regulatory (Government-mandated) requirements are designated by <S> and <E> which correspond to Safety and Emission Shields respectively. The DCC-mandated requirements are designated by <D> and correspond to the Diamond symbol respectively.For specific information on this document, please refer to the contact person shown in the "Publication Information" Section of this document. For general information on obtaining Engineering Standards and Laboratory Procedures, see CS-9800 or contact the Engineering Standards Department atengstds@.12.0 REFERENCESCS-9003CS-9800CS-CORROSIONPF-8500PS-7000PS-1285PS-8810PF-11056PS-11024CPM-583, 526DaimlerChrysler, "Product Assurance Testing" manual (84-231-1311)“Quality System Requirements QS-9000”DaimlerChrysler Process Sign-Off (84-231-1227)The following documents may be obtained from the radio core releasing engineer:PF-11089, Change -, 2005-09-29, Page 11Copyright DaimlerChrysler Corporation (2003-07-08) NTG4 Low Line VF Display Screen RequirementsNTG4 Low Radio SRSNTG4 System SRS“DaimlerChrysler Core Radio DSP Personalization Parameters for 2007 Next Telematics Generation 4 Radios”Radio DDT13.0 ENGINEERING APPROVED SOURCE LISTTABLE 8: ENGINEERING APPROVED SOURCE LISTDescription Supplier Supplier Code Manufacturer's Part NumberREQ - AM/FM/6-DVD (83.3k) Alpine 26777 05064111AAREQ+RSC - AM/FM/6-DVD/SDARS (83.3k) Alpine 26777 05064112AARET (EU) - LW/MW/FM/6-DVD (83.3k) Alpine 26777 05064127AAREL (EU/Japan/ROW) - LW/MW/FM/DVD (83.3k)Alpine 26777 05107096AAREQ - AM/FM/6-DVD (125k) Alpine 26777 05107099AAREQ+RSC - AM/FM/6-DVD/SDARS (125k) Alpine 26777 05064113AARET (EU) - LW/MW/FM/6-DVD (125k) Alpine 26777 05064055AAREL (EU/Japan/ROW) - LW/MW/FM/DVD (125k) Alpine 26777 05064053AA14.0 PUBLICATION INFORMATIONContact/Phone No: Mary Pothen, (248) 576-4499 and Beijing Wang, (248) 576-4473Alternate Contact/Phone No: Hossein Dadkhah, (248) 944-0238, T/L 754-0238Dept. Name & Dept. No./Tech Club/Organization: Audio & Telematics Components, Dept. 6170 Date Standard Originally (Initially) Issued: 2005-09-29Date Published: 2005-09-29Change Notice:Description of Change: Initial Release# # # # #。

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FLY RELIABILITY TEST STANDARDNF TECHNOLOGY SHENZHEN2013FLY 手机可靠性测试标准NF科技深圳2013DISTRIBUTION OF THIS DOCUMENT REQUIRES NF TECHNOLOGY RESEARCH DESIGN AND QUALITY APPROVALDocument Control 文控Document Number 文控编号Fly-NFD002 Version 版本号10.0 Release Date 发布日期2013-01-01 Prepared 起草者Charles Cai Auditor 审计者Brian Preston版本记录Version RecordsRevision Level Author(s)ReleaseDateChange Summary1.0 Ivan Tong 2009-12-19 First of Edition2.0 Ray & Jimmy 2010-01-05 5.5.3 :”12h” change to”24h”。

4.5.5 “six sides four corners”change to “front and rear side” 5K，7CM。

6.1.3: ESD Test change to: Contact Discharge: 5kV AirDischarge: 10kV .Add the Electroacoustical test in section 7.3.0 Jeffrey 2010-03-23 Restructure document4.0 Ivan Tong 2010-07-07 Re-Edition5.0 Ivan & Walle 2010-12-12 Re-Edition6.0 Ivan & Walle 2011-06-27 Re-Edition7.0 Ivan & Walle 2012-03-07 Change Soft pressing test8.0 Ivan Tong 2012-05-17 Change ORT procedure9.0 Ivan Tong 2012-06-01 3.3 Add Carton drop test spec10.0 Charles Cai 2013-01-01 Restructure documentAdded: 3.8 keycap removal testAdded: 3.9 Lens/TP removal testAdded: test figure for 4.1 drop testModified: 4.4 Random vibration test spec. Modified: 4.11 steel ball impact test spec. Modified: 4.13 speaker life test spec.Modified: 4.14 vibrator life test sample size. Modified: 4.15 storage temperature test spec. Modified: 4.16 Damp Heat test sample size. Modified: 4.17 Operational temperatures test spec.本文件属于公司秘密信息，请您恪守保密义务，勿向第三人透露。

谢谢合作。

This file is confidential. Recipient(s) is(are) obligated to maintain secrecy and is(are) not permitted to disclose the contents of this file to others. Thank you.Table of Content 目录1INTRODUCTION 介绍 (6)2FUNCTIONAL VERIFICATION TESTS (7)2.1Baseline (7)2.2Device Assembly / Disassembly Functional Verification Test (10)3COMPONENT / ACCESSORIES TEST (11)3.1RCA Abrasion Test RCA测试 (11)3.2Label abrasion test (Alcohol test)酒精测试 (12)3.3Peeling off（ Cross cutting ） test 百格测试 (13)3.4Pencil Hardness Test 铅笔硬度测试 (14)3.5Bolt Torque Test 螺钉扭矩测试 (16)3.6Man-hand Sweat Corrosion Test 耐手汗测试 (16)3.7Neck Strap Pulling Test挂绳孔拉力测试 (17)3.8Key cap removal test 键帽拉拔力测试 (18)3.9Lens/ TP removal test 镜片/触摸屏拉拔力测试 (19)3.10Safety – Battery 电池 (20)3.11Safety – Charger 充电器 (20)4HANDSET TEST (21)4.1Drop Test - Face Impact 跌落试验 (21)4.2Drop Test - with Gift box 彩盒跌落试验 (23)4.3Drop Test - with Carton box 卡通箱跌落试验 (26)4.4Vibration Test – Random 振动试验—随机 (28)4.5Micro-Drop test 微跌测试 (31)4.6Tumbling box Test 滚筒测试 (32)4.7Twist test 扭曲试验 (33)4.8Soft Compressing Test软压测试 (34)4.9Touch panel sliding durability test 触摸屏划线试验 (35)4.10Touch panel hitting durability test触摸屏点击测试 (36)4.11Display Area Impact Test(Steel ball impact test) 显示区冲击测试(钢球冲击测试) (38)4.12Button, Connector and Device Mechanics Life Tests 按钮，连接器和手机组件寿命测试 (40)4.13Speaker –Life test 扬声器寿命测试 (42)4.14Vibrator–Life test 振动器寿命测试 (43)4.15Storage Temperature (non-operating) test 温度存储实验 (44)4.16Damp heat storage (45)4.17Operational Temperatures test 高低温运行测试 (46)4.18Thermal shock Test 冷热冲击 (47)4.19Temperature Charging Test - 高低温充电测试 (48)4.20Salt test 盐雾试验 (49)4.21Sand and Dust Ingress Test (Dust test) 沙尘试验 (50)4.22ESD - Device-level 静电测试 (51)5ON GOING RELIABILITY TEST (ORT) 可靠性测试 (53)1 INTRODUCTION 介绍The intent of this document is to provide the hardware reliability guidelines for specified the developer of Fly products. The test profiles in this document are designed to meet or exceed the reliability and durability expectation from normal customer usage. These test profiles should be utilized by all validation tests during the product development cycle.All Fly products are expected to meet the requirements outlined in this document. NF technology reserves the right to validate any or all of the tests performed by its suppliers. Validation may include on-site witnessing during test execution, and/or auditing of formal test reports. All tests data shall be made available to NF technology for verification. Unless otherwise specified, all samples must pass all relevant test specifications outlined in this document.2 FUNCTIONAL VERIFICATION TESTS2.1 Baseline2.1.1 PurposeTo demonstrate that the device‘s features function properly at ambient conditions. These functional verifications are typically conducted at pre- and post- of each Reliability test.在适当的环境下演示手机性能，这些性能的验证一般在可靠性测试之前或之后执行。

2.1.2 样品量Perform on all samples in Mechanical-Component Tests, Mechanical-Dynamic,Environmental / Climatic Tests, and Reliability Tests.所有需做结构件测试，环境气候测试和可靠性测试的样机。