数字逻辑设计及应用课程讲稿

第一次课：
课程介绍及要求一学时
课程教学内容安排：
第一章引论
第二章数系与代码
第三章数字电路
第四章组合逻辑设计原理
第五章组合逻辑设计实践
第七章时序逻辑设计原理
第八章时序逻辑设计实践
第十章存储器及其在数字逻辑系统实现中的运用
第十一章其他的实际问题
补充内容模数转换器、数模转换器(ADC/DAC)原理及应用简介
课程教学时间安排：
第一章引论（计划学时数：2学时）
介绍数字逻辑电路的特点、数字逻辑电路在电子系统设计中的地位、数字逻辑电路与模拟电子电路之间的关系、简单介绍EDA设计工具、VHDL语言对数字逻辑设计作用和影响。

第二章数系与代码（计划学时数：6学时）
十进制、二进制、八进制和十六进制数的表示方法以及它们之间的相互转换、非十进制数的加减运算；
符号数的表达格式以及它们之间的相互转换以及带符号数的补码的加减运算；
BCD码、格雷码的特点，它们与二进制数之间的转换关系；简介二进制数的浮点数表达（补充）；
第三章数字电路（计划学时数：4学时）
作为电子开关运用的二极管、双极型晶体管、MOS场效应管的工作方式；以CMOS倒相器电路的构成及工作状态分析；
逻辑电路的静态、动态特性分析，等价的输入、输出模型；
特殊的输入输出电路结构：CMOS传输门、施密特触发器输入结构、三态输出结构、漏极开路输出结构；学习了解其他类型的逻辑电路： TTL,ECL等；
不同类型、不同工作电压的逻辑电路的输入输出逻辑电平规范值以及它们之间的连接配合的问题。

第四章组合逻辑设计（计划学时数：10学时）
逻辑代数的公理、定理，对偶关系，以及在逻辑代数化简时的作用；
逻辑函数的表达形式：积之和与和之积标准型、真值表；组合电路的分析：逻辑函数表达式的产生过程及逻辑函数表达式的基本化简方法；
组合电路的综合过程：将功能叙述表达为组合逻辑函数的表达形式、逻辑函数表达式的化简—函数化简方法
卡诺图化简方法、使用与非门、或非门表达的逻辑函数表达式、逻辑函数的最简表达形式及综合设计的其他问题：
无关项的处理、冒险问题和多输出逻辑化简的方法。

第五章组合逻辑设计实践（计划学时数：10学时）
利用基本的逻辑门完成规定的组合逻辑功能（如译码器、编码器、多路选择器、多路分配器、异或门、比较器、全加器等）的电路设计任务；
利用基本的逻辑门和已有的逻辑功能电路作为设计的基本元素完成更为复杂的组合逻辑电路设计的方法。

第七章时序逻辑设计原理（计划学时数：10学时）
基本时序元件R-S型,D型,J-K型,T型锁存器、触发器的电路结构，工作原理，时序特性等；扫描触发器(Scan Flip-Flop)特性及基本应用；
钟控同步状态机的模型图，状态机类型及基本分析方法和步骤，使用状态图表示状态机状态转换关系；
时序状态机的设计：状态转换过程的建立，状态的化简与编码赋值、未用状态的处理-最小风险方案和最小代价方案、使用状态转换表的设计方法、使用状态图的设计方法。

第八章时序逻辑设计实践（计划学时数：10学时）
利用基本的逻辑门、时序元件作为设计的基本元素完成规定的钟控同步状态机电路的设计任务：计数器、位移寄存器、序列检测电路和序列发生器的设计；
利用基本的逻辑门和已有的中规模集成电路（MSI）时序功能器件作为设计的基本元素完成更为复杂的时序逻辑电路设计的方法。

时序电路设计中的其他问题：组合电路与时序电路的比较，大型时序电路的结构划分，时钟歪斜，异步输入处理等。

第十章存储器及其在数字逻辑系统实现中的运用（计划学时数：4学时）学习了解：存储器（ROM,SRAM）的基本工作原理和结构；
学习掌握：存储器在数字逻辑系统设计的硬件实现中的运用。

第十一章其他的实际问题（计划学时数：2学时）
数字逻辑电路(组合电路和时序逻辑电路)设计的描述说明方法；
数字逻辑系统设计的其他问题：数字逻辑设计中设计工具的作用、设计的可测试性问题、数字逻辑系统可靠性的问题、高速数字逻辑系统中信号传输的相关问题。

补充内容：模数转换器、数模转换器(ADC/DAC)原理及应用简介（计划学时数：4学时）数字-模拟转换器(Digit to Analog Converter,DAC))的基本电路结构（R-2R结构的DAC），工作原理；
模拟-数字转换器(Analog to Digit Converter,ADC) 的基本电路结构（逐次逼近式的ADC），工作原理；
模拟-数字转换器、数字-模拟转换器(ADC/DAC)在电子系统中的作用和应用，特别是在波形发生方面的运用。

课程教学实验内容安排：
课外上机实验教学（计划学时数：16学时）
实验目的：通过使用CAD设计工具对教材中相关例题的分析，加深对教材内容的理解，更好地掌握相关知识。

1、学习使用PSPICE电路分析工具仿真分析CMOS基本逻辑门的静态特性和动态特性、了解电路结构和负载特性对逻辑门静态特性和动态特性的影响。

2、学习数字逻辑电路仿真工具MAX+plusII的基本使用方法；进行基本组合电路基本功能单元，时序电路的基本功能单元进行仿真，加深对基本功能单元功能作用的理解；对教材中大型例题进行仿真分析，加强对大型综合性设计的分析理解能力。

课程考核
课程考核的内容有：平时课外作业练习；课程随堂练习与测验；期中考试和期末考试。

最终成绩组成：平时成绩占40%，期末考试成绩占60%。

期中考试成绩、平时课外作业练习成绩和随堂练习与测验成绩在平时成绩中分占50%，25%，25%。

数字逻辑电路课程结构
数字逻辑电路与其他课程的相关关系
CHAPTER 1 INTRODUCTION
ANALOG VERSUS DIGITAL
Analog signals are the time-varying signals that can take on any value across a continuous range of voltage or current.
For example: the signal sin(ωt )
Analog circuits and systems process analog signal.
A digital signal is modeled as taking on, at any time, only one of two discrete values(0 or 1, low or high, false or true)
Digital circuits and systems process digital signal.
Digital circuits and systems have many uses in our life :
Still pictures.
Video and audio recordings
Automobile carburetors
The telephone systems
Movie effects 。

Why has there now been a digital revolution?
Reproducibility of results（结果的可重现性）
Easy of design （设计的方便性）
Flexibility and functionality
Programmability
Speed
Economy
Steadily advancing technology
Digital devices
The gates: AND gates OR gates NOT gates (inverter)
The combinational logic gates: NOT-AND (NAND) gates, NOT-OR (NOR) gates,….
The flip-flop devices（触发器）
Electronic Aspects of digital design
See the figure 1-2
Integrated circuits
IC
WAFER
DIE
SSI: SMALL-SCALE INTEGRATION
MSI: MEDIUM -SCALE INTEGRATION
LSI: LARGE -SCALE INTEGRATION
PACKAGE
CHAPTER 2 Number Systems and Codes
2.1 Positional Number Systems
In this system, a number is represented by a string of digits, where each digit position has an associated weight, and the value of a number is a weighted sum of the digits.
For example
A decimal number 1734 can be written as :
1734=1*1000 + 7*100 + 3*10 + 4
=1*103+7*102+3*101+4*100
where, 10 is called the base or radix of the number system, and 103is the weight of the position 3.
In general, a number N of the form n p-1n p-2…n2n1n0 . n-1n-2…n-k ,the radix is r (r≥2),has the value
N= n p-1·r p-1n p-2·r p-2…n2·r2n1·r1n0·r0n-1·r-1n-2·r-2…n-k·r-k
∑--=⋅
=
1
p
k
i
i
i
r
n n
i=?(0,1
…r-1)
If r=2, then n
i
=?(0,1), the number system is BINARY number system.
A binary number
B of the form 10101110, the value is
B=1*27+0*26+1*25+0*24+1*23+1*22+1*21+0*20
=1*128+0*64+1*32+0*16+1*8+1*4+1*2+0*1
=174
We write a binary number as b p-1b p-2…b2b1b0 . b-1b-2…b-k, the leftmost bit is called the most significant bit(MSB), and the rightmost bit is the least significant bit(LSB).
If r=8, then n
i
=?(0,1…7), the number system is OCTAL number system.
If r=16, then n
i
=?(0,1…9,A,B,C,D,E,F), the number system is HEXADECIMAL number system.
When dealing with binary and other nondecimal numbers, we use a subscript to indicate the radix of each number. For examples,
100112 means a binary number
1001110 for a decimal number
17868 for an octal number
178616 for a hexadecimal number. ……
2.3 General Positional-Number-System Conversions
Signed Number Binary Codes
Signed binary numbers provide the means by which both positive and negative numbers may be represented.
Binary signed magnitude convention uses the most significant bit position to indicate sign (sign bit) and the remaining lesser significant bits to represent magnitude.
The sign bit is 0 for positive number, 1 for negative one.
Three main signed number binary codes are used: signed-magnitude code, 2s complement, and 1s complement.
Signed--Magnitude Codes
The most significant bit(MSB) position is 0 for all positive values and 1 for negative value. There are two possible representation of zero, “+0” and “-0”, but both have same value. An n-bit signed-magnitude integer lies within the range : -(2n-1-1) through +(2n-1-1) .
Some 8-bit signed-magnitude integers
+ 85
10 =0 1010101
2
- 85
10
=1 1010101
2
+127
10 =0 1111111
2
-127
10
=1 1111111
2
+ 0
10 =0 0000000
2
- 0
10
=1 0000000
2
2s Complement Number
Number A is a n-bit signed binary code
Way 1: the complement of A is equivalent to {[2n +A]|mod(2n)}. Way 2: If A≥ 0 ,
If A <0 ,
A A
complement
s
=
-
2
]
[
Some examples for 2s complement number
[01010101]2s complement =01010101B (+8510) [11010101]2s complement =10101011B (-8510) [00000000]2s complement =00000000 B (010) [10000000]2s complement means -12810
An n-bit 2’s complement number lies within the range : -(2n-1) through +(2n-1-1) Zero is a positive number [10000000]2s complement means -12810
In any complement system ,we normally deal with a fixed number of digits, n. We can convert an n-bit 2s complement number X into an m-bit one. If m>n, we must append m-n copies of X’s sign bit to the left of X.
If m<n,we discard X’s n -m leftmost bits, the result is valid only if all of the discarded bits are the same as the sign bit of the result.
Get [-A] 2s complement from [A] 2s complement
We have an n-bit complement number [A] 2s complement , to obtain the [-A] 2s complement [-A] 2s complement = 2n - [A] 2s complement EX: [A]2s complement =01010101B
[-A]2s complement =10101011B
1s complement number
Number A is a n-bit signed binary code
If A ≥ 0 ,the complement of A is equivalent to A.
If A <0 , the complement of A is equivalent to 2n -1+A Zero is a positive number
Some examples for 1s complement number [01010101]1s complement =01010101B [11010101]1s complement =10101010B [00000000]1s complement =00000000 B
Get 1s complement from signed magnitude number
We have an n-bit signed-magnitude number A , to obtain the [A] 1s complement .we must to: If A ≥ 0, [A] 1s complement =A
If A<0, save the sign bit of A and complement the remaining lesser significant bits (that is,change 0’s to 1’s and 1’s to 0’s) EX: [A] signed-magnitude =11010101B [A] 1s complement =10101010B
Get 2s complement from 1s complement number
We have [A] 1s complement, By following way ,we can get [A] 2s complement
A
A n
complement s -=-2][2
[A] 2s complement = [A] 1s complement, +1
Ex: [A] 1s complement =10101010B + 1 [A] 2s complement =10101011B
2‘s COMPLEMENT ADDITION AND SUBTRACTION ADDITION RULES
2s-complement number can be added by ordinary binary addition, ignoring any carries beyond the MSB.The result will always be the correct sum as long as the range of the number system is not exceeded. [A+B] 2s complement =
[A] 2s complement +[B] 2s complement EX: +3 0011 -2 1110 + +4 +0100 + -5 + 1011 +7 0111 -7 11001
+6 0110 +4 0100 +-3 +1101 + -7 + 1001 +3 10011 -3 1101
OVERFLOW
If an addition operation produces a result that exceeds the range of the number system,overflow is said to occur.
There is a simple rule for detecting overflow in addition: An addition overflows if the carry bits c in into and c out out of the sign position bit are different.
Using double sign bit to detect overflow
+3 00 011 -2 11 110 ++4 +00 100 + -5 +11 011 +7 00 111 -7 11 001 -3 11 101 +5 00 101 +-6 +11 010 ++6 + 00 110 -9 10 111 +11 01 011 If the sign bits have same sign, the sum is valid; If the sign bits are different , the addition overflows
SUBTRACTION RULE
[A-B] 2s complement =[A] 2s complement +[-B] 2s complement AND [-A] 2s complement = 2n - [A] 2s complement EX: [A]2s complement =01010101B [-A]2s complement =10101011B
Overflow in subtraction can be detected by examining the sign of the minuend and the complemented subtrahend, using the same rule as in addition.
Combinational Logic Design Practices
5.1Documentation Standard（文档要求）
Circuit Specification（说明书）
Block Diagram（方框图）
Schematic Diagram(原理图)
Timing Diagram（定时图）
Structured logic device description
Circuit description
5.1.1 BLOCK DIAGRAM
A block diagram shows the inputs, outputs, function modules, internal data paths,and important control signal of a system.
A good block diagram shows in fig 5-1
Fig 5-2(c) is too much detail
BUS（总线）: A bus is a collection of two or more related signal lines. A slash and a number may indicate how many individual signal lines are contained in a bus( the width of a bus). Sometime size may be denoted in the bus name (e.g., INBUS[31..0]).page 315
5.1.2 GATE SYMBOLS
5.1.3 Signal names and Active level
5.1.4 Active level for pins
5.1.5 Bubble-to-bubble logic design
5.1.6 Drawing layout
line crossings and connections
a single page schematic diagram
flat schematic structure (fig 5-14)
hierarchical schematic structure (fig 5-15)
5.1.7 Buses in schematic diagrams
fig 5-16
5.1.8 Additional schematic information
FIG 5-18
5.2 TIMING DIAGRAM
5.2.1 Timing diagrams
5.2.2 Propagation Delay
We defined the propagation delay of a signal path as the time that it takes for a change at the input of the path to produce a change at the output of the path.
5.2.3 Timing Specifications
t
phl and t
plh
Maximum delay
Typical delay
Minimum delay
5.2.4 Timing Analysis
To accurately analyze the timing of a complex circuit is very difficulty.
A signal worst-case delay specification that is the maximum of t phl and t plh specification. By it, the design time can be saved.
5.4 DECODERS（译码器）
A decoder is a multiple_input, multiple_output logic circuit. The number of circuit input is n_bit and the number of circuit output is 2n.
The most commonly used output code is one-out-of-m code, which contains m bits,
2-to-4 binary decoder with an enable control
The output functions:
Y0=EN·I1’·I0’
Y1=EN·I1’·I0
Y2=EN·I1·I0’
Y3=EN·I1 ·I0
2-to-4 binary decoder circuit with an enable control
3-bit Gray-code output of a mechanical encoding disk
Disk position I2 I1 I0 Binary decoder output
0 0 0 0 Y0=1
45 0 0 1 Y1=1
90 0 1 1 Y2=1
135 0 1 0 Y3=1
180 1 1 0 Y4=1
225 1 1 1 Y5=1
270 1 0 1 Y6=1
315 1 0 0 Y7=1
74X139 Dual 2-to-4 Decoder
the truth table
INPUTS OUTPUTS
G_L B A Y3_L Y2_L Y1_L Y0_L
1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1
The output functions:
Y0_L=G_L+B+A=[G_L’·B’·A’]’
Y1_L=G_L+B+A’=[G_L’·B’·A]’
Y2_L=G_L+B’+A=[G_L’·B·A’]’
Y3_L=G_L+B’+A’=[G_L’·B·A]’
1/2---74X139 74X139
74X138 3-to-8 Decoder
The truth table
INPUTS OUTPUTS
G1 G2A G2B C B A Y7Y6Y5Y4Y3Y2Y1Y0
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
Y1_L=EN_L+C+B+A’ =[EN·C’·B’·A]’
Y2_L=EN_L+C+B’+A =[EN·C’·B·A’]’
Y3_L=EN_L+C+B’+A’ =[EN·C’·B·A]’
Y4_L=EN_L+C’+B+A =[EN·C·B’·A’]’
Y5_L=EN_L+C’+B+A’ =[EN·C·B’·A]’
Y6_L=EN_L+C’+B’+A =[EN·C·B·A’]’
Y7_L=EN_L+C’+B’+A’ =[EN·C·B·A]’
EN_L= G1’+G2A_L+G2B_L ;
EN= G1·G2A_L’·G2B_L’
ONE FACT:
Y0=EN·(I1’·I0’)
Y1=EN·(I1’·I0)
Y2=EN·(I1·I0’)
Y3=EN·(I1 ·I0)
Y0_L=G_L+B+A=[G_L’·B’·A’]’=[G_L+(B’·A’)’]
Y1_L=G_L+B+A’=[G_L’·B’·A]’ =[G_L+(B’·A)’]
Y2_L=G_L+B’+A=[G_L’·B·A’]’ =[G_L+(B·A’)’]
Y3_L=G_L+B’+A’=[G_L’·B·A]’ =[G_L+(B·A)’]
Y0_L = [G1·G2A_L’·G2B_L’·C’·B’·A’]’
=(EN_L) +(C’·B’·A’)’
Y1_L= (EN_L)+(C’·B’·A)’
Y2_L= (EN_L)+(C’·B·A’)’
Y3_L= (EN_L)+(C’·B·A)’
Y4_L=(EN_L)+(C·B’·A’)’
Y5_L= (EN_L)+(C·B’·A)’
Y6_L= (EN_L)+(C·B·A’)’
Y7_L= (EN_L)+(C·B·A)’
ONE OUTPUT OF DECODER MAP TO ONE MINTERM (OR THE NOT, IF THE OUTPUT IS LOW ACTIVE).
A 4-to-16 decoder using two 74x138
A 5-to-32 decorder with 4 74x138 and 1/2 74x139
EX1: The truth table shows in table 5-11. design the logic circuit with 74x138.
=[( CS_L+RD_L)’·( A2’·A1’·A0’)]’
MARY_L=[CS_L’·RD_L’·A2’·A1’·A0’+CS_L’·RD_L’·A2’·A1’·A0]’ =[(CS-L+RD_L)’·(A2’·A1’·A0’+A2’·A1’·A0)]’
KATE_L=[(CS-L+RD_L)’·(A2’·A1’·A0+A2·A1·A0)]’
JOAN_L=[( CS_L+RD_L)’·( A2’·A1·A0’)]’
PAUL_L=[( CS_L+RD_L)’·( A2’·A1·A0)]’
ANNA_L=[( CS_L+RD_L)’·( A2·A1’·A0’)]’
FRED_L=[( CS_L+RD_L)’·( A2·A1’·A0)]’
DAVE_L=[( CS_L+RD_L)’·( A2·A1·A0’)]’
EX2: To bluid the logic function by 74x138
F=ΣWXYZ(3,6,9,11,13,15)
Let m i for the minterm i
F=ΣWXYZ(3,6,9,11,13,15)=m3+m6+m9+m11+m13+m15 =[ m3’·m6’·m9’·m11’·m13’·m15’]’
SEVEN-SEGMENT DECODERS
INPUT: 8421 BCD CODE,
BI_L(BLANKING INPUT)
OUTPUT: SEVEN-SEGMENT CODE
THE CIRCUIT SHOWN IN FIGTURE 5-45 PAGE 373
5.5 ENCODERS
THE OUTPUT CODE HAS FEWER BITS THAN THE INPUT CODE. BINARY ENCODERS
INPUTS: 1- OUT- OF-M CODE
Y0=I7+I5+I3+I1
Y1=I7+I6+I3+I2
Y2=I7+I6+I5+I4
TIME.
PRIORITY ENCODERS (优先权编码器)
INPUT: BINARY CODE
OUTPUT: THE CODE NUMBER OF THE HIGHEST PRIORITY REQUESTOR.
AND THE OTHER IS THE CIRCUIT WHICH CONVERS THE BINARY CODE INTO 1-OUT-OF –M CODE.
H4=I4·I5’·I6’·I7’
H3=I3·I4’·I5’·I6’·I7’
H2= I2·I3’·I4’·I5’·I6’·I7’
H1= I1·I2’·I3’·I4’·I5’·I6’·I7’
H0= I0·I1’·I2’·I3’·I4’·I5’·I6’·I7’
THE 74X148 PRIORITY ENCODER
THE TRUTH TABLE:
EO_L: ENABLE OUTPUT SIGNAL(NEXT CHIP CONTROL SIGNAL)
GS_L: GROUP SELECT SIGNAL(MEANS THE OUTPUT OF THIS CHIP ARE AVAILABLE)
THE CIRCUIT SHOWN IN FIG 5-50
SIGNAL GS3_L, GS2_L, GS1_L, GS0_L DETERMINE THE OUTPUT RA5, RA4. 习题：
5.8, 5.9, 5.18, 5.19, 5.21, 5.36, 5.39, 5.40, 5.45, 5.46, 5.82 5.85,5.89
5.6 THREE-STATE DEVICES
ONE LOGIN INPUT ;
ONE OUTPUT CONTROL SIGNAL (INPUT); ONE OUTPUT SIGNAL. IF THE OUTPUT SIGNAL IS ASSERTED, THE DEVICE BEHAVES LIKE AN ORDINARY LOGIC DEVICE; IF THE OUTPUT SIGNAL IS NEGATED, THE DEVICE OUTPUT “FLOATS ”; THAT IS , IT GOES TO A HIGH-IMPEDANCE(HI-Z).
THREE-STATE DEVICES ALLOW MULTPLE SOURCE TO SHARE A SINGLE ‘PARTY LINE ’, AS LONG AS ONLY ONE DEVICE “TALK ” ON THE LINE AT A TIME.
FIGHTING: IF BOTH DEVICES WERE TO DRIVE THE PARTY LINE AT THE SAME TIME,AND IF BOTH WRER TRYING TO MAINTAIN OPPOSITE OUTPUT VALUES( 0 AND 1), THEN EXCESSIVE CURRENT WOULD FLOW AND CREAT NOISE IN THE SYSYTEM. THIS IS CALLED FIGHTING.
DEAD TIME: THE TIME ON THE PARTY LINE WHICH NO DEVICE IS DRIVING IT.
STANDARD THREE-STATE DEVICES
4 THREE-STATE NONINVERTING BUFFER 74X125, 74X126, 74X12
5 WITH AN ACTIVE LOW ENABLE, 74X12
6 WITH AN ACTIVE HIGH ENABLE. 74X244, 74X541 OCTAL NONINVERTING
THREE-STATE BUFFER.
74X245 OCTAL BI-DIRECTION THREE-STATE TRANCEIVER.
5.7 MULTIPLEXERS （多路选择器）
A multiplexer is a digital switch, it connects data from one of n sources to its output.
here, iY is a particular output bit, and variable iD J is input of source J. M J represents minterm J of the s select input.
2-input 1-bit multiplexer
EN I1 I0 S OUTPUT 0
X
X
X
0 1 I1X I0X 1 I1X 1 I1X I0X 0 I0X
OR GATE
ENABLE SOURCE INPUT
DECODE OUTPUT AND
GATES AS THE
SWITCHE
S
OUTPUT
74X151: 8-INPUT, 1-BIT MULTIPLEXER(8选一)
74X251：8-INPUT, 1-BIT MULTIPLEXER WITH 3-STATE OUTPUT
32/1 MULTIPLEXER USING 74X151
EX: SHOW HOW TO BUILD THE FOLLOWING LOGIC FUNCTION USING 74X151.
(2,4,6,14)
F=Σ
ABCD
F=A’B’CD’+A’BC’D’+A’BCD’+ABCD’
=(A’B’C+A’BC’+A’BC+ABC)D’
=D’Σ
(1,2,3,7)
ABC
MULTIPLEXER, DEMULTIPLEXER, AND BUSES
EXCLUSIVE-OR GATES AND PARITY CIRCUIT
XOR X=W_L
5.8.2 PARITY CIRCUITS
N XOR GATES MAY BE BUILD AN ODD PARITY CIRCUIT, BACAUSE ITS OUTPUT IS 1 IN AN ODD NUMBER OF ITS INPUTS ARE 1. IF THE OUTPUT OF THE ODD-PARITY CIRCUIT IS INVERTED, WE GET AN EVEN-PARITY CIRCUIT,WHOSE OUTPUT IS 1 IF AN EVEN NUMBER OF ITS INPUT ARE 1.
FIG 5-74
5.8.3 74X280 9-BIT PARITY GENERATOR
随堂练习：
1. FIND THE MINIMUM SUM OF PRODUCTS:
F=Σ
(0,2,3,5,7,8,10,12,13)
WXYZ
F=AD+AB+A’CD’+B’CD+A’BC’D
F =Σ
(0,1,2,5,7,9)+D(6,8,11,13,14,15)
WXYZ
2. Determine any static-0 or static-1 hazards in the follow equation.
(5,7,8,9,10,11,13,15)
F=Σ
ABCD
习题：
REPEAT DRILL 5.19(A),(B),(D), TRY USING 74X151
5.20, 5.21, 5.48, 5.54, 5.60, 5.61, 5.62
5.9 comparators
a circuit that compares two binary words and indicates whether they are equal is called a comparator.
Some comparators interpret their input words as signed or unsigned numbers and also indicate an arithmetic relationship ( greater or less than) between the words. These devices are often called magnitude comparators.
Comparator structure
1 BIT COMPARATOR
The logic function:
DIFF=A 0B 0’+A 0’B 0
The truth table and the circuit: 4-bit comparator:
ITERATIVE CIRCUITS
An iterative circuit is a special type of combinational circuit, with the structure shown in figure5-79. The circuit contains n identical modules, each of which has both primary inputs and primary outputs and cascading inputs and
outputs. A simple iterative algorithm:
1. SET C 0 TO ITS INITIAL VALUE AND SET i TO 0
2. Use C i and PI i to determine the value of PO i and C i+1
3. Increment i
4.
If i<n, go to step 2
The iterative structure
An iterative comparator circuit 1.set EQ 0 to 1 and set i to 0
2.if EQ i is 1 and X i and Y i are equal, set EQ i+1 to 1. else set EQ i+1 to 0.
3.increment i
A0
B0 DIFF
0 0 0
0 1 1
1 0 1 1 1
4.if i<n , go to step 2
The iterative comparator has less cost than the parallel comparator shown in fig 5-78.
STANDARD MSI COMPARATOR
The 74x85 (fig 5-81) is a 4-bit comparator with a greater-than, less-than and equal-to output, and has cascading inputs(greater-than, less-than and equal-to). The logic functions:
AGTBOUT=(A>B)+(A=B)?AGTBIN
AEQBOUT=(A=B)?AEQBIN
ALTBOUT=(A<B)+(A=B)?ALTBIN
AND
A>B=A
3?B
3
’+(A
3
⊕B
3
)’?A
2
?B
2
’
+(A
3
⊕B
3
)’ ?(A
2
⊕B
2
)’?A
1
?B
1
’
+(A
3
⊕B
3
)’ ?(A
2
⊕B
2
)’ ?(A
1
⊕B
1
)’?A
?B
’
…..
SEE PAGE
ARITHMETIC CONDITIONS DERIVED FROM COMPARATOR’S OUTPUTS
AGTB ALTB AEQB AGEB ATEB ANEB
0 1 0 0 1 1
1 0 0 1 0 1
0 0 1 1 1 0 ADDERS, SUBTRACTORS
HALF ADDERS AND FULL ADDERS
HALF ADDER
SUM=X⊕Y=X?Y’+X’?Y
CO= X?Y
FULL ADDER
SUM=X⊕Y⊕C
IN
=X?Y’?C
IN ’+X’?Y?C
IN
’+X’?Y’?C
IN
+X?Y?C
IN
C
OUT =X?Y+C
IN
?(X+Y)
THE CIRCUIT SHOWN IN FIGURE 5-86
RIPPLE ADDERS
A ripple adder is a iterative circuit, shown in fig 5-87 the maximun propagate delay
Subtractors
From the table 2-3
D=X⊕Y⊕BIN
BOUT=X’?Y+BIN?(X’+Y)
=X’?Y+BIN?X’+BIN?Y
BOUT’ =(X+Y’)?(X+BIN’)?(Y’+BIN’)
=X?Y’+BIN’?(X+Y’)
D= X⊕Y⊕BIN= X⊕Y’⊕BIN’
COMPARE WITH THE FULL ADDER:
SUM= X⊕Y⊕CIN
COUT =X?Y+CIN?(X+Y)
D= X⊕Y⊕BIN= X⊕Y’⊕BIN’
BOUT’ =X?Y’+BIN’?(X+Y’)
THE SUBTRACTOR IS SHOWN FIG 5-88
CARRY LOKAHEAD ADDERS
S
i = X
i
⊕Y
i
⊕C
i
C
i+1 =X
i
?Y
i
+C
i
?(X
i
+Y
i
)
LET G
i = X
i
?Y
i
P
i =X
i
+Y
i
SO C
i+1=G
i
+P
i
?C
i
C1=G0+P0?C0
C2=G1+P1?C1=G1+P1?(G0+P0C0)
=G1+P1?G0+P1?P0?C0
C3=G2+P2?C2
=G2+P2?G1+P2?P1?G0+P2?P1?P0?C0
C4=G3+P3?C3
=G3+P3?G2+P3?P2?G1+P3?P2?P1?G0
+P3?P2?P1?P0?C0
运用：用加法器实现补码的加减运算。

随堂练习：
1. FIND THE MINIMUM SUM OF PRODUCTS:
(0,2,3,5,7,8,10,12,13)
F=Σ
WXYZ
F=AD+AB+A’CD’+B’CD+A’BC’D
F =Σ
(0,1,2,5,7,9)+D(6,8,11,13,14,15)
WXYZ
2. Determine any static-0 or static-1 hazards in the follow equation.
(5,7,8,9,10,11,13,15)
F=Σ
ABCD
习题：
REPEAT DRILL 5.19(A),(B),(D), TRY USING 74X151
5.20, 5.21, 5.27, 5.28, 5.29,5.48, 5.54, 5.60, 5.61, 5.62。