isplsi1016-mil CPLD

figure 1). The outputs of the eight GLBs are connected to GLBs and I/O cells. The Clock Distribution Network can
a set of 16 universal I/O cells by the ORP. The ispLSI also be driven from a special clock GLB (B0 on the ispLSI
— tpd = 20 ns Propagation Delay
B P — TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested
ispLSI® 1016/883
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs
H U 1 • COMBINES EASE OF USE AND THE FAST SYSTEM - SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
E IN — Complete Programmable Device Can Combine Glue A Logic and Structured Designs
The basic unit of logic on the ispLSI 1016/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. B7 (see figure 1). There are a total of 16 GLBs in the ispLSI 1016/883 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and
N — 96 Registers
— Wide Input Gating for Fast Counters, Sders, etc.
E — Small Logic Block Size for Random Logic R — Security Cell Prevents Unauthorized Copying E • HIGH PERFORMANCE E2CMOS® TECHNOLOGY E — fmax = 60 MHz Maximum Operating Frequency
January 2002
1016mil_02
1
Specifications ispLSI 1016/883
Functional Block Diagram
Figure 1. ispLSI 1016/883 Functional Block Diagram
Generic Logic Blocks
(GLBs)
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
1016/883 device contains two of these Megablocks.
1016/883 device). The logic of this GLB allows the user
to create an internal clock from a combination of internal
Output Routing Pool Output Routing Pool
A0
B7
A1
DQ
B6
A2
DQ
B5
Logic
A3
Array D Q GLB
B4
A4
B3
DQ
A5
B2
A6
B1
A7 Global Routing Pool (GRP) B0
CLK
Description
The ispLSI 1016/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD883. This military grade device contains 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016/883 features 5Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
Clocks in the ispLSI 1016/883 device are selected using the Clock Distribution Network. Three dedicated clock
pins (Y0, Y1 and Y2) are brought into the distribution
TTL compatible voltages and the output drivers can
D source 4 mA or sink 8 mA.
The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.
VIC NT #05 ispEN
Y0 Y1/RESET*
SCLK/Y2
*Note: Y1 and RESET are multiplexed on the same pin
0139B(1a)-isp.eps
E O N The device also has 32 I/O cells, each of which is directly
Input Bus Output Routing Pool (ORP)
Output Routing Pool (ORP) lnput Bus
EN R I/O0
I/O 1
E I/O 2 E I/O 3
I/O 4
B I/O 5 P I/O 6
I/O 7
I/O 8
S I/O 9 D I/O 10
I/O 11
S D • IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only A — Increased Manufacturing Yields, Reduced Time-toE 0 Market, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556;
— Three Dedicated Clock Input Pins
IC T 5 — Synchronous and Asynchronous Clocks