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Stellaris® LM3S9B96 Development Kit User’s ManualCopyrightCopyright © 2009 Texas Instruments, Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Texas Instruments108 Wild Basin, Suite 350Austin, TX 78746Main: +1-512-279-8800Fax: +1-512-279-8879Stellaris® LM3S9B96 Development Kit User’s ManualTable of ContentsChapter 1: Stellaris® LM3S9B96 Development Board Overview (7)Features (7)Development Kit Contents (10)Block Diagram (11)Development Board Specifications (11)Chapter 2: Stellaris® LM3S9B96 Development Board Hardware Description (13)LM3S9B96 Microcontroller Overview (13)Jumpers and GPIO Assignments (13)Clocking (14)Reset (15)Power Supplies (15)USB (15)Debugging (16)Color QVGA LCD Touch Panel (17)I2S Audio (19)User Switch and LED (19)Chapter 3: Stellaris® LM3S9B96 Development Board External Peripheral Interface (EPI) (21)SDRAM Expansion Board (21)Flash and SRAM Memory Expansion Board (21)Chapter 4: Using the In-Circuit Debugger Interface (23)Appendix A: Stellaris® LM3S9B96 Development Board Schematics (25)Appendix B: Stellaris® LM3S9B96 Development Board Component Locations (33)Appendix C: Stellaris® LM3S9B96 Development Board Connection Details (35)DC Power Jack (35)ARM Target Pinout (35)Appendix D: Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments (37)Appendix E: Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board (41)Installation (41)Features (42)Hardware Description (43)Functional Description (43)Memory Map (45)Component Locations (46)Schematics (46)Appendix F: References (49)List of FiguresFigure1-1.DK-LM3S9B96 Development Board (9)Figure1-2.DK-LM3S9B96 Development Board Block Diagram (11)Figure2-1.Factory Default Jumper Settings (14)Figure4-1.ICD Interface Mode (23)Figure ponent Placement Plot for Top (34)Figure E-1.DK-LM3S9B96-EXP-FS8 Board Image (41)Figure E-2.DK-LM3S9B96 Development Board (42)Figure E-3.DK-LM3S9B96-EXP-FS8 Flash/SRAM/LCD IF Expansion Board Block Diagram (43)Figure ponent Placement Plot for Top and Bottom (46)Stellaris® LM3S9B96 Development Kit User’s ManualList of TablesTable2-1.Board Features and Peripherals that are Disconnected in Factory Default Configuration (13)B-Related Signals (15)Table2-3.Hardware Debugging Configurations (16)Table2-4.Debug-Related Signals (17)Table2-5.LCD-Related Signals (18)Table2-6.I2S Audio-Related Signals (19)Table2-7.Navigation Switch-Related Signals (19)Table C-1.Debug Interface Pin Assignments (35)Table D-1.Microcontroller GPIO Assignments (37)Table E-1.Flash and SRAM Memory Expansion Board Memory Map (45)Table E-2.LCD Latch Register (45)C H A P T E R1Stellaris® LM3S9B96 Development Board Overview The Stellaris® LM3S9B96 Development Board provides a platform for developing systems aroundthe advanced capabilities of the LM3S9B96 ARM® Cortex™-M3-based microcontroller.The LM3S9B96 is a member of the Stellaris Tempest-class microcontroller family. Tempest-classdevices include capabilities such as 80MHz clock speeds, an External Peripheral Interface (EPI)and Audio I2S interfaces. In addition to new hardware to support these features, theDK-LM3S9B96 board includes a rich set of peripherals found on other Stellaris boards.The development board includes an on-board in-circuit debug interface (ICDI) that supports bothJTAG and SWD debugging. A standard ARM 20-pin debug header supports an array of debuggingsolutions.The Stellaris® LM3S9B96 Development Kit accelerates development of Tempest-classmicrocontrollers. The kit also includes extensive example applications and complete source code. FeaturesThe Stellaris® LM3S9B96 Development Board includes the following features.Simple set-up—USB cable provides debugging, communication, and powerFlexible development platform with a wide range of peripheralsColor LCD graphics display–TFT LCD module with 320 x 240 resolution–Resistive touch interface80 MHz LM3S9B96 microcontroller with 256 K Flash, 96 K SRAM, and integrated EthernetMAC+PHY, USB OTG, and CAN communications–– 8 MB SDRAM (plug-in EPI option board)–– EPI break-out board (plug-in option board)1MB serial Flash memoryPrecision 3.00V voltage referenceSAFE RTOS™ operating system in microcontroller ROMI2S stereo audio codec–Line In/Out–Headphone Out–Microphone InController Area Network (CAN) Interface10/100 BaseT EthernetUSB On-The-Go (OTG) Connector–Device, Host, and OTG modesUser LED and push buttonThumbwheel potentiometer (can be used for menu navigation)MicroSD card slotSupports a range of debugging options–Integrated In-circuit Debug Interface (ICDI)–JTAG, SWD, and SWO all supported–Standard ARM® 20-pin JTAG debug connectorUSB Virtual COM PortJumper shunts to conveniently reallocate I/O resourcesDevelop using tools supporting the DK-LM3S9B96 from Keil, IAR, Code Sourcery, and Code RedSupported by StellarisWare® software including the graphics library, the USB library, and the peripheral driver libraryAn optional Flash and SRAM memory expansion board (DK-LM3S9B96-EXP-FS8) is also available for use with the DK-LM3S9B96 development board–Works with the External Peripheral Interface (EPI) of the Stellaris microcontroller–Provides Flash memory, SRAM, and an improved performance LCD interfaceFor more information on the DK-LM3S9B96-EXP-FS8 memory expansion board, seeAppendix E, “Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board,” on page 41.The DK-LM3S9B96-EXP-FS8 memory expansion board is available for purchase separately.Stellaris® LM3S9B96 Development Kit User’s Manual Figure1-1.DK-LM3S9B96 Development BoardAudio Line Output1MB Serial Flash Memory3.5" LCD Touch PanelDevelopment Kit ContentsThe Stellaris® LM3S9B96 Development Kit contains everything needed to develop and run arange of applications using Stellaris microcontrollers:LM3S9B96 development board8MB SDRAM expansion boardEPI signal breakout boardRetractable Ethernet cableUSB Mini-B cable for debugger useUSB Micro-B cable for OTG-to-PC connectionUSB Micro-A to USB A adapter for USB HostUSB Flash memory stickmicroSD Card20-position ribbon cableCDs containing evaluation versions of the following tools:–StellarisWare with example code for this board–ARM RealView® Microcontroller Development Kit (MDK)–IAR Embedded Workbench® Kickstart Edition–Code Red Technologies Red Suite™–CodeSourcery Sourcery G++™ GNU tools.Stellaris® LM3S9B96 Development Kit User’s Manual Block DiagramFigure1-2.DK-LM3S9B96 Development Board Block DiagramDevelopment Board SpecificationsBoard supply voltage: 4.75–5.25 Vdc from one of the following sources:–Debugger (ICDI) USB cable (connected to a PC)–USB Micro-B cable (connected to a PC)–DC power jack (2.1x5.5mm from external power supply)Break-out power output: 3.3 Vdc (100 mA max)Dimensions (excluding LCD panel):– 4.50” x 4.25” x 0.60” (LxWxH) with SDRAM board– 4.50” x 4.25” x 0.75” (LxWxH) with EPI breakout boardAnalog Reference: 3.0V +/-0.2%RoHS status: CompliantNOTE:When the LM3S9B96 Development Board is used in USB Host mode, the host connector is capable of supplying power to the connected USB device. The available supply current is limited to ~200mA unless the development board is powered from an external 5Vsupply with a =600mA rating.C H A P T E R2Stellaris® LM3S9B96 Development Board Hardware DescriptionIn addition to an LM3S9B96 microcontroller, the development board includes a range of usefulperipheral features and an integrated in-circuit debug interface (ICDI). This chapter describes howthese peripherals operate and interface to the microcontrollerLM3S9B96 Microcontroller OverviewThe Stellaris LM3S9B96 is an ARM Cortex-M3-based microcontroller with 256-KB flash memory,80-MHz operation, Ethernet, USB, EPI, SAFE RTOS™ in ROM, and a wide range of peripherals.See the LM3S9B96 Microcontroller Data Sheet (order number DS-LM3S9B96) for completemicrocontroller details.The LM3S9B96 microcontroller is factory-programmed with a quickstart demo program. Thequickstart program resides in on-chip flash memory and runs each time power is applied, unlessthe quickstart has been replaced with a user program.Jumpers and GPIO AssignmentsEach peripheral circuit on the development board is interfaced to the LM3S9B96 microcontrollerthrough a 0.1” pitch jumper/shunt. Figure2-1 on page 14 shows the factory default positions of thejumpers. The jumpers must be in these positions for the quickstart demo program to functioncorrectly.The development board offers capabilities that the LM3S9B96 cannot support simultaneously dueto pin count and GPIO multiplexing limitations. For example, as configured, the board does notsupport SDRAM and I2S receive (microphone or line input) functions at the same time. Thejumpers associated with I2S receive are omitted in the default configuration.Table2-1 lists all features and peripherals that are disconnected in the factory defaultconfiguration. Using these peripherals requires that other peripherals be disconnected.Appendix D, “Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments,” onpage 37 lists alternative jumper configurations used in conjunction with some of theStellarisWare™ example applications for this board.Table2-1.Board Features and Peripherals that are Disconnected in Factory DefaultConfigurationPeripheral JumpersI2S Receive (Audio Input)JP44, 45, 47, 49Controller Area Network (CAN) JP14, 15Ethernet Yellow Status LED (LED2)JP2Analog 3.0V Reference JP33See Appendix D, “Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments,”on page 37, for a complete list of GPIO assignments. The table lists all default and alternateassignments that are supported by the 0.1”jumpers and PCB routing. The LM3S9B96 hasadditional internal multiplexing that enables additional configurations which may require discretewiring between peripherals and GPIO pins.The ICDI section of the board has a GND-GND jumper that serves no function other than toprovide a convenient place to ‘park’ a spare jumper. This jumper may be reused as required.ClockingThe development board uses a 16.0-MHz (Y2) crystal to complete the LM3S9B96microcontroller's main internal clock circuit. An internal PLL, configured in software, multiples thisclock to higher frequencies for core and peripheral timing.A 25.0-MHz (Y1) crystal provides an accurate timebase for the Ethernet PHY.Stellaris® LM3S9B96 Development Kit User’s ManualResetThe RESETn signal into the LM3S9B96 microcontroller connects to the reset switch (SW2) and tothe ICDI circuit for a debugger-controlled reset.External reset is asserted (active low) under any one of the three following conditions:Power-on reset (filtered by an R-C network)Reset push switch SW2 held downBy the ICDI circuit (U12 FT2232, U13D 74LVC125A) when instructed by the debugger (this capability is optional, and may not be supported by all debuggers)The LCD module has special Reset timing requirements requiring a dedicated control line from themicrocontroller.Power SuppliesThe development board requires a regulated 5.0V power source. Jumpers JP34-36 select thepower source, with the default source being the ICDI USB connector. Only one +5V source shouldbe selected at any time to avoid conflict between the power sources.When using USB in Host mode, the power source should be set to either ICDI or to EXT if a +5Vpower supply (not included in the kit) is available.The development board has two main power rails. A +3.3V supply powers the microcontroller andmost other circuitry. +5V is used by the OTG USB port and In-circuit Debug Interface (ICDI) USBcontroller. A low drop-out (LDO) regulator (U5) converts the +5V power rail to +3.3V. Both railsare routed to test loops for easy access.USBThe LM3S9B96’s full-speed USB controller supports On-the-Go, Host, and Device configurations.See Table2-2 for USB-related signals. The 5-pin microAB OTG connector supports all threeinterfaces in conjunction with the cables included in the kit.The USB port has additional ESD protection diode arrays (D1, D2,D5) for up to 15kV of ESDprotection.B-Related SignalsMicrocontroller Pin Board Function Jumper NamePin 70 USB0DM USB Data--Pin 71 USB0DP USB Data+-Pin 73 USB0RBIAS USB bias resistor-Pin 66 USB0ID OTG ID signal (input to microcontroller)OTG IDPin 67 USB0VBUS Vbus Level monitoring+VBUSPin 34 USB0EPE Host power enable (active high)EPENPin 35 USB0PFLT Host power fault signal (active low)PFLTU6, a fault-protected switch, controls and monitors power to the USB host port. USB0EPEN, thecontrol signal from the microcontroller, has a pull-down resistor to ensure host-port power remainsoff during reset. The power switch will immediately cut power if the attached USB device drawsmore than 1Amp, or if the switches’ thermal limits are exceeded by a device drawing more than 500mA. USB0PFLT indicates the over-current status back to the microcontroller.The development board can be either a bus-powered USB device or self-powered USB device depending on the power-supply configuration jumpers.When using the development board in USB-host mode, power to the EVB should be supplied by the In-circuit Debugger (ICDI) USB cable or by a +5V source connected to the DC power jack. Note that the LM3S9B96’s USB capabilities are completely independent from the In-Circuit Debug Interface USB functionality.DebuggingStellaris microcontrollers support programming and debugging using either JTAG or SWD. JTAG uses the TCK, TMS, TDI, and TDO signals. SWD requires fewer signals (SWCLK, SWDIO, and, optionally, SWO for trace). The debugger determines which debug protocol is used.Debugging ModesThe LM3S9B96 development board supports a range of hardware debugging configurations. Table 2-3 summarizes these configurations.Debug In ConsiderationsDebug Mode 3 supports board debugging using an external debug interface such as a Segger J-Link or Keil ULINK. Most debuggers use Pin 1 of the Debug connector to sense the target voltage and, in some cases, power the output logic circuit. Installing the VDD/PIN1 jumper will apply 3.3V power to this pin in order to support external debuggers.Debug USB OverviewAn FT2232 device from Future Technology Devices International Ltd implements USB-to-serial conversion. The FT2232 is factory-configured to implement a JTAG/SWD port (synchronous serial) on channel A and a Virtual COM Port (VCP) on channel B. This feature allows two simultaneous communications links between the host computer and the target device using a single USB cable. Separate Windows drivers for each function are provided on the Documentation and Software CD.The In-Circuit Debug Interface USB capabilities are completely independent from the LM3S9B96’s on-chip USB functionality.Table 2-3.Hardware Debugging ConfigurationsMode Debug Function UseSelected by (1)Internal ICDIDebug on-board LM3S9B96 microcontroller over Debug USB interface.Default mode2ICDI out to JTAG/ SWD headerThe development board is used as a USB to SWD/ JTAG interface to an external target.Connecting to an external target and starting debug software.3 In from JTAG/SWD headerFor users who prefer an external debug interface (ULINK, JLINK, etc.) with the EVB.Connecting an externaldebugger to the JTAG/SWD headerStellaris® LM3S9B96 Development Kit User’s ManualA small serial EEPROM holds the FT2232 configuration data. The EEPROM is not accessible bythe LM3S9B96 microcontroller. For full details on FT2232 operation, go to . USB to JTAG/SWDThe FT2232 USB device performs JTAG/SWD serial operations under the control of the debugger.A simple logic circuit multiplexes SWD and JTAG functions and, when working in SWD mode,provides direction control for the bidirectional data line.Virtual COM PortThe Virtual COM Port (VCP) allows Windows applications (such as HyperTerminal) tocommunicate with UART0 on the LM3S9B96 over USB. Once the FT2232 VCP driver is installed,Windows assigns a COM port number to the VCP channel. Table2-4 shows the debug-relatedsignals.Table2-4.Debug-Related SignalsMicrocontroller Pin Board Function Jumper NamePin 77 TDO/SWO JTAG data out or trace data out TDOPin 78 TDI JTAG data in TDIPin 79 TMS/SWDIO JTAG TMS or SWD data in/out TMSPin 80 TCK/SWCLK JTAG Clock or SWD clock TCKPin 26 PA0/U0RX Virtual Com port data to LM3S9B96VCPRXPin 27 PA1/U0TX Virtual Com port data from LM3S9B96VCPTXPin 64 RSTn System Reset RSTnSerial Wire Out (SWO)The development board supports the Cortex-M3 Serial-Wire Output (SWO) trace capabilities.Under debugger control, on-board logic can route the SWO datastream to the VCP transmitchannel. The debugger software can then decode and interpret the trace information receivedfrom the Virtual Com Port. The normal VCP connection to UART0 is interrupted when using SWO.Not all debuggers support SWO.See the Stellaris LM3S9B96 Microcontroller Data Sheet for additional information on the TracePort Interface Unit (TPIU).Color QVGA LCD Touch PanelThe development board features a TFT Liquid Crystal graphics display with 320 x 240 pixelresolution. The display is protected during shipping by a thin, protective plastic film which shouldbe removed before use.FeaturesFeatures of the LCD module include:Kitronix K350QVG-V1-F display320 x RGB x 240 dots3.5” 262K colorsWide temperature range White LED backlight Integrated RAMResistive touch panelControl InterfaceThe Color LCD module has a built-in controller IC with a multi-mode parallel interface. The development board uses an 8-bit 8080 type interface with GPIO Port D providing the data bus. Table 2-4 shows the LCD-related signals.BacklightThe white LED backlight must be powered for the display to be clearly visible. U7 (FAN5331B) implements a 20mA constant-current LED power source to the backlight. The backlight is not normally controlled by the microcontroller, however, the control signal is available on a header. A jumper may be installed to disable the backlight by connecting it to GND. Alternatively, a wire may be used to control this signal from a spare microcontroller GPIO line.Because the FAN5331B operates in a constant current mode, its output voltage will jump up if the LCD should become disconnected. To prevent over-voltage failure of the IC or diode D3, a zener (D4) clamps the voltage. The current will limit to 20mA, but the total board current will be higher than when the LCD panel is connected. To avoid over-heating the backlighting circuit, install the BLON jumper to completely shut-down the backlighting circuit.PowerThe LCD module has internal bias voltage generators and requires only a single 3.3V dc supply.Resistive Touch PanelThe 4-wire resistive touch panel interfaces directly to the microcontroller, using 2 ADC channels and 2 GPIO signals. See the StellarisWare™ source code for additional information on touch panel implementation.Table 2-5.LCD-Related SignalsMicrocontroller Pin Board Function Jumper Name PE6/ADC1Touch X+X+PE3Touch Y-Y-PE2Touch X-X-PE7/ADC0Touch Y+Y+PB7 LCD Reset LRSTn PD0..7LCD Data Bus 0..7LD0..7PH7LCD Data/Control Select LDC PB5LCD Read Strobe LRDn PH6LCD Write Strobe LWRn -Backlight controlBLONStellaris® LM3S9B96 Development Kit User’s ManualI2S AudioThe LM3S9B96 development board has advanced audio capabilities using an I2S-connectedAudio TLV320AIC23 CODEC. The factory default configuration has Audio output (Line Out and/orHeadphone output) enabled. Four additional I2S signals are required for Audio input (Line Inputand/or Microphone). All four audio interfaces are through 1/8” (3.5mm) stereo jacks. Table2-6shows the I2S audio-related signals.Table2-6.I2S Audio-Related SignalsMicrocontroller Pin Board Function Jumper NameI2C0SDA CODEC Configuration Data SDAI2C0SCL CODEC Configuration Clock SCLI2STXSD Audio Out Serial Data TXSDI2STXWS Audio Out Framing signal TXWSI2STXSCK Audio Out Bit Clock BCLK aI2STXMCLK Audio Out System Clock MCLKI2SRXSD Audio In Serial Data RXSD bI2SRXWS Audio In Framing signal RXWS bI2SRXSCK Audio In Bit Clock BCLK bI2SRXMCLK Audio In System Clock MCLK ba.Shares GPIO line with Analog voltage reference. Jumper installed by default.b.Shares GPIO line with LCD data bus – Port D. Jumper omitted by default.The Audio CODEC has a number of control registers which are configured using the I2C bussignals. CODEC settings can only be written, but not read, using I2C. See the StellarisWare™example applications for programming information and the TLV320AIX23B data sheet forcomplete register details.The Headphone output can be connected directly to any standard headphones. The Line Output issuitable for connection to an external amplifier, including PC desktop speaker sets.User Switch and LEDThe development board provides a user push-switch and LED (see Table2-7).Table2-7.Navigation Switch-Related SignalsMicrocontroller Pin Board Function Jumper NamePJ7User Switch SWITCHPF3User LED LED aa.Shared with Ethernet Jack Yellow LED. This jumper is installed by default.C H A P T E R3Stellaris® LM3S9B96 Development Board External Peripheral Interface (EPI)The External Peripheral Interface (EPI) is a high-speed 8/16/32-bit parallel bus for connectingexternal peripherals or memory without glue logic. Supported modes include SDRAM, SRAM, andFlash memories, as well as Host-bus and FIFO modes.The LM3S9B96 development kit includes an 8MB SDRAM board in addition to an EPI break-outboard. Other EPI expansion boards may be available.SDRAM Expansion BoardThe SDRAM board provides 8MB of memory (4M x 16) which, once configured, becomes part ofthe LM3S9B96’s memory map at either 0x6000.0000 or 0x8000.0000. The SDRAM interfacemultiplexes DQ00..14 and AD/BA0..14 without requiring external latches or buffers. Of the 32 EPIsignals, only 24 are used in SDRAM mode, with the remaining signals used for non-EPI functionson the board.Flash and SRAM Memory Expansion BoardThe optional Flash and SRAM memory expansion board (DK-LM3S9B96-EXP-FS8) is a plug-in forthe DK-LM3S9B96 development board. This expansion board works with the External PeripheralInterface (EPI) of the Stellaris microcontroller and provides Flash memory, SRAM, and animproved performance LCD interface.For more information on the DK-LM3S9B96-EXP-FS8 memory expansion board (sold separately),see Appendix E, “Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board,” on page 41.C H A P T E R4Using the In-Circuit Debugger InterfaceThe Stellaris® LM3S9B96 Development Kit can operate as an In-Circuit Debugger Interface(ICDI). ICDI acts as a USB to the JTAG/SWD adaptor, allowing debugging of any external targetboard that uses a Stellaris microcontroller. See “Debugging Modes” on page16 for a description ofhow to enter Debug Out mode.Figure4-1.ICD Interface Mode`The debug interface operates in either serial-wire debug (SWD) or JTAG mode, depending on theconfiguration in the debugger IDE.The IDE/debugger does not distinguish between the on-board Stellaris microcontroller and anexternal Stellaris microcontroller. The only requirement is that the correct Stellaris device isselected in the project configuration.The Stellaris target board should have a 2x10 0.1” pin header with signals as indicated inTable C-1 on page35. This applies to both an external Stellaris microcontroller target (DebugOutput mode) and to external JTAG/SWD debuggers (Debug Input mode).ICDI does not control RST (device reset) or TRST (test reset) signals. Both reset functions areimplemented as commands over JTAG/SWD, so these signals are usually not necessary.It is recommended that connections be made to all GND pins; however, both targets and externaldebug interfaces must connect pin 5 and at least one other GND pin to GND. Some externaldebug interfaces may require a voltage on Pin 1 to set line driver thresholds. The developmentboard ICDI circuit automatically sets Pin 1 high if an external debugger is connected. In othermodes this pin is unused.A P P E N D I X AStellaris® LM3S9B96 Development Board SchematicsThis section contains the schematics for the DK-LM3S9B96 development board.Micro, EPI connector, USB, and Ethernet on page26LCD CAN, Serial Memory, and User I/O on page27Power Supplies on page28I2S Audio Expansion Board on page29EPI and SDRAM Expansion Boards on page30In-circuit Debug Interface (ICDI) on page3132October 3, 2009A P P E N D I X BStellaris® LM3S9B96 Development Board Component LocationsThis appendix contains details on component locations, including:Component placement plot for top (Figure B-1)October 3, 20093334October 3, 2009October 3, 200935Stellaris® LM3S9B96 Development Board Connection DetailsThis appendix contains the following sections: DC Power Jack (see page 35)ARM Target Pinout (see page 35)DC Power JackThe EVB provides a DC power jack for connecting an external +5V regulated (+/-5%) power source.The socket is 5.5 mm dia with a 2.1 mm pin.ARM Target PinoutIn ICDI input and output mode, the Stellaris® LM3S9B96 Development Kit supports ARM’sstandard 20-pin JTAG/SWD configuration. The same pin configuration can be used for debugging over serial-wire debug (SWD) and JTAG interfaces.Insert Jumper VDD/PIN1 Jumper (JP57) only when using the development board with an external debug interface such as a ULINK or JLINK.Table C-1.Debug Interface Pin AssignmentsFunction Pin Number TDI 5TDO/SWO 13TMS/SWDIO 7TCK/SWCLK 9System Reset 15VDD 1GND 4, 6, 8, 10, 12, 14, 16, 18, 20No Connect2, 3, 11, 17, 19A P P E N D I XC36October 3, 2009A P P E N D I X DStellaris® LM3S9B96 Development Board Microcontroller GPIO AssignmentsTable D-1 shows the pin assignments for the LM3S9B96 microcontroller.Table D-1.Microcontroller GPIO AssignmentsLM3S9B96 GPIO Pin Development Board UseNumber Description Default Function Default Use Alt. Function Alternate Use 26PA0U0Rx Virtual Com Port27PA1U0Tx Virtual Com Port28PA2SSI0Clk SPI29PA3SSI0Fss SD Card CSn30PA4SSI0Rx SPI31PA5SSI0Tx SPI34PA6USB0EPEN USB Pwr Enable CAN0RX35PA7USB0PFLT USB Pwr Fault CAN0TX66PB0USB0ID USB OTG ID67PB1USB0VBUS USB Vbus72PB2I2C0SCL Audio I2C65PB3I2C0SDA Audio I2C92PB4ADC10Potentiometer EPI0S23EPI Breakout91PB5PB5LCD RDn EPI0S22EPI Breakout90PB6PB6I2STXSCK AVREF Ext Volt Ref89PB7PB7LCD RST80PC0TCK/SWCLK JTAG79PC1TMS/SWDIO JTAG78PC2TDI JTAG77PC3TDO/SWO JTAG25PC4EPI0S2SDRAM D02EPI0S0224PC5EPI0S3SDRAM D03EPI0S0323PC6EPI0S4SDRAM D04EPI0S0422PC7EPI0S5SDRAM D05EPI0S05October 3, 200937。

Amlogic原理图

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基于LM3S9B92的锂离子电池充电器的设计与实现

基于LM3S9B92的锂离子电池充电器的设计与实现于LM3S9B92，LM3S9B92 既可以利用其PWM 模块产生所需的PWM 信号，也可以利用定时器模块的16 位PWM 功能来产生PWM 信号。

如果直接利用PWM 模块产生PWM 信号，在设定好周期时，可以适时改变PWM 的匹配值来改变占空比；如果利用定时器模块在16 位PWM 工作模式下产生PWM 波，则定时器配置为16 位的递减计数器，通过配置适当的装载值（决定PWM 周期）和匹配值（决定PWM 占空比）来自动产生PWM 方波信号，并从相应的管脚输出。

本方法的基本思想是利用LM3S9B92 所具有的PWM 管脚，在不改变PWM 方波周期的前提下，通过软件编程的方法调整PWM 控制寄存器的数值来调整PWM 的占空比，从而控制充电电流。

在调整充电电流前，处理器应读取充电电流的大小，然后把设定的充电电流与实际读取的充电电流进行比较，若实际电流偏小，则向增加充电电流的方向调整PWM 的占空比；若实际电流偏大，则向减小充电电流的方向调整PWM 的占空比。

采样电路是指对充电电压和充电电流的采样，采样的电压和电流通过LM3S9B92 的一个集成的10 bit ADC 模块送到LM3S9B92 控制芯片中，LM3S9B92 对数据进行处理与保存。

ADC 模块支持16 个输入通道，并含有4 个可编程的序列发生器，这些序列发生器无需控制器干预即可自动对多个模拟输入源进行采样。

ADC 可使用片内3V 参考电压，也可使用片外参考电平。

图3 中R8、R9 分压后再经过RC 低通滤波，最后接到LM3S9B92 的ADC 引脚作为电池正端电压采样，其目的是防止进入ADC 引脚的电压太大而损坏芯片，为安全起见，在RC 滤波后采取限压保护措施，例如采用钳位保护二极管等。

为了降低成本，设计中对电流的采样不外加传感器，而是通过一个传感电阻R11 将流过电池的电流转换成电压后，再进行ADC 转换取样。

LM3S9B92概述

LM3S9B92概述概述德州仪器(TI)公司Stellaris?所提供一系列的微控制器是首款基于ARM? CortexTM-M3的控制器，它们为对成本尤其敏感的嵌入式微控制器应用方案带来了高性能的32位运算能力。

这些具备领先技术的芯片使用户能够以传统的8位和16位器件的价位来享受32位的性能，而且所有型号都是以小占位面积的封装形式提供。

LM3S9B92微控制器的优势还在于能够方便的运用多种ARM的开发工具和片上系统（SoC）的底层IP应用方案，以及广大的用户群体。

另外，该微控制器使用了兼容ARM Thumb?的Thumb2指令集来减少存储容量的需求，并以此达到降低成本的目的。

最后，LM3S9B92微控制器与Stellaris?系列的所有成员是代码兼容的，这为用户提供了灵活性，能够适应各种精确的需求。

为了能够帮助用户产品快速的上市，德州仪器(TI)公司提供了一整套的解决方案，包括评估和开发板、白皮书和应用笔记、方便使用的外设驱动程序库、以及强大的支持、销售和分销商网络。

特性LM3S9B92包含了下列特性：ARM Cortex-M3处理器内核－80MHz主频，100DMIPS性能－ARM Cortex系统定时器－嵌套向量中断控制器片上存储器－256KB单周期Flash－96KB单周期SRAM－片上ROM StellarisWare 软件Stellaris外设驱动库Stellaris BootLoader高级加密标准（AES）密钥表格循环冗余校验 (CRC) 错误检测功能外围设备接口（EPI）－8/16/32位独立外设并行总线－支持SDRAM、SRAM/Flash、FPGA、CPLD先进的连续性－10/100以太网 MAC/PHY－两路CAN2.0 A/B控制器－USB2.0 OTG/Host/Device－三路支持IrDA和ISO7816的UART（其中一路具有调制解调控制功能）－两个I2C模块－两个SSI模块－I2S模块系统综合性能－DMA控制器－系统控制与时钟（包括片上16MHz高精度振荡器）－4个32位通用定时器－8路CCP管脚－实时时钟－两个看门狗定时器一个定时器时钟源为主振荡器另一个定时器时钟源为片内高精度振荡器－通过配置多达65个GPIO口灵活配置为GPIO或者其他一种外设功能驱动电流可独立配置为2、4或者8mA多达4个GPIO口有18 mA驱动能力先进的运动控制－8路PWM输出，应用于运动控制场合－4种硬件故障处理输入操作，实现低延时关闭－两个QEI模块模拟功能－两个10位共16路采样通道AD转换器，采样率为1Msps －三个模拟比较器－16个数字比较器－一个片上基准源JTAG和SWDLQFP100封装工业级温度范围（-40℃~85℃ )。

LM3S9B96开发板主要特性

TheLM3S9B96isamemberoftheStellarisTem pest-classmicrocontrollerfamily.Tempest-c lassdevicesincludecapabilitiessuchas80MHz clockspeeds,anExternalPeripheralInterface (EPI)andAudioI2Sinterfaces.Inadditiontone whardwaretosupportthesefeatures,theDK-LM3 S9B96boardincludesarichsetofperipheralsfo undonotherStellarisboards.
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精选嵌入式实验四实验报告

精选嵌入式实验四实验报告3.4基于UART的加法器的实现一、实验目的学习lm3s9b92的串口通信学习应用超级终端调试串口学会应用UART有关的库函数二、实验设备计算机、LM3S9B92开发板、USB A型公口转Mini B型5Pin 数据线1 条三、实验原理Stellaris系列ARM的UART具有完全可编程、16C550型串行接口的特性。

Stellaris系列ARM含有2至3个UART模块。

该指导书在第一部分的1.2节中说明，该开发板使用了FT2232芯片实现usb到串口的转换。

并设置在芯片的B通道上使用虚拟COM 接口(VCP)。

虚拟串行端口(VCP)与LM3s9b92上的UART0模块连接。

在安装FTDI驱动程序后，windows会分配一个串行通信端口号到VCP 通道，并允许windows应用程序(如超级终端)通过USB与LM3s9b92上的UART0进行通信。

利用Windows超级终端调试UART的方法对于该开发板，使用的是USB虚拟的COM端口，无须使用DB9连接器。

因此下面讲解一下如何利用Windows附带的超级终端来调试UART接口。

Windows附件里的“超级终端”是个非常实用的应用程序，可以用来调试电脑的COM串行口，也能很好地支持通过USB虚拟的COM 口。

以下是超级终端配置COM端口的过程：四、实验要求采用超级终端作为外部输入与输出的接口，实现多位数的相加。

即通过UART串口分别输入需要相加的多位数A与B，最后把A和B 两个多位数相加的过程和结果，回显给用户。

具体实现方法：既可以采用轮询的方式也可以应用中断。

五、实验步骤1、连接实验设备：使用USB mini B线缆的mini端与开发板ICDI 口相连，另一端接到PC机的USB插口上。

2、根据实验要求编写、调试、运行程序。

并要求在代码上附上相关的注释。

#include#include ;inc/hw_ints.h;#include ;inc/hw_memmap.h;#include ;inc/hw_types.h;#include ;driverlib/debug.h;#include ;driverlib/gpio.h;#include ;driverlib/interrupt.h;#include ;driverlib/sysctl.h;#include ;driverlib/uart.h;#include ;grlib/grlib.h;#include ;drivers/kitronix320x240x16_ssd2119_8bit.h;#include ;drivers/set_pinout.h;#include ;systemInit.h;void uartInit(void){SysCtlPeriEnable(SYSCTL_PERIPH_UART0); // 使能UART模块SysCtlPeriEnable(SYSCTL_PERIPH_GPIOA); // 使能RX/TX所在的GPIO端口GPIOPinTypeUART(GPIO_PORTA_BASE, // 配置RX/TX所在管脚为GPIO_PIN_0 | GPIO_PIN_1); // UART收发功能UARTConfigSet(UART0_BASE, // 配置UART端口9600, // 波特率：9600UART_CONFIG_WLEN_8| // 数据位：8UART_CONFIG_STOP_ONE | // 停止位：1UART_CONFIG_PAR_NONE); // 校验位：无UARTEnable(UART0_BASE); // 使能UART端口}void uartPuts(const char *s){while (*s != ;;){UARTCharPut(UART0_BASE, *(s++));}}main(void){char c,a[12];int sum=0,num=0,i;// jtagWait( ); // 防止JTAG 失效，重要！clockInit( ); // 时钟初始化：晶振，6MHzuartInit( ); // UART 初始化uartPuts(;输入格式m+n= ;);for (;;){c = UARTCharGet(UART0_BASE); // 等待接收字符if(c;=;0;;;c;=;9;)//判断收到的是否为字符{num=num*10+c-;0;; //将收到的字符转换为整形储存} else if(c==;+;){ //接收第二个数sum=sum+num;num=0;}else if(c==;=;) //输出{sum=sum+num;num=0;for(i=0;sum!=0;i++){a[i]=sum%10;sum=(sum-a[i])/10;}for(i--;i;=0;i--){UARTCharPut(UART0_BASE, a[i]+;0;); } UARTCharPut(UART0_BASE, ; ;); }if (c == ; ;) // 如果遇到回车{UARTCharPut(UART0_BASE, ; ;); // 多回显一个换行} }}3、书写实验报告，要求附上程序流程图。

嵌入式系统实验指导书

第1部分DK-LM3S9B92 教学实验平台简介1.1 Stellaris® LM3S9B92开发板本书中的所有实验都是基于DK-LM3S9B92开发平台，LM3S9B92开发板提供了一个平台给基于ARM Cortex-M3的高性能的LM3S9B92微控制器开发系统。

LM3S9B92是Stellaris® Tempest-class微控制器家族的成员之一。

Tempest-class系列设备拥有性能为80MHz的时钟速率，一个外围设备接口（EPI）和Audio I2S接口。

除了支持这些功能的新硬件外，DK-LM3S9B92还包含了一系列丰富的基于其他Stellaris® 板的外设。

开发板包括一个板载线上调试接口（on-board in-circuit debug interface，ICDI），该接口支持JTAG和SWD调试。

一个标准的ARM 20针脚的调试头支持大量的调试解决方案。

Stellaris® LM3S9B92开发套件加快了Tempest-class微控制器的开发。

该套件还包含了完整的实验源代码。

Stellaris® LM3S9B92开发板包含以下特性：⏹ 设置简单的USB线提供调试、通讯和供电功能⏹ 拥有众多外设的灵活开发平台⏹ 彩色LCD图形显示– 320×240分辨率的TFT LCD模块–电阻式触摸接口⏹ 拥有256K闪存，96K SDRAM以及整合以太网、MAC+PHY、USB OTG和CAN通讯功能的80 MHz LM3S9B92 微控制器⏹ 8MB SDRAM扩展（通过EPI接口）⏹ 1MB串行闪存⏹ 精确3.00V电压参考⏹ 微处理器ROM中内建SAFERTOS™操作系统⏹ I2S立体声音频编解码器–输入输出–耳机输出–麦克风输入⏹ 控制器区域网络（CAN）接口⏹ 10/100 BaseT 以太网⏹ USB On-The-Go（OTG）连接器– Device、Host、以及OTG模式⏹ 用户LED和按钮⏹ 指轮电位器（可以用于菜单导航）⏹ MicroSD 卡插槽⏹ 支持一系列调试选项–集成在线调试接口（ICDI）–全面支持JTAG、SWD和SWO–标准的ARM 20 针脚JTAG 调试连接器⏹ USB 虚拟COM 端口⏹ 跳线分流方便重新分配I/O 资源⏹ 为StellarisWare 软件所支持，包括图形库、USB 库和外围驱动库图1-1 DK-LM3S9B92开发板1.1.1 开发工具清单Stellaris® LM3S9B92 开发工具包括开发和运行使用Stellaris®微处理器的应用程序所需的所有东西：⏹ LM3S9B92 开发板⏹ 网线⏹ 用于调试的USB Mini-B 线缆⏹ 用于OTG 连接PC 的USB Micro-B 线缆⏹ 用于USB 主机的连接USB A 适配器的USB Micro-A 线缆⏹ USB 闪存记忆棒⏹ microSD 卡⏹ 20 位带状电缆线⏹ 光盘包含以下工具的评估版本：– StellarisWare 及用于本开发板的实验代码–IAR Embedded Workbench Kickstart Edition1.1.2 系统框图图1-2 DK-LM3S9B92开发板框图1.1.3 开发板说明⏹ 开发板的供电电压：4.75—5.25 VDC，从以下的输入源中的一个得到：–调试器（ICDI）USB 线缆（连接至PC）–USB Micro-B 线缆（连接至PC）–直流电源插孔（2.1x5.5mm 由外部电源供应）⏹ 尺寸：-107mmx 114mm⏹ 模拟参考电压：3.0V +/-0.2%⏹ RoHS 状态：符合注：当LM3S9B92开发板工作在USB主机模式时，主机的连接器供电给已连接的USB 设备。

LM3S8962开发板电路原理图

Schematic page 1
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Stellaris LM3S8962 Microcontroller
A PA0/U0Rx PA1/U0Tx PA2/SSI0CLK PA3/SSI0FSS PA4/SSI0RX PA5/SSI0TX PA6/CCP1 PA7 INT_TCK TMS/SWDIO PC2/TDI PC3/TDO TMS/SWDIO PC2/TDI PC3/TDO PC4/PhA0 PC5 PC6/PhB0 PC7 PE0/PWM4 PE1/PWM5 PE2/PhB1 PE3/PhA1 ADC0 ADC1 ADC2 ADC3 PG0 PG1/PWM1 MCURSTn 26 27 28 29 30 31 34 35 80 79 78 77 25 24 23 22 72 73 74 75 1 2 5 6 19 18 64 17 16 48 49 1 Y1 2 1 Y2 2 OSC32IN OSC32OUT 52 53 50 51 65 76 9 15 21 33 39 42 45 54 57 63 69 82 85 86 87 94 4 97 U1 U2 PA0/U0RX PA1/U0TX PA2/SSI0CLK PA3/SSI0FSS PA4/SSI0RX PA5/SSI0TX PA6/CCP1 PA7 PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO PC4/PhA0 PC5 PC6/PhB0 PC7 PE0/PWM4 PE1/PWM5 PE2/PhB1 PE3/PhA1 ADC0 ADC1 ADC2 ADC3 PG0 PG1/PWM1 RST XTALNPHY XTALPPHY MOSCin MOSCout OSC32in OSC32out WAKE HIB CMOD0 CMOD1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AGND AGND LM3S8962 12.4K 1% resistor required on Pin 41 for compatibility with future LM3S8962 revisions See Product Change Notification PCN-08001 AVDD AVDD VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VBAT LDO VDD25 VDD25 VDD25 VDD25 ERBIAS TXON RXIP 46 40 C5 37 R8 49.9 R9 49.9 C6 10pF C7 10pF 0.1UF R7 330 +3.3V +3.3V 6 RXIN 8 2 1 9 10 C12 0.1UF C13 0.01UF

基于LM3S9B92控制多路信号源的驱动电路设计的开题报告

基于LM3S9B92控制多路信号源的驱动电路设计的开题报告本文的开题报告将介绍基于LM3S9B92控制多路信号源的驱动电路设计，主要包括设计目的、系统框架、设计思路、设计方法、设计流程和预期结果等方面。

1. 设计目的本设计的目的是开发一种基于LM3S9B92控制多路信号源的驱动电路，用于实现对多种不同信号源的控制和驱动。

该驱动电路可以应用于多种场合，如电子测试、信号处理和蓝牙/ WIFI通讯等。

2. 系统框架本设计采用基于MCU的驱动电路框架，包括以下模块：（1）MCU模块：采用Cortex-M3内核的LM3S9B92单片机，主要用于控制和管理整个系统的运行。

（2）存储模块：采用板载Flash存储芯片，用于存储系统所需的各种配置文件和程序代码。

（3）信号源模块：采用多路信号源芯片，用于产生不同类型和频率的信号输出。

（4）驱动模块：用于驱动信号源芯片，使其输出所需的信号。

（5）控制模块：用于控制各种信号源的开关和输出状态，实现对多路信号源的控制和管理。

3. 设计思路本设计的关键在于采用了多路信号源芯片，可以同时输出多种不同类型和频率的信号，满足多种测试和应用需求。

同时，采用基于MCU的驱动电路框架，可以实现对多种信号源的控制和驱动，且具有较高的灵活性和扩展性。

4. 设计方法本设计的主要设计方法是采用硬件和软件相结合的方式，利用MCU芯片的强大功能实现对多路信号源的控制和驱动。

具体包括以下几个方面：（1）利用MCU芯片的定时器和串口等模块，实现对信号源芯片的驱动和控制。

（2）编写程序代码，实现对信号源的控制和管理，包括信号输出的频率、幅度、相位等方面。

（3）借助PC机上的控制软件，实现对整个系统的远程控制和监测。

5. 设计流程本设计的主要设计流程包括以下几个步骤：（1）确定系统框架：根据设计要求和实际应用需求，确定基于MCU的驱动电路框架，并选定相应的MCU芯片、存储芯片、信号源芯片和驱动电路等。

（2）选取元器件：根据系统框架和设计要求，选取相应的电子元器件，包括芯片、电容、电感、晶振、电源等。

SEED-IDM9B9X 硬件用户指南

SEED-IDM9B9X
硬件用户指南
2010-6
LM3S9B9X Solutions
截止印刷时文档名称和编号
SEED-IDM9B9X 硬件用户指南
文档历史
版本号 A 历史 2010-6-12 更新日期 2010-6-12
硬件版本历史
版本号 A 历史 2010-6-12 更新日期 2010-6-12
警告标志
本板卡包含 ESD 敏感器件，请采取适当的预防措施。使用时请不要用手或非绝缘的物体接触板卡。因使用不当造成的板卡损坏，本公司只提供付费的维修。本文中所有类似的警告标识，表明此部分内容有可能损害您的软件、硬件或其它设备。这个信息谨慎的为您提供保护，请仔细阅读阅读。
商标
SEED 是北京合众达电子技术有限责任公司的注册商标。 TI 是 Texas Instruments 的注册商标。
I
SEED-IDM9B9X
基于 LM3S9B9X 的嵌入式控制系统解决方案
硬件用户指南
版本号：A 2010.6

II
声明
北京合众达电子技术有限责任公司保留随时对其产品进行修正、改进和完善的权利，同时也保留在不作任何通告的情况下，终止其任何一款产品的供应和服务的权利。用户在下订单前应及时获取相关信息的最新版本，并验证这些信息是当前的和完整的。
版权© 2010，北京合众达电子技术有限责任公司
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前言
阅前必读
简介
本手册是基于 LM3S9B9X 的嵌入式多媒体系统解决方案板卡 SEED-IDM9B9X 的硬件使用说明书，详细描述了 SEED-IDM9B9X 的硬件构成、原理，以及它的使用方法。
保修
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从0开始学习LM3S9B92

从0开始学习LM3S9B92第一季武学大师曾经说过，真正的高手，都是手里无刀，心中有刀；而这把心中的刀，足以杀掉手持双刀的普通高手。

所以，我们力争要做到手中无芯片，心中有芯片。

恩，做到了，但是客户要的时候，怎么办？拿心中的芯片给他看呗。

我以前主要玩avr，最近项目的问题，觉得avr的有些缺陷已经限制了项目的开展，所以决定要从新学习一款快一些的cpu，选来选去，因为条件比较苛刻（既要温柔善良，又要端庄大方，咦，怎么变成选美去了。

），其实是需要集成以太网mac+phy的，于是乎，没得选择了，只有lm3的芯片满足要求。

左忙右忙的，今天终于抽空学习了下LM3S等等，锅里水开了，一会儿回来。

一、准备：a)学武需要准备啥？衣服，武器，鞋子，天气。

什么，衣服鞋子也要准备？恩，你试着穿着一条紧身牛仔裤去跑800米试试，你试着穿高跟鞋去跳远试试？那天气呢？打雷下雨的时候去跑马拉松看看？所以，计算机，下载器，芯片，板子，网络，嘿嘿，缺一不可。

b)准备好了，怎么办？还要练内功啊，没有内功作为基础，再好的招式也都是花架子。

所以，C语言和电路分析的功底要做好。

c)到此，可以开始练功了，欲练圣功，必先自宫。

二、软硬件a)哈哈，自宫的意思，不是让你把你的身体的某一部分在某种工具的辅助下，利用超大压强与本体强制分离，而是让你在学少林功夫的时候，暂时的忘记武当剑法。

同样，很多同学以前是学习51的，也有avr的，还有msp430的，pi c的，ht的，TM的，既然准备学习lm3s了，就把以前的暂时忘掉。

b)摆好心经。

将从网上下载或者光盘里面带的StellarisWare解压缩到C:\，我的版本是6852c)准备纸笔。

将从网上下载的mdk安装到C:\keil，因为我懒，不想装到其他盘，其他同学别学我。

d)准备武器。

将开发板的电源接起来，正常情况下应该在板子上显示正常，异常情况下应该在板子上显示异常。

连接调试器到计算机，并安装相应的驱动（我用的是jlink）三、开始学习a)打开C:\StellarisWare-6852\boards\dk-lm3s9b96-ili9325\enet_io，里面的enet_io.Uv2，系统会直接调用keil4来打开这个工程，工程打开后，会看到如下招式b)先不管招式怎么来的，怎么练的，怎么有用，怎么没用，怎么怎么，先从总体上看看是怎么样怎么的。