AD8353
AN-835_ 高速ADC测试和评估
应用范围
本应用笔记将介绍ADI公司高速转换器部门用来评估高速 ADC的特征测试和生产测试方法。本应用笔记仅供参考， 不能替代产品数据手册。
动态测试硬件设置
SNR、SINAD、最差杂散和IMD均通过类似于图1的硬件设 置进行测试。在生产测试中，测试硬件均高度集成，但硬 件原理都是一样的。动态测试的基本设置包括一个信号发 生器、带通滤波器、测试夹具、低噪声电源、编码源(通常 集成于评估板中)、数据采集模块和数据分析软件。ADI公 司提供了相应的应用软件和硬件，用以在基准评估中提供 帮助。请参阅“ADC FIFO套件”部分。
修订历史
4/06 — 版本0：初始版
共模输入范围(V) .................................................................... 15 共模抑制比(CMRR, dB) .......................................................... 15 孔径延迟(ps) ............................................................................ 16 孔径抖动或孔径不确定度(ps RMS) ....................................... 17 串扰(dB) ................................................................................... 17 等效输入噪声(LSB RMS) ........................................................ 17 范围外恢复时间(时钟周期) ................................................... 17 数字时域 ................................................................................. 17 转换误码率(CER) .................................................................... 19 直流测试定义 ................................................................................ 20 增益误差(%FS) ........................................................................ 20 增益匹配(%FS) ........................................................................ 20 失调误差(%FS) ........................................................................ 20 失调匹配(mV) ......................................................................... 20 温度漂移(ppm) ........................................................................ 20 高电平输出电压 /低电平输出电压(VOH/VOL, V) ............... 20 线性度 ..................................................................................... 20 电源抑制比(PSRR, dB) ............................................................. 22 参考资料 .......................................................................................... 23
ad835乘法器电路
ad835乘法器电路AD835概述AD835是一款完整的四象限电压输出模拟乘法器，采用先进的介质隔离互补双极性工艺制造。
它产生X和Y电压输入的线性乘积，3dB 输出带宽为250 MHz（小信号上升时间为1 ns）。
满量程（1V至+1V 上升至下降时间为2.5ns（采用150 Ω的标准RL），同样条件下的0.1%建立时间典型值为20 ns。
AD835不仅具有出众的速度性能，而且易于使用，功能丰富。
例如，除允许在输出端添加信号之外，Z输入端还能使AD835的工作电压放大最高约10倍。
因此，该放大器的乘积噪声非常低（50 nV/Hz），远胜于早期产品。
AD835采用8引脚PDIP封装（N）和8引脚SOIC封装（R），额定温度范围为40℃至+85℃工业温度范围。
AD835产品特点和性能优势简单：基本函数为W=XY+Z完整：只需极少的外部元件直流耦合电压输出简化应用高速：满量程的0.1%建立时间仅20ns高差分输入阻抗X、Y和Z输入低乘法器噪声50nV/vHzAD835性能参数与特点AD835是AnalogDevices公司生产的电压输出四象限乘法器电路，能够完成W=XY+Z功能，X和Y输入信号范围为-1～+1V，带宽为250MHz，在20ns内可稳定到满刻度的=±．1％，乘法器噪声为50nV／，差分乘法器输入X和Y、求和输入Z具有高的输入阻抗，输出引脚端W具有低、的输出阻抗，输出电压范围为-2．5～+2．5V，可驱动负载电阻为25Ω。
其电源电压为±5V，电流消耗为25mA；工作温度范围为-40～+85℃。
AD835的引脚功能与封装形式AD835采用PDIP一8或者SOIC一8封装。
引脚端X1和X2、Y1和Y2为差分放大器的正、负输入端，Z为求和输入端，W为乘法器输出端，VP和VN为电源电压正端和负端。
ad835乘法器电路由AD835构成的乘法器电路如图4．1．1所示。
比例系数U可以利用在引脚端W和Z之间的电阻分压器进行调节。
ad835乘法器电路
ad835乘法器电路
AD835是一款高速乘法器电路，由Analog Devices公司生产。
它被设计用于高速信号处理应用，如电信、雷达和图像处理等领域。
AD835采用了一个双极性延迟差分放大器作为主要的乘法功
能单元。
该放大器采用了高度优化的架构，以实现极低的失配和高的线性度。
AD835的输入和输出电平可以接受0.8V至3.8V的范围，其带宽为600MHz。
它具有低的功耗特性，只需25mA的工作电流。
AD835乘法器电路的输入端包括一个正输入端IN+和一个负
输入端IN-，输出端为OUT。
它可以实现精确的乘法运算，将输入信号与一个增益系数相乘，并输出结果。
AD835的主要特点包括：
1. 高速性能：具有600MHz的带宽，适用于高速信号处理。
2. 低功耗：工作电流只需25mA。
3. 高线性度：采用了高度优化的差分放大器架构，实现高线性度和低失配。
4. 宽电压范围：输入和输出电平可以接受0.8V至3.8V的范围。
5. 高精度：能够实现精确的乘法运算。
6. 双极性输出：输出信号可以具有正负两种极性。
AD835乘法器电路可以用于各种应用，如频率合成器、滤波
器、功率测量等。
它能够快速准确地进行乘法运算，提高信号处理的速度和精度。
AD835应用
华中科技大学信号与控制综合实验报告专业：电气工程及其自动化班级：电气0612班日期：2008/10/7实验组别：第一组第一次实验指导老师：
学生姓名：王璠学号： 012006019801 分数：
图1.正弦波幅度调制与解调
图35的基本连接
为信号输入端，为信号输出端，W 和Z 之间的电阻网络起微调电2.AD8W
图4.低通滤波器的频率响应
四、实验步骤及波形记录
调节函数信号发生器，输出频率为500Hz，幅值为1V的正弦波，作为调制信号，接至实验电路的调制信号输入端；运行AD9851驱动程序，使之输出频率为的正弦波，作为载波信号，
接至实验电路的载波信号输入端（两路）
3.电路后级输出有比较大的直流分量。
最初确定的实验方案中，信号输入部分和各级之调节反馈电阻或输出端串电阻等方式使电路达到最佳性能。
AD835内部的基本电路单元也datasheet 中没有给出其带容性负载定合适电容值的方法，在两级AD835之间尝试了104，334，106，2200u 等电容值，发现第直接耦合方式，导致后级有较大的直流分量输出。
此问题有待进一步研究。
间均有设计有隔直电容。
但实际调试时发现高速运放带容性负载时性能比较特殊，需要通过是高速运放，但的特性，由于经验不足，找不到一个确二级AD835的输入端均被拉低，随容值的增大，被拉低的电平有减小趋势。
最终电路采用
附录
附图1.调制与解调电路原理图
附图2.AD9851原理图
附图3.调制与解调电路
附图4.AD9851号产生电路
信。
ad835乘法器乘法公式
ad835乘法器乘法公式AD835乘法器乘法公式1. 什么是AD835乘法器AD835是一款高性能低失真的模拟乘法器芯片，由安捷伦科技公司研发生产。
它通过使用模拟法实现了精确的信号乘法运算，广泛应用于各种电子设备和仪器中。
2. AD835乘法器乘法公式AD835乘法器的乘法运算公式可以表示为：Vout = Vin1 * Vin2其中，Vout表示输出电压，Vin1和Vin2分别表示输入电压。
3. 公式说明和举例解释•输入电压Vin1和Vin2可以是直流电压或交流电压，其幅值范围取决于AD835乘法器的工作电压和规格。
•输出电压Vout是输入电压的乘积，即乘法器对输入信号进行数学乘法运算后得到的结果。
•举例说明：假设Vin1 = 2V，Vin2 = 3V，根据AD835乘法器的乘法公式，可以计算得到输出电压Vout = 2V *3V = 6V。
•AD835乘法器的优点是具有高精度、低失真和宽工作电压范围等特点，可用于模拟信号处理、功率放大器校正、电路调节等应用场景。
•需要注意的是，AD835乘法器的输入电压限制和输出电流限制等参数需要根据具体的应用需求进行选择和设置，以确保乘法器的正常工作和性能表现。
4. 总结AD835乘法器是一款高性能的模拟乘法器芯片，具有广泛的应用场景。
通过乘法器的乘法公式，可以实现输入电压的精确乘法运算，得到相应的输出电压。
该乘法器在模拟信号处理、功率放大器校正等领域具有重要作用，并且具备高精度、低失真等优点。
在应用过程中，需要根据具体需求设置乘法器的输入电压范围和输出电流限制等参数，以确保其良好的工作和性能表现。
5. 其他相关公式除了AD835乘法器的乘法运算公式外，还存在其他与乘法运算相关的公式，例如：乘法的交换律乘法运算具有交换律，即数值相乘的顺序可以改变，得到的结果是相同的。
例如，对于任意实数a和b，有：a *b = b * a举例说明：假设a=2，b=3，则有2 * 3 = 3 * 2 = 6。
3.3射频功率放大器电路设计实例
出OIP3为29dBm，放大器的输出内部匹配在50， MGA83563适合以电池为电源的个人通信设备应用，例 如无线数据、蜂窝电话和PCS。
MGA83563采用SOT-363（SC-70）封装，引脚1为电 源电压（Vd1），引脚2, 4, 5为地（GROUND），引脚 3为输入端（INPUT），引脚6为输出端和电源电压 （OUTPUT and Vd2）。
① PCB版面MGA83563封装引脚焊盘的尺寸
建议采用推荐使用的微型SOT-363（SC-70）封装的印 制电路板引脚焊盘。该设计提供大的容差，可以满足 自动化装配设备的要求，并能够减少寄生效应，保证 MGA83563的高频性能。
② PCB材料的选择
对于频率为3GHz的无线应用来说，可选择型号为FR-4 或G-10印制电路板材料，典型的单层板厚度是0.020～ 0.031英寸，多层板一般使用电介质层厚度在0.005～ 0.010英寸之间。更高的频率应用例如5.8GHz，建议使 用PTFE/玻璃的电介质材料的印制电路板。
3.3.4 基于AD8353的100MHz～2.7GHz
功率放大器驱动电路
AD8353是工作频率为100MHz～2.7GHz的宽带固定增 益的线性放大器，采用CP-8封装，AD8353内部具有二 级反馈放大器，有并联和串联两种反馈。第一级产生 大约10dB的增益。第二级是PNP-NPN达林顿输出级， 它也产生大约10dB的增益。单端输入单端输出，输入 端和输出端的阻抗为50，可直接插入在一个50的系 统中应用。
第1级功率放大器漏极偏置电压输入端（VD1）（引脚
7）连接一个100pF的旁路电容。
第2级功率放大器栅极偏置电压输入端（VG2）（引脚
频分复用硬件电路
第1章频分复用1.1 系统设计设计一个通信系统，首先是定系统指标和各种参数，在确定了通信特点为电缆全双工传输以后，根据通信要求中电缆传输12路语音信号带宽为60KHz～156KHz，我们需要分配带宽，语音信号的主带宽为300-3400Hz，加上各频段之间的保护带，我们给每路语音信号分配4KHz的基带带宽，由于要实现全双工通信，需要24路信道，若采用DSB双边带调制，需要占用2倍基带带宽，则调制后的一路信号占用8K带宽，则总共调制后的信号需要8*24=192KHz的带宽，60-156KHz 的传输带宽只有96KHz，显然不够用，故DSB在这里不被采用，我们选择SSB 单边带调制，可以节约一半的频谱资源，每路话音信号只需要4KHz传输带宽，刚好需要4*24=96KHz，符合信道要求。
划分好频段之后，是选择发送和接收机的调制体系，SSB调制有两种常用方法，一种是移相法，一种是滤波法，为了实现的方便，我们采用滤波法这一更为普遍采用的方法。
由于信号传输频率较低，没有专门的陶瓷或晶体滤波器可用，需要自制边带滤波器，故需要考虑滤波器的可行性，综合考虑了滤波器的参数后，发现一次调制是难以实现的，因此采用多级调制，这里采用二级调制，基本思路为：A到B，第一次用：12KHz，16KHz，20KHz调制形成前群，第二次用84，96，108，120KHz调制，发送传输带宽为60—108KHz；B到A，第一次用：12KHz，16KHz，20KHz调制形成前群，第二次用132KHz，144KHz，156KHz，168KHz 调制，发送传输带宽为108KHz—156KHz。
这样就把96KHz的低48KHz划分给了A的发送，高48KHz划给了B的发送。
由于需要全双工，故这里采用2-4线转换，避免“自发自收”的现象。
SSB信号由于不存在载波分量，故只能用提取导频法来做相干检波解调，因此在发送端第一级调制之后，应在BPF后插入导频。
AD8363资料
Conditions
Pins INHI, INLO, ac-coupled Single-ended drive
Pin 16 - TCM1=0.47V, Pin 1 - TCM2= 1.0V PIN = -10 dBm PIN = -40 dBm CW input, TA = +25°C
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
元器件交易网
Preliminary Technical Data
FEATURES
Accurate RMS-to-DC conversion from 50 Hz to 6 GHz Single ended input dynamic range of >50 dB Waveform and modulation independent, such as
AD835模块说明书
本店出售250M AD835乘法器模块，该板子布局布线紧凑有效，板子采用磁珠，陶瓷电容进行电源管脚去耦。
出色地抑制了电源的高频噪声，提高了芯片的PSRR。
并此类
板非常适合电子设计竞赛以及一些高速信号调理项目使用，能有效加速用户开发进程，性价比非常高。
AD835模块特点和参数
1、工作频率250M@-3dB
2、低噪声，出色的幅度和相位精度
3、公式W=XY+Z
4、工作电压典型+-5V，
5、接口介绍：
J1: Z端OFFESET调整电压输入,
默认接地。
J2:Y 端CARRIER IN 载波输入
J4:X 端MOD IN 调制信号输入
J3:W端OUTPUT 信号输出
6、2个输入端口留有相应的分压电阻，可实现交流耦合，分压等模式，扩展默
认输入+-1V最大输入限制。
输出端口也同样可配置成分压，交流耦合等模式。
7、提供模块PDF原理图
8、所有模块都严格测试后发货
9、静电袋包装后发货
10、提供售后技术支持。
运算放大器的参数、选型与应用
运算放大器的参数、选型与应用唐桃波长江大学国家级电工电子实验教学示范中心创新基地长江大学石油仪器研究室1•1930年TI的前身Geophysical service inc.成立，主要研发地震仪与石油探测仪。
•1950年Geophysical service inc.上市同时改名为TI。
•1956年Burr-Brown Research公司成立。
•1958年7月TI公司的Jack Kilby发明了集成电路(integrated circuit)简称IC。
•1963年Fairchild公司的Bob widlar发明了世界上第一片世界公认的单片集成电路运放μA702但是不是很成功。
•1965年1月MATT LORBER和RAY STATA创建了ADI公司。
•1965年11月Fairchild公司的Bob widlar发明了μA709大获成功，但是μA709不稳定,易烧坏，易锁闭。
•1967年Bob widlar离开Fairchild加入NSC（National Semiconductor后并入TI），同年发表了LM101，后来陆续开发了LM301,LM307，LM308，LM318，LM309等运放。
•1969年Fairchild公司的Dave Fullagar发表了发明了世界上第一款内置30pF相位补偿电容的运放μA741一直应用至今，现在还是各大高校模电实验的首选运放。
2•1975年PMI公司的George Erdi发表了世界上第一款精密运放OP07（后逐渐发展出OP27 OP37 OP177及OP27的JFET版本OPA627，OP37的JFET版本OPA637）.由于OP07太过经典，各大公司都推出了自己的相关产品。
•1972年NSC公司的Russell and Frederiksen引入新技术设计出LM324.•1975年RCA公司发布了CMOS运放CA3130.•1976年NSC公司发布了JFET运放LF356.•1978年TI发布了TL06X TL07X TL08X系列低价格JFET运放。
最常用芯片
器件型号封装数量功能备注运放THS3115ID SOIC-14 1具有关断状态的双路低噪声高输出电流的110MHz 放大器电源：±5V-±15V输出电流：150mA OPA2691 SOIC-14 3具有禁用功能的双路宽带电流反馈运算放大器高速放大器（大于等于50MHz）THS3115ID SOIC-14 2具有关断状态的双路低噪声高输出电流的110MHz 放大器电流反馈AD811 DIP-8 2TLC27L2ACD SOIC-8 2LinCMOS(TM) 精密双路运算放大器低功耗OPA209 SOIC-8 1单通道2.2nV/rtHz、18MHz、36V RRO 精密运算放大器电源：±2.25V to±18V, +4.5V to+36V OPA2209 SOIC-8 7双通道，其他同OPA209OPA699 SOIC-8 2宽带高增益限压放大器带宽积1000M；G=6，-3dB，BW=260M；SR=1400V/us电源：±5V SN10502 SOIC-8 2双路低失真高速轨至轨输出运算放大器；BW=100M（-3dB，G=2）;SR=500V/us；电源：3V-15V MAX4477 SOIC-8 2低噪声、低失真、宽带、满摆幅运算放大器电源：2.7V-5.5VGBW=10M AD603 SOIC-8 4低噪声、90 MHz可变增益放大器AD603 DIP-8 4INA103 SOL-16 1低噪声低失真仪表放大器，GBW=100M(G=1000)内置增益设置电阻：G=1，100电源：±9V/±25 OPA4830 TSSOP-14 1低功耗宽带放大器280MHz (G = +1)120MHz (G = +2)双电源：1.4V to ±5.5V单电源：+2.8V to +11VOPA2340PA DIP-8 3 单电源轨至轨运算放大器带宽: 5.5MHzTLC2262CD SOIC-8 4双路高级LinCMOS(TM) 轨至轨运算放大器低噪声PGA103U SOIC-8 3 可编程增益放大器NE5532DR SOIC-8 8 双路低噪声高速音频运算放大器OPA4354AIPWT SSOP-14 2 250MHz 轨至轨I/O CMOS 四路运算放大器OPA642 SOIC-8 1 单路宽带低失真放大器；GBW = 400M电源：±6.5VSN761666DGKR MSOP- 8 2 AGC 放大器Input Frequency(MHz)30 to 70LF353 DIP-8 1 宽带放大器，增益带宽积：3MHz双电源电压：±5,±9, ±12, ±15VMAX419EPD DIP-14 1 转换速率0.08V/us,增益带宽积150kHzLF411CN SOP-8 1 低偏置、低漂移JFET输入运算放大器线性运算放大器OP070 SOIC-8 4 低噪声JFET 输入解补偿运算放大器标准线性放大器TLV2472 DIP-8 1 双路低功耗轨至轨输入/输出运算放大器低噪声MAX414BCPD DIP-14 2 28M单位增益带宽低电源电压±2.4伏特到±5 VMAX9939 µMAX-10 1 MAX9939为通用、差分输入可编程增益放大器(PGA)，可理想动态变化范围较宽的信号调理超低增益温漂OPA2544T TO-220-11 2 增益带宽积1.4MHz，转换速率8 V/µs单路/双路(±)±10 V ~ 35 VSA7454C DIP-18 5 双通道AB类音频功率放大器D类功放SD7408 Hsop-28-375-0.8 72×10W模拟输入的D类音频功放TPA3123D2PWP SSOP-24 4具有SE 输出的25W 立体声D 类音频功率放大器乘法器AD835 SOIP-8 1AD835是一款完整的四象限电压输出模拟乘法器，采用先进的介质隔离互补双极性工艺制造。
AD8313
0.1 GHz to 2.5 GHz 70 dB Logarithmic Detector/ControllerAD8313Rev. DInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESWide bandwidth: 0.1 GHz to 2.5 GHz min High dynamic range: 70 dB to ±3.0 dBHigh accuracy: ±1.0 dB over 65 dB range (@ 1.9 GHz) Fast response: 40 ns full-scale typical Controller mode with error outputScaling stable over supply and temperature Wide supply range: 2.7 V to 5.5 V Low power: 40 mW at 3 VPower-down feature: 60 mW at 3 V Complete and easy to useAPPLICATIONSRF transmitter power amplifier setpoint control and level monitoringLogarithmic amplifier for RSSI measurement cellular base stations, radio link, radarFUNCTIONAL BLOCK DIAGRAM01085-C -001Figure 1.GENERAL DESCRIPTIONThe AD8313 is a complete multistage demodulating logarithmic amplifier that can accurately convert an RF signal at its differ-ential input to an equivalent decibel-scaled value at its dc output. The AD8313 maintains a high degree of log conformance for signal frequencies from 0.1 GHz to 2.5 GHz and is useful over the range of 10 MHz to 3.5 GHz. The nominal input dynamic range is –65 dBm to 0 dBm (re: 50 Ω), and the sensitivity can be increased by 6 dB or more with a narrow-band input impedance matching network or a balun. Application is straightforward, requiring only a single supply of 2.7 V to 5.5 V and the addition of a suitable input and supply decoupling. Operating on a 3 Vsupply, its 13.7 mA consumption (for T A = 25°C) is only 41 mW . A power-down feature is provided; the input is taken high to initiate a low current (20 µA) sleep mode, with a threshold at half the supply voltage.The AD8313 uses a cascade of eight amplifier/limiter cells, each having a nominal gain of 8 dB and a −3 dB bandwidth of3.5 GHz. This produces a total midband gain of 64 dB. At each amplifier output, a detector (rectifier) cell is used to convert the RF signal to baseband form; a ninth detector cell is placed directly at the input of the AD8313. The current-mode outputs of these cells are summed to generate a piecewise linear approxi-mation to the logarithmic function. They are converted to a low impedance voltage-mode output by a transresistance stage, which also acts as a low-pass filter.When used as a log amplifier, scaling is determined by a separate feedback interface (a transconductance stage) that sets the slope to approximately 18 mV/dB; used as a controller, this stageaccepts the setpoint input. The logarithmic intercept is positioned to nearly −100 dBm, and the output runs from about 0.45 V dc at −73 dBm input to 1.75 V dc at 0 dBm input. The scale and intercept are supply- and temperature-stable.The AD8313 is fabricated on Analog Devices’ advanced 25 GHz silicon bipolar IC process and is available in an 8-lead MSOP package. The operating temperature range is −40°C to +85°C. An evaluation board is available.INPUT AMPLITUDE (dBm)2.0–80O U T P U T V O L T A G E (V D C )1.81.61.41.21.00.80.60.40.20–70–60–50–40–30–20–104O U T P U T E R R O R (d B )01085-C -002Figure 2. Typical Logarithmic Response and Error vs. Input AmplitudeAD8313Rev. D | Page 2 of 24TABLE OF CONTENTSSpecifications.....................................................................................3 Absolute Maximum Ratings............................................................6 ESD Caution..................................................................................6 Pin Configurations and Function Description.............................7 Typical Performance Characteristics.............................................8 Circuit Description.........................................................................11 Interfaces..........................................................................................13 Power-Down Interface, PWDN................................................13 Signal Inputs, INHI, INLO........................................................13 Logarithmic/Error Output, VOUT..........................................13 Setpoint Interface, VSET............................................................14 Applications.....................................................................................15 Basic Connections for Log (RSSI) Mode.................................15 Operating in Controller Mode.................................................15 Input Coupling...........................................................................16 Narrow-Band LC Matching Example at 100 MHz................16 Adjusting the Log Slope.............................................................18 Increasing Output Current........................................................19 Effect of Waveform Type on Intercept.....................................19 Evaluation Board............................................................................20 Schematic and Layout................................................................20 General Operation.....................................................................20 Using the AD8009 Operational Amplifier..............................20 Varying the Logarithmic Slope.................................................20 Operating in Controller Mode.................................................20 RF Burst Response.....................................................................20 Outline Dimensions.......................................................................24 Ordering Guide.. (24)REVISION HISTORY6/04—Data Sheet Changed from Rev. C to Rev. DUpdated Evaluation Board Section..............................................21 2/03—Data Sheet changed from Rev. B to Rev. CTPCs and Figures Renumbered........................................Universal Edits to SPECIFICATIONS.............................................................2 Updated ESD CAUTION................................................................4 Updated OUTLINE DIMENSIONS..............................................7 8/99—Data Sheet changed from Rev. A to Rev. B 5/99—Data Sheet changed from Rev. 0 to Rev. A 8/98—Revision 0: Initial VersionAD8313Rev. D | Page 3 of 24SPECIFICATIONST A = 25°C, V S = 5 V 1, R L 10 kΩ, unless otherwise noted.Table 1.Parameter Conditions M in 2Typ M ax 2Unit SIGNAL INPUT INTERFACE Specified Frequency Range 0.1 2.5 GHz DC Common-Mode Voltage V POS – 0.75 V Input Bias Currents 10 µAInput Impedance f RF < 100 MHz 3900||1.1 Ω||pF 4LOG (RSSI) MODE Sinusoidal, input termination configurationshown in Figure 29100 MHz 5Nominal conditions ±3 dB Dynamic Range 6 53.5 65 dB Range Center −31.5 dBm ±1 dB Dynamic Range 56 dB Slope 17 19 21 mV/dB Intercept −96 −88 −80 dBm 2.7 V ≤ V S ≤ 5.5 V, −40°C ≤ T ≤ +85°C±3 dB Dynamic Range 51 64 dB Range Center −31 dBm ±1 dB Dynamic Range 55 dB Slope 16 19 22 mV/dB Intercept −99 −89 −75 dBm Temperature Sensitivity P IN = −10 dBm −0.022 dB/°C 900 MHz 5 Nominal conditions ±3 dB Dynamic Range 60 69 dB Range Center −32.5 dBm ±1 dB Dynamic Range 62 dB Slope 15.5 18 20.5 mV/dB Intercept −105 −93 −81 dBm 2.7 V ≤ V S ≤ 5.5 V, –40°C ≤ T ≤ +85°C±3 dB Dynamic Range 55.5 68.5 dB Range Center –32.75 dBm ±1 dB Dynamic Range 61 dB Slope 15 18 21 mV/dB Intercept –110 –95 –80 dBm Temperature Sensitivity P IN = –10 dBm –0.019 dB/°C1.9 GHz 7Nominal conditions ±3 dB Dynamic Range 52 73 dB Range Center –36.5 dBm ±1 dB Dynamic Range 62 dB Slope 15 17.5 20.5 mV/dB Intercept –115 –100 –85 dBm 2.7 V ≤ V S ≤ 5.5 V, –40°C ≤ T ≤ +85°C±3 dB Dynamic Range 50 73 dB Range Center –36.5 dBm ±1 dB Dynamic Range 60 dB Slope 14 17.5 21.5 mV/dB Intercept –125 –101 –78 dBm Temperature Sensitivity P IN = –10 dBm –0.019 dB/°CAD8313Rev. D | Page 4 of 24Parameter Conditions M in 2Typ M ax 2Unit2.5 GHz 7Nominal conditions ±3 dB Dynamic Range 48 66 dB Range Center –34 dBm ±1 dB Dynamic Range 46 dB Slope 16 20 25 mV/dB Intercept –111 –92 –72 dBm 2.7 V ≤ V S ≤ 5.5 V, –40°C ≤ T ≤ +85°C±3 dB Dynamic Range 47 68 dB Range Center –34.5 dBm ±1 dB Dynamic Range 46 dB Slope 14.5 20 25 mV/dB Intercept –128 –92 –56 dBm Temperature Sensitivity P IN =–10 dBm –0.040 dB/°C 3.5 GHz 5Nominal conditions ±3 dB Dynamic Range 43 dB ±1 dB Dynamic Range 35 dBSlope 24 mV/dB Intercept –65 dBm CONTROL MODE Controller Sensitivity f = 900 MHz 23 V/dBLow Frequency Gain VSET to VOUT 884 dB Open-Loop Corner Frequency VSET to VOUT 8 700 Hz Open-Loop Slew Rate f = 900 MHz 2.5 V/µs VSET Delay Time 150 ns VOUT INTERFACE Current Drive Capability Source Current 400 µA Sink Current 10 mA Minimum Output Voltage Open-loop 50 mV Maximum Output Voltage Open-loop V POS – 0.1 V Output Noise Spectral Density P IN = –60 dBm, f SPOT = 100 Hz 2.0 µV/√Hz P IN = –60 dBm, f SPOT = 10 MHz 1.3 µV/√Hz Small Signal Response Time P IN = –60 dBm to –57 dBm, 10% to 90% 40 60 ns Large Signal Response Time P IN = No signal to 0 dBm; settled to 0.5 dB 110 160 ns VSET INTERFACE Input Voltage Range 0 V POS V Input Impedance 18||1 kΩ||pF POWER-DOWN INTERFACE PWDN Threshold V POS /2 V Power-Up Response Time Time delay following high to low transitionuntil device meets full specifications.1.8 µs PWDN Input Bias Current PWDN = 0 V 5 µA PWDN = V S <1 µA POWER SUPPLY Operating Range2.7 5.5 V Powered-Up Current 13.7 15.5 mA4.5 V ≤V S ≤5.5 V, –40°C ≤ T ≤ +85°C 18.5 mA 2.7 V ≤V S ≤ 3.3 V, –40°C ≤ T ≤ +85°C 18.5 mA Powered-Down Current 4.5 V ≤V S ≤ 5.5 V, –40°C ≤ T ≤ +85°C 50 150 µA 2.7 V ≤V S ≤ 3.3 V, –40°C ≤ T ≤ +85°C 20 50 µAAD83131 Except where otherwise noted; performance at V S = 3 V is equivalent to 5 V operation.2 Minimum and maximum specified limits on parameters that are guaranteed but not tested are 6 sigma values.3 Input impedance shown over frequency range in Figure 26.4 Double vertical bars (||) denote “in parallel with.”5 Linear regression calculation for error curve taken from –40 dBm to –10 dBm for all parameters.6 Dynamic range refers to range over which the linearity error remains within the stated bound.7 Linear regression calculation for error curve taken from –60 dBm to –5 dBm for 3 dB dynamic range. All other regressions taken from –40 dBm to –10 dBm.8 AC response shown in Figure 12.Rev. D | Page 5 of 24AD8313Rev. D | Page 6 of 24ABSOLUTE MAXIMUM RATINGSTable 2.Supply Voltage V S 5.5 V VOUT, VSET, PWDN0 V, VPOS Input Power Differential (re: 50 Ω, 5.5 V) 25 dBm Input Power Single-Ended (re: 50 Ω, 5.5 V) 19 dBm Internal Power Dissipation 200 mW θJA200°C/W Maximum Junction Temperature 125°COperating Temperature Range –40°C to +85°C Storage Temperature Range –65°C to +150°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performancedegradation or loss of functionality.AD8313Rev. D | Page 7 of 24PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONVPOSINHI INLO VPOS 01085-C -003Figure 3. Pin ConfigurationTable 3. Pin Function DescriptionsPin No. Mnemonic Description1, 4 VPOS Positive Supply Voltage (VPOS), 2.7 V to 5.5 V.2 INHI Noninverting Input. This input should be ac-coupled.3 INLO Inverting Input. This input should be ac-coupled.5 PWDN Connect Pin to Ground for Normal Operating Mode. Connect this pin to the supply for power-down mode.6 COMM Device Common.7 VSET Setpoint Input for Operation in Controller Mode. To operate in RSSI mode, short VSET and VOUT. 8VOUTLogarithmic/Error Output.AD8313Rev. D | Page 8 of 24TYPICAL PERFORMANCE CHARACTERISTICST A = 25°C, V S = 5 V , R L input match shown in Figure 29, unless otherwise noted.INPUT AMPLITUDE (dBm)2.0V O U T (V )1.81.61.41.21.00.80.60.40.2001085-C -004Figure 4. V OUT vs. Input AmplitudeINPUT AMPLITUDE (dBm)6–6–7010–60E R R O R (d B )–50–40–30–20–1042–2–401085-C -005Figure 5. Log Conformance vs. Input AmplitudeINPUT AMPLITUDE (dBm)2.0–70V O U T (V )1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–1010543210–1–2–3–4–5E R R O R (d B )01085-C -006Figure 6. V OUT and Log Conformance vs. Input Amplitude at 100 MHz forMultiple TemperaturesINPUT AMPLITUDE (dBm)2.0–70V O U T (V )1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5E R R O R (d B )01-85-C -007Figure 7. V OUT and Log Conformance vs. Input Amplitude at 900 MHz forMultiple TemperaturesINPUT AMPLITUDE (dBm)2.0–70V O U T (V )1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010E R R O R (d B )01085-C -008Figure 8. V OUT and Log Conformance vs. Input Amplitude at 1.9 GHz forMultiple TemperaturesINPUT AMPLITUDE (dBm)2.0–70V O U T (V )1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5E R R O R (d B )01085-C -009Figure 9. V OUT and Log Conformance vs. Input Amplitude at 2.5 GHz forMultiple TemperaturesAD8313Rev. D | Page 9 of 24FREQUENCY (MHz)22211602500500S L O P E (m V /d B )1000150020002019181701085-C -010Figure 10. V OUT Slope vs. Frequency for Multiple TemperaturesSUPPLY VOLTAGE (V)242.5S L O P E (m V /d B )23222120191817161514 3.03.54.0 4.55.0 5.56.001085-C -011Figure 11. V OUT Slope vs. Supply VoltageFREQUENCY (Hz)01085-C -012Figure 12. AC Response from V SET to V OUT FREQUENCY (MHz)–110I N T E R C E P T (d B m )–70–80–90–10001085-C -013Figure 13. V OUT Intercept vs. Frequency for Multiple TemperaturesSUPPLY VOLTAGE (V)I N T E R C E P T (d B m )01085-C -014Figure 14. V OUT Intercept vs. Supply VoltageFREQUENCY (Hz)1000.1µV / H z11k10k 100k 1M 10M01085-C -015Figure 15. V OUT Noise Spectral DensityAD8313Rev. D | Page 10 of 24PWDN VOLTAGE (V)100.00S U P P L Y C U R R E N T (m A )10.001.000.100.0101085-C -016Figure 16. Typical Supply Current vs. PWDN VoltageCH. 1 GNDCH. 2 GNDCH. 3 GND01085-C -017Figure 17. PWDN Response Time 01085-C -019Figure 18. Response Time, No Signal to –45 dBmCH. 2 GND01085-C -020Figure 19. Response Time, No Signal to 0 dBm________________________________________________________________________________________________________________________________01085-C -018Figure 20. Test Setup for PWDN Response Time01085-C -021Figure 21. Test Setup for RSSI Mode Pulse ResponseCIRCUIT DESCRIPTIONThe AD8313 is an 8-stage logarithmic amplifier, specifically designed for use in RF measurement and power amplifier control applications at frequencies up to 2.5 GHz. A block diagram is shown in Figure 22. For a detailed description of log amp theory and design principles, refer to the AD8307 data sheet.VOUTVSETCOMMPWDN01085-C -001Figure 22. Block DiagramA fully differential design is used. Inputs INHI and INLO (Pins 2 and 3) are internally biased to approximately 0.75 V below the supply voltage, and present a low frequency impedance of nominally 900 Ω in parallel with 1.1 pF. The noise spectral density referred to the input is 0.6 nV/√Hz, equivalent to avoltage of 35 V rms in a 3.5 GHz bandwidth, or a noise power of −76 dBm re: 50 Ω. This sets the lower limit to the dynamic range; the Applications section shows how to increase the sensitivity by using a matching network or input transformer. However, the low end accuracy of the AD8313 is enhanced by specially shaping the demodulation transfer characteristic to partially compensate for errors due to internal noise.Each of the eight cascaded stages has a nominal voltage gain of 8 dB and a bandwidth of 3.5 GHz. Each stage is supported by precision biasing cells that determine this gain and stabilize it against supply and temperature variations. Since these stages are direct-coupled and the dc gain is high, an offset compensation loop is included. The first four stages and the biasing system are powered from Pin 4, while the later stages and the output inter-faces are powered from Pin 1. The biasing is controlled by a logic interface PWDN (Pin 5); this is grounded for normal operation, but may be taken high (to V S ) to disable the chip. The threshold is at V POS /2 and the biasing functions are enabled and disabled within 1.8 µs.Each amplifier stage has a detector cell associated with its output. These nonlinear cells perform an absolute value (full-wave rectification) function on the differential voltages along this backbone in a transconductance fashion; their outputs are in current-mode form and are thus easily summed. A ninth detector cell is added at the input of the AD8313. Since the midrange response of each of these nine detector stages isseparated by 8 dB, the overall dynamic range is about 72 dB (Figure 23). The upper end of this range is determined by the capacity of the first detector cell, and occurs at approximately 0 dBm. The practical dynamic range is over 70 dB to the ±3 dB error points. However, some erosion of this range can occur at temperature and frequency extremes. Useful operation to over 3 GHz is possible, and the AD8313 remains serviceable at 10 MHz, needing only a small amount of additional ripple filtering.INPUT AMPLITUDE (dBm)2.0–80V O U T (V )1.81.61.41.21.00.80.60.40.20–70–60–50–40–30–20–10543210–1–2–3–4–5E R R O R (d B )–9001085-c -023Figure 23. Typical RSSI Response and Error vs. Input Power at 1.9 GHzThe fluctuating current output generated by the detector cells, with a fundamental component at twice the signal frequency, is filtered first by a low-pass section inside each cell, and then by the output stage. The output stage converts these currents to a voltage, V OUT , at VOUT (Pin 8), which can swing rail-to-rail. The filter exhibits a 2-pole response with a corner at approximately 12 MHz and full-scale rise time (10% to 90%) of 40 ns. The residual output ripple at an input frequency of 100 MHz has an amplitude of under 1 mV . The output can drive a small resistive load; it can source currents of up to 400 µA, and sink up to 10 mA. The output is stable with any capacitive load, though settling time could be impaired. The low frequency incremental output impedance is approximately 0.2 Ω.In addition to its use as an RF power measurement device (that is, as a logarithmic amplifier), the AD8313 may also be used in controller applications by breaking the feedback path from VOUT to VSET (Pin 7), which determines the slope of the output (nominally 18 mV/dB). This pin becomes the setpoint input in controller modes. In this mode, the voltage V OUT remains close to ground (typically under 50 mV) until the decibel equivalent of the voltage V SET is reached at the input, when V OUT makes a rapid transition to a voltage close to V POS (see the Operating in Controller Mode section). The logarithmic intercept is nominally positioned at −100 dBm (re: 50 Ω); this is effective in both the log amp mode and the controller mode.With Pins 7 and 8 connected (log amp mode), the output can be stated as)dBm 100(+=IN SLOPE OUT P V Vwhere P IN is the input power stated in dBm when the source is directly terminated in 50 Ω. However, the input impedance of the AD8313 is much higher than 50 Ω, and the sensitivity of this device may be increased by about 12 dB by using some type of matching network (see below), which adds a voltage gain and lowers the intercept by the same amount. Dependence on the ref-erence impedance can be avoided by restating the expression as)V 2.2/(log 20µ×××=IN SLOPE OUT V V Vwhere V IN is the rms value of a sinusoidal input appearing across Pins 2 and 3; here, 2.2 µV corresponds to the intercept, expressed in voltage terms. For detailed information on the effect of signal waveform and metrics on the intercept positioning for a log amp, refer to the AD8307 data sheet. With Pins 7 and 8 disconnected (controller mode), the output can be stated asSET IN SLOPE S OUT V P V V V >→)100/(log when SET IN SLOPE OUT V P V V <→)100/(log when 0when the input is stated in terms of the power of a sinusoidal signal across a net termination impedance of 50 Ω. The transition zone between high and low states is very narrow since the output stage behaves essentially as a fast integrator. The above equations can be restated asSET IN SLOPE S OUT V V V V V >µ→)V 2.2/(log when SET IN SLOPE OUT V V V V <µ→)V 2.2/(log when 0Another use of the separate VOUT and VSET pins is in raising the load-driving current capability by including an external NPN emitter follower. More complete information about usage in these modes is provided in the Applications section.INTERFACESThis section describes the signal and control interfaces and their behavior. On-chip resistances and capacitances exhibit variations of up to ±20%. These resistances are sometimes temperature-dependent, and the capacitances may be voltage-dependent.POWER-DOWN INTERFACE, PWDNThe power-down threshold is accurately centered at the midpoint of the supply as shown in Figure 24. If Pin 5 is left unconnected or tied to the supply voltage (recommended), the bias enable current is shut off, and the current drawn from the supply is predominately through a nominal 300 kΩ chain (20 µA at 3 V). When grounded, the bias system is turned on. The threshold level is accurately at V POS /2. When operating in the device ON state, the input bias current at the PWDN pin is approximately 5 µA for V POS = 3 V .PWDN VPOS COMM 01085-C -024Figure 24. Power-Down Threshold CircuitrySIGNAL INPUTS, INHI, INLOThe simplest low frequency ac model for this interface consists of just a 900 Ω resistance, R IN , in shunt with a 1.1 pF input cap-acitance, C IN , connected across INHI and INLO. Figure 25 shows these distributed in the context of a more complete schematic. The input bias voltage shown is for the enabled chip; when disabled, it rises by a few hundred millivolts. If the input is coupled via capacitors, this change may cause a low level signal transient to be introduced, having a time constant formed by these capacitors and R IN . For this reason, large coupling capacitors should be well matched. This is not necessary when using the small capacitors found in many impedance transforming networks used at high frequencies.COMMVPOS INHI INLO VPOS01085-C -025Figure 25. Input Interface Simplified SchematicFor high frequency use, Figure 26 shows the input impedance plotted on a Smith chart. This measured result of a typical device includes a 191 mil 50 Ω trace and a 680 pF capacitor to ground from the INLO pin.1.1pF01085-C -026Figure 26. Typical Input ImpedanceLOGARITHMIC/ERROR OUTPUT, VOUTThe rail-to-rail output interface is shown in Figure 27. V OUT can run from within about 50 mV of ground, to within about 100 mV of the supply voltage, and is short-circuit safe to either supply. However, the sourcing load current, I SOURCE , is limited to that which is provided by the PNP transistor, typically 400 µA.Larger load currents can be provided by adding an external NPN transistor (see the Applications section). The dc open-loop gain of this amplifier is high, and it may be regarded as an integrator having a capacitance of 2 pF (C INT ) driven by the current-mode signal generated by the summed outputs of the nine detector stages, which is scaled approximately 4.0 µA/dB.LFROM SETPOINT SUMMED DETECTOR OUTPUTS01085-C -027Figure 27. Output Interface CircuitryThus, for midscale RF input of about 3 mV , which is some 40 dB above the minimum detector output, this current is 160 µA, and the output changes by 8 V/µs. When VOUT is connected to VSET, the rise and fall times are approximately 40 ns (for R L ≥ 10 kΩ ). The nominal slew rate is 2.5 V/µs. The HF compensation tech-nique results in stable operation with a large capacitive load, C L , though the positive-going slew rate is then limited by I SOURCE /C L to 1 V/µs for C L = 400 pF.SETPOINT INTERFACE, VSETThe setpoint interface is shown in Figure 28. The voltage, V SET, is divided by a factor of 3 in a resistive attenuator of 18 kΩ total resistance. The signal is converted to a current by the action of the op amp and the resistor R3 (1.5 kΩ), which balances the current generated by the summed output of the nine detector cells at the input to the previous cell. The logarithmic slope is nominally 3 µs × 4.0 µA/dB × 1.5 kΩ = 18 mV/dB.VSETVPOSCOMM185-C-28 Figure 28. Setpoint Interface CircuitryAPPLICATIONSBASIC CONNECTIONS FOR LOG (RSSI) MODE Figure 29 shows the AD8313 connected in its basic measurement mode. A power supply between 2.7 V and 5.5 V is required. The power supply to each of the VPOS pins should be decoupled with a 0.1 µF surface-mount ceramic capacitor and a 10 Ω series resistor.The PWDN pin is shown as grounded. The AD8313 may be disabled by a logic high at this pin. When disabled, the chip current is reduced to about 20 µA from its normal value of 13.7 mA. The logic threshold is at V POS/2, and the enable function occurs in about 1.8 µs. However, that additional settling time is generally needed at low input levels. While the input in this case is terminated with a simple 50 Ω broadband resistive match, there are many ways in which the input termi-nation can be accomplished. These are discussed in the Input Coupling section.VSET is connected to VOUT to establish a feedback path that controls the overall scaling of the logarithmic amplifier. The load resistance, R L, should not be lower than 5 kΩ so that the full-scale output of 1.75 V can be generated with the limited available current of 400 µA max.As stated in the Absolute Maximum Ratings table, an externally applied overvoltage on the VOUT pin, which is outside the range 0 V to V POS, is sufficient to cause permanent damage to the device. If overvoltages are expected on the VOUT pin, a series resistor, R PROT, should be included as shown. A 500 Ω resistor is sufficient to protect against overvoltage up to ±5 V; 1000 Ω should be used if an overvoltage of up to ±15 V is expected. Since the output stage is meant to drive loads of no more than 400 μA, this resistor does not impact device perform-ance for higher impedance drive applications (higher output current applications are discussed in the Increasing Output Current section).Figure 29. Basic Connections for Log (RSSI) Mode OPERATING IN CONTROLLER MODEFigure 30 shows the basic connections for operation in controller mode. The link between VOUT and VSET is broken and a set-point is applied to VSET. Any difference between V SET and the equivalent input power to the AD8313 drives V OUT either to the supply rail or close to ground. If V SET is greater than the equivalent input power, V OUT is driven toward ground, and vice versa.Figure 30. Basic Connections for Operation in the Controller Mode This mode of operation is useful in applications where the output power of an RF power amplifier (PA) is to be controlled by an analog AGC loop (Figure 31). In this mode, a setpoint voltage, proportional in dB to the desired output power, is applied to the VSET pin. A sample of the output power from the PA, via a directional coupler or other means, is fed to the input of the AD8313.185-C-31Figure 31. Setpoint Controller OperationV OUT is applied to the gain control terminal of the power amplifier. The gain control transfer function of the power amplifier should be an inverse relationship, that is, increasing voltage decreases gain.A positive input step on V SET (indicating a demand for increased power from the PA) drives V OUT toward ground. This should be arranged to increase the gain of the PA. The loop settles when V OUT settles to a voltage that sets the input power to the AD8313 to the dB equivalent of V SET.。
射频功率放大器电路设计实例
③ 接地 所有MGA83563的外围元器件的布局以MGA83563的引
脚焊盘为核心。 适当的接地才能保证电路得到最好的性能和维持器件
工作的稳定性。MGA83563全部的接地引脚端通过通孔 被连接到PCB背面的RF接地面。每一个通孔将被设置 紧挨着每个接地引脚，以保证好的RF接地。使用多个 通孔可进一步最小化接地路径的电感。 接地引脚端的PCB 焊盘在封装体下面没有连接在一起 ，以减少连接到多级放大器的接地引脚端，从而减少 级间不需要的反馈。每个接地引脚端都应该有它独立 的接地路径。注意，PCB导线应尽量不要设计隐藏在芯 片封装下面。
HPMX3003的LNA利用GaAs的低噪声特征，可构成一个 匹配的宽带放大器，具有13dB的增益，2.2dB的噪声系 数；HPMX3003的开关为线性操作并提供+55dBm的IP3 ；HPMX3003的功率放大器产生高达27.5dBm的输出功率 ，功率增加效率PAE为35％。HPMX3003采用微型SSOP28封装。
电源电压通过引脚6加到第二级FET的漏极，并与RF输
出连接。电感L3（RFC）被用来隔离RF输出信号到直流 电源去，并在电感RFC的电源端加一个旁路电容C4滤 去高频信号。在输出端的隔直电容C3防止电源电压加
到下一级电路。
为了防止输出功率的损耗，在工作频带上电感RFC的值 （即电抗）为几百欧姆。在更高的工作频率时，可以
3.3.2 基于CGB240的蓝牙功率放大器电路
CGB240是一个蓝牙射频功率放大器，其符合IEEE 802.11b标准，可以应用于蓝牙（1级）、家庭RF、 WLAN、无绳电话、2.4～2.5GHz ISM频带等无线系统 中。
CGB240采用单电源供电，工作电压范围为2.0～5.5V
典型DA转换DAC0832芯片4580
XFER
DGND AGND
13
PC总线
D7~D0
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输入 寄存
ILE
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地 port1 CS
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port2
XFER &
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DAC 寄存
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D/A IOUT2 转换
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IOUT1
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转换一个数据的程序段：
MOV AL, data ;取数字量 MOV DX，port1 OUT DX, AL ;打开第一级锁存 MOV DX, port2 OUT DX, AL ;打开第二级锁存
• 双积分式A/D转换器组成： 积分器A1； 零电压比较器A2； 计数器； 控制逻辑； 标准电压等。
29
双积分式A/D转换
S2
V01
模拟输入
C
VX
S1
VN
标准电压
+ A1
V01 - 比较器 + A2
A/D启动 A/D结束
控制逻辑 ......
控制逻辑 ......
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转换一个数据的程序段：
ad835输入信号幅度过大烧坏
ad835输入信号幅度过大烧坏
AD835是一款高性能、低失真的四象限乘法器，通常用于模拟
信号处理电路中。
如果输入信号幅度过大，可能会导致AD835烧坏。
这个问题涉及到了几个方面，让我们从多个角度来分析：
1. 输入信号幅度过大的原因，输入信号幅度过大可能是由于外
部信号源的输出过载、误操作或者系统设计不当等原因导致的。
2. AD835烧坏的可能原因，当AD835接收到过大的输入信号时，可能会超出其可承受的范围，导致内部电路元件损坏，甚至烧坏。
3. 预防措施，为了避免输入信号幅度过大导致AD835烧坏，可
以采取一些预防措施，比如在输入端增加合适的电压限制电路，或
者在设计电路时考虑输入信号的幅度范围，选择合适的放大器或滤
波器等。
4. 故障排除，如果发现AD835烧坏，需要进行故障排除，首先
要检查输入信号源，确认输入信号幅度是否在规定范围内；其次要
检查AD835周围的电路，查找可能的故障原因，比如电源电压异常、接线错误等。
综上所述，输入信号幅度过大导致AD835烧坏是一个涉及到信号源、电路设计和故障排除的复杂问题，需要综合考虑多个因素并采取相应的预防和处理措施。
希望以上回答能够全面地解答你的问题。
ad835调幅电路输出失真
ad835调幅电路输出失真AD835是一种高性能调幅电路，它能够将输入的信号进行调幅处理，并输出相应的调幅信号。
然而，在使用AD835调幅电路时，我们可能会遇到输出失真的问题。
输出失真是指输出信号与输入信号存在明显的差异或畸变。
在调幅电路中，输出失真可能是由多种因素引起的，例如非线性特性、噪声干扰、电源波动等。
这些因素会导致输出信号的失真，降低调幅电路的性能和工作效果。
非线性特性是导致输出失真的主要原因之一。
调幅电路中的非线性元件会引起输入信号的非线性失真，从而影响输出信号的准确性和稳定性。
为了减少非线性失真，我们可以采取一些措施，如增加负反馈、优化电路设计、选择高品质的元件等。
噪声干扰也是导致输出失真的重要因素。
在实际应用中，调幅电路往往会受到来自外界的各种干扰和噪声，例如电源噪声、环境干扰等。
这些干扰和噪声会引入到电路中，使得输出信号产生失真。
为了降低噪声干扰对输出信号的影响，我们可以采取一些抑制噪声的措施，如增加滤波电路、提高信号与噪声的比例等。
电源波动也会对AD835调幅电路的输出产生影响。
电源波动会导致电路工作点的变化，进而引起输出信号的失真。
为了减少电源波动对输出信号的干扰，我们可以采用稳压电源、增加电源滤波电路等措施，确保电路工作在稳定的工作点上。
除了上述因素外，还有一些其他因素也可能导致AD835调幅电路的输出失真，如温度变化、元件老化等。
因此，在实际应用中，我们需要综合考虑各种因素，选择合适的措施来降低输出失真，提高调幅电路的性能。
为了解决AD835调幅电路的输出失真问题，我们可以采取一些实用的方法。
首先，我们可以对电路进行精确的参数调整和校准，以确保电路工作在最佳状态下。
其次，我们可以选择高品质的元件，提高电路的工作稳定性和可靠性。
此外，合理设计电路布局，降低电路之间的干扰，也是减少输出失真的有效手段。
AD835调幅电路的输出失真是影响其性能的重要因素之一。
我们需要针对不同的失真原因，采取相应的措施来降低失真，提高电路的性能和工作效果。
AM信号
正弦信号发生器作者：曾立丁运鸿陈亮赛前辅导及文稿整理辅导教师：肖看摘要本系统以51单片机及FPGA为控制核心，由正弦信号发生模块、功率放大模块、调幅（AM）、调频（FM）模块、数字键控（ASK，PSK）模块以及测试信号发生模块组成。
采用数控的方法控制DDS芯片AD9851产生5Hz－20MHz正弦信号，经滤波、放大和功放模块放大至6v并具有一定的驱动能力。
测试信号发生模块产生的1kHz正弦信号经过调幅（AM）模块、调频（FM）模块，对高频载波进行调幅或调频。
二进制基带序列信号送入数字键控模块，产生二进制PSK或ASK 信号，同时对ASK信号进行解调，恢复出原始数字序列。
另外，本系统还配备有液晶显示屏、遥控键盘，提供了友好的人机交互界面。
ABSTRACTThis system is in the core of Micro-Processor and FPGA (Field Programmable Gate Array), consist of sine signal generating module, Power amplifier, Amplitude Modulator, Frequency Modulator, ASK/PSK module and test signal generating module. The AD9851 controlled by Micro－Process in digital way to generate sine signal with the bandwidth 5Hz to 20MHz adjustable per 1Hz. After processing by LPF & power amplifier, the output signal has a peak value of move than 6V. The sine signal at 1 KHz was send to AM and FM module to modulate the high frequency carrier waveform. The binary sequential was send to the relative module to generate ASK and PSK signal. At last demodulate module demodulate the ASK signal and got the same binary sequential as set before.In order to provide a friendly user interface, the LCD and remote infrared control keyboard was introduced in this system.一、方案的设计和论证题目要求产生1kHZ－10MHz正弦信号，并在此基础上，产生模拟调幅信号、模拟调频信号、二进制PSK、ASK信号。
ad835乘法器乘法公式
ad835乘法器乘法公式
摘要：
一、引言
二、ad835 乘法器的原理
三、ad835 乘法器的乘法公式
四、ad835 乘法器的应用领域
五、结论
正文：
一、引言
在电子电路设计中，乘法器是一种重要的基础元件。
其中，ad835 乘法器以其独特的性能和广泛的应用而受到广泛关注。
本文将详细介绍ad835 乘法器的原理、乘法公式及应用领域。
二、ad835 乘法器的原理
ad835 乘法器是一种模拟乘法器，它利用电容耦合技术将两个输入信号相乘，并将乘积输出。
ad835 具有高增益、低失真、低噪声等优点，使其成为高性能模拟电路的理想选择。
三、ad835 乘法器的乘法公式
对于ad835 乘法器，其乘法公式可以表示为：
输出信号= A * B
其中，A 和B 分别为输入信号1 和输入信号2。
在实际应用中，乘数和被乘数信号的幅度、相位以及频率等参数都需要满足一定条件，以保证乘法器
能够正常工作。
四、ad835 乘法器的应用领域
ad835 乘法器广泛应用于各种电子设备和系统中，例如音频处理、通信系统、自动控制、仪器仪表等。
在音频处理领域，ad835 乘法器可以实现音量控制、音调调整等功能；在通信系统中，ad835 乘法器可以用于信号处理、滤波器设计等；在自动控制领域，ad835 乘法器可以用于传感器信号处理、误差放大等。
五、结论
总之，ad835 乘法器是一种高性能的模拟乘法器，具有广泛的应用领域。
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1 MHz to 2.7 GHzRF Gain BlockAD8353 Rev. CInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 © 2002–2009 Analog Devices, Inc. All rights reserved.FEATURESFixed gain of 20 dBOperational frequency of 1 MHz to 2.7 GHz Linear output power up to 9 dBmInput/output internally matched to 50 Ω Temperature and power supply stable Noise figure: 5.3 dBPower supply: 3 V or 5 VAPPLICATIONSVCO buffersGeneral Tx/Rx amplificationPower amplifier predriversLow power antenna drivers FUNCTIONAL BLOCK DIAGRAMRFINVPOSRFOUTCOM2 COM12721-1Figure 1.GENERAL DESCRIPTIONThe AD8353 is a broadband, fixed-gain, linear amplifier that operates at frequencies from 1 MHz up to 2.7 GHz. It is intended for use in a wide variety of wireless devices, including cellular, broadband, CATV, and LMDS/MMDS applications. By taking advantage of ADI’s high performance, complementary Si bipolar process, these gain blocks provide excellent stability over process, temperature, and power supply. This amplifier is single-ended and internally matched to 50 Ω with a return loss of greater than 10 dB over the full operating frequency range. The AD8353 provides linear output power of 9 dBm with 20 dB of gain at 900 MHz when biased at 3 V and an external RF choke is connected between the power supply and the output pin. The dc supply current is 42 mA. At 900 MHz, the output third-order intercept (OIP3) is greater than 23 dBm and is19 dBm at 2.7 GHz. The noise figure is 5.3 dB at 900 MHz. The reverse isolation (S12) is −36 dB at 900 MHz and −30 dB at 2.7 GHz.The AD8353 can also operate with a 5 V power supply; in which case, no external inductor is required. Under these conditions, the AD8353 delivers 8 dBm with 20 dB of gain at 900 MHz. The dc supply current is 42 mA. At 900 MHz, the OIP3 is greater than 22 dBm and is 19 dBm at 2.7 GHz. The noise figure is 5.6 dB at 900 MHz. The reverse isolation (S12) is −35 dB. The AD8353 is fabricated on ADI’s proprietary, high performance, 25 GHz, Si complementary, bipolar IC process. The AD8353 is available in a chip scale package that uses an exposed paddle for excellent thermal impedance and low impedance electrical connection to ground. It operates over a −40°C to +85°C temperature range, and an evaluation board is also available.AD8353Rev. C | Page 2 of 16TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ..............................................7 Theory of Operation ...................................................................... 13 Basic Connections ...................................................................... 13 Applications Information .............................................................. 14 Low Frequency Applications Below 100 MHz ........................... 14 Evaluation Board ............................................................................ 15 Outline Dimensions ....................................................................... 16 Ordering Guide .. (16)REVISION HISTORY3/09—Rev. B to Rev. CChanges to Lead Temperature (Soldering, 60 sec) Parameter, Table 3 ................................................................................................ 5 Changes to Ordering Guide . (16)12/05—Rev. A to Rev. BChanges to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Figure 16 ........................................................................ 9 Changes to Figure 32 ...................................................................... 11 Moved Figure 39 to Page 15; Renumbered Sequentially ........... 15 Changes to Ordering Guide . (16)8/05—Rev. 0 to Rev. AUpdated Format .................................................................. U niversal Changes to Product Title .................................................................. 1 Changes to Features, Figure 1, and General Description ............. 1 Changes to Table 1 ............................................................................. 3 Changes to Table 2 ............................................................................. 4 Changes to Figure 2 and Table 4 ...................................................... 6 Changes to Figure 3 caption and Figure 6 caption........................ 7 Changes to Figure 17 caption and Figure 20 caption ................... 9 Changes to Basic Connections Section ....................................... 13 Added Low Frequency Applications Below 100 MHz Section 14 Changes to Table 5 .......................................................................... 15 Changes to Ordering Guide .......................................................... 16 Updated Outline Dimensions ....................................................... 16 2/02—Revision 0: Initial VersionAD8353SPECIFICATIONSV S = 3 V, T A = 25°C, 100 nH external inductor between RFOUT and VPOS, Z O = 50 Ω, unless otherwise noted.Table 1.Parameter Conditions Min Typ Max Unit OVERALL FUNCTIONFrequency Range 1 2700 MHz Gain f = 900 MHz 19.8 dBf = 1.9 GHz 17.7 dBf = 2.7 GHz 15.6 dB Delta Gain f = 900 MHz, −40°C ≤ T A ≤ +85°C −0.97 dBf = 1.9 GHz, −40°C ≤ T A ≤ +85°C −1.15 dBf = 2.7 GHz, −40°C ≤ T A ≤ +85°C −1.34 dB Gain Supply Sensitivity VPOS ± 10%, f = 900 MHz 0.04 dB/Vf = 1.9 GHz −0.004 dB/Vf = 2.7 GHz −0.04 dB/V Reverse Isolation (S12) f = 900 MHz −35.6 dBf = 1.9 GHz −34.9 dBf = 2.7 GHz −30.3 dBRF INPUT INTERFACE Pin RFINInput Return Loss f = 900 MHz 22.3 dBf = 1.9 GHz 20.9 dBf = 2.7 GHz 11.2 dBRF OUTPUT INTERFACE Pin RFOUTOutput Compression Point f = 900 MHz, 1 dB compression 9.1 dBmf = 1.9 GHz 8.4 dBmf = 2.7 GHz 7.6 dBm Delta Compression Point f = 900 MHz, −40°C ≤ T A ≤ +85°C −1.46 dBf = 1.9 GHz, −40°C ≤ T A ≤ +85°C −1.17 dBf = 2.7 GHz, −40°C ≤ T A ≤ +85°C −1 dB Output Return Loss f = 900 MHz 26.3 dBf = 1.9 GHz 16.9 dBf = 2.7 GHz 13.3 dB DISTORTION/NOISEOutput Third-Order Intercept f = 900 MHz, ∆f = 1 MHz, P IN = −28 dBm 23.6 dBmf = 1.9 GHz, ∆f = 1 MHz, P IN = −28 dBm 20.8 dBmf = 2.7 GHz, ∆f = 1 MHz, P IN = −28 dBm 19.5 dBm Output Second-Order Intercept f = 900 MHz, ∆f = 1 MHz, P IN = −28 dBm 31.6 dBm Noise Figure f = 900 MHz 5.3 dBf = 1.9 GHz 6 dBf = 2.7 GHz 6.8 dB POWER INTERFACE Pin VPOSSupply Voltage 2.7 3 3.3 V Total Supply Current 35 41 48 mA Supply Voltage Sensitivity 15.3 mA/V Temperature Sensitivity −40°C ≤ T A ≤ +85°C 60 μA/°CRev. C | Page 3 of 16AD8353V S = 5 V, T A = 25°C, no external inductor between RFOUT and VPOS, Z O = 50 Ω, unless otherwise noted.Table 2.Parameter Conditions Min Typ Max Unit OVERALL FUNCTIONFrequency Range 1 2700 MHz Gain f = 900 MHz 19.5 dBf = 1.9 GHz 17.6 dBf = 2.7 GHz 15.7 dB Delta Gain f = 900 MHz, −40°C ≤ T A ≤ +85°C −0.96 dBf = 1.9 GHz, −40°C ≤ T A ≤ +85°C −1.18 dBf = 2.7 GHz, −40°C ≤ T A ≤ +85°C −1.38 dB Gain Supply Sensitivity VPOS ± 10%, f = 900 MHz 0.09 dB/Vf = 1.9 GHz −0.01 dB/Vf = 2.7 GHz −0.09 dB/V Reverse Isolation (S12) f = 900 MHz −35.4 dBf = 1.9 GHz −34.6 dBf = 2.7 GHz −30.2 dB RF INPUT INTERFACE Pin RFINInput Return Loss f = 900 MHz 22.9 dBf = 1.9 GHz 21.7 dBf = 2.7 GHz 11.5 dB RF OUTPUT INTERFACE Pin RFOUTOutput Compression Point f = 900 MHz 8.3 dBmf = 1.9 GHz 8.1 dBmf = 2.7 GHz 7.5 dBm Delta Compression Point f = 900 MHz, −40°C ≤ T A ≤ +85°C −1.05 dBf = 1.9 GHz, −40°C ≤ T A ≤ +85°C −1.49 dBf = 2.7 GHz, −40°C ≤ T A ≤ +85°C −1.33 dB Output Return Loss f = 900 MHz 27 dBf = 1.9 GHz 22 dBf = 2.7 GHz 14.3 dB DISTORTION/NOISEOutput Third-Order Intercept f = 900 MHz, ∆f = 1 MHz, P IN = −28 dBm 22.8 dBmf = 1.9 GHz, ∆f = 1 MHz, P IN = −28 dBm 20.6 dBmf = 2.7 GHz, ∆f = 1 MHz, P IN = −28 dBm 19.5 dBm Output Second-Order Intercept f = 900 MHz, ∆f = 1 MHz, P IN = −28 dBm 30.3 dBm Noise Figure f = 900 MHz 5.6 dBf = 1.9 GHz 6.3 dBf = 2.7 GHz 7.1 dB POWER INTERFACE Pin VPOSSupply Voltage 4.5 5 5.5 V Total Supply Current 35 42 52 mA Supply Voltage Sensitivity 4.3 mA/V Temperature Sensitivity −40°C ≤ T A ≤ +85°C 45.7 μA/°CRev. C | Page 4 of 16AD8353Rev. C | Page 5 of 16ABSOLUTE MAXIMUM RATINGSTable 3.Parameter Rating Supply Voltage, VPOS 5.5 V Input Power (re: 50 Ω) 10 dBm Equivalent Voltage 700 mV rms Internal Power Dissipation Paddle Not Soldered 325 mW Paddle Soldered 812 mWθJA (Paddle Soldered) 80°C/WθJA (Paddle Not Soldered) 200°C/WMaximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) AD8353ACP (Non-RoHS Compliant) 240°C AD8353ACPZ (RoHS Compliant) 260°CStresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTIONAD8353Rev. C | Page 6 of 16PIN CONFIGURATION AND FUNCTION DESCRIPTIONSCOM1NC RFIN COM2COM1RFOUTVPOSCOM204862-002NC = NO CONNECTFigure 2. Pin ConfigurationTable 4. Pin Function DescriptionsPin No.Mnemonic Description1, 8 COM1 Device Common. Connect to low impedance ground. 2 NC No Connection.3 RFIN RF Input Connection. Must be ac-coupled.4, 5 COM2 Device Common. Connect to low impedance ground. 6 VPOS Positive Supply Voltage.7RFOUTRF Output Connection. Must be ac-coupled.AD8353Rev. C | Page 7 of 16TYPICAL PERFORMANCE CHARACTERISTICS18015012090603033030027024021002721-003Figure 3. S 11 vs. Frequency, V S = 3 V, T A = 25°C, dc ≤ f ≤ 3 GHz02721-004G A I N (d B )FREQUENCY (MHz)Figure 4. Gain vs. Frequency, V S = 2.7 V, 3 V, and 3.3 V, T A = 25°C02721-005R E V E R S E I S O L A T I O N (d B )FREQUENCY (MHz)0–20–30–10–15–25–5–35–40Figure 5. Reverse Isolation vs. Frequency, V S = 2.7 V, 3 V, and 3.3 V, T A = 25°C18015012090603033030027024021002721-006Figure 6. S 22 vs. Frequency, VS = 3 V, T A = 25°C, dc ≤ f ≤ 3 GHz02721-007G A I N (d B )FREQUENCY (MHz)151052025Figure 7. Gain vs. Frequency, V S = 3 V, T A = −40°C, +25°C, and +85°C02721-0085001000150020003000R E V E R S E I S O L A T I O N (d B )2500FREQUENCY (MHz)0–20–30–10–15–25–5–35–40Figure 8. Reverse Isolation vs. Frequency, V S = 3 V, T A = −40°C, +25°C, and +85°CAD8353Rev. C | Page 8 of 1602721-009500100015002000300025000FREQUENCY (MHz)P 1d B (d B m )Figure 9. P 1dB vs. Frequency, V S = 2.7 V, 3 V, and 3.3 V, T A = 25°C02721-010351045250402015305OUTPUT 1dB COMPRESSION POINT (dBm)P E R C E N T A G E (%)Figure 10. Distribution of P 1dB , V S = 3 V, T A = 25°C, f = 2.2 GHz02721-011O I P 3(d B m )FREQUENCY (MHz)26161412282010221824Figure 11. OIP3 vs. Frequency, V S = 2.7 V, 3 V, and 3.3 V, T A = 25°C02721-012500100015002000300025000FREQUENCY (MHz)P 1d B (d B m )Figure 12. P 1dB vs. Frequency, V S = 3 V, T A = −40°C, +25°C, and +85°C02721-013OIP3 (dBm)P E R C E N T A G E (%)19.119.519.920.320.721.121.521.9Figure 13. Distribution of OIP3, V S = 3 V, T A = 25°C, f = 2.2 GHz02721-014O I P 3 (d Bm )FREQUENCY (MHz)26161412282010221824Figure 14. OIP3 vs. Frequency, V S = 3 V, T A = −40°C, +25°C, and +85°CAD8353Rev. C | Page 9 of 1602721-015N O I S E F I G U R E (d B m )FREQUENCY (MHz)5.55.04.54.08.06.57.06.07.5Figure 15. Noise Figure vs. Frequency, V S = 2.7 V, 3 V, and 3.3 V, T A = 25°C02721-016P E R C E N T A G E (%)NOISE FIGURE (dB)103525302015Figure 16. Distribution of Noise Figure, V S = 3 V, T A = 25°C, f = 2.2 GHz02721-0171801501209060300330300270240210Figure 17. S 11 vs. Frequency, V S = 5 V, T A = 25°C, dc ≤ f ≤ 3 GHz 02721-018N O I S E F I G U R E (d B )FREQUENCY (MHz)5.55.04.54.08.08.56.57.06.07.5Figure 18. Noise Figure vs. Frequency, V S = 3 V, T A = −40°C, +25°C, and +85°C02721-019S U P P L Y C U R RE N T (m A )TEMPERATURE (°C)–6010504004530155040352520–40206080–20100Figure 19. Supply Current vs. Temperature, V S = 2.7 V, 3 V, and 3.3 V02721-020180150120906030330300270240210Figure 20. S 22 vs. Frequency, V S = 5 V, T A = 25°C, dc ≤ f ≤ 3 GHzAD8353Rev. C | Page 10 of 1602721-021G A I N (d B )FREQUENCY (MHz)Figure 21. Gain vs. Frequency, V S = 4.5 V, 5 V, and 5.5 V, T A = 25°C02721-022R E V E R S E I S O L A T I O N (d B )FREQUENCY (MHz)5001000150020002500–20–30–3530000–10–40–15–25–50 Figure 22. Reverse Isolation vs. Frequency, V S = 4.5 V, 5 V, and 5.5 V, T A = 25°C02721-023P 1d B (d B m )FREQUENCY (MHz)10Figure 23. P 1dB vs. Frequency, V S = 4.5 V, 5 V, and 5.5 V, TA = 25°C 02721-024G A I N (dB )FREQUENCY (MHz)Figure 24. Gain vs. Frequency, V S = 5 V, T A = −40°C, +25°C, and +85°C02721-025R E V E R S E I S OL A T I O N (d B )FREQUENCY (MHz)–20–30–350–10–40–15–25–5Figure 25. Reverse Isolation vs. Frequency, V S = 5 V, T A = −40°C, +25°C, and +85°C02721-026500100015002000300025000FREQUENCY (MHz)P 1d B (d B m )Figure 26. P 1dB vs. Frequency, V S = 5 V, T A = –40°C, +25°C, and +85°C02721-027351045250402015305OUTPUT 1dB COMPRESSION POINT (dBm)P E R C E N T A G E (%)7.07.27.47.88.28.48.68.08.87.6Figure 27. Distribution of P 1dB , V S = 3 V, T A = 25°C, f = 2.2 GHz02721-028FREQUENCY (MHz)O I P 3 (d B m )500100015002000250020161230002624101814220Figure 28. OIP3 vs. Frequency, V S = 4.5 V, 5 V, and 5.5 V, T A = 27°C02721-029N O I S E F I G U R E (d B )FREQUENCY (MHz)50010001500200025006.55.54.530009.08.04.06.05.07.08.57.50Figure 29. Noise Figure vs. Frequency, V S = 4.5 V, 5 V, and 5.5 V, T A = 25°C 02721-030OIP3 (dBm)P E R C E N T A G E (%)Figure 30. Distribution of OIP3, V S = 5 V, T A = 25°C, f = 2.2 GHz02721-031FREQUENCY (MHz)O I P 3 (d B m )500100015002000250020161230002624101814220Figure 31. OIP3 vs. Frequency, V S = 5 V, T A = –40°C, +25°C, and +85°C02721-032FREQUENCY (MHz)N O I S E F I G U R E (d B m )75109486Figure 32. Noise Figure vs. Frequency, V S = 5 V, T A = –40°C, +25°C, and +85°C02721-033P E R C E N T A G E (%)NOISE FIGURE (dB)10302515520Figure 33. Distribution of Noise Figure, V S = 5 V, T A = 25°C, f = 2.2 GHz02721-034S U P P L Y C U R R E N T (m A )TEMPERATURE (°C)10504004530155352520Figure 34. Supply Current vs. Temperature, V S = 4.5 V, 5 V, and 5.5 V 02721-035P O U T (d B m )G A I N (d B )P IN (dBm)5015–1510–5–10Figure 35. Output Power and Gain vs. Input Power, V S = 3 V, T A = 25°C, f = 900 MHz02721-036P O U T (d B m )G A I N (d B )P IN(dBm)–305015–1510–5–10Figure 36. Output Power and Gain vs. Input Power, V S = 5 V, T A = 25°C, f = 900 MHzTHEORY OF OPERATIONThe AD8353 is a 2-stage, feedback amplifier employing both shunt-series and shunt-shunt feedback. The first stage is degenerated and resistively loaded and provides approximately 10 dB of gain. The second stage is a PNP-NPN Darlington output stage, which provides another 10 dB of gain. Series-shunt feedback from the emitter of the output transistor sets the input impedance to 50 Ω over a broad frequency range. Shunt-shunt feedback from the amplifier output to the input of the Darlington stage helps to set the output impedance to 50 Ω. The amplifier can be operated from a 3 V supply by adding a choke inductor from the amplifier output to VPOS. Without this choke inductor, operation from a 5 V supply is also possible. BASIC CONNECTIONSThe AD8353 RF gain block is a fixed gain amplifier with single-ended input and output ports whose impedances are nominally equal to 50 Ω over the frequency range 1 MHz to 2.7 GHz. Consequently, it can be directly inserted into a 50 Ω system with no impedance matching circuitry required.The input and output impedances are sufficiently stable vs. variations in temperature and supply voltage that no impedance matching compensation is required. A complete set of scattering parameters is available at .The input pin (RFIN) is connected directly to the base of the first amplifier stage, which is internally biased to approximately 1 V; therefore, a dc blocking capacitor should be connected between the source that drives the AD8353 and the input pin, RFIN. It is critical to supply very low inductance ground connections to the ground pins (Pin 1, Pin 4, Pin 5, and Pin 8) as well as to the backside exposed paddle. This ensures stable operation. The AD8353 is designed to operate over a wide supply voltage range, from 2.7 V to 5.5 V. The output of the part, RFOUT, is taken directly from the collector of the output amplifier stage. This node is internally biased to approximately 2.2 V when the supply voltage is 5 V. Consequently, a dc blocking capacitor should be connected between the output pin, RFOUT, and the load that it drives. The value of this capacitor is not critical, but it should be 100 pF or larger.When the supply voltage is 3 V, it is recommended that an external RF choke be connected between the supply voltage and the output pin, RFOUT. This increases the dc voltage applied to the collector of the output amplifier stage, which improves performance of the AD8353 to be very similar to the performance produced when 5 V is used for the supply voltage. The inductance of the RF choke should be approximately100 nH, and care should be taken to ensure that the lowest series self-resonant frequency of this choke is well above the maximum frequency of operation for the AD8353. For lower frequency operation, use a higher value inductor.Bypass the supply voltage input, VPOS, using a large value capacitance (approximately 0.47 μF or larger) and a smaller, high frequency bypass capacitor (approximately 100 pF) physically located close to the VPOS pin.The recommended connections and components are shown in Figure 40.APPLICATIONS INFORMATIONThe AD8353 RF gain block can be used as a general-purpose, fixed gain amplifier in a wide variety of applications, such as a driver for a transmitter power amplifier (see Figure 37). Its excellent reverse isolation also makes this amplifier suitable foruse as a local oscillator buffer amplifier that would drive the local oscillator port of an upconverter or downconverter mixer (see Figure 38).AD8353HIGH POWER AMPLIFIER02721-037Figure 37. AD8353 as a Driver Amplifier04862-038Figure 38. AD8353 as a LO Driver AmplifierLOW FREQUENCY APPLICATIONS BELOW 100 MHzThe AD8353 RF gain block can be used below 100 MHz. To accomplish this, the series dc blocking capacitors, C1 and C2, need to be changed to a higher value that is appropriate for the desired frequency. C1 and C2 were changed to 0.1 μF to accomplish the sweep in Figure 39.21.020.520.019.519.018.518.017.517.016.516.0CH 1: START 300.000kHz STOP 100.000MHzFigure 39. Low Frequency Application from300 kHz to 100 MHz at 5 V VPOS, −12 dBm Input PowerEVALUATION BOARDFigure 40 shows the schematic of the AD8353 evaluation board. Note that L1 is shown as an optional component that is used to obtain maximum gain only when V P = 3 V . The board is powered by a single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by a 0.47 μF and a 100 pF capacitor.02721-03904862-040Figure 40. Evaluation Board SchematicTable 5. Evaluation Board Configuration OptionsComponent Function Default Value C1, C2 AC coupling capacitors. 1000 pF,0603 C3 High frequency bypass capacitor. 100 pF 0603 C4 Low frequency bypass capacitor. 0.47 μF, 0603 L1Optional RF choke, used to increasecurrent through output stage when V P = 3 V. Not recommended for use when V P = 5 V.100 nH, 0603Figure 41. Silkscreen Top04862-041Figure 42. Component SideOUTLINE DIMENSIONS031207-AFigure 43. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]2 mm ×3 mm Body, Very Thin, Dual LeadCP-8-1Dimensions shown in millimetersORDERING GUIDEModel Temperature Range Package Description Package OptionBranding AD8353ACP-R2 −40°C to +85°C 8-Lead LFCSP_VDCP-8-1 JB AD8353ACP-REEL7 −40°C to +85°C 8-Lead LFCSP_VD, 7" Tape and Reel CP-8-1 JB AD8353ACPZ-REEL71 −40°C to +85°C8-Lead LFCSP_VD, 7" Tape and Reel CP-8-1 0EAD8353-EVALZ 1Evaluation Board1Z = RoHS Compliant Part.© 2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02721-0-3/09(C)。