翻译材料排版举例
翻译格式模板
外文翻译(译文字数不少于2000字)齿叶夜睡莲对曼扎拉湖(尼罗河三角洲)周边栽培的水稻的生长及产量的化感作用*学生:×××指导老师:×××摘要:(黑体,小四)在埃及曼扎拉湖周边新开垦的与外界阻隔的湖田中,莲属侵入稻田是导致农作物破坏和谷粒产量下降的一个主要原因。
本研究针对齿叶夜睡莲对水稻的化感作用提出了深刻的见解(Oryza sativa cavr. Giza-177)。
莲根状茎的提取液对水稻种子萌发和幼苗的生长具有抑制作用。
抑制的程度主要是受提取液的类型和浓度的影响。
其中乙醇提取液和水提取液的抑制作用要比氯仿提取液的抑制作用强。
乙醇提取液中的酚醛含量显示了它的最大的抑制作用。
在一个目标作物(水稻)和它的近邻(莲)的盆载实验中,大米的干重和相对生长率受种子年龄和莲根状茎密度的影响,生长率随着莲密度的增大而降低。
对一个生长了莲和未生长莲的稻田中的数据处理证明了生长莲的稻田中水稻的叶面积指数和产量均降低。
通过气相色谱法或质谱分析法识别潜在的化感化合物显示了莲根状茎中存在化感化合物酚醛。
(宋体,小四)关键词:(黑体,小四)莲提取液,酚醛,萌发,幼苗,生长,叶面积指数,谷粒产量,水稻,埃及(宋体,小四)引言(大标题,黑体,四号)在过去的几十年里,尼罗河上大规模面积的湿地都因为各种各样的发展目的而被开垦。
曼扎拉湖的大部分面积也被开垦,并且倾向于当作农田使用。
因为高水位和水稻土,水稻是新开垦区域种植的主要农作物。
很多农田中都有记录大米的产量严重降低。
但是明显的全年的栽培大米和苜蓿并相互更替并不是导致大米产量严重降低的主要原因,其中还包括很多其它因素,但是它们的重要性*原文:Ahmad K. Hegazy, W. M.Amer, A. A. Khedr. Allelopathic effect of Nymphaea lotus L. on growth and yield of cultivated rice around Lake Manzala (Nile Delta). Hydrobiologia, 2001,464: 133–142.还没有完全理解;比如,差的排水系统和部分稻子的不可收割。
翻译排版和一般要求
一、排版要求:1. 格式问题:(1)除有特殊要求外,文件都要做成双语对照的,即将译文一段对一段写在原文的下面。
注意:请不要将译文直接写在原文的后面,要另起一段。
为了格式的统一,译文的格式要和原文尽量保持一致。
一般来说,英翻中的译文首行空两格(两个汉字),中翻英的译文首行不空格。
具体格式如下:Word文件的格式:英译中:原文:The Parties agree that the Owner shall register this Tenancy Agreement within fifteen (15) days from the date of execution with the competent registration authorities at the district or county where the Premises is located in accordance with the relevant laws, and obtain the evidence of the registration and the record of the lease. If this Tenancy Agreement is amended or terminated after it has been registered and recorded, the Owner shall be responsible for registering the amendment or termination with the original registration authorities within fifteen (15) days from the date of such amendment or termination. The Owner shall be liable for all the costs, penalties, fines and disputes arising from its failure in registering this Tenancy Agreement or its amendment or termination.译文:双方约定,出租人应在本租赁协议签署日后十五(15)天内按照相关法律的规定,到房屋所在地区或国家的适当登记部门登记本租赁协议,并获得此登记的证明以及租赁记录。
外文翻译排版格式参考
毕业设计(论文)外文资料翻译系别:电子信息系专业:通信工程班级:B100309姓名:张杨学号: B外文出处:附件: 1. 原文; 2. 译文2014年03月An Introduction to the ARM 7 ArchitectureTrevor Martin CEng, MIEETechnical DirectorThis article gives an overview of the ARM 7 architecture and a description of its major features for a developer new to the device. Future articles will examine other aspects of the ARM architecture.Basic CharacteristicsThe principle feature of the ARM 7 microcontroller is that it is a register based load-and-store architecture with a number of operating modes. While the ARM7 is a 32 bit microcontroller, it is also capable of running a 16-bit instruction set, known as "THUMB". This helps it achieve a greater code density and enhanced power saving. While all of the register-to-register data processing instructions are single-cycle, other instructions such as data transfer instructions, are multi-cycle. To increase the performance of these instructions, the ARM 7 has a three-stage pipeline. Due to the inherent simplicity of the design and low gate count, ARM 7 is the industry leader in low-power processing on a watts per MIP basis. Finally, to assist the developer, the ARM core has a built-in JTAG debug port and on-chip "embedded ICE" that allows programs to be downloaded and fully debugged in-system.In order to keep the ARM 7 both simple and cost-effective, the code and data regions are accessed via a single data bus. Thus while the ARM 7 is capable of single-cycle execution of all data processing instructions, data transfer instructions may take several cycles since they will require at least two accesses onto the bus (one for the instruction one for the data). In order to improve performance, a three stage pipeline is used that allows multiple instructions to be processed simultaneously.The pipeline has three stages; FETCH, DECODE and EXECUTE. The hardware of each stage is designed to be independent so up to three instructions can be processed simultaneously. The pipeline is most effective in speeding up sequential code. However a branch instruction will cause the pipeline to be flushed marring its performance. As we shall see later the ARM 7 designers had some clever ideas to solve this problem.InstructionFig 1 ARM 3- Stage pipelineARM7 Programming ModelThe programmer's model of the ARM 7 consists of 15 user registers, as shown in Fig. 3, with R15 being used as the Program Counter (PC). Since the ARM 7 is a load-and- store architecture, an user program must load data from memory into the CPU registers, process this data and then store the result back into memory. Unlike other processors no memory to memory instructions are available.M1M2M34,R 1,R 2 (R 4=R 0+R 2)3Fig 2 Load And Store ArchitectureAs stated above R15 is the Program Counter. R13 and R14 also have special functions; R13 is used as the stack pointer, though this has only been defined as a programming convention. Unusually the ARM instruction set does not have PUSH and POP instructions so stack handling is done via a set of instructions that allow loading and storing of multiple registers in a single operation. Thus it is possible to PUSH or POP the entire register set onto the stack in a single instruction. R14 has special significance and is called the "link register". When a call is made to a procedure, the return address is automatically placed into R14, rather than onto a stack, as might be expected. A return can then be implemented by moving the contents of R14 into R15, the PC. For multiple calling trees, the contents of R14 (the link register) must be placed onto the stack.15 User registers +PCR13 is used as the stack pointer R14 is the link registerR14 is the Program Counter Current Program Status RegisterFig 3 User Mode Register ModelIn addition to the 16 CPU registers, there is a current program status register (CPSR). This contains a set of condition code flags in the upper four bits that record the result of a previous instruction, as shown in Fig 4. In addition to the condition code flags, the CPSR contains a number of user-configurable bits that can be used to change the processor mode, enter Thumb processing and enable/disable interrupts.31 30 29 28 27Negative Carry OverflowIRQ System UserUndefined instruction AbortThumb instruction setFig 4 Current Program Status Register and Flags Exception And Interrupt ModesThe ARM 7 architecture has a total of six different operating modes, as shown below. These modes are protected or exception modes which have associated interrupt sources and their own register sets.User: This mode is used to run the application code. Once in user mode the CPSR cannot be written to and modes can only be changed when an exception is generated.FIQ: (Fast Interrupt reQuest) This supports high speed interrupt handling. Generally it is used for a single critical interrupt source in a systemIRQ: (Interrupt ReQuest) This supports all other interrupt sources in a system Supervisor: A "protected" mode for running system level code to access hardware or run OS calls. The ARM 7 enters this mode after resetAbort: If an instruction or data is fetched from an invalid memory region, an abort exception will be generatedUndefined Instruction: If a FETCHED opcode is not an ARM instruction, an undefined instruction exception will be generated.The User registers R0-R7 are common to all operating modes. However FIQ mode has its own R8 -R14 that replace the user registers when FIQ is entered. Similarly, each of the other modes have their own R13 and R14 so that each operating mode has its own unique Stack pointer and Link register. The CPSR is also common to all modes. However in each of the exception modes, an additional register一the saved program status register (SPSR),is added. When the processor changes the current value of the CPSR stored in the SPSR,this can be restored on exiting the exception mode.System&User FIQ Supervisor Abort IRQ Undefined Fig 5 Full Register Set For ARM 7Entry to the Exception modes is through the interrupt vector table. Exceptions in the ARM processor can be split into three distinct types.(i) Exceptions caused by executing an instruction, these include software interrupts, undefined instruction exceptions and memory abort exceptions(ii) Exceptions caused as a side effect of an instruction such as a abort caused by trying to fetch data from an invalid memory region.(iii) Exceptions unrelated to instruction execution, this includes reset, FIQ and IRQ interrupts.In each case entry into the exception mode uses the same mechanism. On generation of the exception, the processor switches to the privileged mode, thecurrent value of the PC+4 is saved into the Link register (R14) of the privileged mode and the current value of CPSR is saved into the privileged mode's SPSR. The IRQ interrupts are also disabled and if the FIQ mode is entered, the FIQ interrupts are also disabled, Finally the Program Counter is forced to the exception vector address and processing of the exception can start. Usually the first action of the exception routine will be to push some or all of the user registers onto the stack.Prefetch Abort(instruction fetch memory abort)Software interrupt (SWI)Undefined instruction ResetData Abort (data access momory abort)IRQ (interrupt)FIQ (fast interrupt)Supervisor Undefined Supervisor Abort Abort IRQ FIQ0x000000000x0000001C0x000000040x0000000C 0x000000080x000000100x00000018Fig 6 ARM 7 Vector TableA couple of things are worth noting on the vector table. Firstly, there is a missing vector at 0x000000014. This was used on an earlier ARM architecture and is left empty on ARM 7 to allow backward compatibility. Secondly, the FIQ interrupt is at the highest address so the FIQ routines could start from this address, removing the need for a jump instruction to reach the routine. It helps make entry into the FIQ routine as fast as possible.Once processing of the exception has finished, the processor can leave the privileged mode and return to the user mode. Firstly the contents of any registers previously saved onto the stack must be restored. Next the CSPR must be restored from the SPSR and finally the Program Counter is restored by moving the contents of the link register to R15, . the Program Counter). The interrupted program flow can then restart.Data TypesThe ARM instruction set supports six data types namely 8 bit signed and unsigned, 16 bit signed and unsigned plus 32 bit signed and unsigned. The ARM processor instruction set has been designed to support these data types in Little or Big-endian formats. However most ARM silicon implementations use the Little-endian format. ARM instructions typically have a three-operand format, as shown below ADD Rl ,R2, R3 ; Rl=R2+R3ARM7 Program Flow ControlIn all processors there is a small group of instructions that are conditionally executeddepending on a group of processor flags. These are branch instructions such as branch not equal. Within the ARM instruction set, all instructions are conditionally executable.31 28CONDFig. 7 Instruction Condition Code BitsThe top four bits of each instruction contain a condition code that must be satisfied if the instruction is to be executed. This goes a long way to eliminating small branches in the program code and eliminating stalls in the pipeline so increasing the overall program performance. Thus for small conditional branches of three instructions or less, conditional execution of instructions should be used. For larger jumps, normal branching instructions should be used.Fig. 8 Instruction Condition CodesThus our ADD instruction below could be prefixed with a condition code, as shown. This adds no overhead to instruction executionEQADD R1,R2,R3 ;If(Zero flag = 1)then R1 = R2+R3The ARM7 processor also has a 32-bit barrel shifter that allows it to shift or rotate one of the operands in a data processing instruction. This takes place in the same cycle as the instruction. The ADD instruction could be expanded as followsEQADD R1,R2 R3,LSL #2 ; If ( Zero flag = 1) then R1 = R2+ (R3 x 4)Finally the programmer may decide if a particular instruction can set the condition code flags in the CPSR.EQADDS R1,R2 R3,LSL #2; If (Zero flag = 1) then R1 = R2 + (R3 x4)and set condition code flagsIn the ARM instruction set there are no dedicated call or return instructions. Instead these functions are created out of a small group of branching instructions.The standard branch (B) instruction allows a jump of around+-32Mb. A conditional branch can be formed by use of the condition codes. For example, a "branch not equal" would be the branching instruction B and the condition code "NE" for not equal giving "BNE". The next form of the branch instruction is the branch with link. This is the branch instruction but the current value of the PC +4 is saved into R14, the link register. This acts as a CALL instruction by saving the return address into R14. A return instruction is not necessary since a return can be implemented by moving R14 into the PC. The return is more complicated in the case of an interrupt routine. Depending on the type of exception, it may be necessary to modify the contents of the link register to get the correct return address. For example, in the case of an IRQ or FIQ interrupt, the processor will finish its current instruction, increment the PC to the next instruction and then jumping to the vector table. This means that the value in the link register is PC+4 or one instruction ahead of the return address. This means we need to subtract 4 from the value in the link register to get the correct return address.This can be done in a single instruction thus:SUBS pc, r14,#40x80000x400PC=0x80000x4000x8000Both thebranch and branch-with-link may perform an exchange between 32-bit and 16-bit instruction sets and vice versa .The Branch exchange will jump to a location and start to execute 16-bit Thumb instructions. Branch link exchange will jump to a location, save PC+4 into the linkregister and start execution of 16-bit Thumb instructions. In both cases, the T bit is set in the CPSR. An equivalent instruction is implemented in the Thumb instruction set to return to 32-bit ARM instruction processing.0x8000T=1Y=10x4000x4000x8000Fig. 10 Branch Exchange and Branch Link Exchange Instruction OperationSoftware InterruptsThe ARM instruction set has a software interrupt instruction. Execution of this instruction forces an exception as described above; the processor willenter supervisor mode and jump to the SWI vector at 0x00000008.Fig. 11 Software Interrupt InstructionThe bit field 0-23 of the SWI instruction is empty and can be used to hold an ordinal. On execution of an SWI instruction, this ordinal can be examined to determine which SWI procedure to run and gives over 16 million possible SWI functions.…Swi_ #1 . call swi function one…Tn the swi handlerregister unsigned*link ptr asm ("r14");In order to access OS calls or SFR registers, the user code must make a SWI call . All these functions are the running in a supervisor mode, with a separate stack and link register.As well as instructions to transfer data to and from memory and to CPU registers, the ARM 7 has instructions to save and load multiple registers. It is possible to load or save all 16 CPU registers or a selection of registers in a single instruction. Needless to say, this is extremely useful when entering or exiting a procedure.M0Fig. 12 Load and Store Multiple Instruction OperationThe CPSR and SPSR are only accessed by two special instructions to move their contents to and from a CPU register. No other instruction can act on them directly.MSRR15R15Fig. 13 Programming The SPSR And CPSR RegistersTHUMB SupportThe ARM processor is capable of executing both 32-bit (ARM) instructions and 16- Bit (Thumb instructions). The Thumb instruction set must always be entered by running a Branch exchange or branch link exchange instruction and NOT by setting the T bit in the CPSR. Thumb instructions are essentially a mapping of their 32 bit cousins but unlike the ARM instructions, they are unconditionally executed except though for branch instructions.Fig. 14 Thumb Instruction ProcessingThumb instructions reduced number of only have unlimited access to registers RO-R7 and R13一Rl5. A instructions can access the full register set.Thumb programmers modelThe Thumb instruction set has the same load and store multiple instructions as ARM and in addition, has a modified version of these instructions in the form of PUSH and POP that implement a full descending stack in the conventional manner. The Thumb instruction set also supports the SWI instruction, except that the ordinal field is only 8 bits long to support 256 different SWI calls. When the processor is executing Thumb code and an exception occurs, it will switch to ARM mode in order to process the exception. When the CPSR is restored the, Thumb bit will be reset and the processor continues to run Thumb instructions.BCXBXThumb Exception ProcessingThumb has a much higher code density than ARM code, needing some 70% of the space of the latter. However in a 32-bit memory, ARM code is some 40% faster than Thumb. However it should be noted that if you only have 16-bit wide memory then Thumb code will be faster than ARM code by about 45%. Finally the other important aspect of Thumb is that it can use up to 30% less power than ARM code.ARM7的体系结构介绍 特里沃马丁曾,鼠技术总监本文给出了ARM 7架构的概述和开发新的设备,以及主要功能的描述,未来将研究ARM 体系结构的其他方面。
外文翻译排版格式参考
毕业设计(论文)外文资料翻译系别:电子信息系专业:通信工程班级:B100309姓名:张杨学号:B10030942外文出处:附件: 1. 原文; 2. 译文2014年03月An Introduction to the ARM 7 ArchitectureTrevor Martin CEng, MIEETechnical DirectorThis article gives an overview of the ARM 7 architecture and a description of its major features for a developer new to the device. Future articles will examine other aspects of the ARM architecture.Basic CharacteristicsThe principle feature of the ARM 7 microcontroller is that it is a register based load-and-store architecture with a number of operating modes. While the ARM7 is a 32 bit microcontroller, it is also capable of running a 16-bit instruction set, known as "THUMB". This helps it achieve a greater code density and enhanced power saving. While all of the register-to-register data processing instructions are single-cycle, other instructions such as data transfer instructions, are multi-cycle. To increase the performance of these instructions, the ARM 7 has a three-stage pipeline. Due to the inherent simplicity of the design and low gate count, ARM 7 is the industry leader in low-power processing on a watts per MIP basis. Finally, to assist the developer, the ARM core has a built-in JTAG debug port and on-chip "embedded ICE" that allows programs to be downloaded and fully debugged in-system.In order to keep the ARM 7 both simple and cost-effective, the code and data regions are accessed via a single data bus. Thus while the ARM 7 is capable of single-cycle execution of all data processing instructions, data transfer instructions may take several cycles since they will require at least two accesses onto the bus (one for the instruction one for the data). In order to improve performance, a three stage pipeline is used that allows multiple instructions to be processed simultaneously.The pipeline has three stages; FETCH, DECODE and EXECUTE. The hardware of each stage is designed to be independent so up to three instructions can be processed simultaneously. The pipeline is most effective in speeding up sequential code. However a branch instruction will cause the pipeline to be flushed marring its performance. As we shall see later the ARM 7 designers had some clever ideas to solve this problem.InstructionFig 1 ARM 3- Stage pipelineARM7 Programming ModelThe programmer's model of the ARM 7 consists of 15 user registers, as shown in Fig. 3, with R15 being used as the Program Counter (PC). Since the ARM 7 is a load-and- store architecture, an user program must load data from memory into the CPU registers, process this data and then store the result back into memory. Unlike other processors no memory to memory instructions are available.M1M2M34,R1,R2 (R4=R0+R2)3Fig 2 Load And Store ArchitectureAs stated above R15 is the Program Counter. R13 and R14 also have special functions; R13 is used as the stack pointer, though this has only been defined as a programming convention. Unusually the ARM instruction set does not have PUSH and POP instructions so stack handling is done via a set of instructions that allow loading and storing of multiple registers in a single operation. Thus it is possible to PUSH or POP the entire register set onto the stack in a single instruction. R14 has special significance and is called the "link register". When a call is made to a procedure, the return address is automatically placed into R14, rather than onto a stack, as might be expected. A return can then be implemented by moving the contents of R14 intoR15, the PC. For multiple calling trees, the contents of R14 (the link register) must be placed onto the stack.15 User registers +PCR13 is used as the stack pointer R14 is the link registerR14 is the Program Counter Current Program Status RegisterFig 3 User Mode Register ModelIn addition to the 16 CPU registers, there is a current program status register (CPSR). This contains a set of condition code flags in the upper four bits that record the result of a previous instruction, as shown in Fig 4. In addition to the condition code flags, the CPSR contains a number of user-configurable bits that can be used to change the processor mode, enter Thumb processing and enable/disable interrupts.31 30 29 28 27Negative Carry OverflowIRQ System UserUndefined instruction AbortThumb instruction setFig 4 Current Program Status Register and Flags Exception And Interrupt ModesThe ARM 7 architecture has a total of six different operating modes, as shown below. These modes are protected or exception modes which have associated interruptsources and their own register sets.User: This mode is used to run the application code. Once in user mode the CPSR cannot be written to and modes can only be changed when an exception is generated. FIQ: (Fast Interrupt reQuest) This supports high speed interrupt handling. Generally it is used for a single critical interrupt source in a systemIRQ: (Interrupt ReQuest) This supports all other interrupt sources in a system Supervisor: A "protected" mode for running system level code to access hardware or run OS calls. The ARM 7 enters this mode after resetAbort: If an instruction or data is fetched from an invalid memory region, an abort exception will be generatedUndefined Instruction:If a FETCHED opcode is not an ARM instruction, an undefined instruction exception will be generated.The User registers R0-R7 are common to all operating modes. However FIQ mode has its own R8 -R14 that replace the user registers when FIQ is entered. Similarly, each of the other modes have their own R13 and R14 so that each operating mode has its own unique Stack pointer and Link register. The CPSR is also common to all modes. However in each of the exception modes, an additional register一the saved program status register (SPSR),is added. When the processor changes the current value of the CPSR stored in the SPSR,this can be restored on exiting the exception mode.System&User FIQ Supervisor Abort IRQ Undefined Fig 5 Full Register Set For ARM 7Entry to the Exception modes is through the interrupt vector table. Exceptions in the ARM processor can be split into three distinct types.(i) Exceptions caused by executing an instruction, these include software interrupts, undefined instruction exceptions and memory abort exceptions(ii) Exceptions caused as a side effect of an instruction such as a abort caused by trying to fetch data from an invalid memory region.(iii) Exceptions unrelated to instruction execution, this includes reset, FIQ and IRQ interrupts.In each case entry into the exception mode uses the same mechanism. On generation of the exception, the processor switches to the privileged mode, the current value of the PC+4 is saved into the Link register (R14) of the privileged mode and the current value of CPSR is saved into the privileged mode's SPSR. The IRQ interrupts are also disabled and if the FIQ mode is entered, the FIQ interrupts are also disabled, Finally the Program Counter is forced to the exception vector address and processing of the exception can start. Usually the first action of the exception routine will be to pushPrefetch Abort(instruction fetch memory abort)Software interrupt (SWI)Undefined instruction ResetData Abort (data access momory abort)IRQ (interrupt)FIQ (fast interrupt)Supervisor Undefined Supervisor Abort Abort IRQ FIQ0x000000000x0000001C0x000000040x0000000C 0x000000080x000000100x00000018Fig 6 ARM 7 Vector TableA couple of things are worth noting on the vector table. Firstly, there is a missing vector at 0x000000014. This was used on an earlier ARM architecture and is left empty on ARM 7 to allow backward compatibility. Secondly, the FIQ interrupt is at the highest address so the FIQ routines could start from this address, removing the need for a jump instruction to reach the routine. It helps make entry into the FIQ routine as fast as possible.Once processing of the exception has finished, the processor can leave the privileged mode and return to the user mode. Firstly the contents of any registers previously saved onto the stack must be restored. Next the CSPR must be restored from the SPSR and finally the Program Counter is restored by moving the contents of the link register to R15, (i.e. the Program Counter). The interrupted program flow can then restart.Data TypesThe ARM instruction set supports six data types namely 8 bit signed and unsigned, 16 bit signed and unsigned plus 32 bit signed and unsigned. The ARM processor instruction set has been designed to support these data types in Little or Big-endian formats. However most ARM silicon implementations use the Little-endian format. ARM instructions typically have a three-operand format, as shown belowADD Rl,R2, R3 ; Rl=R2+R3ARM7 Program Flow ControlIn all processors there is a small group of instructions that are conditionally executed depending on a group of processor flags. These are branch instructions such as branch not equal. Within the ARM instruction set, all instructions are conditionally executable.31 28CONDFig. 7 Instruction Condition Code BitsThe top four bits of each instruction contain a condition code that must be satisfied if the instruction is to be executed. This goes a long way to eliminating small branches in the program code and eliminating stalls in the pipeline so increasing the overall program performance. Thus for small conditional branches of three instructions or less, conditional execution of instructions should be used. For larger jumps, normal branching instructions should be used.Fig. 8 Instruction Condition CodesThus our ADD instruction below could be prefixed with a condition code, as shown. This adds no overhead to instruction executionEQADD R1,R2,R3 ;If(Zero flag = 1)then R1 = R2+R3The ARM7 processor also has a 32-bit barrel shifter that allows it to shift or rotate one of the operands in a data processing instruction. This takes place in the same cycle as the instruction. The ADD instruction could be expanded as followsEQADD R1,R2 R3,LSL #2 ; If ( Zero flag = 1) then R1 = R2+ (R3 x 4) Finally the programmer may decide if a particular instruction can set the condition code flags in the CPSR.EQADDS R1,R2 R3,LSL #2; If (Zero flag = 1) then R1 = R2 + (R3 x4)and set condition code flagsIn the ARM instruction set there are no dedicated call or return instructions. Instead these functions are created out of a small group of branching instructions.The standard branch (B) instruction allows a jump of around+-32Mb. A conditional branch can be formed by use of the condition codes. For example, a "branch notequal" would be the branching instruction B and the condition code "NE" for not equal giving "BNE". The next form of the branch instruction is the branch with link. This is the branch instruction but the current value of the PC +4 is saved into R14, the link register. This acts as a CALL instruction by saving the return address into R14. A return instruction is not necessary since a return can be implemented by moving R14 into the PC. The return is more complicated in the case of an interrupt routine. Depending on the type of exception, it may be necessary to modify the contents of the link register to get the correct return address. For example, in the case of an IRQ or FIQ interrupt, the processor will finish its current instruction, increment the PC to the next instruction and then jumping to the vector table. This means that the value in the link register is PC+4 or one instruction ahead of the return address. This means we need to subtract 4 from the value in the link register to get the correct return address. This can be done in a single instruction thus: SUBS pc, r14, #4// PC=Link register-40x80000x400PC=0x80000x4000x8000Fig 9 Branch and Branch Link Instruction OperationBranching instructions are also used to enter the 16-bit Thumb instruction set. Both the branch and branch-with-link may perform an exchange between 32-bit and 16-bit instruction sets and vice versa .The Branch exchange will jump to a location and start to execute 16-bit Thumb instructions. Branch link exchange will jump to a location, save PC+4 into the link register and start execution of 16-bit Thumb instructions. In both cases, the T bit is set in the CPSR. An equivalent instruction is implemented in the Thumb instruction set to return to 32-bit ARM instruction processing.0x8000T=1Y=10x4000x4000x8000Fig. 10 Branch Exchange and Branch Link Exchange Instruction Operation Software InterruptsThe ARM instruction set has a software interrupt instruction. Execution of thisinstruction forces an exception as described above; the processor will enter supervisor mode and jump to the SWI vector at 0x00000008.Fig. 11 Software Interrupt InstructionThe bit field 0-23 of the SWI instruction is empty and can be used to hold an ordinal. On execution of an SWI instruction, this ordinal can be examined to determine which SWI procedure to run and gives over 16 million possible SWI functions.…Swi_ #1 . call swi function one…Tn the swi handlerregister unsigned*link ptr asm ("r14");// define a pointer to the hnk register Switch ((*(link-ptr-1))&Ox00FFFFFF) //calculate the number of the swi function{Case 0x01 : SWI_unction (); //Call the function…}This can be used to provide a hardware abstraction layer. In order to access OS calls or SFR registers, the user code must make a SWI call . All these functions are therunning in a supervisor mode, with a separate stack and link register.As well as instructions to transfer data to and from memory and to CPU registers, the ARM 7 has instructions to save and load multiple registers. It is possible to load or save all 16 CPU registers or a selection of registers in a single instruction. Needless tosay, this is extremely useful when entering or exiting a procedure.M0Fig. 12 Load and Store Multiple Instruction OperationThe CPSR and SPSR are only accessed by two special instructions to move their contents to and from a CPU register. No other instruction can act on them directly.MSRMRSR15R15Fig. 13 Programming The SPSR And CPSR RegistersTHUMB SupportThe ARM processor is capable of executing both 32-bit (ARM) instructions and 16- Bit (Thumb instructions). The Thumb instruction set must always be entered byrunning a Branch exchange or branch link exchange instruction and NOT by setting the T bit in the CPSR. Thumb instructions are essentially a mapping of their 32 bit cousins but unlike the ARM instructions, they are unconditionally executed except though for branch instructions.Fig. 14 Thumb Instruction ProcessingThumb instructions reduced number of only have unlimited access to registers RO-R7 and R13一Rl5. A instructions can access the full register set.Fig.15 Thumb programmers modelThe Thumb instruction set has the same load and store multiple instructions as ARM and in addition, has a modified version of these instructions in the form of PUSH and POP that implement a full descending stack in the conventional manner. The Thumb instruction set also supports the SWI instruction, except that the ordinal field is only 8 bits long to support 256 different SWI calls. When the processor is executing Thumb code and an exception occurs, it will switch to ARM mode in order to process the exception. When the CPSR is restored the, Thumb bit will be reset and the processor continues to run Thumb instructions.BCXBXFig.16 Thumb Exception ProcessingThumb has a much higher code density than ARM code, needing some 70% of the space of the latter. However in a 32-bit memory, ARM code is some 40% faster than Thumb. However it should be noted that if you only have 16-bit wide memory then Thumb code will be faster than ARM code by about 45%. Finally the other important aspect of Thumb is that it can use up to 30% less power than ARM code.ARM7的体系结构介绍特里沃马丁曾,鼠技术总监本文给出了ARM 7架构的概述和开发新的设备,以及主要功能的描述,未来将研究ARM体系结构的其他方面。
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外文翻译原文1(中文宋体、英文Times New Roman Title of media choices, especially the Internet, prestige.Author (宋体小四顶格):Nationality (宋体小四顶格):Originate from (宋体小四顶格):译文1(中文宋体、英文Times New Roman译文标题作者国籍(宋体小四顶格):出处(宋体小四顶格):附件3外文翻译原文1Information technology capability and valueInformation technology (IT) has become an essential element of firm capability and a source of sustainable competitive advantage. Although it is widely accepted that IT resources contribute to performance and future growth potential of the firm, the empirical results of the relationship between IT capability and firm performance is still ambiguous [1,2]. The unavailability of publicly available data, the accelerated pace of IT innovation,the possible interactive effects betweenHypothesis 2 predicts that the relationship between human capital investment and firm performance will be positive and results from all the five models strongly support this hypothesis.Alternative Hypotheses 3A and 3B predict the possible interaction effects of IT capability and human capital investment on firm performance. Results from Models 1, 2 and 3 support Hypothesis 3B.……作者:Zorayda Ruth B.Andam国籍:菲律宾出处:Amercan Management Association译文1信息技术能力和价值创造:来自美国银行业的实证信息技术已成为企业能力的一个重要组成部分和可持续竞争优势的资源之一。
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Plant Model Generation for PLC SimulationHyeong-Tae ParkAbstract:This paper reports an automated procedure for constructing a plant model for PLC simulation. Since PLC programs contain only the control logic without information on the plant model, it is necessary to build the corresponding plant model to perform the simulation. Conventionally, a plant model for PLC simulation has been constructed manually, which requires much effort and indepth knowledge of the simulation. As a remedy for this problem, we propose an automated procedure for generating a plant model from the symbol table of a PLC program. To do so, we propose a naming rule for PLC symbols so that the symbol names include sufficient information on the plant model. By analysing such symbol names, we extract a plant model automatically. The proposed methodology has been implemented and test runs performed.Keywords: agile manufacturing; CAD/CAM; CAPP; simulation1. IntroductionTo survive and prosper in the modern manufacturing era, manufacturers need to continuously improve their products, as well as their production systems. A modern manufacturing line is a highly integrated system composed of automated workstations, such as robots with tool-changing capabilities, a hardware handling system and storage system, and a computer control system that controls the operations of the- 1 -entire system.Since the implementation of a manufacturing line requires heavy investment, proper verification of a line’s operational status sho uld be performed to ensure that the highly automated manufacturing system will successfully achieve the intended benefits. Simulation technology is considered to be an essential tool in the design and analysis of complex systems that cannot be easily described by analytical or mathematical models . Simulation is useful for calculating utilisation statistics, finding bottlenecks, pointing out scheduling errors, and even for creating manufacturing schedules. Traditionally, various simulation languages, including ARENA and AutoMod, have been used for the simulation of manufacturing systems. These simulation languages have been widely accepted both by industry and by academia; however, they remain as analysis tools for the rough design stage of a production line, because their simulation models are not sufficiently realistic to be utilised for a detailed design or for implementation purposes. For example, real production lines are usually controlled by PLC (Programmable Logic Controller) programs (Rullan 1997), but conventional simulation languages roughly describe the control logic with independent entity flows (job flows) between processes.- 2 -Production systems typically consist of simultaneously operating machines, which are controlled by PLCs, currently the most suitable and widely employed industrial control technology. A PLC emulates the behaviour of an electric ladder diagram. As they are sequential machines, to emulate the workings of parallel circuits that respond instantaneously, PLCs use an input/output symbol table and a scanning cycle. When a program is being run in a PLC it is continuously executing a scanning cycle. The program scan solves the Boolean logic related to the information in the input table with that in the output and internal relay tables. In addition, the information in the output and internal relay tables is updated during the program scan. In a PLC, this Boolean logic is typically represented using a graphical language known as a ladder diagram (IEC 2003).Since the abstraction levels of conventional simulators and PLC programs are quite different, the control logic of conventional simulators cannot be reused for the generation of PLC programs. Usually, electrical engineers manually write PLC programs by referring to the rough control logic of conventional simulators, as shown in Figure 1. Since PLC programming is a very tedious and error-prone job, it is essential to verify the PLC programs offline to reduce the stabilisation time of a production system.Previous approaches to a PLC program can be categorised into two groups:- 3 -(1) verification of a given PLC programand (2) generation of a dependable PLC program. In the first group, various software tools have been developed for the verification of PLC based systems via the use of timed automata, such as UPPAAL2k, KRONOS, Supremica and HyTech, mainly for programs written in a statement list language, also termed Boolean (Manesis and Akantziotis 2005). Such software tools verify PLC programs to a certain extent; however, they remain limited. Since they mainly focus on the checking of theoretical attributes (safety, liveness, and reachability), it is not easy for users to determine whether the PLC programs actually achieve the intended control objectives. In the second group, many researchers have focused on the automatic generation of PLC programs from various formalisms including state diagrams, Petri nets, and IDEF0. These formalisms can help the design process of control logics; however, it is still difficult to find hidden errors, which is the most difficult part of verifying a control program.Figure 2. The concept of PLC simulation.To overcome the aforementioned problems, it is necessary to utilise simulation techniques for PLC program verification. By simulating PLC programs, it is possible to analyse the control logic in various ways and recognise hidden errors more intuitively (David 1998). Although PLC simulation can be a very powerful tool for the detailed verification of a production system, the accompanying construction of a plant model is a major obstacle (the counterpart model of a control program). Since PLC programs only contain the control information, without device models, it is necessary to build a corresponding plant model to perform simulation, as shown in- 4 -Figure 2. However, constructing a plant model requires an excessive amount of time and effort. Sometimes, the plant model construction requires much more time than the PLC programming. This serves as the motivation for exploring the possibility of finding an automatic procedure for generating a plant model from a given PLC program.Figure3.Symbol table of a PLC program.Although the objective of a PLC program is not to describe a plant model (device models), the symbol table of a PLC program can provide a glimpse of the plant model. As shown in Figure 3, symbols in a PLC program usually contain some information related to the plant. For example, ‘EXLINE_MB_AGV_P1’ means that the symbol is a signal that is related to the control of an ‘AGV’ (Auto Guided Vehicl e) belonging to the ‘MB’ station of ‘EXLINE’ line. The above scenario reveals the key idea of the present study. If we can develop a proper naming rule for PLC symbols, then it might be possible to extract a plant model by analysing the symbol names.This paper has two major objectives: (1) to propose a proper naming rule for PLC symbols and (2) to develop a procedure for generating a plant model by analysing the symbol names. The application area of the proposed methodology includes all types of automated manufacturing systems controlled by PLC programs, such as automotive production lines, FMSs (flexible manufacturing systems), and ASRSs (automatic storage and retrieval systems). The overall structure of the paper is as follows. Section 2 addresses the specifications of a plant model for PLC simulation. Section 3 describes a naming rule for PLC symbols, which enables the automatic generation of a plant model. Finally, concluding remarks are given in Section 4.2. Plant model for PLC simulationBefore explaining the specification of a plant model enabling PLC simulation, we want to address the importance of the PLC simulation. Chuang et al. (1999) proposed a procedure for the development of an industrial automated production system that- 5 -- 6 -consists of nine steps, as follows: (1) define the process to be controlled; (2) make a sketch of the process operation; (3) create a written sequence of the process; (4) on the sketch, add the sensors needed to carry out the control sequence; (5) add the manual controls needed for the process setup or for operational checks; (6) consider the safety of the operating personnel and make additions and adjustments as needed;(7) add the master stop switches required for a safe shutdown; (8) create a ladder logic diagram that will be used as a basis for thePLC program; and (9) consider the possible points where the process sequence may go astray. The most time-consuming task for the control logic designers is the eighth step, which is usually done by the repetitive method of code writing, testing, and debugging until the control objectives are achieved (Manesis and Akantziotis 2005). This is the reason why conventional PLC programming is often inefficient and prone to human error. As the configurations of production lines and their control programs become more complicated, there is a strong need for a more efficient PLC simulation environment. It is hoped that this paper will take positive steps in this direction.A PLC can be considered as a dedicated computer system having input and output signals. To run a PLC, the corresponding plant model (the counterpart system) is required to interact with the input and output of the PLC. The behaviour of the plant model should be the same as that of the actual system to achieve PLC verification. Since a production line consists of various devices, including robots, transporters, jigs, solenoids, proximity sensors, and light sensors (Groover 2006), we can consider a plant model as a set of device models. To build such a device model, this paper em ploys Zeigler’s DEVS (Discrete Event Systems Specifications) formalism (Zeigler 1984, Kim 1994), which supports the specification of discrete event models in a hierarchical, modular manner. The semantics of the formalism are highly compatible with object-oriented specifications for simulation models. We use the atomic model of the DEVS formalism to represent the behavior of a device model. Formally, an atomic model M is specified by a 7-tuple:M =〈X, S,Y, sin δ,ext δ,λ ,t a 〉X input events setS sequential states setY output events setsin δ S→S: internal transition functionext δQ*X→S: external transition functionQ={(s, e)∣s ∈S, 0≤e ≤t a (s)}: total state of MλS →Y: output function- 7 -t a S →Real: time advance functionThe four elements in the 7-tuple, namely sin δ,ext δ,λand t a , are called the characteristic functions of an atomic model. The atomic model of the DEVS formalism can be considered as a timed-FSA (finite state automata), and it is suitable for describing the behaviour of a device model. Once the device models (plant model) are obtained, it becomes possible to perform the PLC simulation. Currently, device models should be construed manually, which takes much time and effort. To cope with the problem, the objective of the paper is to propose an automated generation procedure for device models.Before explaining the automatic generation procedure of a plant model, let us take a look at the manual procedure to construct device models. To construct a device model, first it is necessary to identify the set of tasks that are assigned to the device. The activation of each task is normally triggered by an external signal from PLC programs. Once the set of tasks is identified for a device, it is then possible to extract the state transition diagram, which defines an atomic model of the DEVS formalism. Figure 4(a) shows a simple example of an AGV (Automatic Guided Vehicle) with two tasks, T1 (movement from p1 to p2) and T2 (movement from p2 to p1). As the two tasks should be triggered by external events, the shell part of the AGV must have two input ports, termed here as Signal_1 and Signal_2, as shown in Figure 4(b).From the set of tasks, it is possible to instantiate the state transition diagram. For this example, there are four states, P1, DoT1, P2 and DoT2. While P1 and P2 take external events from the input ports (Signal_1, Signal_2) for state transitions, DoT1 and DoT2 take internal events that are the end events of the two tasks (T1 and T2). The DEVS atomic model of the virtual device, corresponding to the AGV, can be described as follows:- 8 -Shell of a virtual device:M=〈X,S,Y,sin δ,ext δ,λ ,t a 〉}2_,1_{Signal Signal =X S={P1,DOT1,P2,DOT2} Y={T1Done,T2Done}sin δ(DOT1)=P2 s i nδ(DOT2)=P1 ext δ(P1,Signal_1)=DOT1 ext δ(P2,Signal_2)=DOT2λ(DOT1)=T1Done λ(DOT2)=T2Donet a (DOT1)=Time_1 t a (DOT2)=Time_2Once a plant model has been constructed, it is possible to perform the PLC simulation, which enables the intuitive verification of a PLC program. Figure 5 shows the connections between a PLC program and a plant model. The plant model includes all device models of a production system, and the PLC program contains the control logic for the plant model. To integrate the plant model and the PLC program, it is necessary to define the mapping between the plant model and the PLC program, which is described by I/O mapping. To enable the visual verification of a PLC program, it is necessary to import 3D graphic models, which are controlled by the logical device models (the state transition diagrams). Since 3D graphic models are not always necessary, they are optional for PLC simulation. As mentioned already, the objective of this paper is to extract device models from the symbol names of PLC programs. To do so, it is necessary to develop a proper naming rule for PLC symbols. The naming rule will be addressed in the next section.3. Symbol naming for plant model generationAlthough IEC 61131-3 provides various standard specifications for a PLC, the naming rules of PLC symbols have rarely been brought into focus. Since there have been no standard rules for the naming of PLC symbols, it has been fully dependent on individual PLC programmers.To generate device models from PLC symbols, it is necessary to make PLC symbols that include enough information concerning the plant model. To achieve this objective, we interviewed many PLC programmers and analysed various conventional rules. As a result, we came up with a naming structure consisting of five fields: (1) line name, (2) process number, (3) device name, (4) input or output, and (5) task name (or state name). Figure 6 shows the naming structure for PLC symbols.If the PLC symbols are named according to the proposed naming structure, then it becomes possible to extract device models (atomic models of DEVS formalism) by simply analysing the symbol names. There are two types of symbols (signals), input or output, which are specified by the fourth field. The purpose of the output signal is to trigger a task that is specified by the fifth field. Thus, it is possible to identify the set of tasks of a device by analysing the output symbols. As mentioned already, once the set of tasks is identified for a device, it is then possible to extract the state transition diagram for the device model, which defines an atomic model of the DEVS formalism. While an output signal (symbol) is issued by a PLC to trigger a task, an input signal (symbol) is issued by a device to report the completion of the task to theδand internal transition functions PLC. This means that external transition functionsextδof a device model can be automatically extracted from the output and input sinsymbols, respectively. We demonstrate the generation procedure of a plant modelfrom PLC symbols using an example, as shown in Figure 7.- 9 -- 10 -In the example cell, we assume a part is loaded manually on the AGV by a worker. When the AGV senses the existence of a part, it moves to transfer the part to the machine. After the transfer, the machine performs machining to convert the part into a finished product. In this case, the plant model consists of two device models: an AGV model and a machine model. The PLC program to control the simple manufacturing cell is shown in Figure 8(a), and its symbol table is shown in Figure 8(b).As shown in Figure 8(b), the AGV model has two output symbols and two input symbols. From the output symbols (EX_OP_AGV_O_GOP1, EX_OP_AGV_O_GOP2), we can intuitively recognise that the AGV has two tasks- 11 -(movement from P2 to P1, and movement from P1 to P2). By using the output symbols, we can extract the state transition diagram, as well as the external transitionfunctions, as shown in Figure 9(a).As mentioned already, an output symbol triggers a task of a device model, and an input symbol is made by the device to notify the completion of the task. Since the execution of a task is performed internally by the device, the internal transition functions of a device model can easily be extracted from the input symbols(EX_OP_AGV_I_DONEGOP1, EX_OP_AGV_I_DONEGOP2). In this way, the device model of the machine can be extracted from the related symbols(EX_OP_MC_, etc.), as shown in Figure 9(b). The procedure for the construction of a device model can be described as follows.- 12 -(1) Identify all corresponding pairs between output symbols and input symbols. While an output symbol triggers a task, the corresponding input symbol reports the completion of the task. For example, EX_OP_AGV_O_GOP1 corresponds toEX_OP_AGV_I_DONEGOP1. (2) Define the states of a device mode using the last naming fields of input/output symbols. In the case of the AGV, we can define four states, GoP1, DoneGoP1, GoP2, and DoneGoP2. (3) Define external (internal) transition functions using output (input) symbols. Once a plant model has been obtained, it becomes possible to perform the PLC simulation by defining the I/O mapping relations between the plant model and the PLC symbols. Through the PLC simulation, we can efficiently check whether the PLC program achieves the control objectives or not.The proposed methodology was implemented in C++language, and test runs were made on a personal computer, as shown in Figure 10. The PLC program shown in Figure 8(a) was written using GX IEC developer version 7.0 provided byMitsubishi Electric Corporation. The GX IEC developer can export a symbol table in the form of an Excel file, as shown in Figure 8(b). The exported symbol table becomes the input for the generation of a plant model. Figure 10 shows that the generated device models by analysing the exported symbol table.4. Discussion and conclusionsThrough PLC simulation, it is possible to analyse control logic in various ways and recognise hidden errors more intuitively. Although PLC simulation can be a very powerful tool for the detailed verification of a production system, the accompanying construction of a plant model requires too much time and effort. To remedy this problem, we have proposed an automated procedure to generate a plant model from the symbol table of a PLC program. To do so, we have also proposed a naming rule for PLC symbols so that the symbol names include sufficient information on the plant model. By analysing the symbol names, a plant model can be extracted automatically. Since a plant consists of various manufacturing devices, we can consider a plant model as a set of device models. To represent such a device model, the proposed method employs Zeigler’s DEVS formalism. We use the atomic model of the DEVS formalism to describe the logical behavior of a device model. In other words, it is necessary to extract the device models from the symbol table in the form of an atomic model of the DEVS formalism. Although the proposed methodology only deals with the local verification of PLC programs, it is also possible to extend the methodologyto include the verification of mechanical aspects of the plant .- 13 -工厂模型生成PLC仿真Hyeong-Tae Park摘要 :本文介绍一个自动程序可编程序控制器(PLC)生成工厂模型仿真。
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2016届本科毕业设计(论文)文献翻译题目宋体三号字,加粗学院宋体四号字专业宋体四号字班级宋体四号字学号宋体四号字姓名宋体四号字指导教师宋体四号字开题日期宋体四号字文献一:(宋体五号)英文题目(居中,Times New Roman字体,三号加粗)正文(英文不少于10000印刷符号,Times New Roman字体,五号,首行缩进2.5字符,单倍行距,两边对齐)翻译一:(宋体五号,另起一页)中文题目(居中,黑体,三号加粗)正文(中文不少于2000字,宋体,五号,单倍行距,首行缩进2字符)文献二:(宋体五号,另起一页)英文题目(居中,Times New Roman字体,三号加粗)正文(英文不少于10000印刷符号,Times New Roman字体,五号,首行缩进2.5字符,单倍行距,两边对齐)翻译二:(宋体五号,另起一页)中文题目(居中,黑体,三号加粗)正文(中文不少于2000字,宋体,五号,单倍行距,首行缩进2字符)(请参照下面模板)文献一:Research on Spillover Effect of Foreign Direct Investment1. IntroductionIn recent decades, economists have begun to identify technical progress, or more generally, knowledge creation, as the major determinant of economic growth. Until the 1970s, the analysis of economic growth was typically based on neoclassical models that explain growth with the accumulation of labor, capital, and other production factors with diminishing returns to scale. In these models, the economy converges to steady state equilibrium where the level of per capita income is determined by savings and investment, depreciation, and population growth, but where there is no permanent income growth. Any observed income growth per capita occurs because the economy is still converging towards its steady state, or because it is in transition from one steady state to another.The policies needed to achieve growth and development in the framework of these models is therefore straightforward: increases in savings and investments and reductions in the population growth rate, shift the economy to a higher steady state income level. From the view of developing countries, however, these policies are difficult to implement. Low income and development levels are not only consequences, but also causes of low savings and high population growth rates. The importance of technical progress was also recognized in the neoclassical growth models, but the determinants of the level of technology were not discussed in detail; instead, technology was seen as an exogenous factor. Yet, it was clear that convergence in income percapita levels could not occur unless technologies converged as well.From the 1980s and onwards, growth research has therefore increasingly focused on understanding and ontogenetic technical progress. Modern growth theory is largely built on models with constant or increasing returns to reproducible factors as a result of the accumulation of knowledge. Knowledge is, to some extent, a public good, and R&D, education, training, and other investments in knowledge creation may generate externalities that prevent diminishing returns to scale for labor and physical capital. Taking this into account, the economy may experience positive long-run growth instead of the neoclassical steady state where per capita incomes remain unchanged. Depending on the economic starting point, technical progress and growth can be based on creation of entirely new knowledge, or adaptation and transfer of existing foreign technology.Along with international trade, the most important vehicle for international technology transfer is foreign direct investment (FDI). It is well known that multinational corporations (MNCs) undertake a major part of the world’s private R&D efforts and production, own and control most of the world’s advanced technology. When a MNC sets up a forei gn affiliate, the affiliate receives some amount of the proprietary technology that constitutes the parent’s firm specific advantage and allows it to compete successfully with local firms that have superior knowledge of local markets, consumer preferences, and business practices. This leads to a geographical diffusion of technology, but not necessarily to any formal transfer of technology beyond the boundaries of the MNCs; the establishment of a foreign affiliate is, almost per definition, a decision to internalize the use of core technology.However, MNC technology may still leak to the surrounding economy through external effects or spillovers that raise the level of human capital in the host country and createproductivity increases in local firms. In many cases, the effects operate through forward and backward linkages, as MNCs provide training and technical assistance to their local suppliers, subcontractors, and customers. The labor market is another important channel for spillovers, as almost all MNCs train operatives and managers who may subsequently take employment in local firms or establish entirely new companies.It is therefore not surprising that attitudes towards inward FDI have changed considerably over the last couple of decades, as most countries have liberalized their policies to attract all kinds of foreign investment. Numerous governments have even introduced various forms of investment incentives to encourage foreign MNCs to invest in their jurisdiction. However, productivity and technology spillovers are not automatic consequences of FDI. Instead, FDI and human capital interact in a complex manner, where FDI inflows create a potential for spillovers of knowledge to the local labor force, at the same time as the host country’s level of human capital determines how much FDI it can attract and whether local firms are able to absorb the potential spillover benefits.2. Foreign Direct Investment and SpilloversThe earliest discussions of spillovers in the literature on foreign direct investment date back to the 1960s. The first author who systematically introduced spillovers (or external effects) among the possible consequences of FDI was MacDougall (1960), who analyzed the general welfare effects of foreign investment. The common aim of the studies was to identify the various costs and benefits of FDI.Productivity externalities were discussed together with several other indirect effects that influence the welfare assessment, such as those arising from the impact of FDI on government revenue, tax policies, terms of trade, and the balance of payments. The fact that spillovers included in the discussion was generally motivated by empirical evidence from case studies rather than by comprehensive theoretical arguments.Yet, the early analyses made clear that multinationals may improve locatives efficiency by entering into industries with high entry barriers and reducing monopolistic distortions, and induce higher technical efficiency if the increased competitive pressure or some demonstration effect spurs local firms to more efficient use of existing resources. They also proposed that the presence may lead to increases in the rate of technology transfer and diffusion. More specifically, case studies showed that foreign MNCs may:(1) Contribute to efficiency by breaking supply bottlenecks (but that the effect may become less important as the technology of the host country advances);(2) Introduce new know-how by demonstrating new technologies and training workers who later take employment in local firms;(3) Either break down monopolies and stimulate competition and efficiency or create a more monopolistic industry structure, depending on the strength and responses of the local firms;(4) Transfer techniques for inventory and quality control and standardization to their local suppliers and distribution channels;Although this diverse list gives some clues about the broad range of various spillover effects, it says little about how common or how important they are in general. Similar complaints can be made about the evidence on spillovers gauged from the numerous case studies discussing various aspects of FDI in different countries and industries. These studies often contain valuable circumstantial evidence of spillovers, but often fail to show how significant the spillover effectsare and whether the results can be generalized.For instance, many analyses of the linkages between MNCs and their local suppliers and subcontractors have documented learning and technology transfers that may make up a basis for productivity spillovers or market access spillovers. However, these studies seldom reveal whether the MNCs are able to extract all the benefits that the new technologies or information generate among their supplier firms. Hence, there is no clear proof of spillovers, but it is reasonable to assume that spillovers are positively related to the extent of linkages.Similarly, there are many works on the relation between MNCs entry and presence and market structure in host countries, and this is closely related to the possible effects of FDI on competition in the local markets. There are also case studies of demonstration effects, technology diffusion, and labor training in foreign MNCs. However, although these studies provide much detailed information about the various channels for spillovers, they say little about the overall significance of such spillovers.The statistical studies of spillovers, by contrast, may reveal the overall impact of foreign presence on the productivity of local firms, but they are generally not able to say much about how the effects come about. These studies typically estimate production functions for locally owned firms, and include the foreign share of the industry as one of the explanatory variables. They then test whether foreign presence has a significant positive impact on local productivity once other firm and industry characteristics have been accounted.Research conclude that domestic firms exhibited higher productivity in sectors with a larger foreign share, but argue that it may be wrong to conclude that spillovers have taken place if MNC affiliates systematically locate in the more productive sectors. In addition, they are also able to perform some more detailed tests of regional differences in spillovers. Examining the geographical dispersion of foreign investment, they suggest that the positive impact of FDI accrue mainly to the domestic firms located close to the MNC affiliates. However, effects seem to vary between industries.The results on the presence of spillovers seem to be mixed; recent studies suggest that there should be a systematic pattern where various host industry and host country characteristics influence the incidence of spillovers. For instance, the foreign affiliate’s levels of tech nology or technology imports seem to influence the amount of spillovers to local firms. The technology imports of MNC affiliates, in turn, have been shown to vary systematically with host country characteristics. These imports seem larger in countries and industries where the educational level of the local labor force is higher, where local competition is tougher, and where the host country imposes fewer formal requirements on the affiliates’ operations.Some recent studies have also addressed the apparent contradictions between the earlier statistical spillover studies, with the hypothesis that the host country’s level of technical development or human capital may matter as a starting point.In fact, in some cases, large foreign presence may even be a sign of a weak local industry, where local firms have not been able to absorb any productivity spillovers at all and have therefore been forced to yield market shares to the foreign MNCs.3. FDI Spillover and Human Capital DevelopmentThe transfer of technology from MNC parents to its affiliates and other host country firms is not only mbodied in machinery, equipment, patent rights, and expatriate managers and technicians,but is also realized rough the training of local employees. This training affects most levels of employees, from simple manufacturing operatives through supervisors to technically advanced professionals and top-level managers. While most recipients of training are employed in the MNCs own affiliates, the beneficiaries also include employees among the MNCs suppliers, subcontractors, and customers.Types of training ranged from on-the-job training to seminars and more formal schooling to overseas education, perhaps at the parent company, depending on the skills needed. The various skills gained through the elation with the foreign MNCs may spill over directly when the MNCs do not charge the full value of the training provided to local firms or over time, as the employees move to other firms or set up their own businesses.While the role of MNCs in primary and secondary education is marginal, there is increasingly clear evidence hat FDI may have a noticeable impact on tertiary education in their host countries. The most important effect is perhaps on the demand side. MNCs provide attractive employment opportunities to highly skilled graduates in natural sciences, engineering, and business sciences, which may be an incentive for gifted students to complete tertiary training, and MNCs demand skilled labor, which may encourage governments to invest in higher education.Many studies undertaken in developing countries have emphasized the spillovers of management skills. There is evidence of training and capacity development in technical areas, although the number of detailed studies appears smaller.While training activities in manufacturing often aim to facilitate the introduction of new technologies that are embodied in machinery and equipments, the training in service sectors is more directly focused on strengthening skills and know-how embodied in employees. This means that training and human capital development are often more important in service industries. Furthermore, many services are not tradable across international borders, which mean that service MNCs to a great extent are forced to reproduce home country technologies in their foreign affiliates. As a consequence, service companies are often forced to invest more in training, and the gap between affiliate and parent company wages tends, therefore, to be smaller than that in manufacturing.4. ConclusionThis paper has noted that the interaction of FDI and spillovers is complex and highly non-linear, and that several different outcomes are possible. FDI inflows create a potential for spillovers of knowledge to the local labor force, at the same time as the host country’s level of human capital determines how much FDI it can attract and whether local firms are able to absorb the potential spillover benefits. Hence, it is possible that host economies with relatively high levels of human capital may be able to attract large amounts of technology intensive foreign MNCs that contribute significantly to the further development of labor skills. At the same time, economies with weaker initial conditions are likely to experience smaller inflows of FDI, and those foreign firms that enter are likely to use simpler technologies that contribute only marginally to local learning and skill development.翻译一:外商直接投资溢出效应研究1.引言在最近几十年中,经济学家们已开始确定技术进步,或更普遍认为知识创造,作为经济增长原动力的一个重要决定因素,直到20世纪70年代,分析经济增长运用典型的新古典主义模型来解释经济增长的积累,劳动力、资本等生产要素与收益递减的规模。
翻译正文格式说明及实例
一、翻译分项说明1.注释以脚注形式出现,每页单独编号,注释1 先说明原文出处,格式按参考文献。
小五字号,其他同下要求。
如果原文也有脚注(尾注则保持位置不变),则译文在脚注前加上“译者注”三个字,原文脚注什么也不用加。
2.译文题目为英文的:采用3号字、Times New Roman字体、加黑、居中、与内容空1行;译文题目为汉语的:采用3号字、黑体、加黑、居中。
二级、三级标题分别采用四号字体,其他同正文题目。
3.译文为英文的:内容采用小4号Times New Roman字体,1.5行距,首句空4格。
4.译文为中文的:内容采用小4号宋体、首句空2格、1.5行距。
5.目录中的摘要、关键词分别对应原文和译文摘要,关键词,如果原文没有摘要或关键词,译者需要根据原文内容自己写出相应的摘要和关键词,关键词是指翻译过程中重要或者频繁出现的词语,一般在6-10个。
6.翻译作品有章节的,目录、正文中按相应顺序排序。
没有划分相应章节的,目录、正文中按:译文、参考文献(译者所用)、翻译问题研究报告、翻译心得、致谢排序。
翻译问题研究报告、翻译心得、致谢部分要求用英语完成,中间可以出现中文例证或者说明,如果是英译中,目录可以是中文,正文题目可以是英文,如致谢(目录中为中文,正文题目为英文Acknowledgements,主要是为了前后一致,更美观一些)。
7.翻译问题研究报告部分一般应包括:时间(time),工作量(workload),安排(arrangement),措辞(diction)句式(syntax),文体(style),技巧原则(skill and principle),工具(dictionary and technology)等。
翻译心得部分一般应包括:收获(achievement or progress ),发现(findings),思考(reflections),局限(limitation),建议(suggestions),未来努力方向(further research),等。
翻译稿件图片排版格式
中文
START
开始
Provide remote support
提供远程支持
5.简易报告图片通常可作图,效果图如下:
反应器段Oleflex工艺装置(丙烯)蒸汽锅炉段工艺流程图
起草人
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ED
2061-10-341-A1
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3.CAD图纸
建议让客户提供CAD原图纸,排版部可通过CAD原图纸一次性导出文字,无需录入
4.PDF中无法转化图片,如果手动绘制流程图,很费时
建议原图片截图,下面采用对照格式翻译:
FUEL GAS PREPARATION SYSTEM (BY OTHERS)
燃料气制备系统(他方提供)
右下角表格,可以直接制作成表格形式:
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起草人
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UOP
霍尼韦尔有限公司
UOP LLC地址:美国伊利诺伊州德斯普兰斯东阿尔冈路25号,邮编:60017-5017
工艺流程框图Process Flow Diagram
建议采用对照格式翻译,显示如下:
卸油区含油污水
Oily sewage inoil unloading area
供油区含油污水
Oily sewage in oil supply area
刮油机
Oil scraper
卸油区隔油池
Oil separatingtankin oil unloading area
1.文本框流程图
建议采用对照格式翻译,显示如下:
外协外购件
翻译排版
This means that to take this and drive这就表示要接受这种输入信号并去驱动100瓦的扬声器,放大电路就必须将信号的电流和电压同时放大109倍。
In practice, many devices which实际上,许多需要大电流和大功率的设备往往都在特定的条件下工作,即由信号的电压决定响应的幅度,继而由设备吸收其所需要的电流而工作。
The summing amplifier is used for加法放大器用于对多个信号进行组合。
两输入加法放大器最常见的应用是放大一个减去固定常数(直流偏差)的信号。
This transfer function describes accurately the只要所用运放的闭环增益比开环增益A小得多(即不能超过1000),这个传递函数就能准确地描述输出信号,且v o的预期值在运放的工作范围之内。
Its capability to reject a common signal差分放大器抑制共模信号的能力使它特别适于放大受同样大小噪声(共模信号)干扰的小压差信号。
CMOS logic is a newer technologyCMOS逻辑电路是一种基于互补MOS型晶体管来完成逻辑运算的新技术,工作时几乎不需要电流。
因此,这些门在电池供电的应用中十分有用。
它们可以在低到3伏、高到15伏的电压范围内工作,这也有助于实际应用。
Mathematical models. The mathematical description数学模型系统动态特性的数学描述叫数学模型。
动态系统分析的第一步就是推导出其模型。
我们必须记住,推导出合适的数学模型是整个分析中最重要的一部分工作。
In particular, if a linear lumped-parameter mathematical model特别是在需要采用线性集总参数数学模型(即常微分方程)时,总是要忽略掉物理系统中存在的一定的非线性因素和分布参数(即产生偏微分方程的参数)。
外文翻译原文模板
1、外文资料翻译内容要求:外文资料的内容应为本学科研究领域,并与毕业设计(论文)选题相关的技术资料或专业文献,译文字数应不少于3000汉字以上,同时应在译文末注明原文的出处。
不可采用网络中直接有外文和原文的。
2、外文资料翻译格式要求:译文题目采用小二号黑体,居中;译文正文采用宋体小四号,段前、段后距为0行;行距:固定值20磅。
英文原文如果为打印的话用新罗马(Times New Roman)小四号字。
装订时原文在前,译文在后。
文章中有引用的地方在原文中也要体现。
参考文献也要翻译成中文!An Energy-Efficient Cooperative Algorithm for Data Estimation inWireless Sensor NetworksAbstract – In Wireless Sensor Networks (WSN), nodes operate on batteries and network’s lifetime depends on energy consumption of the nodes. Consider the class of sensor networks where all nodes sense a single phenomenon at different locations and send messages to a Fusion Center (FC) in order to estimate the actual information. In classical systems all data processing tasks are done in the FC and there is no processing or compression before transmission. In the proposed algorithm, network is divided into clusters and data processing is done in two parts. The first part is performed in each cluster at the sensor nodes after local data sharing and the second part will be done at the Fusion Center after receiving all messages from clusters. Local data sharing results in more efficient data transmission in terms of number of bits. We also take advantage of having the same copy of data at all nodes of each cluster and suggest a virtual Multiple-Input Multiple-Output (V-MIMO) architecture for data transmission from clusters to the FC. A Virtual-MIMO network is a set of distributed nodes each having one antenna. By sharing their data among themselves, these nodes turn into a classical MIMO system. In the previously proposed cooperative/virtual MIMO architectures there has not been any data processing or compression in the conference phase. We modify the existing VMIMO algorithms to suit the specific class of sensor networks that is of our concern. We use orthogonal Space-Time Block Codes (STBC) for MIMO part and by simulation show that this algorithm saves considerable energy compared to classical systems.I. INTRODUCTIONA typical Wireless Sensor Network consists of a set of small, low-cost and energy-limited sensor nodes which are deployed in a field in order to observe a phenomenon and transmit it to a Fusion Center (FC). These sensors are deployed close to one another and their readings of the environment are highly correlated. Their objective is to report a descriptive behavior of the environment based on all measurements to the Fusion Center. This diversity in measurement lets the system become more reliable and robust against failure. In general, each node is equipped with a sensing device, a processor and a communication module (which can be either a transmitter or transmitter/receiver).Sensor nodes are equipped with batteries and are supposed to work for a long period of time without battery replacement. Thus, they are limited in energy and one of the most important issues in designing sensor networks will be the energy consumption of the sensor nodes. To deal with this problem, we might either reduce the number of bits to be transmitted by source compression or reduce the required power for transmission by applying advanced transmission techniques while satisfying certain performance requirement.A lot of research has been done in order to take advantage of the correlation among sensors’ data for reducing the number of bits to be transmitted. Some are based on distributed source coding[1]while others use decentralized estimation[2-5]. In [1], authors present an efficient algorithm that applies distributed compression based on Slepian – Wolf[14] encoding technique and use an adaptive signal processing algorithm to track correlation among sensors data. In [2-5] the problem of decentralized estimation in sensor networks has been studied under different constraints. In these algorithms, sensors perform a local quantization on their data considering that their observations are correlated with that of other sensors. They produce a binary message and send it to the FC. FC combines these messages based on the quantization rules used at the sensor nodes and estimates the unknown parameter. Optimal local quantization and final fusion rules are investigated in these works. The distribution of data assumed for sensor observation in these papers has Uniform probability distribution function. In our model we consider Gaussian distribution introduced in [17] for sensor measurements which ismore likely to reality.As an alternative approach, some works have been done using energy-efficient communication techniques such as cooperative/virtual Multiple-Input Multiple-Output (MIMO) transmission in sensor networks [6-11]. In these works, as each sensor is equipped with one antenna, nodes are able to form a virtual MIMO system by performing cooperation with others. In [6] the application of MIMO techniques in sensor networks based on Alamouti[15] space-time block codes was introduced. In [8,9] energy-efficiency of MIMO techniques has been explored analytically and in [7] a combination of distributed signal processing algorithm presented and in [1] cooperative MIMO was studied.In this paper, we consider both techniques of compression and cooperative transmission at the same time. We reduce energy consumption in two ways; 1) processing data in part at the transmitting side, which results in removing redundant information thus having fewer bits to be transmitted and 2) reducing required transmission energy by applying diversity and Space-Time coding. Both of these goals will be achieved by our proposed two-phase algorithm. In our model, the objective is to estimate the unknown parameter which is basically the average of all nodes’ measurements. That is, exact measurements of individual nodes are not important and it is not necessary to spend a lot of energy and bandwidth to transmit all measured data with high precision to the FC. We can move some part of data processing to the sensors side. This can be done by local data sharing among sensors. We divide the network into clusters of ‘m’ members. The number of members in the cluster (m) is both the compression factor in data processing and also the diversity order in virtual-MIMO architecture. The remaining of this paper is organized as following: in section II we introduce our system model and basic assumptions. In section III we propose our collaborative algorithm. In section IV we present the mathematical analysis of the proposed algorithm and in section V we give some numerical simulations. Finally section VI concludes the paper.II. SYSTEM MODELA. Network ModelThe network model that we use is similar to the one presented in [2-5].Our network consists of N distributed Sensor Nodes (SN) and a Fusion Center (FC). Sensors are deployed uniformly in the field, close to one another and each taking observations on an unknown parameter (θ). Fusion Center is located far from the nodes. All nodes observe same phenomenon but with different measurements. These nodes together with the Fusion Center are supposed to find the value of the unknown parameter. Nodes send binary messages to Fusion Center. FC will process the received messages and estimate the unknown value.B. Data ModelIn our formulation we use the data model introduced in[17]. We assume that all sensors observe the same phenomenon (θ) which has Gaussian distribution with variance σx 2. They observe different versions of θ and we model this difference as an additive zero mean Gaussian noisewith variance σn 2. Therefore, sensor observations will be described byn i i θx += (1) Where θ ~ N (0, σx 2) and n i ~ N (0, σn 2) for i = 1, 2, … , N .Based on thisassumption the value of θ can be estimated by taking the numerical average of the nodes observations, i.e.∑==N i i x N 11θ(2)C. Reference System ModelOur reference system consists of N conventional Single Input Single Output (SISO) wireless links, each connecting one of the sensor nodes to the FC. For the reference system we do not consider any communication or cooperation among the sensors. Therefore each sensor quantizes its observation by an L-bit scalar quantizer designed for distribution of θ, generates a message of length L and transmits it directly to the FC. Fusion Center receives all messages and performs the processing, which is calculation of the numerical average of these messages.III. COOPERATIVE DATA PROCESSING ALGORITHMSensor readings are analog quantities. Therefore, each sensor has to compress its data into several bits. For data compression we use L -bit scalar quantizer [12,13].In our algorithm, network is divided into clusters, each cluster having a fixed and pre-defined number of members (m). Members of each cluster are supposed to cooperate with one another in two ways:1. Share, Process and Compress their data2. Cooperatively transmit their processed data using virtual MIMO.IV. ANALYSISThe performance metric considered in our analysis is the total distortion due to compression and errors occurred during transmission. The first distortion is due to finite length quantizer, used in each sensor to represent the analog number by L bits. This distortion depends on the design of quantizer.We consider a Gaussian scalar quantizer which is designed over 105 randomly generated samples. The second distortion is due to errors occurred during transmission through the channel. In our system, this distortion is proportional to the probability of bit error. Since the probability of bit error (Pe) is a function of transmission energy per bit (Eb), total distortion will be a function of Eb. In this section we characterize the transmission and total consumed energy of sensors and find the relationship between distortion and probability of bit error.V. SIMULATION AND NUMERICAL RESULTS To give a numerical example, we assume m = 4 members in each cluster. Therefore our Virtual-MIMO scheme will consist of 4 transmit antennas. We assume that network has N = 32 sensors. Sensor observations are Gaussian with σx2= 1 and are added to a Gaussian noise of σn2= 0.1 .Nodes are deployed uniformly in the field and are 2 meters apart from each other and the Fusion Center is located 100 meters away from the center of the field. The values for circuit parameters are quoted from [6] and are listed in Table I. These parameters depend on the hardware design and technological advances. Fig. 1 illustrates the performance (Distortion) of reference system and proposed two-phase V-MIMO scheme versus transmission energy consumption in logarithmic scale. As shown in the figures, depending on how much precision is needed in the system, we can save energy by applying the proposed algorithm.TABLE IFig. 2 illustrates the Distortion versus total energy consumption of sensor nodes. That is, in this figure we consider both the transmission and circuit energy consumption. The parameters that lead us to these results may be designed to give better performance than presented here. However, from these figures we can conclude that the proposed algorithm outperforms the reference system when we want to have distortion less than 10−3 and it can save energy as high as 10 dB.VI. CONCLUSIONIn this paper we proposed a novel algorithm which takes advantage of cooperation among sensor nodes in two ways: it not only compresses the set of sensor messages at the sensor nodes into one message, appropriate for final estimation but also encodes them into orthogonal space-time symbols which are easy to decode and energy-efficient. This algorithm is able to save energy as high as 10 dB.REFERENCES[1] J.Chou,D.Petrovic and K.Ramchandran “A distributed and adaptive signalprocessing approach to reducing energy consumption in sensornetworks,”Proc. IEEE INFOCOM,March 2003.[2] Z.Q.Luo, “Universal decentralized estimation in a bandwidth constrainedsensor network,” IEEE rmation The ory, vol.51,no.6,June 2005.[3] Z.Q.Luo,“An Isotropic Universal decentralized estimation scheme for abandwidth constrained Ad Hoc sensor network,”IEEEm. vol.23,no. 4,April 2005.[4] Z.Q.Luo and J.-J. Xiao, “Decentralized estimation i n an inhomogeneoussensing environment,” IEEE Trans. Information Theory, vol.51, no.10,October 2005.[5] J.J.Xiao,S.Cui,Z.-Q.Luo and A.J.Goldsmith, “Joint estimation in sensornetworks under energy constraints,” Proc.IEEE First conference on Sensor and Ad Hoc Communications and Networks, (SECON 04),October 2004.[6] S.Cui, A.J.Goldsmith, and A.Bahai,“Energy-efficiency of MIMO andcooperative MIMO techniques in sensor networks,”IEEEm,vol.22, no.6pp.1089–1098,August 2004.[7] S.K.Jayawe era and M.L.Chebolu, “Virtual MIMO and distributed signalprocessing for sensor networks-An integrated approach”,Proc.IEEEInternational Conf. Comm.(ICC 05)May 2005.[8] S.K.Jayaweera,"Energy efficient virtual MIMO-based CooperativeCommunications for Wireless Sensor Networks",2nd International Conf. on Intelligent Sensing and Information Processing (ICISIP 05),January 2005.[9] S.K.Jayaweera,“Energy Analysis of MIMO Techniques in Wireless SensorNetworks”, 38th Annual Conference on Information Sciences and Systems (CISS 04),March 2004.[10] S.K.Jayaweera and M.L.Chebolu,“Virtual MIMO and Distributed SignalProcessing for Sensor Networks - An Integrated Approach”,IEEEInternational Conf.on Communications (ICC 05),May 2005.[11] S.K.Jayaweera,“An Energy-efficient Virtual MIMO CommunicationsArchitecture Based on V-BLAST Processing for Distributed WirelessSensor Networks”,1st IEEE International Conf.on Sensor and Ad-hocCommunications and Networks (SECON 2004), October 2004.[12] J.Max,“Quantizing for minimum distortion,” IRE rmationTheory,vol.IT-6, pp.7 – 12,March 1960.[13] S.P.Lloyd,“Least squares quantization in PCM ,”IEEE rmationTheory,vol.IT-28, pp.129-137,March 1982.[14] D.Slepian and J.K.Wolf “Noiseless encoding of correlated inf ormationsources,” IEEE Trans. on Information Theory,vol.19, pp.471-480,July1973.[15] S.M.Alamouti,“A simple transmit diversity technique for wirelesscommunications,” IEEE m., vol.16,no.8,pp.1451–1458,October 1998.[16] V.Tarokh,H.Jafarkhani,and A.R.Calderbank. “Space-time block codesfrom orthogonal designs,’’IEEE rmationTheory,vol.45,no.5,pp.1456 -1467,July 1999.[17] Y.Oohama,“The Rate-Distortion Function for the Quadratic GaussianCEO Problem,” IEEE Trans. Informatio nTheory,vol.44,pp.1057–1070,May 1998.。
翻译正文格式说明及实例
翻译正文格式说明及实例一、翻译分项说明1.注释以脚注形式出现,每页单独编号,注释1 先说明原文出处,格式按参考文献。
小五字号,其他同下要求。
如果原文也有脚注(尾注则保持位置不变),则译文在脚注前加上“译者注”三个字,原文脚注什么也不用加。
2.译文题目为英文的:采用3号字、Times New Roman字体、加黑、居中、与内容空1行;译文题目为汉语的:采用3号字、黑体、加黑、居中。
二级、三级标题分别采用四号字体,其他同正文题目。
3.译文为英文的:内容采用小4号Times New Roman字体,1.5行距,首句空4格。
4.译文为中文的:内容采用小4号宋体、首句空2格、1.5行距。
5.目录中的摘要、关键词分别对应原文和译文摘要,关键词,如果原文没有摘要或关键词,译者需要根据原文内容自己写出相应的摘要和关键词,关键词是指翻译过程中重要或者频繁出现的词语,一般在6-10个。
6.翻译作品有章节的,目录、正文中按相应顺序排序。
没有划分相应章节的,目录、正文中按:译文、参考文献(译者所用)、翻译问题研究报告、翻译心得、致谢排序。
翻译问题研究报告、翻译心得、致谢部分要求用英语完成,中间可以出现中文例证或者说明,如果是英译中,目录可以是中文,正文题目可以是英文,如致谢(目录中为中文,正文题目为英文Acknowledgements,主要是为了前后一致,更美观一些)。
7.翻译问题研究报告部分一般应包括:时间(time),工作量(workload),安排(arrangement),措辞(diction)句式(syntax),文体(style),技巧原则(skill and principle),工具(dictionary and technology)等。
翻译心得部分一般应包括:收获(achievement or progress ),发现(findings),思考(reflections),局限(limitation),建议(suggestions),未来努力方向(further research),等。
译文模板及格式说明(2014.3)
关于译文的格式说明1.译文封面:要同时写外文题目及中文题目,英文题目在上、中文题目在下。
其中英文单词首个字母大写,连接词必须小写。
2.标题:小三号宋体。
3.译文:小四号宋体。
4.译文装订顺序:(1)封面(2)英文原文(3)中文。
5.译文正文:章标题(一级标题),小三号宋体居中,以下空两行。
节标题(二级标题),顶格写,四号宋体,上下空一行。
节标题(三级标题),顶格写,小四宋体,上下内容不空行。
6.译文对应的中文不少于3000汉字。
7.译文部分的页码单独编排。
8.译文的样式如下:序号(学号):041140601长春光华学院毕业设计(论文)译文Integration of shortwave narrowband FMreceiver design集成短波窄带调频接收机设计姓名李伟业教学院电气信息学院专业通信工程系班级通信 10402指导教师李广军教授2014 年 5 月26 日┊┊┊┊┊┊┊┊┊┊┊┊┊装┊┊┊┊┊订┊┊┊┊┊线┊┊┊┊┊┊┊┊┊┊┊┊┊Integration of shortwave narrowband FM receiver designIn this desing of a SW-FM receiver,a single chip FM receiver IC MC3362 servers as the core,a frequency syn- thesizer is employed to impleoyed local oscillator with high stability and a single chip processor actsas the main controller to perform in collaboration with the fr- equency synthesizer,multiple functions,such as manu-al,automatic radio station searching and the carrier fr- equency displaying.Aserial E2PROM is used to storethe data of radio stations permanently.With a digital adju- stable resistance,the digital volume adjustment is acc- omplished.Owing to a capacitor distributing filter at the input of the antenna,the improvement of mirror res- training rato and the optimal match between the antenna and receiver are achieved.MC3362 is the MOTOROLA company produces the monolithic NFM receiving circuit, mainly used in voice communication and data transmission of wireless receiver. On chip contains oscillation circuit, mixing circuit, limiting amplifier, integral frequency discriminator, field strength indicator drive and carrier frequency detection circuit from the antenna input to the audio output of all the secondary inverter circuit, also includes the mixing with an output buffer, FSK detection data limit comparator. With low voltage, low power consumption, high sensitivity and SNR, widely used in the voice and digital communications receiving equipment. Its main features are as follows:Secondary all inverter circuit·Low operating voltage: 2.0-6.0 V·low power consumption (Vcc = 3.0 V, power typical values only 3.6 mA, except for high power pipes)·Extreme sensitivity: 0.6 uV (typical values, 12 db SINAD) ·Adjustable, carrier frequency detection• data plastic comparator• receiving field strength indicator• a small number of ext ernal components• manufactured MOTOROLA "MOSAIC" technology┊┊┊┊┊┊┊┊┊┊┊┊┊装┊┊┊┊┊订┊┊┊┊┊线┊┊┊┊┊┊┊┊┊┊┊┊┊• DIP24 and SO - 24 two packaging forms• MC13135 to new models of choiceCarrier frequency signal from MC3363 Pin2 input, high by the internalpipes by Pin4 after high frequency amplifier output, connected to thePin4 is a LC resonance high-frequency transformer, center frequency forRF carrier frequency, the T1 is coupled to the Pin1 and Pin2 to enterthe first level mixing. Internal oscillation circuit and the Pin25 andPin26 LC components of the first magnitude of vibration, and the carrierfrequency RF input signal in internal mixer, the difference frequency10.7 MHz first intermediate frequency signal after amplification by Pin23output, after 10.7 ceramic filter frequency selective level by the secondpin21 to internal mixing. Internal oscillation circuit and Pin5 and Pin6external crystal and capacitance constitutes the second vibration level,frequency selection is lower than the first intermediate frequency anintermediate frequency (i.e. frequency of 455 KHZ) of 10.245 MHz. 10.7MHz first intermediate frequency signal and the second vibrationfrequency mixing, the difference frequency is: 10.700-10.245 = 10.700MHz, namely 455 KHZ second intermediate frequency signal.The second intermediate frequency signal output by the Pin7 by 455 KHZ frequency selective ceramic filter, then through Pin9 into MC3363 limiting amplifier with high gain amplifier, limiting amplifier stage is the main gain of the circuit. Pin13 external LC components of 455 KHZ frequency resonant circuit, after amplification of the intermediate frequency signal in internal frequency demodulation, and after the audio level voltage amplification by Pin19 output audio signal.Pin12 and Pin13 field indicates the external drive circuit element, adjust the Pin12 200 k resistor can change the field indicates the gain drive circuit. MC3363 internal also have primary data signal amplifier stage, Pin17 for input, Pin18 for output. Can undertake plastic and magnified the data waveform. Pin10 and Pin11 as the second level into the decoupling capacitor. To guarantee the stability of circuit to work.System introductionThe system consists of a receiver, frequency synthesizer, single-chip microcomputer system of three parts. The system block diagram as shown in figure 3-1. From the antenna input signals through 8 to 10┊┊┊┊┊┊┊┊┊┊┊┊┊装┊┊┊┊┊订┊┊┊┊┊线┊┊┊┊┊┊┊┊┊┊┊┊┊MHz bandpass filter filter, 10.7 MH. Trap trap (intermediate frequency interference suppression), after into MC3362 secondary mixing, frequency processing, reduction of the audio signal. MC3362 this vibration frequency generated by the frequency synthesizer, and provide single chip lock level, and single chip microcomputer system according to the different search patterns to produce the corresponding parallel code sent to the frequency synthesizer, produce different frequency of the vibration signals, and on the digital tube display the corresponding information.Phase-locked frequency synthesis circuit and analysisPhase-locked loop (PLL: Phase locked loops) is a kind of using Feedback (Feedback) control principle of frequency and Phase synch- ronization technology, its role is the output clock circuit and its external reference clock in sync. When the reference clock frequency or Phase change, the phase-locked loop will detect this change, and through its internal feedback system to adjust output frequency, until both to resynchronize, this synchronization is also known as the "lock" (Phase - locked).It is used in the receiver of communication, its role is the received signal processing, and extracted from the phase information of a clock. Or, for the received signal, the generic a clock signal, make the two signals from a certain perspective is synchronous (or, coherent). Because the lock case (i.e., after finishing the capture), the imitation of the clock signal relative to the clock signal in the received signal has a certain difference, so it is vividly called the phase locking device.Phase-locked loop consists of phase discriminator, loop filter and the voltage-controlled oscillator. Phase detector is used to identify the input signal of the phase difference between the Ui and the output signal Uo and output error voltage Ud. Ud the noise and interference elements are low connectivity loop filter filter, form a voltage-controlled os- cillator (VCO) the control voltage of Uc. Uc ACTS on thevoltage-controlled oscillator is the result of the pull it the output of the oscillation frequency fo to loop the input signal frequency fi, when two equal, the loop is locked, is called into the lock. Maintain lock control dc voltage is provided by phase discriminator and therefore phase discriminator retain certain phase difference between the two input signals.Direct Digital Frequency Synthesis (DDS - Digital Direct Frequency short) technology is a new method of Frequency Synthesis, Frequency Synthesis┊┊┊┊┊┊┊┊┊┊┊┊┊装┊┊┊┊┊订┊┊┊┊┊线┊┊┊┊┊┊┊┊┊┊┊┊┊technology is a revolution, JOSEPH TIERNEY and so on 3 people in 1971, puts forward the idea of Direct Digital Frequency Synthesis, but due to the microelectronics technology and Digital signal processing technology, DDS technology can't be said often enough, with the actual needs in the field of electrical engineering and the development of Digital integrated circuit and microelectronic technology, DDS technology is increasingly showing its superiority.DDS is A kind of fully digital frequency synthesizer, the phase accumulator, waveform ROM, D/A converter and low pass filter. After A given clock frequency, the output signal frequency depends on the fre- quency of the controller, the frequency resolution depends on the acc- umulator digits, phase resolution depends on the ROM address line number, amplitude quantization noise depends on the ROM data word length and D/A converter digits.DDS has the following advantages:More than (1) high frequency resolution, output frequency points, can be up to N frequency phase accumulator (N digits);(2) frequency switching speed, can reach us mass;(3) frequency switch phase continuous;(4) can output broadband orthogonal signal;(5)output phase noise is low, could improve the phase noise of reference frequency source;(6)can generate arbitrary waveform;Once fully digital implementation, facilitate integration, small volume, light weight, so all countries since the eighty s in their respective DDS product research and development, such as the United States QUALCOMM Q2334, Q2220; STANFORD firm STEL - 1175, STEL - 1175. The AD company AD7008, AD9850, AD9854, etc. The DDS chip clock frequency range from A few MHZ to several hundred MHZ, from general function to the integrated chip have A D/A converter and quadrature modulator.PLL: Phase Locked Logic Phase synchronization LogicPhase-locked loop is the purpose of the establish carrier synchronization in charge, both communication and synchronization. Because it is the working process of an automatic frequency (phase) adjustment of the closed loop, so called ring. Phase-locked loop analog phase-locked loop and digital phase-locked loop.The basic principle of workVoltage-controlled oscillator is given a signal, one part as the output, the other part by frequency division and PLL IC this vibration signals generated by the phase comparison, in order to keep the same┊┊┊┊┊┊┊┊┊┊┊┊┊装┊┊┊┊┊订┊┊┊┊┊线┊┊┊┊┊┊┊┊┊┊┊┊┊frequency, requires phase difference do not change, if there is the change of the phase difference, the PLL IC voltage changes, the output voltage to control the VCO, until phase recovery! To achieve the purpose of locking frequency! Can make the controlled oscillator frequency and phase are to keep with the input signal to determine the relationship between closed-loop electronic circuit.1) to simulate the working principle of the phase-locked loopAnalog phase locked loop is mainly composed of phase reference extraction circuit, voltage controlled oscillator, phase comparator, control circuit, etc. Output of the voltage-controlled oscillator is and requires continuous signals frequency is very close, and by the phase reference extract extracted from signal circuit reference signal is sent to the phase comparator at the same time, with the comparative form of error by control circuit to reduce the frequency of the vco direction error of the absolute value of continuous change, achieve phase locked, so as to achieve synchronization.2) working principle of the digital phase-locked loopDigital phase-locked loop is mainly composed of reference phase ext- raction circuit, crystal oscillator, frequency divider, phase comparator, pulse wipe door, etc. Frequency divider output signal frequency and the frequency is very close to it and extracted from signal phase reference signal is sent to the phase comparator at the same time, the comparison results shows high frequency when the local by covering with door erase an input pulse frequency divider, equivalent to the local oscillation frequency; If, on the other hand, shows the local frequency low in fre- quency divider when inserted between two input pulses at the input a pulse, equivalent to the local oscillation frequency goes up, so as to achieve synchronization.Phase-locked frequency synthesis circuit phase-locked frequency syn- thesis unit is a key part of the machine work. System structure as shown in figure ⅣD-2-7, circuit as shown in figure lVD- 2-8. Acc- ording to the topic request and design, the reference frequency fr set to 5 kHz output frequency fo 18.7-20.7 MHz, can use direct frequency division, loop programmable divider frequency division than Ⅳ cal- culated by type:rffN/=Calculate the minimum points frequency ratio3740min=N, maximumfrequency division ratio4140max=N.Currently on the market of the frequency synthesizer integrated circuit a lot, we choose MC145151 of MOTOROLA. The chip is a piece of l4 the single mode of parallel code input, monolithic PLL frequency┊┊┊┊┊┊┊┊┊┊┊┊┊┊装┊┊┊┊┊订┊┊┊┊┊线┊┊┊┊┊┊┊┊┊┊┊┊┊集成短波窄带调频接收机设计本短波调频接收机的设计是以单片机 FM 接收芯片MC3362 为核心,采用频率合成器实现高稳定度的本振;利用单片机作为主控器与频率合成器配合完成手动、自动搜台、载频显示等功能;采用串行 E2PROM 实现电台数据存储并永久保存;数字电位器的引入实现了数字音量调节;天线输入端采用电容分压式滤波器,即可提高镜像抑制比,又可使天线与接收机达到最佳匹配。
文言文翻译对照手帐排版
---封面:- 文言文原文:汉典籍,载文明,传千古,继往开来。
- 现代文翻译:汉代经典,承载着文明,流传千古,继承前人,开创未来。
---第一页:目录- 文言文原文:目录:经史子集,诗词歌赋,诸子百家,成语典故。
- 现代文翻译:目录:经史子集部分,诗词歌赋,诸子百家的学说,成语典故。
---第二页:正文示例一- 文言文原文:子曰:“学而时习之,不亦说乎?有朋自远方来,不亦乐乎?人不知而不愠,不亦君子乎?”- 现代文翻译:孔子说:“学习并且按时复习,不是很愉快吗?有朋友从远方来,不是很快乐吗?别人不了解我,我却不生气,这不也是君子之风吗?”---第三页:正文示例二- 文言文原文:夫君子之行,静以修身,俭以养德。
非淡泊无以明志,非宁静无以致远。
- 现代文翻译:君子的行为,以静心修身,以节俭养德。
不淡泊名利就无法明确志向,不宁静淡泊就无法达到远大的目标。
---第四页:字词解释- 文言文原文:静以修身,俭以养德。
非淡泊无以明志,非宁静无以致远。
- 现代文翻译:通过保持内心的平静来修养身心,通过节俭的生活方式来培养品德。
如果不淡泊名利就无法明确自己的志向,如果不保持内心的宁静就无法实现远大的理想。
---第五页:成语典故- 文言文原文:破釜沉舟,百二秦关终属楚。
- 现代文翻译:破掉锅子,沉掉船只,表示决心一战到底,百二秦关最终归属于楚国。
---第六页:诗词欣赏- 文言文原文:人生得意须尽欢,莫使金樽空对月。
- 现代文翻译:人生得意之时要尽情享受,不要让空空的酒杯对着月亮。
---第七页:心得体会- 文言文原文:读史使人明智,读诗使人灵秀。
- 现代文翻译:读历史可以使人明智,读诗歌可以使人心灵得到升华。
---第八页:附录:常用文言文词汇表- 文言文原文:常用文言文词汇表。
- 现代文翻译:常用文言文词汇表。
---第九页:总结- 文言文原文:文言文,中华瑰宝,传承文化,启迪智慧。
- 现代文翻译:文言文,中华文化的瑰宝,传承着文化,启迪着智慧。
英文翻译材料格式参考
北方民族大学毕业设计材料翻译系(部)名称: 计算机科学与工程学院学生姓名:专业: 学号:指导教师姓名:北方民族大学教务处制目录I. Introduction (1)II. Language Types (1)III. Classification of High-Level Languages (2)IV. Language Structure and Components (3)V. History (4)一、引言 (1)二、语言类型 (1)三、高级语言的分类 (2)四、语言的结构与成分 (3)五、历史 (3)Computer Language and ProgrammingI. IntroductionProgramming languages, in computer science, are the artificial languages used to write a sequence of instructions (a computer program) that can be run by a computer. Similar to natural languages, such as English, programming languages have a vocabulary, grammar, and syntax. However, natural languages are not suited for programming computers because they are ambiguous, meaning that their vocabulary and grammatical structure may be interpreted in multiple ways. The languages used to program computers must have simple logical structures, and the rules for their grammar, spelling, and punctuation must be precise.Programming languages vary greatly in their sophistication and in their degree of versatility. Some programming languages are written to address a particular kind of computing problem or for use on a particular model of computer system. For instance, programming languages such as FORTRAN and COBOL were written to solve certain general types of programming problems—FORTRAN for scientific applications, and COBOL for business applications. Although these languages were designed to address specific categories of computer problems, they are highly portable, meaning that they may be used to program many types of computers. Other languages, such as machine languages, are designed to be used by one specific model of computer system, or even by one specific computer in certain research applications. The most commonly used programming languages are highly portable and can be used to effectively solve diverse types of computing problems. Languages like C, PASCAL , and BASIC fall into this category.II. Language TypesProgramming languages can be classified as either low-level languages or high-level languages. Low-level programming languages, or machine languages, are the most basic type of programming languages and can be understood directly by a computer. Machine languages differ depending on the manufacturer and model of computer. High-level languages are programming languages that must first be translated into a machine language before they can be understood and processed by a computer. Examples of high-level languages are C, C++, PASCAL, and FORTRAN. Assembly languages are intermediate languages that are very close to machine languages and do not have the level of linguistic sophistication exhibited by other high-level languages, but must still be translated into machine language.1. Machine LanguagesIn machine languages, instructions are written as sequences of 1s and 0s, called bits, that a computer can understand directly. An instruction in machine language generally tells the computer four things: (1) where to find one or two numbers or simple pieces of data in the main computer memory (Random Access Memory, or RAM), (2) a simple operation to perform, such as adding the two numbers together, (3) where in the main memory to put the result of this simple operation, and (4) where to find the next instruction to perform. While all executable programs are eventually read by the computer in machine language, they are not all programmed in machine language. It is extremely difficult to program directly in machine language because the instructions are sequences of 1s and 0s. A typical instruction in a machine language might read 10010 1100 1011 and mean add the contents of storage register A to the contents of storage register B.2. High-Level LanguagesHigh-level languages are relatively sophisticated sets of statements utilizing words and syntax from human language. They are more similar to normal human languages than assembly or machine languages and are therefore easier to use for writing complicated programs. These programming languages allow larger and more complicated programs to be developed faster. However, high-level languages must be translated into machine language by another program called a compiler before a computer can understand them. For this reason, programs written in a high-level language may take longer to execute and use up more memory than programs written in an assembly language.3. Assembly LanguagesComputer programmers use assembly languages to make machine-language programs easier to write. In an assembly language, each statement corresponds roughly to one machine language instruction. An assembly language statement is composed with the aid of easy to remember commands. The command to add the contents of the storage register A to the contents of storage register B might be written ADD B, A in a typical assembly language statement. Assembly languages share certain features with machine languages. For instance, it is possible to manipulate specific bits in both assembly and machine languages. Programmers use assembly languages when it is important to minimize the time it takes to run a program, because the translation from assembly language to machine language is relatively simple. Assembly languages are also used when some part of the computer has to be controlled directly, such as individual dots on a monitor or the flow of individual characters to a printer.III. Classification of High-Level LanguagesHigh-level languages are commonly classified as procedure-oriented, functional, object-oriented, or logic languages. The most common high-level languages today are procedure-oriented languages. In these languages, one or more related blocks of statements that perform some complete function are grouped together into a program module, or procedure, and given a name su ch as “procedure A.” If the same sequence of operations is needed elsewhere inthe program, a simple statement can be used to refer back to the procedure. In essence, a procedure is just a mini-program. A large program can be constructed by grouping together procedures that perform different tasks. Procedural languages allow programs to be shorter and easier for the computer to read, but they require the programmer to design each procedure to be general enough to be used in different situations.Functional languages treat procedures like mathematical functions and allow them to be processed like any other data in a program. This allows a much higher and more rigorous level of program construction. Functional languages also allow variables—symbols for data that can be specified and changed by the user as the program is running—to be given values only once. This simplifies programming by reducing the need to be concerned with the exact order of statement execution, since a variable does not have to be redeclared, or restated, each time it is used in a program statement. Many of the ideas from functional languages have become key parts of many modern procedural languages.Object-oriented languages are outgrowths of functional languages. In object-oriented languages, the code used to write the program and the data processed by the program are grouped together into units called objects. Objects are further grouped into classes, which define the attributes objects must have. A simple example of a class is the class Book. Objects within this class might be Novel and Short Story. Objects also have certain functions associated with them, called methods. The computer accesses an object through the use of one of the object’s methods. The method performs some action to the data in the object and returns this value to the computer. Classes of objects can also be further grouped into hierarchies, in which objects of one class can inherit methods from another class. The structure provided in object-oriented languages makes them very useful for complicated programming tasks.Logic languages use logic as their mathematical base. A logic program consists of sets of facts and if-then rules, which specify how one set of facts may be deduced from others, for example:If the statement X is true, then the statement Y is false.In the execution of such a program, an input statement can be logically deduced from other statements in the program. Many artificial intelligence programs are written in such languages.IV. Language Structure and ComponentsProgramming languages use specific types of statements, or instructions, to provide functional structure to the program. A statement in a program is a basic sentence that expresses a simple idea—its purpose is to give the computer a basic instruction. Statements define the types of data allowed, how data are to be manipulated, and the ways that procedures and functions work. Programmers use statements to manipulate common components of programming languages, such as variables and macros (mini-programs within a program).Statements known as data declarations give names and properties to elements of a program called variables. Variables can be assigned different values within the program. The properties variables can have are called types, and they include such things as what possible values might be saved in the variables, how much numerical accuracy is to be used in the values, and how one variable may represent a collection of simpler values in an organized fashion, such as a table or array. In many programming languages, a key data type is a pointer. Variables that are pointers do not themselves have values; instead, they have information that the computer can use to locate some other variable—that is, they point to another variable.An expression is a piece of a statement that describes a series of computations to be performed on some of th e program’s variables, such as X+Y/Z, in which the variables are X, Y, and Z and the computations are addition and division. An assignment statement assigns a variable a value derived from some expression, while conditional statements specify expressions to be tested and then used to select which other statements should be executed next.Procedure and function statements define certain blocks of code as procedures or functions that can then be returned to later in the program. These statements also define the kinds of variables and parameters the programmer can choose and the type of value that the code will return when an expression accesses the procedure or function. Many programming languages also permit minitranslation programs called macros. Macros translate segments of code that have been written in a language structure defined by the programmer into statements that the programming language understands.V. HistoryProgramming languages date back almost to the invention of the digital computer in the 1940s. The first assembly languages emerged in the late 1950s with the introduction of commercial computers. The first procedural languages were developed in the late 1950s to early 1960s: FORTRAN, created by John Backus, and then COBOL, created by Grace Hopper. The first functional language was LISP, written by John McCarthy in the late 1950s. Although heavily updated, all three languages are still widely used today.In the late 1960s, the first object-oriented languages, such as SIMULA, emerged. Logic languages became well known in the mid 1970s with the introduction of PROLOG, a language used to program artificial intelligence software. During the 1970s, procedural languages continued to develop with ALGOL, BASIC, PASCAL, C, and Ada. SMALLTALK was a highly influential object-oriented language that led to the merging of object-oriented and procedural languages in C++ and more recently in JA V A. Although pure logic languages have declined in popularity, variations have become vitally important in the form of relational languages for modern databases, such as SQL.计算机语言与编程一、引言在计算机科学中,编程语言是用来编写可被计算机运行的一系列指令(计算机程序)的人工语言。
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编号南京航空航天大学金城学院毕业论文附件材料题目中小企业融资:对不同信贷结构的需要程度和反应学生姓名张琳璐学号2007033524材料目录二〇一二年四月原文:SMEs Financing: the Extent of Need andthe Responses of Different Credit Structures Daniel BĂDULESCU University of Oradea daniel.badulescu@ IntroductionSmall and medium enterprises (SMEs) play an essential role in the development of any country. They can be assimilated as the engines of growth in developing economies, and the importance and future of SMEs tend to be a major policy concern, with strategic importance in reshaping the productive sectors, employment and innovation. But, in order to accomplish all this expectations, we have to admit that one of the biggest problem the SMEs faces is the non-availability of adequate financing facilities, the lack of availability of financial institutions or private equity investors to meet the SMEs financing requirements.Banks, like other businesses, concentrate on creating value under a controlled risk (OECD, 2006, Pathrose, 2005). Analyzing a loan application, a bank has to focus on the risks involved and the methods to mitigate those risks. The banks are reluctant to lend to SMEs for a number of reasons, including the following:1. The information asymmetry that arises from small businesses' lack of financial information and standardized financial statements, in addition to the bank's limited knowledge about the borrower company (Badulescu, Badulescu, 2010). The quantity and quality of the information hold by the entrepreneur regarding their business cannot be accessed in the same measure and efficiency by the prospective creditor. Thus, the lenders is unable to separate between good (bankable) projects and doubtful projects, and the price (for example, the interest of the loan) doesn’t make an efficient selection; rather it will increase the bank credit portfolio with risky loans: some of them with interesting perspective, others failures for sure (this phenomenon is the adverse selection). The second issue created by informational asymmetry is the moral hazard: once the loan granted, the control of its use according to the original application (and the risk and opportunity analysis) could face serious difficulties and the loan could be used – even part of it – for other purpose. In order to reduce this risk, the financer will ask as guarantee collateral: assets, receivables, personal goods, immovable, or will pretend the early repayment of the loan, or, if it is possible, will restrict theaccess on the rest of unused loan.2.The high risks involved in lending to the SMEs as a result of limited Assets that can be used as collateral, high failure rates, low capitalization and vulnerability to market risks. The finance institutions consider the environment of SMEs being competitive and very uncertain (compared to large companies), implying a high variability of return of similar SMEs in the same sector, and finally high failure rate. The limited power in market, considerable share of intangible assets, lack of relevant financial and commercial track records, insufficient circulating assets or tangible fixed assets tends to create a higher risk profile of SMEs for potential investors (OECD, 2004, Lin, Sun, 2006, Toivanen, Cresy, 2000, OECD, 2000). Insufficient collaterals compared to the lenders’ request in order to overcome the risks associated to moral hazard is probably the most claimed cause of the difficulties in accessing a credit by a SME. The collatera ls’ insufficiency can be the expression of an incipient stage of the business, unconsolidated yet, up to an exaggerated sizing of the credit request, upon the firm real capacity to sustain the project.3. As small businesses cannot offer adequate collateral, the banks are unable to determine whether the borrower possesses the technical, managerial and marketing skills to generate adequate cash flows and service the loan. The SMEs are characterized by unsatisfactory technical endowment, difficulties in assuring qualified technical staff and experimented management (human capital) in order to adapt to the multiple and rapid changes of present-day economy. At least, the reports accuracy, business protection under contractual basis is precarious, even for internal or external reasons; make barriers for the financial institution in order to compute the real profitability of the company, the repayment capacity, even the reliability of some collateral. In developing countries, the risk profile is supplementary marked by the unstable legislative and competitive environment, with negative consequences on the transactions security.1. The size of financing needs and the prevalence of bank loansBased on a recent research-Flash Euro barometer Access to finance (No. 271), commissioned by the European Commission’s DG Enterprise and Industry, in cooperation with the European Central Bank (ECB), to measure EU comp anies’ use of various sources of finance, the difficulties in accessing finance, we notice that one of the most pressing concern of SME managers from EU is access to financing, adding more than 16% from answers (after finding customers but far away of the competition or availability of skilled staff)(European Central Bank, 2009, Gallup Organization,2009)Source: ECB (2009).Figure 1. Compan ies’ m ost pressing problemAs expected, inside de EU there are significant differences between countries, for example very important for SME in Greece (39%) and Spain (23%) or Romania (19%) but moderate for Poland, Belgium SMEs (see Figure 2).Source: ECB (2009).Figure 2. Companies identifying access to finance as the most pressing problemsRegarding the profile of companies we notice th at the “acce s s to finance” was more often selected as the most pressing problem by managers of companies with a turnover of less than €10 million (16%-17% vs. 8%-10% for companies with a turnover above €10 million), established between two and nine years ago (20%-21% vs. 12% in companies established less than two years ago and 14% in companies existing for 10 years or more), in the construction sector 20% vs. 14% in the services sector and 17% in trade and industry or that have introduced innovation in at least one area –products or services, marketing, production and management (18% vs. 14% in non-innovative companies).Almost half (47%) of managers in the EU answered that they had used internal funds in the past six months to finance their operations (as seen above –some had only used internal funds, while others had used these in combination with external financing).The most popular source of debt financing was a bank: 30% of companies had used bank overdraft facilities or a credit line and 26% had received a bank loan. Debt can also be issued by a public source or even a friend or family member: 10% of interviewees referred to grants or subsidized bank loans and 7% mentioned “other loans”. A few (1%) managers said they had used a subordinated loan, participation loan or similar financing structures.Other financing forms as leasing, factoring or hire-purchasing were preferred by 23% from managers and 16% said they had used trade credit as a source of short-term financing. Regarding debt securities issuing, in the past six months, the majority of managers considered this type of financing not to be relevant for their needs.Equity issuance or external equity investments were mentioned by 2% of managers as one of the sources of external financing they had used in the past six months (European Central Bank, 2009, Gallup Organization, 2009).Source: ECB (2009).Figure 3. Internal and external sources of financing for EU SMEs (2009)The chart above shows the importance for the companies of the bank lending products (as debt financing, overdrafts, working capital line or other credit loans) in the past six months, as another source of external financing –i.e. equity issuance, equity investors, debt securities are very low utilization. Looking at company characteristics, we can see that micro-companies (with less than 10employees) were the most likely to use only internal funds in the past six months but, while, increasing the staff, a company is determined to use an external financing instruments.Regarding the sector of activity, we can notice that businesses in the industry sector were more interested to use both internal funds and external sources of finance in the past six months. Also, innovative companies were more active to seek and combine internal and external financing sources comparing with non-innovative ones (37% vs.31%). On the other hand, the new-established companies (active for less than two years) were the most likely to have only used internal funds to finance their operations (22% compared to 14%-17% for longer-established companies) (European Central Bank, 2009, Gallup Organization, 2009).2. Financial institutions structure and lending to SMEsWhile SMEs trust regularly on bank financing is important to know what kind of market structure is more suitable for SME financing. The analysis of SME financing, various theoretical studies or empirical evidence provides a considerable quantity of information regarding relationship between structures of the financial institution, technologies, management. Moreover, recent researches (Berger, Udell, 2004, Beck et al., 2010) try to show some distinction between lending technologies versus relationship lending to understand the very different transactions technologies, focusing on the comparative advantages of different types of financial institutions in using transactions lending technologies versus relationship lending (Berger, Udell, 1996, Miller, 2003, Berger, Udell, 2004).For our purpose, briefly we can define transactions lending as a banking technologies prim arily based on “hard” qu antitative data that may be observed and verified at about the time of the credit origination. This hard information may include: financial indicators computed from financial statements; credit scoring based on historical data provided by bank database, or SME itself, credit bureaus records; collateral registrations, or other information about solicitors from transparent sources (suppliers, payment incidents, external ratings, etc.). The main characteristic of this type of information is that it is relatively easily observed, verified, and transmitted through the communications channels within the financial institution.On the other hand, the relationship lending technology is based mostly on “soft”qualitative information provided by certain specialized persons, through a long, continuous, often discrete but intuitive contact over time with the SME owner, manager or com pany’s staff, or with members ofthe local community. The soft information may include the character and reliability of the SME’s owner based on direct contact over time by the institution’s loan officer; the payment and behavioral history of the SME regarding loans, cheques, deposits, other services to the SME by the institution; or the future prospects of the SME based of various data from SM E’s suppliers, customers, or neighboring businesses, local authorities or community. The soft information is given both by to the loan officer or other banking staff, but in general it may not be easily observed or verified by others risk managers, or inside bank deciders, especially when they received this information through communications channels within the financial institution (Berger, Udell, 2004).2.1. Does market concentration affect SM E’s lending efficiency?Several studies generally showed that a greater market concentration often result in a diminishing of credit access through any lending technology (Berger, Demirgüç-Kunt, Levine, Carlson, Haubrich, 2003). This comes about no mater of size, owner or country origin of parent bank but simply because the main financial actors in more concentrated markets may exercise greater market power. These institutions will choose to preserve or even increase their profit not only by an efficient activity or more flexible approach of SME requirements but through rising interest rates or fees on loans to SMEs. These institutions can be less interested innovation or in quality of service to the clients, based mainly on their sure position and power on the market. The banks can reduce the risk or implication in portfolio monitoring simply through tightening credit standards for SMEs. Some studies (Sharpe, 1990, Petersen, Rajan, 1995) show that this market power encourages the bank institution to press on a long-term implicit contract in which the borrower receives a lower interest rate in the short-term, but after a period the bank uses by its discretionary right to rise the costs of the loan (variable interests, advance repayment fee, administration fee etc) forcing the borrower to pay a higher-than-competitive rate in a later period.2.2. What kind of bank for SME’s lending?2.2.1. Are domestically-owned banks more interested in SMEs financing compared to foreign owned banks?On the first sight, foreign-owned institutions may have comparative advantages in SME technologies lending and domestically-owned institutions may have comparative advantages in relationship lending (de Haas, Naaborg, 2005, Berger, Udell, 2004). This assumption can beexplained by following reasons:1. Foreign-owned institutions are part of large organizations, and these behavior can be assimilated with specific typologies of big banks actions on the market;2. Foreign bank has often difficulties in processing and transmitting soft information over greater distances, through more managerial layers. Furthermore, they have to deal with multiple and different economic, cultural, language, and regulatory conditions environments which affect the relationship lending aspects;3.Small and domestic banks are more suitable to finance SMEs because they are better engaged in “relati onship lending”, a type of financing based on “soft” information collected by the loan officer having continuous, personalized, direct contacts with SMEs, with their owners and managers, and the local community;4. On the other hand foreign-owned institutions settled in developing economies may have additional advantages in transactions lending to some SMEs because they have a better access at information technologies for collecting and assessing hard information, cheap funds or greater expertise, even training for loan officer and risk managers in their headquarters.Some recent researches (Beck, Demirgüç-Kunt, Martinez, 2010), for a better understanding of the SME financing, tackle from the supply side using cross-country data, instead of large literature based of demand supply position. Based on an impressive collection of analyzed data(1) the results show significant differences across ownership types in lending technologies and organizational structures:1. Foreign banks are more likely to use hard information relative to private domestic banks. The share of secured SME loans is higher among foreign banks than domestic banks.2. Compared to domestic banks, foreign banks tend to be least likely to decentralize loan decision making and risk management, confirming the assertion that foreign banks use different lending techniques and organizational structures to reach out to SMEs.In spite of all these different approaches, the results show that different lending techniques and organizational structures lead at similar results in terms of SME lending. Most notably, the researches find no evidence that foreign banks tend to lend less to SMEs than other banks. The conclusion of these studies is that different bank types, applying different lending technologies and organizational structures, can play an important role in financing SMEs, in developing economies.2.2.2. What kind of banks are more efficient in the relationship with SMEs: state-owned banks versus private-owned banks?State-owned institutions may have comparative advantages in transactions lending comparing with privately-owned institutions which try to obtain comparative advantages in relationship lending, but these cannot always transform in an advantage. The explanation came from various evidences as:1. In general, state-owned institutions are larger than private local banks (excepting private foreign banks), but this dimension often prolongs/ extends communication channels and negative affects network efficiency;2. State owned- banks generally operate with government subsidies and often have mandates to supply additional credit to SMEs or specific industries, sectors, or regions. Apparently, this can be an advantage, both for banks or SME, but, in reality, the effects on SME lending are unclear or even an opposite effect. For example, some fund goes to SME unable to repay the amount at maturity or are not creditworthy, but are supported by different political or local power. In other case, these funds, instead to finance new, profitable business, based on strong cash flow, positive net present value projects are designated to repaid former credit, some of them in difficulty;3. State-owned institutions may also perform inconsistent credits monitoring and avoid a firm, steady policy of collection (or forced execution) procedures, because of lack of market discipline.2.2.3. Large banks or small banks?In the first stage we can admit that large bank institutions may have comparative advantages transactions lending technologies which are based on hard information and small institutions may have comparative advantages in using the relationship lending technology which is based on soft information.Referring on scale economies the large bank could take advantage from hard information processing, but disadvantaged in processing soft information because the difficulties to quantify and transmit this kind of data through the long communication channels. This may give comparative advantages in relationship lending to small institutions with lower administration costs, a less distinctive separation between ownership and management and fewer levels of management (Stein, 2002, Berger, Udell, 2002).Finally, it is often argued that large institutions are relatively disadvantaged at relationshiplending to SMEs because of organizational diseconomies, so this large bank prefer to enter in loan transaction and other wholesale services with large corporate customers. The empirical literature on this topic usually based the conclusions from the characteristics of the SME borrowers and contract terms on credits contract between SMEs and banks of different sizes (Berger, Rosen, Udell, 2003):1. Large bank institutions are found to lend to larger, older, more financially secure SMEs, often argued that large institutions lending prefer borrowers with a clear implemented corporative governance,2. Large banks are found to promote lower interest rates and obtain lower yields on SME loan contracts comparing with small institution which explained this differential through flexible, non bureaucratic and rapid procedures in credit assessment(Berger, Rosen, Udell, 2003, Berger, 2004);3. Small banks are found to have more longer, privileged and personal relationships with their SME loan customers, comparing with larger banks, based on long distance, impersonal and short terms of their relation with customers, appreciated as weaker (Berger, Miller, Petersen, Rajan, Stein) and often unsatisfactory for a better loan decision;4. Large banks institution appear to base their SME credit decisions more on strong financial ratios than on relationships.3. ConclusionsThe present paper try to offer an analysis of the role of different types of financial institution, their availability for SME lending , removing the opaque characteristic of this sectors on risk assessment, and a better acknowledgment of reasons and particularities, both from principal actors but from regulation and legislative framework, infrastructure etc.First, financial institution structure –the presence in the market of different types of institutions and the competition among them –may have important effects on SME credit availability because institutions of different types may have comparative advantages in different lending technologies. The lending infrastructure – the information environment, the legal, judicial and bankruptcy environment, and the tax and regulatory environments – may directly affect SME credit availability.Second, the presence of foreign-owned and state owned institutions, as well the presence of large and small institutions and the measure of financial institution concentration are elements that may affect SME credit availability through comparative advantages in the different lendingtechnologies. In particular, a greater presence of foreign-owned institutions and a lesser presence of state-owned institutions are likely to be associated with significantly higher SME credit availability in developing nations because foreign-owned institutions appear to have advantages in some of the lending technologies, and state-owned institutions appear to be generally disadvantaged.Third, the result of our research str ongly suggests that “better” lending in frastructures may make significant differences in SME credit availability directly through facilitating the use of the various lending technologies. A careful and restrictive regulatory environment may influence the financial institution structure, preventing some types of financial institutions to gain sufficient market shares in order to capitalize their comparative advantages in specific lending technologies and use in their interest the relative market power. It is the case of many developing countries in last decades that trying to reduce the considerable market share of state banks in favor of more efficient privately-owned institutions has to face now with particular problems generate by a very large presence of foreign owned bank in their banking sector.Finally, we consider that a well balanced structure of banking sector, with important state banks, involved in large national projects, dynamic and flexible small private banks, closed to relationship lending, and a provocative foreign bank presence can exploit all opportunities on the economies, creating a large base for meeting SME financing requirements.译文:中小企业融资:对不同信贷结构的需要程度和反应丹尼尔简介中小型企业在任何国家的发展中都起着非常重要的角色。