DT-2RV23-A7;中文规格书,Datasheet资料

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TMDSDCDCLEDKIT;中文规格书,Datasheet资料

Quick Start GuideSPRUGV0–May2010 TMS320C2000™DC/DC LED Lighting Developer's KitQuick Start GuideThis document provides instructions to run a GUI that controls the DC/DC LED Lighting Developer’s Kit board using the Piccolo F28035microcontroller.Contents of the DC/DC LED Lighting Developer’s Kit include:•DC/DC LED Lighting power board•Piccolo F28035controlCARD.•LED panel•12V power adapter•Banana Plug Cable•USB Cable•USB drive with GUI executable•CCS4Installation CDFeatures of the DC/DC LED Lighting Developer’s Kit include:•Independent closed-loop brightness control of eight LED strings(six strings included with kit)with PWM dimming•Closed-loop voltage control of the LED bus using a shared SEPIC stage•On-board isolated JTAG emulation•Over-current and over-voltage protection for the SEPIC stage using the F28x trip-zone(TZ)submodule •UART communication available for host-control•Hardware Developer’s Package is available and includes schematics,bill of materials,Gerber files,etc. 1OverviewThe DC/DC LED Lighting Developer’s Kit uses a12to36V DC input.This voltage is then regulated to a different level by a SEPIC converter.SEPIC,as a buck-boost topology,is able to increase or decrease the input voltage.For our application,we will be setting the SEPIC output voltage to approximately20V,independent of the board input.The SEPIC output is then connected to each of the LED strings.To1 SPRUGV0–May2010TMS320C2000™DC/DC LED Lighting Developer's Kit Quick Start GuideDC12-Overview perform independent LED string dimming,a MOSFET is placed in series with each string,and the on-time of this string’s MOSFET will control the average current through an LED string.Since the brightness of an LED is roughly proportional to the LED current,we use the duty cycle of each string’s PWM to control the average current drawn.The figure below illustrates the hardware that is present on the DC/DC LEDLighting Developer’s Kit.A typical power conversion board is made up of several power stages.On the Lighting_DCDC board,each of these power stages takes the form of a macro section.Each of these macro sections is bounded by its own silkscreen area.Below is a list of all the macro blocks’names and a short description of theirfunctions.Refer to the image on the next page for placement of macro areas.Lighting_DCDC Main Board -Consists of a controlCARD socket,a few communications jumpers,[Main]and the routing of signals between the controlCARD and the macroblocks.This section includes all of the area outside of the macroblocks.DC-PwrEntry Macro –[M1]Generates the 15V,5V,and 3.3V DC rails from a 12V supplyincluded with the kit or an external DC power supply.Isolated-USB-to-JTAG Macro –Provides on-board isolated JTAG connection through USB to the[M2]host.It is also used to provide isolated SCI (UART)communicationfor connection with the GUI.SEPIC-LV Macro –[M3]A SEPIC DC/DC conversion stage,used to increase or decrease theinput voltage to the voltage needed by the LED strings.LED-dimming Macro –[M4]-[M7]Stages used to individually dim an LED string.Each macro consistsof the components needed to control two strings.In this guide,each component is named first with its macro number,followed by the reference name.For example,[M2]-J1would refer to the jumper J1located in the macro M2,and [Main]-J1would refer to theJ1located on the board outside of the other defined macro blocks.2TMS320C2000™DC/DC LED Lighting Developer's Kit Quick Start GuideSPRUGV0–May 2010[Main]-J6EmulationEnable/DisableJumper [Main]-BS2Sepic Out Connector[M1]-JP1 12V Input Connector[M1]-J1JP1=DcBusEnable/Disable [M1]-TB1External DCSupply (not used)[M1]-SW1Main PowerSwitch [M2]-JP1 USBEmulatorConnector [Main]-BS3LED Bus ConnectorM7M6M5M4M2 Quick Start GUI 2Quick Start GUIThis kit comes with a GUI which provides a convenient way to evaluate the functionality of this kit and the F28035device,without having to learn and configure the underlying project software or install CodeComposer Studio™.The interactive interface using sliders,buttons,and text boxes,allows LED lighting with the C2000device to be demonstrated quickly and easily.2.1Hardware SetupListed below are some of the major connectors and features of the DC/DC LED Lighting board.Step 1.On the Piccolo F28035controlCARD,check the following switches:•SW1,make sure this switch is in the “OFF”(down)position •SW2,make sure position 1and 2are both in the “ON”(up)position Step 2.Put a F28035control card into the socket on the LED Lighting board,and connect a cablefrom the USB connector on the board to the computer.[M2]-LD1,near the LED Lightingboard’s USB connector,should turn on.3SPRUGV0–May 2010TMS320C2000™DC/DC LED Lighting Developer's Kit Quick Start GuideQuick Start GUI On the next screen select“Install from specific location”Click next and the drivers will be installed.The driver install screen will appearthree times,repeat this procedure each time.Step3.Connect the LED panel to the LED Lighting board via[Main]-TB1to TB8.Step4.Connect of verify the following:•Connect a jumper on[M1]-J1•Connect a jumper on[M2]-J4•Remove any jumpers placed on[Main]-J6Step5.Connect the banana-to-banana plug wire that came with the kit between the SEPIC-out Connector(BS2)and the LED Bus connector(BS3).Step6.Place[M1]-SW2into the"OFF"position.This switch will not be used in this demonstration.Step7.Connect a12V power supply to power up to[M1]-JP1of the board.Turn[M1]-SW1to the "ON"position.When on,[M1]-LD1and[M1]-LD2should turn on.2.2Software SetupThe GUI used to conveniently evaluate the kit can be found on the USB drive that is included with this kit.It is named Lighting_DCDC.exe.This.exe contains all the software necessary to do a quick evaluation of this kit.To explore deeper,the underlying reference software can be found as a Code Composer Studio project within controlSUITE.NOTE:The GUI requires framework3.0to run.Please ensure that this software isinstalled prior to running this program.•To install the CCS4project built to run with this kit,use the most up-to-date software,and find all reference software for the C2000MCU.Please install controlSUITE which can be downloaded at:/controlSUITE•Once controlSUITE is installed,the GUI mentioned in this guide can be found at the following location:c controlSUITE/development_kits/Lighting_DCDC_vX.X/~GUI/Lighting_DCDC.exe4TMS320C2000™DC/DC LED Lighting Developer's Kit Quick Start Guide SPRUGV0–May2010 Quick Start GUI •The source code for this GUI was written in C#using Microsoft Visual and can be found at:controlSUITE/development_kits/Lighting_DCDC_vX.X/~GUI/~Source/•The kit ships with a F28035controlCARD that has been pre-flashed with the code that enables it to run with the GUI that comes with this kit.If for any reason,the software needs to be reflashed so that itworks with the GUI again,this flash image can be found at:controlSUITE/development_kits/Lighting_DCDC_vX.X/~GUI/Lighting_DCDC-FlashImage_v1.0.out •The underlying Code Composer Studio4project documentation and how to run guide can be found at: controlSUITE/development_kits/Lighting_DCDC_vX.X/Lighting_DCDC/~Docs/Lighting_DCDC.pdf2.3Running the GUIThe following steps will allow you to run the GUI:1.Browse to and double-click on Lighting_DCDC.exe.If this is the first time that the GUI is run,the GUIwill ask the user to read a license agreement.Assuming that the license is accepted,the image belowwill be seen:2.Click“Setup Connection”on the GUI and ensure the Baud Rate is set to57600and that the“Boot onConnect”box is unchecked.3.Next you will need to select your serial comport.This can be found by going to:Control Panel->System->Hardware tab->Device Manager->Ports(COM&LPT)Look for the comport that is named“USB Serial Port”or similar,then select this comport in the“SetupConnection”window.4.Click“OK.”This will close the“Setup Connection”window.5.Turn on the board by switching[M1]-SW1to the“ON”position.6.On the Main Window,click“Connect.”When connected,the status bar at the bottom left of the GUIshould say“Connected.”5 SPRUGV0–May2010TMS320C2000™DC/DC LED Lighting Developer's Kit Quick Start GuideReferences 7.Move the“Sepic Output”slider to approximately20V.This sets the reference to which the controllerwill try to regulate the output of the Sepic.8.Change the value of LED string1’s target current to0.04A.Note that the“LED String1Current”rampsuntil it reaches approximately0.04A.9.Edit the other strings’target currents as desired.Note that the average LED current draw isproportional to LED lumen output for most high brightness LEDs.Therefore,in this program,thebrightness of the LEDs is being controlled.NOTE:Near the bottom of the GUI there is a checkbox control named“Merge LED controls.”Thiscontrol enables/disables individual control of each LED string and has the controller try andoutput the same current for each string.This reference is set by a slider.NOTE:There will be some variation from LED to LED from0.0to approximately0.02A.This isbecause the LEDs used are not guaranteed,from the manufacturer,to be identical until theLED current is greater than0.05A.10.When finished,set the“Sepic Output”to0V then click“Disconnect.”11.Power off the board by switching[M1]-SW1to the"OFF"position.3ReferencesFor more information,please see the following guides:•Lighting_DCDC–provides detailed information on the CCS4Lighting_DCDC project within an easy to use lab-style format.C:\TI\controlSUITE\development_kits\Lighting_DCDC_vX.X\Lighting_DCDC\~Docs\Lighting_DCDC.pdf •Lighting_DCDC-HWdevPkg–a folder containing various files related to the hardware on the Motor Control and PFC Developer’s Kit board(schematics,bill of materials,Gerber files,PCB layout,etc).C:\TI\controlSUITE\development_kits\Lighting_DCDC_vX.X\~Lighting_DCDC-HwdevPkg\•Lighting_DCDC-HWGuide–presents full documentation on the hardware found on the Lighting_DCDC board.C:\TI\controlSUITE\development_kits\Lighting_DCDC_vX.X\~Docs\Lighting_DCDC-HWGuide.pdf6TMS320C2000™DC/DC LED Lighting Developer's Kit Quick Start Guide SPRUGV0–May2010IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use any non-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDLP®Products Communications and /communicationsTelecomDSP Computers and /computersPeripheralsClocks and Timers /clocks Consumer Electronics /consumer-appsInterface Energy /energyLogic Industrial /industrialPower Mgmt Medical /medicalMicrocontrollers Security /securityRFID Space,Avionics&/space-avionics-defenseDefenseRF/IF and ZigBee®Solutions /lprf Video and Imaging /videoWireless /wireless-appsMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2010,Texas Instruments Incorporated分销商库存信息: TI TMDSDCDCLEDKIT。

V23074A1002A403;中文规格书,Datasheet资料

101-2013, Rev. 0113Datasheets and product specification ac-Datasheets and product data is subject to the Datasheets, product data, ‘Definitions’ sec-Micro Relay A/VFMA1) The values apply to a resistive or inductive load with suitable spark suppression and atmaximum 13.5VDC for 12VDC or 27VDC for 24VDC load voltages.2) For a load current duration of maximum 3s for a make/break ratio of 1:10.3) Current and time are compatible with circuit protection by a typical automotive fuse. Relay will make, carry and break the specified current.4) See chapter Diagnostics of Relays in our Application Notes or consult the internet at /appnotes/5) Electrical endurance data are only valid for the variants with resistor.6) Not applicable for polarity reverse loads like powerwindowsn High current version with limiting continuous current 30A at 85°C n Pin assignment according to ISO 7588 part 3n Customized versions on request– 24VDC versions with special contact gap – Integrated components (e.g. diode) – Customized marking– Special covers (e.g. notches, release features) – For latching version refer to Micro Relay Latching – For low noise version refer to Micro Relay Low Noise – For high current version refer to part number table Typical applicationsCross carline up to 30A for example: ABS control, blower fans, cooling fan, door control, door lock, fuel pump, heated front screen, immobilizer, interior lights, seat control, seatbelt pretensioner, sun roof, trunk lock, valves, window lifter, wiper control.Max. DC load breaking capacityLoad limit curve 1: arc extinguishes during transit time (CO contact).Load limit curve 2: safe shutdown, no stationary arc (NO contact).Load limit curves measured with low inductive resistors verified for 1000 switching events.Contact DataForm A – StandardForm C Form A – HCContact arrangement 1 form A, 1 NO 1 form A, 1 NO 1 form C, 1 CO 1 form C, 1 CO 1 form A, 1 NORated voltage 12VDC 24VDC 12VDC 24VDC 6) 12VDCLimiting continuous current, form A/form B NO/NC NO/NC 23°C 30A 30A 30/20A 30/20A 35A 85°C 25A 25A 25/15A 25/15A 30A 125°C 10A 10A 10/8A 10/8A 15ALimiting making current 1)2), A/B (NO/NC) 120A 120A 120/40A 120/20A 120ALimiting breaking current 30A 20A 30/15A 20/10A 30A Limiting short-time current,overload current, ISO 8820-33) 1.35 x 25A, 1800s 1.35 x 25A, 1800s 1.35 x 30A, 1800s 2.00 x 25A, 5s 2.00 x 25A, 5s 2.00 x 30A, 5s 3.50 x 25A, 0.5s 3.50 x 25A, 0.5s 3.50 x 30A, 0.5s 6.00 x 25A, 0.1s 6.00 x 25A, 0.1s 6.00 x 30A, 0.1s Jump start test 24VDC for 5min conducting nominal current at 23°C Contact material silver based Min. recommended contact load 4) 1A at 5VDC Initial voltage drop NO contact at 10A, typ./max. 15/200mV NC contact at 10A, typ./max. 20/250mV Frequency of operation 6 ops./min (0.1Hz)Electrical endurance 5)resistive load at 14VDC >1x105 ops. >1x105 ops. >1x105 ops.25A 25A (NO) 30A resistive load at 28VDC >1x105 ops. >1x105 ops. 15A 15A (NO) >1x105 ops. 10A (NC)Mechanical endurance typ. 107 ops. F074_fcw1_bwFVFMA_fcw1c201-2013, Rev. 0113Datasheets and product specification ac-Datasheets and product data is subject to the Datasheets, product data, ‘Definitions’ sec-Other DataEU RoHS/ELV compliance compliant Ambient temperature -40 to +125°C Climatic cycling with condensation, EN ISO 6988 6 cycles, storage 8/16h Temperature cycling, IEC 60068-2-14, Nb 10 cycles, -40/+85°C (5°C/min) Damp heat cyclic,IEC 60068-2-30, Db, Variant 1 6 cycles, upper air temp. 55°C Damp heat constant,IEC 60068-2-3 (78), Ca 56 days Category of environmental protection, IEC 61810 RT I – dustproof Degree of protection, IEC 60529 IP54 Corrosive gas IEC 60068-2-42 10±2cm 3/m 3 SO 2, 10 days IEC 60068-2-43 1±0.3cm 3/m 3 H 2S, 10 days Vibration resistance (functional) IEC 60068-2-6 (sine sweep) 10 to 500Hz min. 5g 8) Shock resistance (functional) IEC 60068-2-27 (half sine) min. 20g 11ms 8) Drop test, free fall, IEC 60068-2-32 1m onto concrete Terminal type plug-in, QC Cover retention axial force 150N pull force 150N push force 200N Terminal retention pull force 100N push force 100N resistance to bending 10N 9) force applied to side 10N 9) torque 0.3Nm Weight approx. 16 to 20g (0.5 to 0.7oz)Packaging unit Micro A 480 pcs. VFMA 600 pcs.8) No change in the switching state >10µs. Valid for NC contacts, NO contact values significantly higher.9) Values apply 2mm from the end of the terminal. When the force is removed, the terminal must not have moved by more than 0.3mmAccessoriesFor details see datasheetConnectors for Micro ISO RelaysCoil DataCoil voltage range 12/24VDCCoil versions, DC coil Coil Rated Operate Release Coil Rated coil code voltage voltage voltage resistance 7) power 7) VDC VDC VDC Ω±10% W 001 12 7.2 1.6 119 1.20 002 24 14.4 3.6 430 1.34 005 12 7.2 1.6 144 1.00 F 12 7.2 1.2 90 1.60 H 24 14.4 3.6 430 1.34All figures are given for coil without pre-energization, at ambient temperature +23°C.7) Without components in parallel.Insulation DataInitial dielectric strength between open contacts 500VAC rms between contact and coil 500VAC rms Load dump testISO 7637-1 (12VDC), test pulse 5 Vs=+86.5VDC ISO 7637-2 (24VDC), test pulse 5Vs=+200VDCNOD1 form A, 1 NO with diodeNOR1 form A, 1 NO with resistorTerminal Assignment COD1 form C, 1 CO with diodeCOR1 form C, 1 CO with resistor5435435353Does not take into account the temperature rise due to the contact currentE = pre-energization.Does not take into account the temperature rise due to the contact current E = pre-energization Coil operating range301-2013, Rev. 0113Datasheets and product specification ac-Datasheets and product data is subject to the Datasheets, product data, ‘Definitions’ sec-View of the terminals (bottom view)Quick connect terminal similar to ISO 8092-1.Micro A: Terminals without holes401-2013, Rev. 0113Datasheets and product specification ac-Datasheets and product data is subject to the Datasheets, product data, ‘Definitions’ sec-Product code structureTypical product code V23074 -A 1 001 -A4 02Type V23074 Micro Relay A Version A Standard H High current Coil suppression 1 Resistor 2 Diode Coil 001 12VDC 002 24VDC00512VDC for high current versionContact material -A4 Silver based -A5 Silver based for high current version Contact arrangement 02 1 form A, 1 NO031 form C, 1 COProduct code structureTypical product codeVFMA -1 1 F 4 1 -S01Type VFMA VFMA Series Version 1 Standard Contact arrangement 1 1 form A, 1 NO 5 1 form C, 1 COCoil F 12VDC H 24VDC Contact material 4 Silver based 7Silver based for high current versionTerminals 1 Plug-in Coil suppression S01 ResistorOther types on request.This list represents the most common types and does not show all variants covered by this datasheet.分销商库存信息: TE ConnectivityV23074A1002A403。

FMB2222A;中文规格书,Datasheet资料

Thermal Characteristics
Symbol
PD RθJA
TA = 25°C unless otherwise noted
Characteristic
Total Device Dissipation Derate above 25°C Thermal Resistance, Junction to Ambient Effective 4 Die Each Die FFB2222A 300 2.4 415
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Spice Model
NPN (Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)
300
VCE(sat) VBE(sat)
Collector-Emitter Saturation Voltage* Base-Emitter Saturation Voltage*
0.3 1.0 1.2 2.0
V V V V
SMALL SIGNAL CHARACTERISTICS
fT Cobo Cibo NF Current Gain - Bandwidth Product Output Capacitance Input Capacitance Noise Figure IC = 20 mA, VCE = 20 V, f = 100 MHz VCB = 10 V, IE = 0, f = 100 kHz VEB = 0.5 V, IC = 0, f = 100 kHz IC = 100 µA, VCE = 10 V, RS = 1.0 kΩ, f = 1.0 kHz 300 4.0 20 2.0 MHz pF pF dB

FGH40N65UFDTU;中文规格书,Datasheet资料

Figure 3. Typical Saturation Voltage Characteristics
120
Common Emitter
100
VGE = 15V TC = 25oC
80 TC = 125oC
20
VGE = 8V
0
0.0
1.5
3.0
4.5
6.0
Collector-Emitter Voltage, VCE [V]
0
0
1
2
3
4
Collector-Emitter Voltage, VCE [V]
Figure 5. Saturation Voltage vs. Case Temperature at Variant Current Level
3.5 Common Emitter VGE = 15V
3.0 80A
0 5 6 7 8 9 10 11 12 Gate-Emitter Voltage,VGE [V]
120 TC = 125oC
100
15V 20V
12V
Collector Current, IC [A]
Collector Current, IC [A]
80
80
60
60
10V
10V
40
40
20
VGE = 8V
0
0.0
1.5
3.0
4.5
6.0
Collector-Emitter Voltage, VCE [V]
Figure 4. Transfer Characteristics
120
Common Emitter VCE = 20V 100 TC = 25oC TC = 125oC 80

2N7002K,215;中文规格书,Datasheet资料

2N7002KTrenchMOS™ logic level FETRev. 01 — 20 October 2003Product dataM3D0881.Product proﬁle1.1DescriptionN-channel enhancement mode ﬁeld-effect transistor in a plastic package using TrenchMOS™ technology.1.2Features1.3Applications1.4Quick reference data2.Pinning informations Logic level compatible s Very fast switchings Subminiature surface mount package s Gate-source ESD protection diodes.s Relay drivers High speed line driver.s V DS ≤60V s I D ≤340mA s P tot ≤0.83Ws R DSon ≤3.9Ω.Table 1:Pinning - SOT23, simpliﬁed outline and symbolPin Description Simpliﬁed outlineSymbol1gate (g)SOT232source (s)3drain (d)MSB003Top view123gds03ab603.Ordering informationTable 2:Ordering informationType number PackageName Description Version2N7002K SOT23Plastic surface mounted package; 3 leads.SOT23 4.Limiting valuesTable 3:Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max Unit V DS drain-source voltage (DC)25°C≤T j≤150°C-60VV DGR drain-gate voltage (DC)25°C≤T j≤150°C; R GS=20kΩ-60VV GS gate-source voltage (DC)-±15VI D drain current (DC)T sp=25°C; V GS=10V;Figure2and3-340mAT sp=100°C; V GS=10V;Figure2-215mA I DM peak drain current T sp=25°C; pulsed; t p≤10µs;Figure3-680mA P tot total power dissipation T sp=25°C;Figure1-0.83W T stg storage temperature−65+150°C T j junction temperature−65+150°C Source-drain diodeI S source (diode forward) current (DC)T sp=25°C-340mA I SM peak source (diode forward) current T sp=25°C; pulsed; t p≤10µs-680mA Electrostatic discharge voltageV esd electrostatic discharge voltage Human Body Model1; C=100pF; R=1.5kΩ-1kVFig 1.Normalized total power dissipation as afunction of solder point temperature.Fig 2.Normalized continuous drain current as afunction of solder point temperature.T sp =25°C; I DM is single pulse; V GS =10VFig 3.Safe operating area; continuous and peak drain currents as a function of drain-source voltage.03aa1704080120050100150200(%)T sp (°C)P der 03aa2504080120050100150200T sp (°C)I der (%)P der P totP tot 25C °()-----------------------100%×=I der I DI D 25C °()-------------------100%×=03an6610-210-11110102V DS (V)I D (A)DC100 ms10 msLimit R DSon = V DS / I D1 mst p = 10 µs100 µs5.Thermal characteristics5.1Transient thermal impedanceTable 4:Thermal characteristicsSymbol ParameterConditionsMin Typ Max Unit R th(j-sp)thermal resistance from junction to solder point Figure 4--150K/W R th(j-a)thermal resistance from junction to ambientminimum footprint;mounted on a printed-circuit board-350-K/WFig 4.Transient thermal impedance from junction to solder point as a function of pulse duration.03aa3911010210310-510-410-310-210-1110t p (s)Z th(j-sp)(K/W)single pulseδ = 0.50.20.10.050.02t pt p TPtTδ =6.CharacteristicsTable 5:CharacteristicsT j=25°C unless otherwise speciﬁed.Symbol Parameter Conditions Min Typ Max Unit Static characteristicsV(BR)DSS drain-source breakdown voltage I D=10µA; V GS=0VT j=25°C6075-VT j=−55°C55--VV(BR)GSS drain-source breakdown voltage I G=±1mA; V DS=0V1622-VV GS(th)gate-source threshold voltage I D=1mA; V DS=V GS;Figure9VT j=25°C12-VT j=150°C0.6--VT j=−55°C-- 3.5VI DSS drain-source leakage current V DS=48V; V GS=0VT j=25°C-0.011µAT j=150°C--10µA I GSS gate-source leakage current V GS=±10V; V DS=0V-50500nA R DSon drain-source on-state resistance V GS=10V; I D=500mA;Figure7and8T j=25°C- 2.8 3.9ΩT j=150°C- 5.27.2ΩV GS=4.5V; I D=200mA;Figure7and8- 3.8 5.3ΩDynamic characteristicsC iss input capacitance V GS=0V; V DS=10V; f=1MHz;Figure11-1340pFC oss output capacitance-830pF C rss reverse transfer capacitance-410pFt on turn-on time V DD=50V; R L=250Ω;V GS=10V;R G=50Ω; R GS=50Ω-310nst off turn-off time-915ns Source-drain diodeV SD source-drain (diode forward) voltage I S=300mA; V GS=0V;Figure12-0.93 1.5Vt rr reverse recovery time I S=300mA; dI S/dt=−100A/µs;V GS=0V; V R=25V -30-nsQ r recovered charge-30-nCT j =25°C T j =25°C and 150°C; V DS >I D x R DSonFig 5.Output characteristics: drain current as afunction of drain-source voltage;typical values.Fig 6.Transfer characteristics: drain current as afunction of gate-source voltage; typical values.T j =25°CFig 7.Drain-source on-state resistance as a functionof drain current; typical values.Fig 8.Normalized drain-source on-state resistance factor as a function of junction temperature.03an7000.10.20.30.40.500.511.52V DS (V)I D (A) 3.5 VT j = 25 °CV GS = 10V4 V4.5 V3 V6 V03an7200.10.20.30.40.50246V GS (V)I D (A)V DS > I D x R DSonT j = 25 °C150 °C03an71024681000.10.20.30.40.5I D (A)R DSon (Ω)V GS = 3.5 VT j = 25 °C4.5 V4 V10 V6 V 03aa2800.61.21.82.4-6060120180a T j (°C)a RDSon R DSon 25C °()----------------------------=I D =1mA; V DS =V GS T j =25°C; V DS =5VFig 9.Gate-source threshold voltage as a function ofjunction temperature.Fig 10.Sub-threshold drain current as a function ofgate-source voltage.V GS =0V; f =1MHzFig 11.Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.03aa3400.61.21.82.4-6060120180T j (°C)V GS(th)(V)typmin03aa3710-610-510-410-310-210-100.61.21.82.4V GS (V)I D (A)typmin03aa4611010210-11 10102V DS (V)C (pF)C issC ossC rssT j =25°C and 150°C; V GS =0V I D =0.5A; V DD =48VFig 12.Source (diode forward) current as a function ofsource-drain (diode forward) voltage; typical values.Fig 13.Gate-source voltage as a function of gatecharge; typical values.03an7300.10.20.30.40.500.30.60.91.2V SD (V)I S (A)T j = 25 °C150 °CV GS = 0 V03ab090510150.30.60.91.2Q G (nC)V GS (V)I D = 0.5AV DD = 48 V T j = 25 °C7.Package outlineFig 14.SOT23.UNIT A 1max.b p c D E e 1H E L p Q w v REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE 97-02-2899-09-13IECJEDEC EIAJmm0.10.480.380.150.093.02.81.41.20.95e 1.92.52.10.550.450.10.2DIMENSIONS (mm are the original dimensions)0.450.15SOT23TO-236ABb pD e 1eAA 1L pQdetail XH EE w M v M ABAB 01 2 mmscaleA 1.10.9cX123Plastic surface mounted package; 3 leadsSOT238.Revision historyTable 6:Revision historyRev Date CPCN Description0120031020Product data (9397 750 11703)分销商库存信息: NXP2N7002K,215。

74HC245DTR2G, 规格书,Datasheet 资料

74HC245Octal 3−State Noninverting Bus TransceiverHigh −Performance Silicon −Gate CMOSThe 74HC245 is identical in pinout to the LS245. The device inputs are compatible with standard CMOS outputs; with pull −up resistors,they are compatible with LSTTL outputs.The HC245 is a 3−state noninverting transceiver that is used for 2−way asynchronous communication between data buses. The device has an active −low Output Enable pin, which is used to place the I/O ports into high −impedance states. The Direction control determines whether data flows from A to B or from B to A.Features•Output Drive Capability: 15 LSTTL Loads•Outputs Directly Interface to CMOS, NMOS, and TTL •Operating V oltage Range: 2.0 to 6.0 V •Low Input Current: 1.0 m A•High Noise Immunity Characteristic of CMOS Devices•In Compliance with the Requirements Defined by JEDEC Standard No. 7A•ESD Performance: HBM > 2000 V; Machine Model > 200 V•Chip Complexity: 308 FETs or 77 Equivalent Gates •This is a Pb −Free Device120MARKING DIAGRAMSHC 245ALYW GGTSSOP −20DT SUFFIX CASE 948ESee detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.ORDERING INFORMATIONHC245= Device CodeA = Assembly Location L = Wafer Lot Y = YearW = Work WeekG = Pb −Free Package(Note: Microdot may be in either location)Figure 1. Pin Assignment A5A3A2A1DIRECTIONGNDA8A7A6A4B3B2B1OUTPUT ENABLE V CCB8B7B6B5B4A DATA PORTA8A7A6A5A3A4A2A1DIRECTION OUTPUT ENABLEPIN 10 = GND PIN 20 = V CCB1B2B3B4B5B6B7B8B DATA PORTFigure 2. Logic DiagramFUNCTION TABLEControl Inputs OperationOutput Enable DirectionL L Data Transmitted from Bus B to Bus A L H Data Transmitted from Bus A to Bus B H XBuses Isolated (High −Impedance State)X = don’t careORDERING INFORMATIONDevicePackage Shipping †74HC245DTR2GTSSOP −20*2500 / Tape & Reel†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.*This package is inherently Pb −Free.MAXIMUM RATINGS (Note 1)Symbol Parameter Value Unit V CC DC Supply Voltage*0.5 to )7.0V V IN DC Input Voltage*0.5 to V CC)0.5V V OUT DC Output Voltage(Note 2)*0.5 to V CC)0.5VI IK DC Input Diode Current$20mAI OK DC Output Diode Current$35mA I OUT DC Output Sink Current$35mAI CC DC Supply Current per Supply Pin$75mA I GND DC Ground Current per Ground Pin$75mA T STG Storage Temperature Range*65 to )150_C T L Lead Temperature, 1 mm from Case for 10 Seconds260_C T J Junction Temperature Under Bias)150_C q JA Thermal Resistance TSSOP128_C/W P D Power Dissipation in Still Air at 85_C TSSOP450mW MSL Moisture Sensitivity Level 1F R Flammability Rating Oxygen Index: 30% to 35%UL 94 V−0 @ 0.125 inV ESD ESD Withstand Voltage Human Body Model (Note 3)Machine Model (Note 4)u2000u200VI LATCHUP Latchup Performance Above V CC and Below GND at 85_C (Note 5)$300mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow.2.I O absolute maximum rating must observed.3.Tested to EIA/JESD22−A114−A.4.Tested to EIA/JESD22−A115−A.5.Tested to EIA/JESD78.RECOMMENDED OPERATING CONDITIONSSymbol Parameter Min Max Unit V CC DC Supply Voltage (Referenced to GND) 2.0 6.0VV in, V out DC Input Voltage, Output Voltage (Referenced to GND)0V CC V T A Operating Temperature, All Package Types–55+125_Ct r, t f Input Rise and Fall Time V CC = 2.0 V (Figure 3)V CC = 4.5 VV CC = 6.0 V 01000500400nsDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitSymbol Parameter Test Conditions V CCV–55 to25_C v 85_C v 125_C UnitV IH Minimum High−Level Input Voltage V out = V CC – 0.1 V|I out| v 20 m A 2.03.04.56.01.52.13.154.21.52.13.154.21.52.13.154.2VV IL Maximum Low−Level Input Voltage V out = 0.1 V|I out| v 20 m A 2.03.04.56.00.50.91.351.80.50.91.351.80.50.91.351.8VV OH Minimum High−Level Output Voltage V in = V IH|I out| v 20 m A2.04.56.01.94.45.91.94.45.91.94.45.9VV in = V IH|I out| v 2.4 mA|I out| v 6.0 mA|I out| v 7.8 mA3.04.56.02.483.985.482.343.845.342.23.75.2V OL Maximum Low−Level Output Voltage V in = V IL|I out| v 20 m A2.04.56.00.10.10.10.10.10.10.10.10.1VV in = V IL|I out| v 2.4 mA|I out| v 6.0 mA|I out| v 7.8 mA3.04.56.00.260.260.260.330.330.330.40.40.4I in Maximum Input Leakage Current V in = V CC or GND 6.0±0.1±1.0±1.0m AI OZ Maximum Three−State LeakageCurrent Output in High−Impedance StateV in = V IL or V IHV out = V CC or GND6.0±0.5±5.0±10m AI CC Maximum Quiescent SupplyCurrent (per Package)V in = V CC or GNDI out = 0 m A6.0 4.04040m Armation on typical parametric values and high frequency or heavy load considerations can be found in the ON SemiconductorHigh−Speed CMOS Data Book (DL129/D).AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6 ns)Symbol Parameter V CCVGuaranteed LimitUnit –55 to25_C v85_C v 125_Ct PLH, t PHL Maximum Propagation Delay,A to B,B to A(Figures 1 and 3)2.03.04.56.07555151395701916110802219nst PLZ, t PHZ Maximum Propagation Delay,Direction or Output Enable to A or B(Figures 2 and 4)2.03.04.56.011090221914011028241651303328nst PZL, t PZH Maximum Propagation Delay,Output Enable to A or B(Figures 2 and 4)2.03.04.56.011090221914011028241651303328nst TLH, t THL Maximum Output Transition Time,Any Output(Figures 1 and 3)2.03.04.56.0602312107527151390321815nsC in Maximum Input Capacitance (Pin 1 or Pin 19)−101010pFC out Maximum Three−State I/O Capacitance(I/O in High−Impedance State)−151515pF7.For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−SpeedCMOS Data Book (DL129/D).C PD Power Dissipation Capacitance (Per Transceiver Channel) (Note 8)Typical @ 25°C, V CC = 5.0 VpF40ed to determine the no−load dynamic power consumption: P D = C PD V CC f + I CC V CC. For load considerations, see the ONSemiconductor High−Speed CMOS Data Book (DL129/D).V CCGNDFigure 3. Switching Waveform OUTPUT ENABLE A OR B A OR BV CCGNDHIGHIMPEDANCEV OLV OHHIGHIMPEDANCEV CCGNDFigure 4. Switching WaveformDIRECTION*Includes all probe and jig capacitanceC L*TEST POINTFigure 5. Test Circuit*Includes all probe and jig capacitanceTEST POINTFigure 6. Test CircuitCONNECT TO V CC WHENTESTING t PLZ AND t PZL.CONNECT TO GND WHENTESTING t PHZ AND t PZH.A DATA PORTBDATAPORTB1B2B3B4B5B6B7B8Figure 7. Expanded Logic DiagramPACKAGE DIMENSIONSTSSOP −20CASE 948E −02ISSUE CDIM A MIN MAX MIN MAX INCHES 6.600.260MILLIMETERS B 4.30 4.500.1690.177C 1.200.047D 0.050.150.0020.006F 0.500.750.0200.030G 0.65 BSC 0.026 BSC H 0.270.370.0110.015J 0.090.200.0040.008J10.090.160.0040.006K 0.190.300.0070.012K10.190.250.0070.010L 6.40 BSC 0.252 BSCM0 8 0 8 ____NOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION:MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSIONSHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08(0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY .7.DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W −.6.400.252−−−−−−16X0.360.65PITCHSOLDERING FOOTPRINT**For additional information on our Pb −Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。

BYV32EB-200,118;中文规格书,Datasheet资料

BYV32EB-200Dual rugged ultrafast rectifier diode, 20 A, 200 VRev. 04 — 2 March 2009Product data sheet 1.Product profile1.1General descriptionUltrafast dual epitaxial rectifier diode in a SOT404 (D2PAK) surface-mountable plasticpackage.1.2Features and benefitsHigh reverse voltage surge capability High thermal cycling performanceLow thermal resistance Soft recovery characteristic minimizes power consuming oscillationsSurface-mountable packageVery low on-state loss1.3ApplicationsOutput rectifiers in high-frequencyswitched-mode power supplies1.4Quick reference dataTable 1.Quick referenceSymbol Parameter Conditions Min Typ Max Unit V RRM repetitive peak reverse voltage--200VI O(AV)average output current square-wave pulse; δ=0.5;T mb≤115°C; both diodes conducting;see Figure 1; see Figure 2--20AI RRM repetitive peak reverse current t p=2µs; δ=0.001--0.2AV ESD electrostatic discharge voltage HBM; C = 250 pF; R = 1.5 kΩ; all pins--8kV Dynamic characteristicst rr reverse recovery time I F=1A; V R=30V;dI F/dt=100A/µs;T j=25°C; ramp recovery; see Figure 5-2025nsI R=1A;I F=0.5A;T j=25°C; measuredat reverse current = 0.25 A; steprecovery; see Figure 6-1020nsStatic characteristicsV F forward voltage I F=8A; T j=150°C; see Figure 4-0.720.85V2.Pinning information[1]it is not possible to make a connection to pin 2 of the SOT404 package3.Ordering informationTable 2.Pinning information Pin Symbol Description Simplified outline Graphic symbol1A1anode 1SOT404 (D2PAK)2K cathode [1]3A2anode 2mbKmounting base; cathodemb132sym125Table 3.Ordering information Type number PackageName DescriptionVersion BYV32EB-200D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads (onelead cropped)SOT4044.Limiting valuesTable 4.Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).Symbol ParameterConditionsMin Max Unit V RRM repetitive peak reverse voltage-200V V RWM crest working reverse voltage -200V V R reverse voltage DC-200V I O(AV)average output currentsquare-wave pulse; δ=0.5; T mb ≤115°C; both diodes conducting; see Figure 1; see Figure 2-20A I FRM repetitive peak forward currentδ=0.5; t p =25µs; T mb ≤115°C; per diode -20A I FSMnon-repetitive peak forward currentt p =8.3ms; sine-wave pulse; T j(init)=25°C; per diode-137A t p =10ms; sine-wave pulse; T j(init)=25°C;per diode-125A I RRM repetitive peak reverse currentδ=0.001; t p =2µs -0.2A I RSM non-repetitive peak reverse current t p =100µs-0.2A T stg storage temperature -40150°C T j junction temperature-150°C V ESDelectrostatic discharge voltageHBM; C = 250 pF; R = 1.5 k Ω; all pins -8kV5.Thermal characteristics6.CharacteristicsTable 5.Thermal characteristics Symbol ParameterConditionsMin Typ Max Unit R th(j-mb)thermal resistance from junction to mounting base with heatsink compound; both diodes conducting -- 1.6K/W with heatsink compound; per diode; seeFigure 3-- 2.4K/W R th(j-a)thermal resistance from junction to ambientminimum footprint FR4 board -50-K/WTable 6.Characteristics Symbol Parameter ConditionsMin Typ Max Unit Static characteristicsV F forward voltage I F =8A; T j =150°C; see Figure 4-0.720.85V I F =20A; T j =25°C -1 1.15V I Rreverse currentV R =200V; T j =25°C -630µA V R =200V; T j =100°C-0.20.6mADynamic characteristics Q r recovered charge I F =2A; V R =30V;dI F /dt =20A/µs -812.5nC t rrreverse recovery timeI F =1A; V R =30V;dI F /dt =100A/µs; ramp recovery; T j =25°C; see Figure 5-2025ns I F =0.5A; I R =1A; measured at reverse current = 0.25 A; step recovery; T j =25°C; see Figure 6-1020nsV FRforward recovery voltageI F =1A; dI F /dt =10A/µs; see Figure 7--1V7.Package outlinePlastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)SOT404Fig 8.Package outline SOT404 (D2PAK)8.Revision historyTable 7.Revision historyDocument ID Release date Data sheet status Change notice SupersedesBYV32EB-200_420090302Product data sheet-BYV32E_SERIES_3 Modifications:•The format of this data sheet has been redesigned to comply with the new identityguidelines of NXP Semiconductors.•Legal texts have been adapted to the new company name where appropriate.•Package outline updated.•Type number BYV32EB-200 separated from data sheet BYV32E_SERIES_3BYV32E_SERIES_320010301Product specification-BYV32E_SERIES_2 BYV32E_SERIES_219980701Product specification-BYV32EB_SERIES_1 BYV32EB_SERIES_119960801Product specification--9.Legal information9.1Data sheet status[1]Please consult the most recently issued document before initiating or completing a design.[2]The term 'short data sheet' is explained in section "Definitions".[3]The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL .9.2DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequences of use of such information.Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.9.3DisclaimersGeneral — Information in this document is believed to be accurate andreliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including withoutlimitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure ormalfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmentaldamage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Quick reference data — The Quick reference data is an extract of theproduct data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in theCharacteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at /profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.9.4TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.10.Contact informationFor more information, please visit: For sales office addresses, please send an email to: salesaddresses@Document status [1][2]Product status [3]DefinitionObjective [short] data sheet Development This document contains data from the objective specification for product development.Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.Product [short] data sheetProductionThis document contains the product specification.11.Contents1Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . .11.1General description . . . . . . . . . . . . . . . . . . . . . .11.2Features and benefits. . . . . . . . . . . . . . . . . . . . .11.3Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.4Quick reference data . . . . . . . . . . . . . . . . . . . . .12Pinning information. . . . . . . . . . . . . . . . . . . . . . .23Ordering information. . . . . . . . . . . . . . . . . . . . . .24Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .35Thermal characteristics . . . . . . . . . . . . . . . . . . .46Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .47Package outline. . . . . . . . . . . . . . . . . . . . . . . . . .68Revision history. . . . . . . . . . . . . . . . . . . . . . . . . .79Legal information. . . . . . . . . . . . . . . . . . . . . . . . .89.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . . .89.2Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .89.4Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . .810Contact information. . . . . . . . . . . . . . . . . . . . . . .8Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.© NXP B.V.2009.All rights reserved.For more information, please visit: For sales office addresses, please send an email to: salesaddresses@分销商库存信息: NXPBYV32EB-200,118。

ADE7878ACPZ;ADE7854ACPZ;ADE7854ACPZ-RL;ADE7858ACPZ-RL;ADE7868ACPZ-RL;中文规格书,Datasheet资料

Polyphase Multifunction Energy Metering ICADE7854/ADE7858/ADE7868/ADE7878 Rev. EInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.FEATURESHighly accurate; supports EN 50470-1, EN 50470-3,IEC 62053-21, IEC 62053-22, and IEC 62053-23 standards Compatible with 3-phase, 3- or 4-wire (delta or wye), and other 3-phase servicesSupplies total (fundamental and harmonic) active, reactive (ADE7878, ADE7868, and ADE7858 only), and apparent energy, and fundamental active/reactive energy (ADE7878 only) on each phase and on the overall systemLess than 0.1% error in active and reactive energy over a dynamic range of 1000 to 1 at T A = 25°CLess than 0.2% error in active and reactive energy over a dynamic range of 3000 to 1 at T A = 25°CSupports current transformer and di/dt current sensors Dedicated ADC channel for neutral current input (ADE7868 and ADE7878 only)Less than 0.1% error in voltage and current rms over a dynamic range of 1000 to 1 at T A = 25°CSupplies sampled waveform data on all three phases and on neutral currentSelectable no load threshold levels for total and fundamental active and reactive powers, as well as for apparent powersLow power battery mode monitors phase currents for antitampering detection (ADE7868 and ADE7878 only) Battery supply input for missing neutral operationPhase angle measurements in both current and voltage channels with a typical 0.3° errorWide-supply voltage operation: 2.4 V to 3.7 VReference: 1.2 V (drift 10 ppm/°C typical) with external overdrive capabilitySingle 3.3 V supply40-lead lead frame chip scale package (LFCSP), Pb-free Operating temperature: −40°C to +85°CFlexible I2C, SPI, and HSDC serial interfaces APPLICATIONSEnergy metering systemsGENERAL DESCRIPTIONThe ADE7854/ADE7858/ADE7868/ADE7878 are high accuracy, 3-phase electrical energy measurement ICs with serial interfaces and three flexible pulse outputs. The ADE78xx devices incorporate second-order sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), a digital integrator, reference circuitry, and all of the signal processing required to perform total (fundamental and harmonic) active, reactive (ADE7878, ADE7868, and ADE7858), and apparent energy measurement and rms calcu-lations, as well as fundamental-only active and reactive energy measurement (ADE7878) and rms calculations. A fixed function digital signal processor (DSP) executes this signal processing. The DSP program is stored in the internal ROM memory. The ADE7854/ADE7858/ADE7868/ADE7878 are suitable for measuring active, reactive, and apparent energy in various 3-phase configurations, such as wye or delta services, with both three and four wires. The ADE78xx devices provide system calibration features for each phase, that is, rms offset correction, phase calibration, and gain calibration. The CF1, CF2, and CF3 logic outputs provide a wide choice of power information: total active, reactive, and apparent powers, or the sum of the current rms values, and fundamental active and reactive powers.The ADE7854/ADE7858/ADE7868/ADE7878 contain wave-form sample registers that allow access to all ADC outputs. The devices also incorporate power quality measurements, such as short duration low or high voltage detections, short duration high current variations, line voltage period measurement, and angles between phase voltages and currents. Two serial interfaces, SPI and I2C, can be used to communicate with the ADE78xx. A dedicated high speed interface, the high speed data capture (HSDC) port, can be used in conjunction with I2C to provide access to the ADC outputs and real-time power information. The ADE7854/ADE7858/ADE7868/ADE7878 also have two interrupt request pins, IRQ0 and IRQ1, to indicate that an enabled interrupt event has occurred. For the ADE7868/ADE7878, three specially designed low power modes ensure the continuity of energy accumulation when the ADE7868/ADE7878 is in a tam-pering situation. See for a quick reference chart listing each part and its functions. The ADE78xx are available in the 40-lead LFCSP, Pb-free package.Table 1Table 1. Part ComparisonPart No. WATT VARIRMS,VRMS,andVA di/dtFundamentalWATT andVARTamperDetectand LowPowerModes ADE7878 Yes Yes Yes Yes Yes Yes ADE7868 Yes Yes Yes Yes No Yes ADE7858 Yes Yes Yes Yes No No ADE7854 Yes No Yes Yes No NoADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 2 of 96TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Revision History...............................................................................3 Functional Block Diagrams.............................................................4 Specifications.....................................................................................8 Timing Characteristics..............................................................11 Absolute Maximum Ratings..........................................................14 Thermal Resistance....................................................................14 ESD Caution................................................................................14 Pin Configuration and Function Descriptions...........................15 Typical Performance Characteristics...........................................17 Test Circuit......................................................................................19 Terminology....................................................................................20 Power Management........................................................................21 PSM0—Normal Power Mode (All Parts)................................21 PSM1—Reduced Power Mode (ADE7868, ADE7878 Only)21 PSM2—Low Power Mode (ADE7868, ADE7878 Only).......21 PSM3—Sleep Mode (All Parts)................................................22 Power-Up Procedure..................................................................24 Hardware Reset...........................................................................25 Software Reset Functionality....................................................25 Theory of Operation......................................................................26 Analog Inputs..............................................................................26 Analog-to-Digital Conversion..................................................26 Current Channel ADC...............................................................27 di/dt Current Sensor and Digital Integrator..............................29 Voltage Channel ADC...............................................................30 Changing Phase Voltage Datapath...........................................31 Power Quality Measurements...................................................32 Phase Compensation.................................................................37 Reference Circuit........................................................................39 Digital Signal Processor.............................................................39 Root Mean Square Measurement.............................................40 Active Power Calculation..........................................................44 Reactive Power Calculation—ADE7858, ADE7868, ADE7878 Only..............................................................................................49 Apparent Power Calculation.....................................................54 Waveform Sampling Mode.......................................................57 Energy-to-Frequency Conversion............................................57 No Load Condition....................................................................61 Checksum Register.....................................................................63 Interrupts.....................................................................................64 Serial Interfaces..........................................................................65 ADE7878 Evaluation Board......................................................72 Die Version..................................................................................72 Silicon Anomaly.............................................................................73 ADE7854/ADE7858/ADE7868/ADE7878 FunctionalityIssues............................................................................................73 Functionality Issues....................................................................73 Section 1. ADE7854/ADE7858/ADE7868/ADE7878Functionality Issues....................................................................74 Registers List...................................................................................75 Outline Dimensions.......................................................................93 Ordering Guide.. (93)ADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 3 of 96REVISION HISTORY4/11—Rev. D to Rev. EChanges to Input Clock FrequencyParameter, Table 2..............10 Changes to Current RMS Offset Compensation Section..........42 Changes to Voltage RMS Offset Compensation Section...........44 Changes to Note 2, Table 30...........................................................77 Changes to Address 0xE707, Table 33..........................................80 Changes to Table 45........................................................................87 Changes to Table 46........................................................................88 Changes to Bit Location 7:3, Default Value, Table 54.. (92)2/11—Rev. C to Rev. DChanges to Figure 1...........................................................................4 Changes to Figure 2...........................................................................5 Changes to Figure 3...........................................................................6 Changes to Figure 4...........................................................................7 Changes to Table 2............................................................................8 Changed SCLK Edge to HSCLK Edge, Table 5...........................13 Change to Current Channel HPF Section...................................28 Change to di/dt Current Sensor and Digital IntegratorSection..............................................................................................30 Changes to Digital Signal Processor Section...............................39 Changes to Figure 59......................................................................44 Changes to Figure 62......................................................................47 Changes to Figure 65......................................................................49 Changes to Figure 66......................................................................52 Changes to Line Cycle Reactive Energy Accumulation Mode Section and to Figure 67.................................................................53 No Load Detection Based On Total Active, Reactive Powers Section..............................................................................................61 Change to Equation 50...................................................................63 Changes to the HSDC Interface Section......................................70 Changes to Figure 87 and Figure 88.............................................71 Changes to Figure 89......................................................................72 Changes to Table 30 (77)11/10—Rev. B to Rev. CChange to Signal-to-Noise-and-Distortion Ratio, SINADParameter, Table 1.............................................................................9 Changes to Figure 18......................................................................18 Changes to Figure 22......................................................................19 Changes to Silicon Anomaly Section............................................72 Added Table 28 to Silicon Anomaly Section, RenumberedTables Sequentially..........................................................................73 8/10—Rev. A to Rev. BChanges to Figure 1..........................................................................4 Changes to Figure 2..........................................................................5 Changes to Figure 3..........................................................................6 Changes to Figure 4..........................................................................7 Change to Table 8............................................................................16 Changes to Power-Up Procedure Section....................................23 Changes to Equation 6 and Equation 7........................................33 Changes to Equation 17.................................................................43 Changes to Active Power Offset Calibration Section.................45 Changes to Figure 63......................................................................46 Changes to Reactive Power Offset Calibration Section.............49 Changes to Figure 82......................................................................65 Added Silicon Anomaly Section, Renumbered TablesSequentially (71)3/10—Rev. 0 to Rev. AAdded ADE7854, ADE7858, and ADE7878..................Universal Reorganized Layout...........................................................Universal Added Table 1, Renumbered Sequentially.....................................1 Added Figure 1, Renumbered Sequentially...................................3 Added Figure 2..................................................................................4 Added Figure 3..................................................................................5 Changes to Specifications Section..................................................7 Changes to Figure 9........................................................................14 Changes to Table 8..........................................................................14 Changes to Typical Performance Characteristics Section.........16 Changes to Figure 22......................................................................18 Changes to the Power Management Section...............................20 Changes to the Theory of Operation Section..............................25 Changes to Figure 31 and Figure 32.............................................27 Change to Equation 28...................................................................47 Changes to Figure 83......................................................................66 Changes to Figure 86......................................................................68 Changes to the Registers List Section...........................................72 Changes to Ordering Guide.. (91)2/10—Revision 0: Initial VersionADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 4 of 96FUNCTIONAL BLOCK DIAGRAMSR E S E TR E F C L K I C L K O U I A I A V A I B I B V B I C I C V C V S C L K/S C LS D AH S DA08510-204Figure 1. ADE7854 Functional Block DiagramADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 5 of 96R E S E TR E F C L K I C L K O U I A I A V A I B I B V B I C I C V C V S C L K/S C LS D AH S DA08510-203Figure 2. ADE7858 Functional Block DiagramADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 6 of 96R E S E TR E F C L K I C L K O U I A I A V A I B I B V B I C I C V C V S C L K/S C LS D AH S DAI N I N 08510-202Figure 3. ADE7868 Functional Block DiagramADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 7 of 96R E S E TR E F C L K I C L K O U I A I A V A I B I B V B I C I C V C V S C L K/S C LS D AH S DAI N I N 08510-201Figure 4. ADE7878 Functional Block DiagramADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 8 of 96SPECIFICATIONSVDD = 3.3 V ± 10%, AGND = DGND = 0 V , on-chip reference, CLKIN = 16.384 MHz, T MIN to T MAX = −40°C to +85°C. Table 2.Parameter 1, 2 Min Typ Max Unit Test Conditions/Comments ACCURACYActive Energy MeasurementActive Energy Measurement Error (per Phase)Total Active Power0.1%Over a dynamic range of 1000 to 1, PGA = 1, 2, 4; integrator off0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;integrator off0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;integrator onFundamental Active Power (ADE7878 Only) 0.1% Over a dynamic range of 1000 to 1, PGA = 1, 2, 4; integrator off 0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;integrator off0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;integrator onPhase Error Between Channels Line frequency = 45 Hz to 65 Hz, HPF on Power Factor (PF) = 0.8 Capacitive ±0.05 Degrees Phase lead 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag 60° AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz, IPx = VPx =±100 mV rmsOutput Frequency Variation 0.01 % DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc Output Frequency Variation 0.01 %Total Active Energy MeasurementBandwidth2 kHz REACTIVE ENERGY MEASUREMENT(ADE7858, ADE7868, AND ADE7878)Reactive Energy Measurement Error(per Phase)Total Active Power 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;integrator off0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;integrator off0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;integrator onFundamental Active Power (ADE7878 Only) 0.1% Over a dynamic range of 1000 to 1, PGA = 1, 2, 4; integrator off 0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;integrator off0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;integrator onPhase Error Between Channels Line frequency = 45 Hz to 65 Hz, HPF on PF = 0.8 Capacitive ±0.05 Degrees Phase lead 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag 60° AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz, IPx = VPx =±100 mV rmsOutput Frequency Variation 0.01 %ADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 9 of 96Parameter 1, 2Min Typ Max Unit Test Conditions/Comments DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc Output Frequency Variation0.01% Total Reactive Energy Measurement Bandwidth2kHzRMS MEASUREMENTSI rms and V rms Measurement Bandwidth2 kHz I rms and V rms Measurement Error (PSM0 Mode)0.1 % Over a dynamic range of 1000 to 1, PGA = 1 MEAN ABSOLUTE VALUE (MAV)MEASUREMENT (ADE7868 AND ADE7878)I mav Measurement Bandwidth (PSM1 Mode)260 Hz I mav Measurement Error (PSM1 Mode) 0.5 % Over a dynamic range of 100 to 1, PGA = 1, 2, 4, 8 ANALOG INPUTSMaximum Signal Levels±500mV peakDifferential inputs between the following pins: IAP and IAN, IBP and IBN, ICP and ICN; single-ended inputs between the following pins: VAP and VN, VBP and VN, VCP and VN Input Impedance (DC)IAP , IAN, IBP , IBN, ICP , ICN, VAP , VBP , and VCP Pins 400 kΩVN Pin130 kΩADC Offset Error±2 mV PGA = 1, uncalibrated error, see the Terminology sectionGain Error±4 % External 1.2 V referenceWAVEFORM SAMPLINGSampling CLKIN/2048, 16.384 MHz/2048 = 8 kSPS Current and Voltage Channels See the Waveform Sampling Mode section Signal-to-Noise Ratio, SNR70 dB PGA = 1 Signal-to-Noise-and-Distortion Ratio, SINAD60 dB PGA = 1Bandwidth (−3 dB)2 kHz TIME INTERVAL BETWEEN PHASESMeasurement Error0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on CF1, CF2, CF3 PULSE OUTPUTSMaximum Output Frequency 8 kHz WTHR = VARTHR = VATHR = PMAX = 33,516,139 Duty Cycle50%If CF1, CF2, or CF3 frequency > 6.25 Hz and CFDEN is even and > 1(1 + 1/CFDEN) × 50% If CF1, CF2, or CF3 frequency > 6.25 Hz andCFDEN is odd and > 1Active Low Pulse Width 80 ms If CF1, CF2, or CF3 frequency < 6.25 Hz Jitter 0.04 % For CF1, CF2, or CF3 frequency = 1 Hz andnominal phase currents are larger than 10% of full scaleREFERENCE INPUT REF IN/OUT Input Voltage Range 1.1 1.3 V Minimum = 1.2 V − 8%; maximum = 1.2 V + 8% Input Capacitance 10 pF ON-CHIP REFERENCE Nominal 1.207 V at the REF IN/OUT pin at T A = 25°C PSM0 and PSM1 Modes Reference Error ±2 mV Output Impedance 1.2 kΩ Temperature Coefficient 10 50 ppm/°C Maximum value across full temperature rangeof −40°C to +85°CADE7854/ADE7858/ADE7868/ADE78781 See the Typical Performance Characteristics section.2 See the Terminology section for a definition of the parameters.Rev. E | Page 10 of 96分销商库存信息:ANALOG-DEVICESADE7878ACPZ ADE7854ACPZ ADE7854ACPZ-RL ADE7858ACPZ-RL ADE7868ACPZ-RL ADE7878ACPZ-RL ADE7858ACPZ ADE7868ACPZ EVAL-ADE7878EBZ。

MRT23-A;MRX108-A;MRT22-A;MRX204-A;MRT23;中文规格书,Datasheet资料

(20.0) .787
(5.0) .197
(0.8) .031 Thk = (0.9) .035
Shaft
Terminal
G24 /
1
6
(3.15) Dia .124
T
Shaft Actuated with Solder Lug Terminals *
Poles & Circuits
108 SP with 2-8 Positions 204 DP with 2-4 Positions 402 4P with 2 Positions
106 106G
SP with 2-6 Positions
Installation
Mounting Torque: Cap Installation Force: Soldering Time & Temperature:
.686Nm (6.08 lb•in) 19.6 ~ 29.4N (4.41 ~ 6.61 lbf) Manual Soldering: See Profile A in Supplement section.
SP with 2-6 Positions Gold Contacts 0.4VA
22 DPDT ON-NONE-ON 23 DPDT ON-OFF-ON
Knobs A Plain Black B Small Color Tipped C Large Color Tipped
Colors
For Plain Knob
No Code
Black
For Color Tipped
A
Black
B
White
C
Red
E
Yellow

BT23 Datasheet说明书

BT23 Datasheet Amp’ed RF Technology, Co., Ltd.BT23 Product Specification11.6mm x 13.5mmDescriptionOur micro-sized Bluetooth module, with integrated antenna, is the smallest form factor available providing a complete RF platform. The BT23 is designed for maximum performance in a minimal space and includes 6 general purpose and ADC/DAC IO lines, several serial interface options, and up to 1.5M bps data throughput.The BT23 is a surface mount PCB module that provides fully embedded, ready to use Bluetooth wireless technology. The reprogrammable flash memory contains embedded firmware for serial cable replacement using the Bluetooth SPP profile. Other popular Bluetooth profiles, such as OBEX, are also available.Customized firmware for peripheral device interaction, power optimization, security, and other proprietary features may be supported and can be ordered pre-loaded and configured . Additional Documentation ● BT HW Design Guide ● BT Getting Started Guide ● abSerial User Guide ● abSerial Reference Guide ● abSerial Configuration GuideFeatures Bluetooth Radio● Fully embedded Bluetooth v2.1 Serial and OBEXProfiles● Class 2 radio● Complete RF ready module ● 128-bit encryption security ● Range up to 25m LOS ● FCC & Bluetooth qualified ● Multipoint mode supportedST Micro ARM Cortex microprocessor up to 72MHz Memory● 256K bytes flash memory ● 48K bytes RAM memory Data Rate● 1.5M bps typical data rate ● EDR supported Serial Interface● UART, up to 2M baud ● Buffered SPI interface ● I2C interface General I/O● 6 general purpose I/O● 4x12-bit A/D input ● 1 DAC output ● 1 LPO input User Interface ● AT command set● Firmware upgrade over UARTTable of Contents1 Software Architecture (4)1.1 Lower Layer Stack (4)1.2 Upper Layer Stack: Amp’ed UP (4)1.3 HCI Interface (4)1.4 AT Command Set: abSerial (4)2 Hardware Specifications (5)2.1 Recommended Operating Conditions (5)2.2 Current Consumption (5)2.3 Selected RF Characteristics (6)2.4 Absolute Maximum Ratings (6)2.5 I/O Operating Characteristics (6)2.6 Pin Assignment (7)2.7 Pin Placement Diagram (Top View) (7)2.8 Layout Drawing, BT23 (8)3 Hardware Block Diagram (8)4 Hardware Design (9)4.1 Module Reflow Installation (9)4.2 GPIO Interface (9)4.3 UART Interface (10)4.4 Reset Circuit (11)4.4.1 External Reset Circuit: (11)4.4.2 Internal Reset Circuit: (11)4.5 External LPO Input Circuit (12)4.6 Apple CP Reference Design (12)5 FCC Regulatory Compliance (14)5.1 Modular Approval, FCC and IC (14)5.2 FCC Label Instructions (14)6 Ordering Information (15)7 Feature Comparison (15)8 Revision History (15)1 Software Architecture1.1 Lower Layer Stack●Full Bluetooth v2.1 enhanced data rate (EDR)●Device power modes: active, sleep and deep sleep●Wake on Bluetooth feature optimized power consumption of host CPU●Authentication and encryption●Encryption key length from 8 to 128 bits●Persistent FLASH memory for BD Address and user parameter storage●ACL (Asynchronous Connection Less) packet types: DM1, DH1, DM3, DH3, DM5, DH5, 2-DH1, 2-DH3, 2-DH5, 3-DH1, 3-DH3, 3-DH5, AUX1●SCO and eSCO (Synchronous Connection Oriented) packet support.●Point to multipoint and scatternet support: 3 master and 7 slave links allowed (10 active linkssimultaneously)●Sniff, and hold modes: fully supported to maximum allowed intervals●Master slave switch, supported during connection and post connection●Dedicated Inquiry Access Code, for improved inquiry scan performance●Dynamic packet selection, channel quality driven data rate to optimize link performance●Bluetooth test modes per Bluetooth v2.1 specification●802.11b/g/n co-existence: AFH●Vendor specific HCI commands to support device configuration and certification test modes1.2 Upper Layer Stack: Amp’ed UP●SPP, OBEX, SDAP, GAP, and DUN protocols●RFComm, SDP, and L2CAP supported●Multipoint with 7 simultaneous slaves1.3 HCI Interface●Bluetooth v2.1 specification compliant●HCI UART transport layer (H4)1.4 AT Command Set: abSerial●Please see abSerial Reference Guide for details2 Hardware SpecificationsGeneral Conditions (V IN= 3.0V and 25°C)2.1 Recommended Operating Conditions2.2 Current Consumption2.3 Selected RF Characteristics2.4 Absolute Maximum Ratings2.5 I/O Operating Characteristics2.6 Pin Assignment2.7 Pin Placement Diagram (Top View)2.8 Layout Drawing, BT23Size: 11.6 mm x 13.5 mm x 2.2 mm (height)3 Hardware Block Diagram4 Hardware DesignAmp’e d RF modules support UART, USB, SPI, and GPIO hardware interfaces. Please note that the usage of these interfaces is dependant upon the firmware that is loaded into the module, and is beyond the scope of this document. The AT command interface uses the main UART by default.Notes●All unused pins should be left floating; do not ground.●All GND pins must be well grounded.●The area around the antenna should be free of any ground planes, power planes, trace routings,or metal for at least 6.5 mm in all directions.●Traces should not be routed underneath the module.4.1 Module Reflow InstallationThe BT23 is a surface mount Bluetooth module supplied on a 14 pin, 6-layer PCB. The final assembly recommended reflow profiles are:For non Pb-free applications, Sn63Pb37 solder is recommended.●Maximum peak temperature of 208° - 210°C (below 220°C).●Maximum rise and fall slope after liquidous of < 2°C/second.●Maximum rise and fall slope after liquidous of < 2°C/second.●Maximum time at liquidous of 50 – 90 seconds.For RoHS/Pb-free applications, Sn96.5/Ag3.0/Cu0.5 solder is recommended.●Maximum peak temperature of 230° - 240°C (below 250°C).●Maximum rise and fall slope after liquidous of < 2°C/second.●Maximum rise and fall slope after liquidous of < 3°C/second.●Maximum time at liquidous of 40 – 80 seconds.4.2 GPIO InterfaceAll GPIOs are capable of sinking and sourcing 4mA of I/O current. GPIO [1] to GPIO [6] are internally pulled down with 100KΩ (nominal) resistors.4.3 UART InterfaceThe UART is compatible with the 16550 industry standard. Four signals are provided with the UART interface. The TXD and RXD pins are used for data while the CTS and RTS pins are used for flow control.Typical RS232 CircuitConnection to Host Device4.4 Reset CircuitTwo types of system reset circuits are detailed below.4.4.1 External Reset Circuit:Note: R PU ranges from 30K ohm to 50K ohm internally.4.4.2 Internal Reset Circuit:Notes:- R PU ranges from 30K ohm to 50K ohm internally.- R RST should be from 1K ohm to 10K ohm4.5 External LPO Input CircuitAn optional low power oscillator input may be added to allow deep sleep and sniff modes.4.6 Apple iOS CP Reference DesignPart 1. BT moduleLPO Parameters:Frequency: 32.768 KHz Tolerance: 150 ppm Voltage LevelsLow: 0.9 V High: 1.8 VInput Capacitance: 2.5 pF maximumConfigurations:See configuration guide: UseExtLPO AllowSniffNote: PT30 located on the bottom of the modulePart 2. Co-processorPart 3. Power switch5 FCC Regulatory ComplianceThis module has been tested and found to comply with the FCC Part15 and IC RSS-210 rules. These limits are designed to provide reasonable protection against harmful interference in approved installations. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.Modifications or changes to this equipment not expressly approved by Amp’ed RF Technology may void the user’s authority to operate this equipment.5.1 Modular Approval, FCC and ICFCC ID: X3ZBTMOD2IC: 8828A-MOD2In accordance with FCC Part 15, the BT23 is listed above as a Limited ModularTransmitter device.5.2 FCC Label InstructionsThe outside of final products that contain a BT23 device must display a label referring to the enclosed module. This exterior label can use wording such as the following:Contains Transmitter ModuleFCC ID: X3ZBTMOD2IC: 8828A-MOD2Any similar wording that expresses the same meaning may be used.6 Ordering Information7 Feature Comparison8 Revision History。

PVD2352N;中文规格书,Datasheet资料

Data Sheet No. PD10053 revISeries PVD33N & PbFMicroelectronic Power ICHEXFET ® Power MOSFET Photovoltaic RelaySingle-Pole, Normally-Open0-300V DC, 240mAGeneral DescriptionThe PVD33 Series DC Relay (PVD) is a single-pole,normally open, solid-state replacement for electromechanical relays used for general purpose switching of analog signals. It utilizes International Rectifier’s HEXFET power MOSFET as the output switch, driven by an integrated circuit photovoltaic generator of novel construction. The output switch is controlled by radiation from a GaAlAs light emitting diode (LED), which is optically isolated from the photovoltaic generator.The PVD33 Series overcomes the limitations of both conventional electromechanical and reed relays by offering the solid state advantages of long life, fast operating speed, low pick up power, bounce-free operation, low thermal offset voltages and miniature package. These advantages allow product improvement and design innovations in many applications such as process control, multiplexing,automatic test equipment and data acquisition.The PVD33 can switch analog signals from thermocouple level to 300 Volts peak DC. Signal frequencies into the RF range are easily controlled and switching rates up to 500Hz are achievable. The extremely small thermally generated offset voltages allow increased measurement accuracies.These relays are packaged in 8-pin, molded DIP packages and available with either thru-hole or surface-mount (“gull-wing”) leads, in plastic shipping tubes.Applications§Process Control §Data Acquisition §Test Equipment§Multiplexing and ScanningFeatures§ Bounce-Free Operation §1010 Off-State Resistance §1,000 V/µsec dv/dt § 5 mA Input Sensitivity §4,000 V RMS I/O Isolation §Solid-State Reliability §UL Recognized §ESD Tolerance:4000V Human Body Model 500V Machine Model(HEXFET is the registered trademark for International Rectifier Power MOSFETs)Part IdentificationPVD2352N & PbF PVD3354N & PbFPVD2352NS & PbF PVD3354NS & PbFsurface-mount (gull-wing) 1thru-holeOBSOLETESeries PVD33N & PbF 2Electrical Specifications (-40°C ≤ T A ≤ +85°C unless otherwise specified )International Rectifier does not recommend the use of this product in aerospace, avionics, military or life support ers of this International Rectifier product in such applications assume all risks of such use and indemnify International Rectifier against all damages resulting from such use.Series PVD33N & PbF3Figure 1. Current Derating CurvesFigure 2. Typical Control Current RequirementsFigure 4. Typical On-ResistanceR D (o n ) (N o r m a l i z e d25o C )I LED (mA)M a x . L o a d C u r r e n t (m A )Ambient Temperature (°C)5 mA Control l D = 50 mASeries PVD33N & PbF 4I D O f f /I D O f f 25°CFigure 5. Normalized Off-State LeakageFigure 6. Input Characteristics(Current Controlled)Figure 7.Typical Delay TimesFigure 8. Delay Time DefinitionsLED Forward Voltage Drop (Volts DC)I n p u t C u r r e n t (m A )Ambient Temperature (°C)Series PVD33N & PbFWiring DiagramIR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105Data and specifications subject to change without notice. 2/2008 6分销商库存信息: IRPVD2352N。

S320;中文规格书,Datasheet资料

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
1000 100 10 1 0.1 0.01 1E-3 20
T =100 oC A
T =75 oC A
T =25 oC A
40
60
80
100
120
Percent of Rated Peak Voltage, [%]
Reverse Current, I [uA] R
Instantaneous Forward Current, I [A] F
Figure 1. DC Forward Current Derating Curve

AO4850;中文规格书,Datasheet资料

SymbolTyp Max t ≤ 10s 5062.5Steady-State 82110Steady-StateR θJL4150°C/WUnits R θJA °C/W °C/W Thermal Characteristics Maximum Junction-to-Ambient A Maximum Junction-to-Ambient A Maximum Junction-to-Lead CParameterAO4850SymbolMin TypMaxUnits BV DSS 75V 1T J =55°C5I GSS 100nA V GS(th)1 2.33V I D(ON)15A 105130T J =125°C158195126165m Ωg FS 10S V SD 0.771V I S2.5A C iss 290380pF C oss 54pF C rss 24pF R g2.43.5ΩQ g (10V) 5.147nC Q g (4.5V) 2.34nC Q gs 0.97nC Q gd 1.18nC t D(on)4ns t r 3.4ns t D(off)14.4ns t f 2.4ns t rr 30.245ns Q rr21.5nCTHIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE.Body Diode Reverse Recovery TimeBody Diode Reverse Recovery Charge I F =3.1A, dI/dt=100A/µsDrain-Source Breakdown Voltage On state drain currentI D =10mA, V GS =0V V GS =10V, V DS =5V V GS =10V, I D =3.1AReverse Transfer Capacitance I F =3.1A, dI/dt=100A/µsElectrical Characteristics (T J =25°C unless otherwise noted)STATIC PARAMETERS Parameter Conditions I DSS µA Gate Threshold Voltage V DS =V GS I D =250µA V DS =75V, V GS =0VV DS =0V, V GS = ±25V Zero Gate Voltage Drain Current Gate-Body leakage current R DS(ON)Static Drain-Source On-ResistanceForward TransconductanceDiode Forward Voltagem ΩV GS =4.5V, I D =2AI S =1A,V GS =0V V DS =5V, I D =3.1ATotal Gate Charge Gate Source Charge Gate resistanceV GS =0V, V DS =0V, f=1MHzTurn-On Rise Time Turn-Off DelayTime V GS =10V, V DS =30V, R L =9.7Ω, R GEN =3ΩTurn-Off Fall TimeMaximum Body-Diode Continuous CurrentInput Capacitance Output Capacitance Turn-On DelayTime DYNAMIC PARAMETERS V GS =10V, V DS =30V, I D =3.1ATotal Gate Charge Gate Drain Charge V GS =0V, V DS =30V, f=1MHz SWITCHING PARAMETERS A: The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The value in any given application depends on the user's specific board design. The current rating is based on the t ≤10s thermal resistance rating.B: Repetitive rating, pulse width limited by junction temperature.C. The R θJA is the sum of the thermal impedence from junction to lead R θJL and lead to ambient.D. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max.E. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The SOA curve provides a single pulse rating. Rev 1: May. 2007分销商库存信息: AOSAO4850。

74HC138DR2G;74HC138DTR2G;中文规格书,Datasheet资料

16 1
16 1
MARKING DIAGRAMS
16
SOIC−16 D SUFFIX CASE 751B
HC138G AWLYWW
1
TSSOP−16 DT SUFFIX CASE 948F
16
HC 138 ALYW G
G
1
HC138 = Device Code
A
= Assembly Location
Standard No. 7A
• ESD Performance: HBM > 2000 V; Machine Model > 200 V • Chip Complexity: 100 FETs or 29 Equivalent Gates • These are Pb−Free Devices

Features
• Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC
level (e.g., either GND or VCC). Unused outputs must be left open.
TL Lead Temperature, 1 mm from Case for 10 SecSSOP Package)

DS1603;中文规格书,Datasheet资料

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: /errata .FEATURES§ Two 32-bit counters keep track of real -time and elapsed time§ Counters keep track of seconds for over 125 years§ Battery powered counter counts seconds from the time battery is attached until V BAT is less than 2.5V§ V CC powered counter counts seconds while V CC is above V TP and retains the count in the absence of V CC under battery backup power § Clear function resets selected counter to 0 § Read/write serial port affords low pin count § Powered internally by a lithium energy cell that provides over 10 years of operation§ One-byte protocol defines read/write, counter address and software clear function§ Self-contained crystal provides an accuracy of ±2 min per month§ Operating temperature range of 0°C to +70°C § Low-profile SIP module§ Underwriters Laboratory (UL) recognized PIN ASSIGNMENTPIN DESCRIPTIONRST- Reset CLK - ClockDQ - Data Input/Output GND - Ground V CC - +5VOSC - 1Hz Oscillator Output NC- No ConnectDESCRIPTIONThe DS1603 is a real -time clock/elapsed time counter designed to count seconds when V CC power is applied and continually count seconds under battery backup power with an additional counter regardless of the condition of V CC . The continuous counter can be used to derive time of day, week, month, and year by using a software algorithm. The V CC powered counter will automatically record the amount of time that V CC power is applied. This function is particularly useful in determining the operational time of equipment in which the DS1603 is used. Alternatively, this counter can also be used under software control to record real -time events. Communication to and from the DS1603 takes place via a 3-wire serial port. A 1-byte protocol selects read/ write functions, counter clear functions and oscillator trim. The device contains a 32.768kHz crystal that will keep track of time to within ±2 min/mo. An internal lithium energy source contains enough energy to power the continuous seconds counter for over 10 years.OPERATIONThe main elements of the DS1603 are shown in Figure 1. As shown, communications to and from the elapsed time counter occur over a 3-wire serial port. The port is activated by driving RST to a high state.V CC RST DQ NC CLK OSC GND DS1603Elapsed Time Counter Moduleselect, register clear, and oscillator trim information. Each bit is serially input on the rising edge of the clock input. After the first eight clock cycles have loaded the protocol register with a valid protocol additional clocks will output data for a read or input data for a w rite. V CC must be present to access the DS1603. If V CC < V TP, the DS1603 will switch to internal power and disable the serial port to conserve energy. When running off of the internal power supply, only the continuous counter will continue to count and the counter powered by V CC will stop, but retain the count, which had accumulated when V CC power was lost. The 32-bit V CC counter is gated by V CC and the internal 1Hz signal.PROTOCOL REGISTERThe protocol bit definition is shown in Figure 2. Valid protocols and the resulting actions are shown in Table 1. Each data transfer to the protocol register designates what action is to occur. As defined, the MSB (bit 7 which is designated ACC) selects the 32-bit continuous counter for access. If ACC is a logical 1 the continuous counter is selected and the 32 clock cycles that follow the protocol will either read or write this counter. If the counter is being read, the contents will be latched into a different register at the end of protocol and the latched contents will be read out on the next 32 clock cycles. This avoids reading garbled data if the counter is clocked by the oscillator during a read. Similarly, if the counter is to be written, the data is buffered in a register and all 32 bits are jammed into the counter simultaneously on the rising edge of the 32nd clock. The next bit (bit 6 which is designated AVC) selects the 32–bit V CC active counter for access. If AVC is a logical 1 this counter is selected and the 32 clock cycles that follow will either read or write this counter. If both bit 7 and bit 6 are written to a logic high, all clock cycles beyond the protocol are ignored and bit 5, 4, and 3 are loaded into the oscillator trim register. A value of binary 3 (011) will give a clock accuracy of ±120 seconds per month at +25°C. Increasing the binary number towards 7 will cause the real-time clock to run faster. Conversely, lowering the binary number towards 0 will cause the clock to run slower. Binary 000 will stop the oscillator completely. This feature can be used to conserve battery life during storage. In this mode the internal power supply current is reduced to 100 nA maximum. In applications where oscillator trimming is not practical or not needed, a default setting of 011 is recommended. Bit 2 of protocol (designated CCC) is used to clear the continuous counter. When set to logic 1, the continuous counter will reset to 0 when RST is taken low. Bit 1 of protocol (designated CVC) is used to clear the V CC active counter. When set to logical 1, the V CC active counter will reset to 0 when RST is taken low. Both counters can be reset simultaneously by setting CCC and CVC both to a logical 1. Bit 0 of the protocol (designated RD) determines whether the 32 clocks to follow w ill write a counter or read a counter. When RD is set to a logical 0 a write action will follow when RD is set to a logical 1 a read action will follow. When sending the protocol, 8 bits should always be sent. Sending less than 8 bits can produce erroneous results. If clearing the counters or trimming the oscillator, the data transfer can be terminated after the 8-bit protocol is sent. However, when reading or writing the counters, 32 clock cycles should always follow the protocol.RESET AND CLOCK CONTROLAll data transfers are initiated by driving the RST input high. The RST input has two functions. First, RST turns on the serial port logic, which allows access to the protocol register for the protocol data entry. Second, the RST signal provides a method of terminating the protocol transfer or the 32-bit counter transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For write inputs, data must be valid during the rising edge of the clock. Data bits are output on the falling edge of the clock when data is being read. All data transfers terminate if the RST input is transitioned low and the DQ pin goes to a high-impedance state. RST should only be transitioned low while the clock is high to avoid disturbing the last bit of data. All data transfers must consist of 8 bits when transferring protocol only or 8 + 32 bits when reading or writing either counter. Data tran sfer is illustrated in Figure 3.DATA INPUTFollowing the 8-bit protocol that inputs write mode, 32 bits of data are written to the selected counter on the rising edge of the next 32 CLK cycles. After 32 bits have been entered any additional CLK cycles will be ignored until RST is transitioned low to end data transfer and then high again to begin new data transfer.DATA OUTPUTFollowing the eight CLK cycles that input read mode protocol, 32 bits of data will be output from the selected counter on the next 32 CLK cycles. The first data bit to be transmitted from the selected 32-bit counter occurs on the falling edge after the last bit of protocol is written. When transmitting data from the selected 32-bit counter, RST must remain at high level as a transition to low level will terminate data transfer. Data is driven out the DQ pin as long as CLK is low. When CLK is high the DQ pin is tristated. OSCILLATOR OUTPUTPin 6 of the DS1603 module is a 1Hz output signal. This signal is present only when V CC is applied and greater than the internal power supply. However, the output is guaranteed to meet TTL requirement only while V CC is within normal limits. This output can be used as a 1-second interrupt or time tick needed in some applications.INTERNAL POWERThe internal battery of the DS1603 module provides 35mAh and will run the elapsed time counter for over 10 years in the absence of power.PIN DESCRIPTIONSV CC, GND – DC power is provided to the device on these pins. V CC is the +5V input. When 5V is applied within normal limits, the device is fully accessible and data can be written and read. When a 3V battery is connected to the device and V CC is below 1.25 x V BAT, reads and writes are inhibited. As V CC falls below V BAT the continuous counter is switched over to the internal battery.CLK (Serial Clock Input) – CLK is used to synchronize data movement on the serial interface.DQ (Data Input/Output) – The DQ pin is the bi-directional data pin for the 3-wire interface.RST (Reset) – The reset signal must be asserted high during a read or a write.OSC (One Hertz Output Signal) – This signal is only present when Vcc is at a valid level and the oscillator is enabled.Figure 1. ELAPSED TIME COUNTER BLOCK DIAGRAMFigure 2. PROTOCOL BIT MAP7 6 5 4 3 2 1 0ACC AVC OSC2 OSC1 OSC0 CCC CVC RDTable 1. VALID PROTOCOLSPROTOCOLACTIONACC AVC OSC2 OSC1 OSC0 CCC CVC RDFUNCTION ReadContinuous Counter 1 0 X X X X X 1Output continuouscounter on the 32 clocksfollowing protocol.Oscillator trim registeris not updated. Countersare not reset.WriteContinuous Counter 1 0 X X X X X 0Input data to continuouscounter on the 32 clocksfollowing protocol.Oscillator trim registeris not updated. Countersare not reset.Read V CCActive Counter 0 1 X X X X X 1Output V CC activecounter on the 32 clocksfollowing protocol,oscillator trim registeris not updated. Countersare not reset.Write V CCActive Counter 0 1 X X X X X 0Input data to continuouscounter on the 32 clocksfollowing protocol.Oscillator trim registeris not updated. Countersare not reset.ClearContinuous Counter 0 0 X X X 1 X XResets the continuouscounter to all zeros atthe end of protocol.Oscillator trim registeris not updated.Clear V CCActive Counter 0 0 X X X X 1 XResets the V CC activecounter to all zeros atthe end of protocol.Oscillator trim registeris not updated.Set Oscillator Trim Bits 1 1 A B C X X 0Sets the oscillator trimregister to a value ofABC. Counters areunaffected.X = Don’t CareFigure 3. DATA TRANSFERTIMING DIAGRAM: READ/WRITE DATA TRANSFERNote: t CL, t CH, t R, and t F apply to both read and write data transfer.ABSOLUTE MAXIMUM RATINGSVoltage Range on Any Pin Relative to Ground -0.3V to +7.0VOperating Temperature Range 0°C to +70°CStorage Temperature Range -40°C to +70°CSoldering Temperature Range See IPC/JEDEC J-STD-020A (See Note 11)This is a stress rating only and functional operation of the device at these or any other conditions beyond t h ose indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.RECOMMENDED DC OPERATING CONDITIONS (0°C to +70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage V CC 4.5 5.0 5.5 V 1 Logic 1 Input V IH 2.0 V CC + 0.3 V 1 Logic 0 Input V IL-0.3 0.8 V 1DC ELECTRICAL CHARACTERISTICS (0°C to +70°C; V CC = 5V ±10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage I LI-1 +1 µAI/O Leakage I LO-1 +1 µALogic 1 Output V OH 2.4 V 2 Logic 0 Output V OL0.4 V 3 Active Supply Current I CC 1 mA 4 Timekeeping Current I CC150 µA 5 Battery Trip Point V TP 3.0 4.5 V 9 CAPACITANCE (T A = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C I 5 pFI/O Capacitance C I/O10 pF(T A = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Datat DR10 years 10 Retention TimeNOTES:1) All voltages are referenced to ground.2) Logic 1 voltages are specified at a source current of 1mA.3) Logic 0 voltages are specified at a sink current of 4mA.4) I CC is specified with the DQ pin open.5) I CC1 is specified with V CC at 5.0V and RST = GND.6) Measured at V IH= 2.0V or V IL = 0.8V.7) Measured at V OH = 2.4V or V OL - 0.4V.8) Load capacitance = 50pF.9) Battery trip point is the point at which the V CC powered counter and the serial port stops operation.The battery trip point drops below the minimum once the internal lithium energy cell is exhausted. 10) The expected t D R is defined as accumulative time in the absence of V CC with the clock oscillatorrunning.11) Real-time clock modules can be successfully processed through conventional wave-solderingtechniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used.DS1603DS1603 7-PIN MODULEPKG7-PIN DIM MIN MAX A IN. MM 0.830 21.08 0.850 21.59 B IN. MM 0.650 16.51 0.670 17.02 C IN. MM 0.310 7.87 0.330 8.38 D IN. MM 0.015 0.38 0.030 0.76 E IN. MM 0.110 2.79 0.140 3.56 F IN. MM 0.015 0.38 0.021 0.53 G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.105 2.67 0.135 3.43 J IN. MM 0.360 9.14 0.390 9.91分销商库存信息: MAXIMDS1603。

SGH23N60UFDTU;中文规格书,Datasheet资料

SGH23N60UFDSGH23N60UFDUltra-Fast IGBTGeneral DescriptionFairchild's Insulated Gate Bipolar Transistor(IGBT) UFDseries provides low conduction and switching losses.UFD series is designed for the applications such as motorcontrol and general inverters where High Speed Switchingis required.ApplicationAC & DC Motor controls, General Purpose Inverters, Robotics, Servo ControlsSGH23N60UFD Electrical Characteristics of IGBT T C = 25°C unless otherwise notedElectrical Characteristics of DIODE TC = 25°C unless otherwise notedSymbol Parameter Test Conditions Min.Typ.Max.UnitsOff CharacteristicsBV CES Collector-Emitter Breakdown Voltage V GE = 0V, I C = 250uA600----V∆B VCES/∆T J Temperature Coeff. of BreakdownVoltageV GE = 0V, I C = 1mA--0.6--V/°CI CES Collector Cut-Off Current V CE = V CES, V GE = 0V----250uA I GES G-E Leakage Current V GE = V GES, V CE = 0V ----± 100nAOn CharacteristicsV GE(th)G-E Threshold Voltage I C = 12mA, V CE = V GE 3.5 4.5 6.5VV CE(sat)Collector to EmitterSaturation VoltageI C = 12A, V GE = 15V-- 2.1 2.6VI C = 23A, V GE = 15V-- 2.6--VDynamic CharacteristicsC ies Input CapacitanceV CE = 30V, V GE = 0V,f = 1MHz --720--pFC oes Output Capacitance--100--pF C res Reverse Transfer Capacitance--25--pFSwitching Characteristicst d(on)Turn-On Delay TimeV CC = 300 V, I C = 12A,R G = 23Ω, V GE = 15V,Inductive Load, T C = 25°C --17--nst r Rise Time--27--ns t d(off)Turn-Off Delay Time--60130ns t f Fall Time--70150ns E on Turn-On Switching Loss--115--uJ E off Turn-Off Switching Loss--135--uJ E ts TotalSwitchingLoss--250400uJt d(on)Turn-On Delay TimeV CC = 300 V, I C = 12A,R G = 23Ω, V GE = 15V,Inductive Load, T C = 125°C --23--nst r Rise Time--32--ns t d(off)Turn-Off Delay Time--100200ns t f Fall Time--220250ns E on Turn-On Switching Loss--205--uJ E off Turn-Off Switching Loss--320--uJ E ts TotalSwitchingLoss--525800uJQ g Total Gate ChargeV CE = 300 V, I C = 12A,V GE = 15V --4980nCQ ge Gate-Emitter Charge--1117nC Q gc Gate-Collector Charge--1422nC L e Internal Emitter Inductance Measured 5mm from PKG--14--nHSymbol Parameter Test Conditions Min.Typ.Max.UnitsV FM Diode Forward Voltage I F = 12A T C = 25°C-- 1.4 1.7V T C = 100°C-- 1.3--t rr Diode Reverse Recovery TimeI F = 12A,di/dt = 200A/us T C = 25°C--4260ns T C = 100°C--80--I rr Diode Peak Reverse RecoveryCurrentT C = 25°C-- 3.5 6.0AT C = 100°C-- 5.6--Q rr Diode Reverse Recovery Charge T C = 25°C--80180nC T C = 100°C--220--SGH23N60UFDSGH23N60UFDACEx™Bottomless™CoolFET™CROSSVOLT™DOME™E2CMOS™EnSigna™FACT™FACT Quiet Series™FAST®FASTr™GlobalOptoisolator™GTO™HiSeC™ISOPLANAR™MICROWIRE™OPTOLOGIC™OPTOPLANAR™POP™PowerTrench®QFET™QS™QT Optoelectronics™Quiet Series™SuperSOT™-3SuperSOT™-6SuperSOT™-8SyncFET™TinyLogic™UHC™VCX™TRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL.As used herein:1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONSDefinition of TermsDatasheet Identification Product Status DefinitionAdvance Information Formative or InDesign This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.Preliminary First Production This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign.No Identification Needed Full Production This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.分销商库存信息: FAIRCHILDSGH23N60UFDTU。

PZU5.1BA,115;PZU24BA,115;PZU6.2B2A,115;PZU7.5B3A,115;PZU3.9B1A,115;中文规格书,Datasheet资料

1.Product proﬁle1.1General descriptionGeneral-purpose Zener diodes in a SOD323(SC-76) very small Surface-Mounted Device (SMD) plastic package.1.2Features1.3ApplicationsI General regulation functions1.4Quick reference data[1]Pulse test: t p ≤300µs;δ≤0.02.[2]t p =100µs; square wave; T j =25°C prior to surge[3]Device mounted on an FR4Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.PZUxBA seriesSingle Zener diodesRev. 01 — 19 September 2008Product data sheetI Non-repetitive peak reverse power dissipation: P ZSM ≤40WI Low reverse current I R range I Total power dissipation: P tot ≤320mW I Small plastic package suitable for surface-mounted design I T olerance series:B:approximately ±5%;B1,B2,B3:approximately ±2%I AEC-Q101 qualiﬁedI Wide working voltage range:nominal 2.4V to 36V (E24range)Table 1.Quick reference data Symbol Parameter Conditions Min Typ Max Unit V F forward voltageI F =100mA[1]-- 1.1V P ZSM non-repetitive peak reverse power dissipation [2]--40W P tottotal power dissipationT amb ≤25°C [3]--320mW2.Pinning information[1]The marking bar indicates the cathode.3.Ordering information[1]The series consists of 97types with nominal working voltages from 2.4V to 36V .[2]/DG: halogen-freeTable 2.PinningPin Description Simpliﬁed outlineGraphic symbol1cathode [1]2anode21006aaa15221Table 3.Ordering informationType numberPackage NameDescriptionVersion PZU2.4BA to PZU36BA [1]SC-76plastic surface-mounted package; 2leadsSOD323PZU2.4BA/DG to PZU36BA/DG [1][2]4.MarkingTable 4.Marking codesType number[1]Marking code Type number[1]Marking codeB B1B2B3B B1B2B3PZU2.4*A X8---PZU2.4*A/DG Y8---PZU2.7*A X9XA XB-PZU2.7*A/DG Y9YA YB-PZU3.0*A XT XU XV-PZU3.0*A/DG YT YU YV-PZU3.3*A XW XX XY-PZU3.3*A/DG YW YX YY-PZU3.6*A XZ MC MD-PZU3.6*A/DG YZ NC ND-PZU3.9*A ME MF MG-PZU3.9*A/DG NE NF NG-PZU4.3*A MM MN MP MR PZU4.3*A/DG NM NN NP NRPZU4.7*A MS MT MU MV PZU4.7*A/DG NS NT NU NVPZU5.1*A MW MX MY MZ PZU5.1*A/DG NW NX NY NZPZU5.6*A LF LG LH LK PZU5.6*A/DG RF RG RH RKPZU6.2*A LL LM LN LP PZU6.2*A/DG RL RM RN RPPZU6.8*A LR LS LT LU PZU6.8*A/DG RR RS RT RUPZU7.5*A LV LW LX L Y PZU7.5*A/DG RV RW RX RYPZU8.2*A LZ CR CS CT PZU8.2*A/DG RZ ER ES ETPZU9.1*A CU CV CW CX PZU9.1*A/DG EU EV EW EXPZU10*A VA VB VC VD PZU10*A/DG WA WB WC WDPZU11*A VE VF VG VH PZU11*A/DG WE WF WG WHPZU12*A VK VL VM VN PZU12*A/DG WK WL WM WNPZU13*A VP VR VS VT PZU13*A/DG WP WR WS WTPZU14*A--VU-PZU14*A/DG--WU-PZU15*A VV VW VX VY PZU15*A/DG WV WW WX WYPZU16*A VZ X1X2X3PZU16*A/DG WZ Y1Y2Y3PZU18*A X4X5X6X7PZU18*A/DG Y4Y5Y6Y7PZU20*A XC XD XE XF PZU20*A/DG YC YD YE YFPZU22*A XG XH XK XL PZU22*A/DG YG YH YK YLPZU24*A XM XN XP XR PZU24*A/DG YM YN YP YRPZU27*A XS---PZU27*A/DG YS---PZU30*A MH---PZU30*A/DG NH---PZU33*A MK---PZU33*A/DG NK---PZU36*A ML---PZU36*A/DG NL---[1]* = B: tolerance series B, approximately±5%* = B1, B2, B3: tolerance series B1, B2, B3: approximately±2%5.Limiting values[1]t p =100µs; square wave; T j =25°C prior to surge[2]Device mounted on an FR4PCB, single-sided copper, tin-plated and standard footprint.[3]Device mounted on an FR4PCB, single-sided copper, tin-plated, mounting pad for cathode 1cm 2.6.Thermal characteristics[1]Device mounted on an FR4PCB, single-sided copper, tin-plated and standard footprint.[2]Device mounted on an FR4PCB, single-sided copper, tin-plated, mounting pad for cathode 1cm 2.[3]Soldering point of cathode tab.7.Characteristics[1]Pulse test: t p ≤300µs;δ≤0.02.Table 5.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max Unit I F forward current-200mAI ZSMnon-repetitive peak reverse current[1]-see Table 8and 9P ZSM non-repetitive peak reverse power dissipation [1]-40W P tot total power dissipation T amb ≤25°C[2]-320mW [3]-490mW T j junction temperature -150°C T amb ambient temperature −55+150°C T stgstorage temperature−65+150°CTable 6.Thermal characteristics Symbol ParameterConditions Min Typ Max Unit R th(j-a)thermal resistance from junction to ambient in free air[1]--390K/W [2]--255K/W R th(j-sp)thermal resistance from junction to solder point[3]--55K/WTable 7.CharacteristicsT j =25°C unless otherwise speciﬁed.Symbol Parameter ConditionsMin Typ Max Unit V Fforward voltage[1]I F =10mA --0.9V I F =100mA--1.1V[1]f =1MHz; V R =0V[2]t p =100µs; square wave; T j =25°C prior to surgeTable 8.Characteristics per type; PZU2.4BA to PZU5.6B3A and PZU2.4BA/DG to PZU5.6B3A/DG T j =25°C unless otherwise speciﬁed.PZUxBASelWorking voltage V Z (V)Differential resistance r dif (Ω)Reverse currentI R (µA)Temperature coefﬁcient S Z (mV/K)Diode capacitance C d (pF)[1]Non-repetitivepeak reverse current I ZSM (A)[2]I Z =5mA I Z =0.5mA I Z =5mA I Z =5mA MinMax Max Max Max V R (V)Typ Max Max 2.4B 2.3 2.61000100501−1.645082.7B 2.5 2.91000100201−2.04408B1 2.5 2.75B22.65 2.93.0B 2.8 3.2100095101−2.14258B1 2.8 3.05B22.953.23.3B 3.1 3.510009551−2.44108B1 3.1 3.35B23.25 3.53.6B 3.4 3.810009051−2.43908B1 3.4 3.65B23.55 3.83.9B 3.7 4.110009031−2.53708B1 3.7 3.97B23.874.104.3B 4.01 4.4810009031−2.53508B1 4.01 4.21B2 4.15 4.34B34.28 4.484.7B 4.42 4.98008021−1.43258B1 4.42 4.61B2 4.55 4.75B34.69 4.95.1B 4.84 5.37250602 1.50.3300 5.5B1 4.84 5.04B2 4.98 5.2B35.14 5.375.6B 5.31 5.92100401 2.5 1.9275 5.5B1 5.31 5.55B2 5.49 5.73B35.675.92Table 9.Characteristics per type; PZU6.2BA to PZU36BA and PZU6.2BA/DG to PZU36BA/DG T j=25°C unless otherwise speciﬁed.PZUxBA Sel WorkingvoltageV Z(V)Differential resistancer dif(Ω)ReversecurrentI R(nA)TemperaturecoefﬁcientS Z(mV/K)DiodecapacitanceC d(pF)[1]Non-repetitivepeak reversecurrentI ZSM(A)[2]I Z=5mA I Z=0.5mA I Z=5mA I Z=5mAMin Max Max Max Max V R(V)Typ Max Max 6.2B 5.86 6.5380305003 2.7250 5.5B1 5.86 6.12B2 6.06 6.33B3 6.26 6.536.8B 6.477.146020500 3.5 3.4215 5.5B1 6.47 6.73B2 6.65 6.93B3 6.867.147.5B7.067.8460105004 4.0170 3.5B17.067.36B27.287.60B37.527.848.2B7.768.6460105005 4.6150 3.5B17.768.1B28.028.36B38.288.649.1B8.569.5560105006 5.5120 3.5B18.568.93B28.859.23B39.159.5510B9.4510.5560101007 6.4110 3.5 B19.459.87B29.7710.21B310.1110.5511B10.4411.56601010087.41083 B110.4410.88B210.7611.22B311.111.5612B11.4212.6801010098.41053 B111.4211.9B211.7412.24B312.0812.613B12.4713.968010100109.4103 2.5 B112.4713.03B212.9113.49B313.3713.96[1]f =1MHz; V R =0V[2]t p =100µs; square wave; T j =25°C prior to surge14B213.7014.3080101001110.4101215B 13.8415.528015501111.4992B113.8414.46B214.3414.98B314.8515.5216B 15.3717.098020501212.497 1.5B115.3716.01B215.8516.51B316.3517.0918B 16.9419.038020501314.493 1.5B116.9417.7B217.5618.35B318.2119.0320B 18.8621.0810020501516.488 1.5B118.8619.7B219.5220.39B320.2121.0822B 20.8823.1710025501718.484 1.3B120.8821.77B221.5422.47B322.2323.1724B 22.9325.5712030501920.480 1.3B122.9323.96B223.7224.78B324.5425.5727B 25.128.915040502123.473130B 283220040502326.666133B 313525*********.7600.936B343830060502733.0590.8Table 9.Characteristics per type; PZU6.2BA to PZU36BA and PZU6.2BA/DG to PZU36BA/DG …continued T j =25°C unless otherwise speciﬁed.PZUxBASelWorking voltage V Z (V)Differential resistance r dif (Ω)Reverse currentI R (nA)Temperature coefﬁcient S Z (mV/K)Diode capacitance C d (pF)[1]Non-repetitivepeak reverse current I ZSM (A)[2]I Z =5mA I Z =0.5mA I Z =5mA I Z =5mA MinMaxMaxMax Max V R (V)Typ Max MaxT j =25°C (prior to surge)T j =25°CFig 1.Non-repetitive peak reverse power dissipation as a function of pulse duration; maximum valuesFig 2.Forward current as a function of forward voltage; typical valuesT j =25°C to 150°C V Z =2.4V to 4.3VT j =25°C to 150°C V Z =4.7V to 12VFig 3.Temperature coefﬁcient as a function of working current; typical valuesFig 4.Temperature coefﬁcient as a function of working current; typical values006aab21510210103P ZSM (W)1t p (s)10−410−210−3V F (V)0.610.8mbg781100200300I F (mA)00600−2−3−1mgl2732040I Z (mA)S Z (mV/K)4.33.93.63.33.02.42.702016100−55mgl2744812I Z (mA)S Z (mV/K)4.71211109.18.27.56.86.25.65.1T j =25°C V Z =2.4V to 4.3VT j =25°C V Z =4.7V to 12VFig 5.Working current as a function of working voltage; typical valuesFig 6.Working current as a function of working voltage; typical valuesT j =25°C V Z =13V to 36VFig 7.Working current as a function of working voltage; typical values006aab24610−110−2101102I Z (mA)10−3V Z (V)054231V Z(nom) (V) = 2.42.73.03.33.63.94.3006aab24710−110−2101102I Z (mA)10−3V Z (V)01410128624V Z(nom) (V) = 4.75.15.66.26.87.58.29.1101112006aab24810−110−2101102I Z (mA)10−3V Z (V)10403020V Z(nom) (V) = 1318202224273033361415168.Test information8.1Quality informationThis product has been qualiﬁed in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualiﬁcation for discrete semiconductors , and is suitable for use in automotive applications.9.Package outline10.Packing information[1]For further information and the availability of packing methods, see Section 13.Fig 8.Package outline SOD323(SC-76)03-12-17Dimensions in mm0.250.100.450.152.72.3 1.81.60.400.251.10.81.351.1512Table 10.Packing methodsThe indicated -xxx are the last three digits of the 12NC ordering code.[1]Type number Package DescriptionPacking quantity 300010000PZU2.4BA to PZU36BA SOD3234mm pitch, 8mm tape and reel-115-135PZU2.4BA/DG to PZU36BA/DG分销商库存信息:NXPPZU5.1BA,115PZU24BA,115PZU6.2B2A,115 PZU7.5B3A,115PZU3.9B1A,115PZU20B1A,115 PZU10BA,115PZU11BA,115PZU12BA,115 PZU13BA,115PZU15BA,115PZU16BA,115 PZU18BA,115PZU2.4BA,115PZU2.7BA,115 PZU20BA,115PZU22BA,115PZU27BA,115 PZU3.0BA,115PZU3.3BA,115PZU3.6BA,115 PZU3.9BA,115PZU30BA,115PZU33BA,115 PZU36BA,115PZU4.3BA,115PZU4.7BA,115 PZU5.6BA,115PZU6.2BA,115PZU6.8BA,115 PZU5.1B1A,115PZU10B1A,115PZU10B2A,115 PZU10B3A,115PZU11B1A,115PZU11B2A,115 PZU11B3A,115PZU12B1A,115PZU12B2A,115 PZU12B3A,115PZU13B1A,115PZU13B2A,115 PZU13B3A,115PZU14B2A,115PZU15B1A,115 PZU15B2A,115PZU15B3A,115PZU16B1A,115 PZU16B2A,115PZU16B3A,115PZU18B1A,115 PZU18B2A,115PZU18B3A,115PZU2.7B1A,115 PZU2.7B2A,115PZU20B2A,115PZU20B3A,115 PZU22B1A,115PZU22B2A,115PZU22B3A,115 PZU24B1A,115PZU24B2A,115PZU24B3A,115 PZU3.0B1A,115PZU3.0B2A,115PZU3.3B1A,115 PZU3.3B2A,115PZU3.6B1A,115PZU3.6B2A,115 PZU4.3B1A,115PZU8.2B1A,115PZU8.2B2A,115。

L3GD20TR;L3GD20;中文规格书,Datasheet资料

August 2011Doc ID 022116 Rev 11/44L3GD20MEMS motion sensor:three-axis digital output gyroscopeFeatures■Three selectable full scales (250/500/2000 dps)■I 2C/SPI digital output interface ■16 bit-rate value data output ■8-bit temperature data output■Two digital output lines (interrupt and data ready)■Integrated low- and high-pass filters with user-selectable bandwidth■Wide supply voltage: 2.4 V to 3.6 V ■Low voltage-compatible IOs (1.8 V)■Embedded power-down and sleep mode ■Embedded temperature sensor ■Embedded FIFO ■High shock survivability■Extended operating temperature range (-40 °C to +85 °C)■ECOPACK ® RoHS and “Green” compliantApplications■Gaming and virtual reality input devices ■Motion control with MMI (man-machine interface)■GPS navigation systems ■Appliances and roboticsDescriptionThe L3GD20 is a low-power three-axis angular rate sensor.It includes a sensing element and an IC interface capable of providing the measured angular rate to the external world through a digital interface (I 2C/SPI).The sensing element is manufactured using a dedicated micro-machining process developed by STMicroelectronics to produce inertial sensors and actuators on silicon wafers.The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics.The L3GD20 has a full scale of ±250/±500/ ±2000 dps and is capable of measuring rates with a user-selectable bandwidth.The L3GD20 is available in a plastic land grid array (LGA) package and can operate within a temperature range of -40 °C to +85 °C.Table 1. Device summaryOrder code Temperature range (°C)Package Packing L3GD20-40 to +85LGA-16 (4x4x1 mm)Tray L3GD20TR-40 to +85LGA-16 (4x4x1 mm)T ape and reelContents L3GD20Contents1Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 92.1Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.3Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.4Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 112.4.1SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.4.2I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.5Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.6Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.6.1Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.6.2Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.7Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.1Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.2FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.2.1Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.2.2FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.2.3Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.2.4Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2.5Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2.6Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1.1I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.2SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.2.1SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/44Doc ID 022116 Rev 1L3GD20Contents5.2.2SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275.2.3SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276Output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317.1WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317.2CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317.3CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327.4CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337.5CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347.6CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347.7REFERENCE/DAT ACAPTURE (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.8OUT_TEMP (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.9STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.10OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.11OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.12OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.13FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.14FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377.15INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377.16INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387.17INT1_THS_XH (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.18INT1_THS_XL (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.19INT1_THS_YH (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.20INT1_THS_YL (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.21INT1_THS_ZH (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.22INT1_THS_ZL (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.23INT1_DURA TION (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Doc ID 022116 Rev 13/44List of tables L3GD20 List of tablesTable 2.Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3.Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4.Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5.Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6.SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7.I2C slave timing values (TBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9.Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 10.I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11.SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 12.Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 13.Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 14.Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 24 Table 15.Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 24 Table 16.Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 17.WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18.CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 19.CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 20.DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 21.Power mode selection configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 22.CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 23.CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 24.High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 25.High-pass filter cut off frequency configuration [Hz]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 26.CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 27.CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 28.CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 29.CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 30.CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 31.CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 32.REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 33.REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 34.OUT_TEMP register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 35.OUT_TEMP register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 36.STATUS_REG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 37.STATUS_REG description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 38.REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 39.REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 40.FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 41.FIFO_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 42.FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 43.INT1_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 44.INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 45.INT1_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 46.INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 47.INT1_THS_XH register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 48.INT1_THS_XH description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 49.INT1_THS_XL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/44Doc ID 022116 Rev 1L3GD20List of tables Table 50.INT1_THS_XL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 51.INT1_THS_YH register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 52.INT1_THS_YH description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 53.INT1_THS_YL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 54.INT1_THS_YL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 55.INT1_THS_ZH register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 56.INT1_THS_ZH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 57.INT1_THS_ZL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 58.INT1_THS_ZL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 59.INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 60.INT1_DURATION description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 61.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Doc ID 022116 Rev 15/44List of figures L3GD20 List of figuresFigure 1.Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2.Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4.I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5.L3GD20 electrical connections and external component values . . . . . . . . . . . . . . . . . . . . 15 Figure 6.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7.Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8.FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9.Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 10.Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11.Trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12.Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 13.SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 14.Multiple byte SPI read protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15.SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16.Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17.SPI read protocol in 3-wire mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 18.INT1_Sel and Out_Sel configuration block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 19.Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 20.Wait enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 21.LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6/44Doc ID 022116 Rev 1Doc ID 022116 Rev 17/441 Block diagram and pin descriptionFigure 1.Block diagramNote:The vibration of the structure is maintained by drive circuitry in a feedback loop. The sensing signal is filtered and appears as a digital signal at the output.1.1 Pin descriptionFigure 2.Pin connectionFIFOTRIMMING CIRCUITSREFERENCEMIXERCHARGE AMPCLOCK LOW-PASS FILTER+Ωx,y,zI2C SPICSSCL/SPCSDA/SDO/SDI SDOY+Z+Y-Z-X+X-DRIVING MASSFeedback loopM U XA D D C I G I T A LF I L T E R I N GCONTROL LOGIC&INTERRUPT GEN.INT1DRDY/INT2A D C T E M P E R A T U R ES E N S O R12&PHASE GENERATORAM10126V1(TOP VIEW)DIRECTION S OF THE DETECTABLE ANGULAR RATE SXVdd_IO S CL/S PC S DA/S DI/S DOS DO/S A0RE S RE S RE S RE SI N T 1D R D Y /I N T 2C SR E SR E SR E SV d dG N D18125491316+ΩZ+ΩXBOTTOMVIEW+ΩYAM10127V18/44Doc ID 022116 Rev 1Table 2.Pin descriptionPin#Name Function1Vdd_IO (1)1.100 nF filter capacitor recommended.Power supply for I/O pins 2SCL SPC I 2C serial clock (SCL)SPI serial port clock (SPC)3SDA SDI SDO I 2C serial data (SDA)SPI serial data input (SDI)3-wire interface serial data output (SDO)4SDO SA0SPI serial data output (SDO)I 2C less significant bit of the device address (SA0)5CS I 2C/SPI mode selection (1: SPI idle mode / I 2C communication enabled; 0: SPI communication mode / I 2C disabled)6DRDY/INT2Data ready/FIFO interrupt (Watermark/Overrun/Empty)7INT1Programmable interrupt 8Reserved Connect to GND 9Reserved Connect to GND 10Reserved Connect to GND 11Reserved Connect to GND 12Reserved Connect to GND 13GND 0 V supply14Reserved Connect to GND with ceramic capacitor (2)2. 1 nF min value must be guaranteed under 11 V bias condition.15Reserved Connect to Vdd 16Vdd (3)3.100 nF plus 10 µF capacitors recommended.Power supply2 Mechanical and electrical specifications2.1 Mechanicalcharacteristics@ Vdd = 3.0 V, T = 25 °C unless otherwise noted.Table 3.Mechanical characteristics(1)Symbol Parameter Test condition Min. Typ.(2)Max.UnitFS Measurement range User-selectable±250dps ±500±2000So Sensitivity FS = 250 dps8.75mdps/digit FS = 500 dps17.50FS = 2000 dps70SoDr Sensitivity change vs.temperatureFrom -40 °C to +85 °C±2%DVoff Digital zero-rate level FS = 250 dps±10dps FS = 500 dps±15FS = 2000 dps±75OffDr Zero-rate level changevs. temperatureFS = 250 dps±0.03dps/°CFS = 2000 dps±0.04dps/°CNL Non linearity Best fit straight line0.2% FS Rn Rate noise density0.03ODR Digital output data rate 95/190/380/760HzTop Operating temperaturerange-40+85°C1.The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table4.2.Typical specifications are not guaranteed.dps Hz(⁄Doc ID 022116 Rev 19/4410/44Doc ID 022116 Rev 12.2 Electrical characteristics@ Vdd =3.0 V , T=25 °C unless otherwise noted.2.3 Temperature sensor characteristics@ Vdd =3.0 V , T=25 °C unless otherwise noted.Table 4.Electrical characteristics (1)Symbol ParameterTest conditionMin.Typ.(2)Max.Unit Vdd Supply voltage2.43.03.6V Vdd_IO I/O pins supply voltage (3) 1.71Vdd+0.1V Idd Supply current 6.1mA IddSL Supply currentin sleep mode (4)Selectable by digital interface2mA IddPdn Supply current in power-down mode Selectable by digital interface5µA VIH Digital high level input voltage0.8*Vdd_IOV VIL Digital low level input voltage0.2*Vdd_IO V T opOperating temperature range-40+85°C1.The product is factory calibrated at 3.0 V.2.Typical specifications are not guaranteed.3.It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses; in this condition themeasurement chain is powered off.4.Sleep mode introduces a faster turn-on time relative to power-down mode.Table 5.Electrical characteristics (1)Symbol ParameterTest conditionMin.Typ.(2)Max.Unit TSDr T emperature sensor output change vs. temperature--1°C/digit TODR T emperature refresh rate 1Hz T opOperating temperature range-40+85°C1.The product is factory calibrated at 3.0 V.2.Typical specifications are not guaranteed.分销商库存信息:STML3GD20TR L3GD20。

AMSAFE AAIR V23系统产品说明书

Rev. NCTABLE OF CONTENTS1.0INTRODUCTION (1)2.0AIRWORTHINESS REQUIREMENTS (2)3.0AAIR SYSTEM DEFINITION (3)3.1AAIR System Overview (3)3.2Seatbelt Airbag Assembly and Belt Extender (4)3.3Inflator Assembly (5)3.4Electronics Module Assembly (7)3.5Cable Interface Assembly (10)3.6System Diagnostic Tool (11)4.0AAIR V23 SYSTEM OPERATION (12)4.1Normal Operation (12)4.2Diagnostics Operation (12)FIGURESFigure 1 – AAIR V23 System Components – Two Seat Placement (3)Figure 2 – Seatbelt Airbag Features (5)Figure 3 – Inflator Assembly Features (6)Figure 4 – Inflation Igniter Connector (7)Figure 5 – EMA Assembly (8)Figure 6 – AAIR V23 System Schematic (9)Figure 7 – EMA with Cable Interface Assembly (10)Figure 8 – V23 System Diagnostic Tool (11)Rev. NC1.0 INTRODUCTIONThis report provides the system description of the AMSAFE Aviation Inflatable Restraint (AAIR®) System, Version V23, using a Three-point Seatbelt Airbag Restraint with Dual Sensor EMA. This description defines all system components, their critical features, and their operation.The AAIR V23 System is comprised of various core components. The core components are equivalent in design and manufacture for all aircraft using this generation product (referred to as AAIR System, Version V23, or AAIR V23 System) using a three-point restraint along with a dual sensor EMA. Certification data for the core components is common to all programs. These core items will be certified through dynamic testing (installation on seat test fixture) and vibration testing of the AAIR System. Refer to Paragraph 3.1 for further information on core components.Rev. NC 2.0 AIRWORTHINESSREQUIREMENTSThe AAIR System will be installed in aircraft to comply with the requirements of Special Condition 1 of the Proposed Special Conditions listed below. The applicable airworthiness requirements are:14 CFR Part 23, up to Amdt 23-55 Federal Aviation RegulationsFAA AC 23.1309 Federal Aviation Administration Advisory Circular –Equipment, Systems, and InstallationsRTCA-DO160D Environmental Conditions and Test Procedures for AirborneEquipmentRTCA-DO183 Minimum Operational Performance Standards for Emergency Locator TransmittersFAA TSO C114 FAA Technical Standard Order C114: Torso Restraint SystemsFAA Notice 23-03-01-SC, 17-Jul-03 Proposed Special ConditionsRev. NC3.0 AAIR SYSTEM DEFINITIONThe AAIR is a self-contained, modular restraint specifically designed to improve occupant protection from serious head injury during a survivable accident. The lapbelt is a three-point restraint system including the AAIR airbag attached to standard webbing, a webbing retractor, fixed anchor point, and buckle anchor point. This AAIR System is primarily located in the front two (pilot and copilot) aircraft seats, and can be used for passenger-only aircraft seating. It is completely independent with no interface to aircraft wiring.The system is divided into the components listed below. These have means to be inspected or replaced as required for continued airworthiness. This design, verification, and certification testing have considered environmental conditions as specified in document RTCA DO-160D, as well as vibration robustness to RTCA DO-183.3.1 AAIR SYSTEM OVERVIEWThe AAIR System contains the following core components corresponding to Figure 1.Seatbelt Airbag Assembly (SAA)Electronics Module Assembly (EMA) Inflator AssemblySystem Diagnostics Tool (not shown) Figure 1 – AAIR V23 System Components – Two Seat PlacementEMA and End-Release Buckle Assy Inflator Assy Diagnostic Connector Airbag Assy w/Inertia ReelRev. NC 3.2 SEATBELT AIRBAG ASSEMBLY AND BELT EXTENDERThe Seatbelt Airbag Assembly (SAA) is the basic lapbelt restraint and is certified to FAA TSO C114. The SAA consists of standard polyester webbing, the packed airbag assembly, a webbing retractor assembly, a fixed anchor point, and a buckle assembly anchor point. The AAIR SAA has the same basic configuration as conventional, three-point, non-inflatable lapbelts, but has the addition of an airbag, a gas delivery hose, and an activation circuit. The buckle is located at a fixed point and uses a push-button type release mechanism. The buckle assembly has a built-in activation system using a magnet and a reed switch. Buckling the lapbelt automatically activates the AAIR System. The lapbelt also includes stiffening device that mechanically resists buckling 180 degrees out of phase, i.e., twisting the belt. Any limitations and information necessary for safe operation of the AAIR are included in the AAIR SMM (Supplemental Maintenance Manual). Special instructions are not required for the passenger to use the device. Child seats are not allowed with pilot/copilot aircraft configurations of the AAIR V23 System. Reference Figures 2, 3, and 7 for seatbelt airbag features and end-release buckle assy features.The AAIR SAA components and their special features are listed below and referenced in Figures 2 and 3:•Standard polyester webbing with standard attachment anchors (ref. 2A).•Airbag sewn to webbing with approximately 30-liter airbag volume made of two fabric panels. The panels consist of a 315-denier nylon 6,6 substrate with an anti-flammability treatment (ref. 2B). The webbing also retracts within an Inertia Reel (ref. 2E) automatically maintaining tight fit of the seatbelt to an individual occupant’s body shape.•Cover with a tearable seam, which opens upon deployment. Cover is constructed of a durable material which protects the internal components from contamination and wear (ref.2B).•Gas delivery hose is tubular woven 1100-denier polyester with Kevlar-like filler and EPDM hose lining. The hose also contains a protective sleeve, which consists of a urethane-type treated, 1100-denier polyester fabric. The hose to inflation device connector is a threaded anodized aluminum fitting with a stainless steel ferrule. The gas hose construction provides resistance to wear and tear and provides safeguards preventing in-service tampering (ref.2C).•Activation circuit consists of a magnetically-activated reed switch and durable magnet mounted onto the end-release buckle assembly. The circuit conductors are strain-relieved, 20-gauge, copper-stranded cables with aerospace-specification connectors (ref. 2D). •Igniter Connector connects the activation circuit to the inflation device’s electrically activated igniter.Rev. NCFigure 2 – Seatbelt Airbag Features• Standard push-button type release mechanism (ref. 2A).• The End-Release Buckle Assembly contains magnet and a reed switch to passively closeactivation circuit. (ref. 2A and 2D).No belt extender is allowed with the AAIR V23 System.The system does not contain sharp or hard surfaces that could cause injury to occupants during normal operation, during a crash, or in secondary impacts. The following design features remove hard points or sharp edges from interfacing with the occupant:• Deployment gas ducted from behind-seat area removes inflation devices from occupantvicinity.• The airbag, belt, and protective cover do not contain any hard points or sharp edges.3.3 INFLATOR ASSEMBLYThe Inflator Assembly is mounted behind each seat position and provides the gas source to inflate the airbag upon command from the EMA. The Inflator Assembly has adhesive labels with appropriate product and shipping information. The Inflator Assembly and its electrical connection are standard automotive components produced and used in high volume with extremely high reliability and safe operation. The Inflator Assembly contains special features for safety and tamper resistance. Reference Figures 3 and 4.The Inflator Assembly components and their special features are listed below:• The inflation device is a stored gas, single-stage, blow-down type using only non-heatedinert helium gas to fill the airbag (ref. 3A).• The inflation device uses a shielded, electrically activated igniter to burst a stainless steelmembrane to release the gas to fill the airbag (ref. 3B). The igniter uses a self-shunting pin clip to automatically safe the Inflator Assembly when the igniter connector is removed. Cover with Airbag folded inside D B A Standard webbing and anchormechanism for three-point seatbelt Retractor DeviceE CRev. NC• The inflation device is a cylindrical, extruded steel, pressure vessel with welded end capsand a welded membrane. Helium gas is contained at a nominal pressure of 6,250 psig. The low carbon alloy steel vessel and all manufacturing processes are specially developed and controlled for high reliability and long-life gas storage (less than 5% gas loss over 15 years). Design values and verification testing are conducted using industry recognized statistical methods. The factors of safety for the pressure vessel are 2.7 at the maximum expected operating pressure and 3.1 at ambient temperature. The Inflator Assembly meets DOT Class 9 and UN3268 requirements for compressed, non-flammable gas devices (ref. 3A).• The inflation device and igniter have independent automatic gas release mechanisms thatare temperature activated (~ +210°C) to protect from vessel fragmentation in the event of prolonged exposure to fire (not shown).• The gas is released from the Inflator through a machined fitting assembly which isconnected to the Inflator via a threaded attachment. It is connected to the gas hose by a threaded end on the fitting (ref. 3C).Figure 3 – Inflator Assembly Features• The Inflator Assembly Igniter Connector (type FCI ABX-3) is attached to the SAA’s activationcircuit by a separate wire cable leg of the End-Release Buckle Assembly (ref. 4A).Inflation Device Body Inflator Fitting Assy and Gas Hose Connection Point A IgniterRev. NCIgniter ConnectorAFigure 4 – Inflation Igniter Connector3.4 ELECTRONICS MODULE ASSEMBLYThe Electronics Module Assembly (EMA) is a plastic box mounted to the aircraft structure on the floor. One EMA is mounted to aircraft floor for each pilot/copilot seat assembly. The EMA enclosure is designed to resist moisture and contamination and can withstand electrostatic discharge. The EMA contains crash sensors, electrical circuits, power, and connectors to service one pilot/copilot seat assembly. Reference Figures 5 and 6 for EMA and AAIR V23 System schematic, respectively.The EMA components and their special features are listed below:•The crash sensors are a spring-mass-damper type inertial switch used in high volume in automotive airbag sensor systems, but calibrated specifically for an aircraft’s operating environment. Proper deployment of the AAIR requires it to deploy at a predetermined threshold. This threshold allows enough time for proper airbag fill, but will not allow inadvertent deployment during normal operations. Below the activation threshold, the AAIR System functions as a conventional seatbelt.•Power is provided by two non-rechargeable, lithium cells with a fused thermal protection circuit. This arrangement precludes short circuits or other failures causing the batteries to release electrolyte or energy into the system in an uncontrolled manner. The system operates nominally at 7.2 VDC, and can maintain functional capability down toRev. NC approximately 7 VDC. The long-life, lithium/thionyl chloride battery system has stand-by capability of 10 years at room temperature.•The electrical connectors have 20-gauge pins and a mistake proof, keyed interface.•The “pigtail” cable consists of 20-gauge, copper-stranded insulated conductors with a woven protective wrap.The EMA assembly has a total mass of approximately .85 pounds. The housing is fabricated from ABS plastic which is lightweight, durable, and rugged. The housing is made up of a body and a lid with the lid held to the body using four machine screws. The internal components consist of a printed circuit board (PCB) onto which are attached the sensors. The battery pack (complete with capacitors and fuse) is connected to the PCB.Under an inertial load of 9g, the internal components could exert a maximum combined force of 5 lbs on the EMA housing, far below the rated capability of the housing or the fasteners including a factor of safety of 1.5. Under extremely severe circumstances, should the internalRev. NC3.5 CABLE INTERFACE ASSEMBLYThe Cable Interface Assembly consists of a connector that interfaces to the EMA pigtail connector on one side and the SAA connector on the other. A Diagnostic Tool Connector leg branches from the EMA connection leg. This diagnostics connector mates with the connector on the System Diagnostic Tool to allow functional testing of the AAIR V23 System. This cable is independent and routed separately from all other aircraft wiring (ref. Figure 7).The connectors have 20-gauge pins and a mistake proof, keyed interface. The cable is 20-gauge, copper-stranded insulated conductors with a woven protective wrap.Diagnostic ToolConnectorEMA ConnectorSAA ConnectorsFigure 7 – EMA with Cable Interface AssemblyRev. NC3.6SYSTEM DIAGNOSTIC TOOLA System Diagnostic Tool (SDT) is used to check the functional status of the AAIR. This small, portable, hand-held device has been designed for use by maintenance personnel at intervals predetermined by the AAIR System Safety Assessment, E508436. The SDT has a connector on the end of a short length of cable and a set of red/green/amber indicator lights. The connector plugs into the Diagnostic Tool Connector on the Electrical Interface Cable. The SDT provides readouts for proper and improper function for the seat position. The SDT has a built-in power supply that does not drain the AAIR battery. The SDT battery is replaceable by the user with a standard, commercially available, 9-volt battery. Figure 8 provides an illustration of the SDT.Figure 8 – V23 System Diagnostic ToolON/OFF SwitchSDT Battery LED SEAT LEDsRev. NC4.0 AAIR V23 SYSTEM OPERATIONThe AAIR V23 System requires no intervention during normal operation. The AAIR is active (able to deploy) upon buckling the seatbelt by the seat occupant and deactivated upon release of the same. The two functional states, active and inactive, both occur in the normal AAIR operational mode. The system has another non-functional, fundamental mode of operation, the diagnostic mode. This mode occurs when the SDT is connected and the system is undergoing a diagnostic test.OPERATION4.1 NORMALThe AAIR System is fully operational and considered “active” when properly installed and buckled. When buckled, the activation switch closes, completing its portion of the deployment circuit. This will allow the system to deploy upon closure of the sensor switch. When active, the AAIR is designed to protect the pilot/copilot occupants seated in the cockpit during emergency landing conditions. Proper deployment of the AAIR requires it to deploy at a predetermined deceleration level, known as the activation point. This is a point in the beginning of a crash that allows enough time for proper airbag fill. Impacts below the activation point will not cause deployment and the system functions as a conventional three-point seatbelt. Decelerations equal to or above the activation point will cause the EMA to sense the crash and initiate the firing sequence and deploy the system as previously described.The inflated airbag acts as a cushion to decelerate the head and torso of the occupant. The kinetic energy of the seat occupant is dissipated on impact with the airbag. The airbag accommodates a range of occupant sizes, and the total time period for inflation and deflation of the airbag poses no hazard to egress.The AAIR System operates within all aspects of the flight envelop environment.OPERATION4.2 DIAGNOSTICSThe system diagnostic check is conducted at pre-determined intervals. This interval must be determined such that the resulting system reliability calculated from the System Safety Assessment (reference AMSAFE document E508436) meets regulatory requirements (FAA AC 23.1309).Maintenance personnel perform the diagnostics check by using a hand-held SDT. First, the seatbelt is buckled to close the circuit and activate the system. Second, the protective cap covering the Diagnostics Tool Connector is removed. Third, the SDT is connected to the Diagnostics Tool Connector and the diagnostics check is performed. Indicators on the SDT provide system status for the seat position’s circuit.。

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