Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic N

This research was supported by NSF Grant No MIP-9502575
at the Georgia Institute of Technology.
power minimization is accomplished through conjoint optimization of both device and circuit designs for a speci c logic schematic, activity pro le and critical path delay requirement. In particular, we determine the optimal supply voltage for the entire module, one or more distinct threshold voltage values for groups of MOSFETs and a channel width for each transistor that minimizes total power or the total energy consumption per cycle while satisfying the critical path delay constraint. The resulting designs operate at low supply voltages and have comparable leakage and switching power dissipation components. The leakage current becomes signi cant due to the need to reduce threshold voltage with reduced supply voltage to maintain speed. The underlying optimization algorithms and the associated CAD tools allow an order of magnitude reduction in power consumption over designs optimized for only supply voltage and device widths as opposed to supply voltage, device widths and threshold voltage . The algorithms discussed in this paper can be used to design a CMOS process for ultra low power designs the algorithms in uence threshold voltage selection. In determining the threshold voltage for a process being developed for future applications, one may use the algorithms on existing benchmarks with predicted circuit timing parameters to nd the most desirable threshold voltage. Also, the methods discussed in this paper can be used to statically adjust the threshold voltage as follows. The threshold-adjust implant step 2 which produces low Vts natural nmos and pmos transistors is eliminated. A static reverse bias is applied to the p-substrate and the n-wells to obtain the desired nmos and pmos Vts values, respectively. An example of an inverter designed this way is shown in Figure 1. A key advantage of this approach is that one can design ultra low-power VLSI with existing CMOS manufacturing technology.
Abstract
We demonstrate a new approach for minimizing the total of the static and the dynamic power dissipation components in a CMOS logic network required to operate at a speci ed clock frequency using joint optimization of both device and circuit designs for a speci c logic schematic and activity pro le. We present a new approach to designing ultra low-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths for a speci ed speed constraint. The static leakage and dynamic switching energy components are considered and an e cient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods.
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks
Pankaj Pant Georgia Institute of Technology pant@ Vivek De Intel Corp., Hillsboro, OR vde@ Abhijit Chatterjee Georgia Institute of Technology abhijit.chatterjee@
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1 Introduction
Traditionally, approaches to minimizing the dynamic power dissipation or switching energy consumption of static CMOS logic networks have advocated straightforward reduction in the supply voltage. It has been shown that the resulting throughput loss on account of increased gate delay can be e ectively compensated through increased data-path parallelism in special-purpose signal-processing applications and by careful transistor sizing 3 . Methodologies for minimizing the sum total of static or leakage and dynamic energy consumption in general-purpose CMOS processes without regard to a performance requirement have also been proposed 2 . Total power is minimized through selection of supply and threshold voltage values such that the leakage and switching components of the dissipation are equal. The accompanying performance loss can be compensated to some degree by minimizing the product of the switching energy and the propagation delay instead of power or energy alone. The relationship between transistor sizing and power has been examined in 10 . A study of supply and threshold voltage selection for low power has been performed in 7 . However, the focus of this study is di erent from the CMOS circuit networks discussed in our paper. In this paper, we propose a comprehensive approach to the minimization of the sum total of the static and dynamic energy dissipation components in a CMOS random logic network required to operate at a speci ed clock frequency. This