UCC5672PWPTR中文资料

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LMC567CN中文资料

LMC567Low Power Tone DecoderGeneral DescriptionThe LMC567is a low power general purpose LMCMOS ™tone decoder which is functionally similar to the industry standard LM567.It consists of a twice frequency voltage-controlled oscillator (VCO)and quadrature dividers which establish the reference signals for phase and ampli-tude detectors.The phase detector and VCO form a phase-locked loop (PLL)which locks to an input signal fre-quency which is within the control range of the VCO.When the PLL is locked and the input signal amplitude exceeds an internally pre-set threshold,a switch to ground is activated on the output pin.External components set up the oscillator to run at twice the input frequency and determine the phase and amplitude filter time constants.Featuresn Functionally similar to LM567n 2V to 9V supply voltage range n Low supply current drainn No increase in current with output activated n Operates to 500kHz input frequency n High oscillator stability n Ground-referenced inputn Hysteresis added to amplitude comparator n Out-of-band signals and noise rejected n20mA output current capabilityBlock Diagram(with External Components)LMCMOS ™is a trademark of National Semiconductor Corp.DS008670-1Order Number LMC567CM or LMC567CN See NS Package Number M08A or N08EJune 1999LMC567Low Power Tone Decoder©1999National Semiconductor Corporation Absolute Maximum Ratings (Note 1)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Input Voltage,Pin 32V p–pSupply Voltage,Pin 410V Output Voltage,Pin 813V Voltage at All Other Pins Vs to GndOutput Current,Pin 830mA Package Dissipation500mWOperating Temperature Range (T A )−25˚C to +125˚CStorage Temperature Range −55˚C to +150˚C Soldering Information Dual-In-Line Package Soldering (10sec.)260˚C Small Outline Package Vapor Phase (60sec.)215˚C Infrared (15sec.)220˚C See AN-450“Surface Mounting Methods and Their Effect on Product Reliability”for other methods of soldering surface mount devices.Electrical CharacteristicsTest Circuit,T A =25˚C,V s =5V,RtCt #2,Sw.1Pos.0,and no input,unless otherwise noted.Symbol Parameter ConditionsMinTyp MaxUnitsI4Power Supply Current RtCt #1,Quiescent or ActivatedV s =2V 0.3mAdcV s =5V 0.50.8V s =9V0.8 1.3V3Input D.C.Bias 0mVdc R3Input Resistance 40k ΩI8Output Leakage 1100nAdc f 0Center Frequency,F osc ÷2RtCt #2,Measure Oscillator Frequency and Divide by 2V s =2V 98kHzV s =5V 92103113V s =9V105∆f 0Center Frequency Shift with Supply 1.0 2.0%/VV inInput ThresholdSet Input Frequency Equal to f 0Measured Above,Increase Input Level Until Pin 8Goes Low.V s =2V 112027mVrms V s =5V 173045V s =9V45∆V in Input Hysteresis Starting at Input Threshold,Decrease Input Level Until Pin 8goes High. 1.5mVrms V8Output ’Sat’Voltage Input Level >Threshold Choose RL for Specified I8I8=2mA 0.060.15VdcI8=20mA 0.7L.D.B.W.Largest Detection BandwidthMeasure F osc with Sw.1in Pos.0,1,and 2;V s =2V 71115%V s =5V 111417V s =9V15∆BWBandwidth Skew±1.0%f max Highest Center Freq.RtCt #3,Measure Oscillator Frequency and Divide by 2700kHz V inInput Threshold at f maxSet Input Frequency Equal to f max measured Above,Increase Input Level Until Pin 8goes Low.35mVrmsNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is func-tional,but do not guarantee specific performance limits.Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guar-antee specific performance limits.This assumes that the device is within the Operating Ratings.Specifications are not guaranteed for parameters where no limit is given,however,the typical value is a good indication of device performance. 2Test CircuitDS008670-2RtCt Rt Ct#1100k300pF#210k300pF#3 5.1k62pF3Typical Performance CharacteristicsApplications Information(refer to BlockDiagram)GENERALThe LMC567low power tone decoder can be operated atsupply voltages of2V to9V and at input frequencies rangingfrom1Hz up to500kHz.The LMC567can be directly substituted in most LM567ap-plications with the following provisions:1.Oscillator timing capacitor Ct must be halved to doublethe oscillator frequency relative to the input frequency(See OSCILLATOR TIMING COMPONENTS).2.Filter capacitors C1and C2must be reduced by a factorof8to maintain the same filter time constants.3.The output current demanded of pin8must be limited tothe specified capability of the LMC567.OSCILLATOR TIMING COMPONENTSThe voltage-controlled oscillator(VCO)on the LMC567mustbe set up to run at twice the frequency of the input signaltone to be decoded.The center frequency of the VCO is setby timing resistor Rt and timing capacitor Ct connected topins5and6of the IC.The center frequency as a function ofRt and Ct is given by:Since this will cause an input tone of half F osc to be decoded,This equation is accurate at low frequencies;however,above50kHz(F osc=100kHz),internal delays cause theactual frequency to be lower than predicted.The choice of Rt and Ct will be a tradeoff between supplycurrent and practical capacitor values.An additional supplycurrent component is introduced due to Rt being switched toV s every half cycle to charge Ct:I s due to Rt=V s/(4Rt)Thus the supply current can be minimized by keeping Rt aslarge as possible(see supply current vs.operating fre-quency curves).However,the desired frequency will dictatean RtCt product such that increasing Rt will require a smallerCt.Below Ct=100pF,circuit board stray capacitances be-gin to play a role in determining the oscillation frequencywhich ultimately limits the minimum Ct.To allow for I.C.and component value tolerances,the oscil-lator timing components will require a trim.This is generallyaccomplished by using a variable resistor as part of Rt,al-though Ct could also be padded.The amount of initial fre-quency variation due to the LMC567itself is given in theelectrical specifications;the total trim range must also ac-commodate the tolerances of Rt and Ct.Supply Current vs.Operating FrequencyDS008670-3Bandwidth vs.Input Signal LevelDS008670-7Largest DetectionBandwidth vs.Temp.DS008670-8Bandwidth asa Function of C2DS008670-9Frequency Driftwith TemperatureDS008670-10Frequency Driftwith TemperatureDS008670-11 4Applications Information(refer to Block Diagram)(Continued)SUPPLY DECOUPLINGThe decoupling of supply pin4becomes more critical at high supply voltages with high operating frequencies,requiring C4to be placed as close as possible to pin4.INPUT PINThe input pin3is internally ground-referenced with a nomi-nal40kΩresistor.Signals which are already centered on0V may be directly coupled to pin3;however,any d.c.potential must be isolated via a coupling capacitor.Inputs of multiple LMC567devices can be paralleled without individual d.c. isolation.LOOP FILTERPin2is the combined output of the phase detector and con-trol input of the VCO for the phase-locked loop(PLL).Ca-pacitor C2in conjunction with the nominal80kΩpin2inter-nal resistance forms the loop filter.For small values of C2,the PLL will have a fast acquisition time and the pull-in range will be set by the built in VCO fre-quency stops,which also determine the largest detection bandwidth(LDBW).Increasing C2results in improved noise immunity at the expense of acquisition time,and the pull-in range will begin to become narrower than the LDBW(see Bandwidth as a Function of C2curve).However,the maxi-mum hold-in range will always equal the LDBW.OUTPUT FILTERPin1is the output of a negative-going amplitude detectorwhich has a nominal0signal output of7/9V s.When the PLLis locked to the input,an increase in signal level causes thedetector output to move negative.When pin1reaches2/3V s the output is activated(see OUTPUT PIN).Capacitor C1in conjunction with the nominal40kΩpin1in-ternal resistance forms the output filter.The size of C1is atradeoff between slew rate and carrier ripple at the outputcomparator.Low values of C1produce the least delay be-tween the input and output for tone burst applications,whilelarger values of C1improve noise immunity.Pin1also provides a means for shifting the input thresholdhigher or lower by connecting an external resistor to supplyor ground.However,reducing the threshold using this tech-nique increases sensitivity to pin1carrier ripple and also re-sults in more part to part threshold variation.OUTPUT PINThe output at pin8is an N-channel FET switch to groundwhich is activated when the PLL is locked and the input toneis of sufficient amplitude to cause pin1to fall below2/3V s.Apart from the obvious current component due to the exter-nal pin8load resistor,no additional supply current is re-quired to activate the switch.The on resistance of the switchis inversely proportional to supply;thus the“sat”voltage fora given output current will increase at lower supplies. 5Physical Dimensions inches(millimeters)unless otherwise notedMolded Small Outline(SO)Package(M)Order Number LMC567CMNS Package Number M08AMolded Dual-In-Line Package(N)Order Number LMC567CNNS Package Number N08E 6NotesLIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices orsystems which,(a)are intended for surgical implant into the body,or(b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a lifesupport device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.National Semiconductor CorporationAmericasTel:1-800-272-9959 Fax:1-800-737-7018 Email:support@ National SemiconductorEuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National SemiconductorAsia Pacific CustomerResponse GroupTel:65-2544466Fax:65-2504466Email:sea.support@National SemiconductorJapan Ltd.Tel:81-3-5639-7560Fax:81-3-5639-7507 LMC567 Low Power Tone DecoderNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。

LM567中文资料及LM567

2.4 全自动红外水龙头2.4.1 水龙头的构成及红外传感器控制水龙头采用了反射式红外传感器。

红外线的发射和接收一般使用红外发光二极管和红外接收管来完成。

当有物体靠近时，一部分红外光被发射到接收管。

反射式红外传感器如图4所示。

图4 反射式红外传感器红外水龙头控制过程是，当人或物体接近自动水龙头时，红外发射光电管发出的红外信号经人或物体反射到红外接收光电管。

接收光电管接收到的反射光信号自动转换为电信号，经过后续电路进一步放大、整形、译码，最后驱动电路控制电磁阀动作打开水源。

当人或物体离开自动水龙头时，接收光电管接收不到反射光信号，驱动电路断开电磁阀电源。

2.4.2 红外感应系统组成方框图全自动红外线控制水龙头整个过程分5个模块。

系统组成方框图如图5所示。

图5 系统组成方框图多谐振荡器调幅红外光电磁阀动作红外接收音频译码（LM567）电压放大（LM741）3 红外线控制电路系统的工作原理由于红外线水龙头控制电路构成较多，原理复杂，所以下面部分着重介绍红外控制水龙头组成及工作原理。

3.1 红外线水龙头控制电路系统的组成红外线水龙头控制电路包括发射电路和接收译码控制电路。

其中发射电路由多谢振荡器和三个TLN104型红外发射二极管；接收电路包括红外接收管VD0和VD1，运算放大器（LM741）、音频译码器（LM567）、继电器K0、电源电路等组成。

3.2 红外线水龙头控制电路原理图（见附录）3.3 红外线水龙头控制电路工作原理工作原理：发射电路中，多谐振荡器由IC（555）、R0、R1和C7等组成。

其振荡频率为f=1.43÷(R0+2R1)÷C7附录中所示的参数对应频率为40KHZ，它的震荡输出信号驱动TLN104型的LED1~LED3工作，从而产生红外脉冲调制波。

接收电路中红外接收头VD0、VD1与发射中的发射管相匹配，采用TLN104型。

红外脉冲调制经VD0、VD1接收管转换成电信号，经C1耦合至LM741，再经C2输入到LM567的第3管脚，经识别译码后，使得中心频率f=1÷1.1R6C3与红外调制频率40KHZ一致，使第8管脚输出为低电平，又经反相后，驱动VT2导通，继电器接收到控制信号后动作，电磁阀电源接通，水源打开。

PC5672A-12F中文资料

Ultraminiature Automoti ve PCB Twin Power RelayFEATURESUltraminiature design very ligh t weightSensitive Coil (low pull in volta ge) available Sealed, immersion cleanableContact switching capacity up to 30 Amps Up to105 degrees C operating temperaturePC567Max. Switching Voltage 16 VDC CONTACT RATINGSCHARACTERISTICSOperate Time 2.5 ms. typical (no coil suppression)Release Time Insulation Resistance 1.2 ms. typical (no coil suppression)100 megohms min, at 500VDC, 50%RH Dielectric Strength 1000 Vrms, 1 min. between coil and contacts Shock Resistance 30 g, 6 ms, functional; 100 g, destructive Vibration Resistance 6g, 10 - 500 HzPower Consumption 0.64 W and 0.80 WAmbient Temperature Range -40 to 85 degrees C or -40 to 105 degrees C op eratingWeight4.1 grams approx.Sales: Call Toll Free (888)997-3933 Fax (818) 342-5296 email: pickerwest@ URL: 3220 Commander Drive, Suite 102, Carrollton, T exas 75006PC567 Rev B 4-14-04PAGE 1CONTACT DATAMaterialInitial Contact Resistance Service LifeMechanical ElectricalAgSnO (Silver Tin Oxide)100 milliohms max @ 0.1A, 6VDC 1 X 1061 X 105Operations OperationsContact FormMax Switching Current 25 Amps at 14 VDC30 Amps 25 Amps Max. Continuous Current Max. Switching Power480 WDrop Resistance 1 Meter height drop on concrete Motor Locked Rotor ORDERING INFORMATIONExample:PC567Model -2CContact Form Coil Power-12Nil: 0.64 W; H: Sensitive 0.80 W Coil VoltageH2A or 2C Ambient Temperature RatingNil: 85 Degrees C; F: 105 Degrees CF2 X Form A or 2 X Form C 2 X SPST NO or 2 X SPDTPC567PC567COIL DATACoil Voltage12Resistanceohms + 10%Must OperateVoltage Max.(VDC)Must Release Voltage Min.(VDC)Coil Power Consumption(W)2251806.51.00.80_Sales: Call Toll Free (888) 997-3933 F ax (818) 342-5296 email: pickerwest@sbc URL: 3220 Commander Drive, Suite 102, Car rollton, Texas 75006PAGE 2Tolerances +.010 unless otherwise notedNotes:Contact Form C shownOn Contact Form A Unused Pin is Omitted 7.2 1.00.6412 (H)Wiring DiagramDimensions in Inches (millimet ers)Side ViewEnd ViewPC Board LayoutDrawings are 2X actual size。

W567CXXX 16通道语音+音乐处理器（BandDirector Series）说明书

W567CXXX DATASHEET16-CHANNEL SPEECH+MELODY PROCESSOR(BandDirector TM Series)Table of Contents-1.GENERAL DESCRIPTION (2)2.FEATURES (3)3.PIN DESCRIPTION (4)4.BLOCK DIAGRAM (5)5.ITEM VS PIN TABLE (6)6.ELECTRICAL CHARACTERISTICS (7)6.1Absolute Maximum Ratings (7)6.2DC Characteristics (7)6.3AC Characteristics (8)7.TYPICAL APPLICATION CIRCUIT (9)8.REVISION HISTORY (12)1. GENERAL DESCRIPTIONThe W567Cxxx is a powerful microcontroller (uC) dedicated to speech and melody synthesis applications. With the help of the embedded 8-bit microprocessor & dedicated H/W, the W567Cxxx can synthesize 16-channel speech+melody simultaneously.The two channels of synthesized speech can be in different kinds of format, for example ADPCM and MDPCM. The W567Cxxx can provide 16-channel high-quality WinMelody TM , which can emulate the characteristics of musical instruments, such as piano and violin. The output of speech/melody channels are mixed together through the on-chip digital mixer to produce colorful effects. With these hardware resources, the W567Cxxx is very suitable for high-quality and sophisticated scenario applications.The W567Cxxx provides at most 24 bi-directional I/Os, maximum 512 bytes RAM, IR carrier, Serial Interface Management, and 32KHz-Divider for more and more sophisticated applications, such as interactive toys, cartridge toys and final count down function. 3 LED output pins with 256-level control means that numerous combination of RGB colors may result in a versatility of colorful effects. In addition, W567Cxxx also provides PWM mode output to save power during playback and Watch Dog Timer to prevent latch-up situation occurring.Note:*: The duration time is based on 5-bit MDPCM at 6 KHz sampling rate. The firmware library and timber library have beene xcluded from user’s ROM space for the duration estimation.2. FEATURES∙Wide range of operating voltage:-************~5.5volt-************~5.5volt∙Power management:- 4 ~ 8 MHz system clocks, with Ring type or crystal type.-Stop mode for stopping all IC operations∙Provides up to 24 I/O pins∙F/W speech synthesis:Multiple format parser that supportsNew 4-bit MDPCM(NM4), 5-bit MDPCM(MDM), 4-bit MDPCM(MD4), 4-bitADPCM(APM), 8-bit Log PCM(LP8) algorithm can be usedPitch shippable ADPCM for voice changer applicationProgrammable sample rate∙Melody synthesis:16 melody channels that can emulate characteristics of musical instrumentsMulti-MIDI simultaneousMulti-MIDI channels dynamic controlMore MIDI events are supported for colorful melody playback∙Built-in IR carrier generation circuit for simplifying firmware IR application∙Built-in TimerG0 for general purpose applications∙Harmonized synchronization among MIDI, Speech, LED, and Motor∙Build-in 3 LED outputs with 256-level control of brightness.∙Built-in Watch-Dog Timer (WDT) and Low Voltage Reset (LVR)∙Built-in 32KHz crystal oscillator with divider for time-keeping application∙Provide serial interface to access the external memoryW55Fxx, W551CxxSPI flash∙Dynamic control of the Pan assignment to the dual speaker output for stereo effects in the parts of W567Cxx6∙Stereophonic current type digital-to-analog converters (DAC) with 13-bit resolution to drive speaker output∙Stereophonic direct-drive 12-bit PWM output to save power consumption∙Support PowerScript TM for developing codes in easy way∙Full-fledged development systemSource-level ICE debugger (Assembly & PowerScript TM format)Ultra I/O TM tool for event synchronization mechanismICE system with USB portUser-friendly GUI environment∙Available package form:COB is essential3. PIN DESCRIPTION1Only W567Cxx6 series provides these pins for dual speaker output.4. BLOCK DIAGRAMDAC/PWM+PWM-5. ITEM VS PIN TABLE6. ELECTRICAL CHARACTERISTICS6.1 Absolute Maximum RatingsNote: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.6.2 DC Characteristics(V DD-V SS = 4.5 V, F M = 8 MHz, Ta = 25︒C, No Load unless otherwise specified)6.3 AC Characteristics(V DD-V SS = 4.5 V, F M = 8 MHz, Ta = 25︒C; No Load unless otherwise specified)7. TYPICAL APPLICATION CIRCUIT(a) Rosc with 2 BatteryNotes:1. The block (1): If the project is two-battery application (Voltage 3.6V~2.2V), it is necessary to connect CVDD to VDD.2. The block (2): The low-pass filter circuit is necessary for VDD stability, in order to avoid VDDSPK noise.3. The block (3): The capacitor,4.7uF, shunted between VDD and GND is necessary for power stability. However, thevalue of capacitor depends on the power loading of the application.4. The typical value of Rosc is 300 KΩ for 8MHz and 390 KΩ for 6MHz, and the Rosc should be connected to GND(VSS). Please refer to design guide to get typical Rosc value for each part number.5. The block (4):The capacitor, 120pF, shunted between OSCIN and VDD is optional for Fosc stability, which canprevent noise from happening, because it can block the affection of larger current while playing. However, the value of capacitor depends on the application (100pF~200pF is recommended)6. The block (5): The Rs value is suggested of 270Ω ~ 1KΩ to limit large DAC output current flowing into transistor.7. The above application circuit is for reference only. No warranty for mass production.(b) Rosc with 3 BatteryNotes:1. The block (1): If the project is three-battery application (Voltage 5.5V~3.0V), it is necessary to connect a 0.1uFbetween CVDD and GND (VSS).2. The block (2): The low-pass filter circuit is necessary for VDD stability, in order to avoid VDDSPK noise3. The block (3): The capacitor,4.7uF, shunted between VDD and GND is necessary for power stability. However,the value of capacitor depends on the power loading of the application.4. The typical value of Rosc is 300 KΩfor 8MHz and 390 KΩfor 6MHz, and the Rosc should be connected toGND (VSS). Please refer to design guide to get typical Rosc value for each part number.5. The block (4)The capacitor, 120pF, shunted between OSCIN and VDD is optional for Fosc, which can preventnoise from happening, because it can block the affection of larger current while playing. However, the value of capacitor depends on the application (100pF~200pF is recommended)6. The block (5): The Rs value is suggested of 270Ω~ 1KΩto limit large DAC output current flowing intotransistor.7. The above application circuit is for reference only. No warranty for mass production.(c) CrystalNotes:1. The block (1): Please refer to (a) and (b) circuits for two-battery or three-battery application.2. The block (2): The low-pass filter circuit is necessary for VDD stability, in order to avoid VDDSPK noise.3. The block (3): The capacitor,4.7uF, shunted between VDD and GND is necessary for power stability. However thevalue of capacitor depends on the power loading of the application4. The block (4): Cp1 and Cp2 (15~30pF) are optional for main Crystal, which can be skipped normally.5. The block (5): The Rs value is suggested of 270Ω ~ 1KΩ to limit large DAC output current flowing into transistor.6. Cp3 and Cp4 (15~30pF) are optional for 32KHz Crystal, which can be skipped normally.7. Please connect all VDD pins include VDDOSC/VDD_BP1 to VDD. If with SIM application, the VDD_BP1 pin canconnect to different voltage for SPI flash or W551Cxx and the BP10~BP17 also use the same power VDD_BP1.8. The above application circuit is for reference only. No warranty for mass production.9. Other application circuits please refer to Design Guide.(d) PCB layout guide1. The IC substrate should be connected to VSS in PCB layout, but VSSSPK can’t connect withIC substrate directly. Both VSS and VSSSPK tie together in battery negative power.2. Each VDD, VDDOSC, VDD_BP1, VDD1 and VDDSPK pad must connect to positive power tosupport stable voltage for individual function work successfully. (Don’t let them be floating.)8. REVISION HISTORYA0.0 Dec 2006 Preliminary release.A1.0 May 2007 ●Add IO description for different body ●Modify application circuitA2.0 Nov 2007 ●Modify application circuit (naming) ●Modify LogoA3.0 Sep. 2008 ●Change logoA4.0 Jun. 2009 ●Modify application circuitA5.0 Jun. 2010 ●Add application circuit for 2 batteryA6.0 Dec. 2010 ●UpdateoutputcurrentforBP1/******/*********************●Add application circuit for Ring OSCin pin to 120pF to VDD for option●Modify the description for application circuit●Support MD4 format for F/W library79~159~153A7.0 July 2011 ●Add new chip W567C151/171 application circuit 2, 5 9~18A8.0 Aug. 2011 ●Remove W567C150/170●Add new chip W567C151/171 pad description●Add new chip W567C151/171 application circuit●Add SIM application circuits259~2020A9.0 Jan. 2012 ●Add W567CP80 OTP chip●Add items vs pad table●Modify application circuits27A10.0 Mar. 2012●BP00~BP03 share pins as OTP writer in W567CP80.●Update operating current DC spec. 4 9A11.0 Jun. 2012 ●Revised VDD_SIM to VDD_BP1 5, 7 11~13Important NoticeNuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life.All Insecure Usage shall be made a t customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton.。

LM567中文资料及LM567工作原理及应用在超声波红外等的电路

LM567中文资料及LM567工作原理及应用在超声波红外等的电路567为通用音调译码器，当输入信号于通带内时提供饱和晶体管对地开关，电路由I与Q检波器构成，由电压控制振荡器驱动振荡器确定译码器中心频率。

用外接元件独立设定中心频率带宽和输出延迟。

主要用于振荡、调制、解调、和遥控编、译码电路。

如电力线载波通信，对讲机亚音频译码，遥控等。

用外接电阻20比1频率范围逻辑兼容输出具有吸收100mA电流吸收能力。

可调带宽从0%至14%宽信号输出与噪声的高抑制对假信号抗干扰高稳定的中心频率中心频率调节从0.01Hz到500kHz电源电压5V--15V，推荐使用8V。

应用举例：输入端接104电容，输出端接上拉电阻10K，C1、C2为1uF。

R1、C1决定振荡频率，一般C1为104电容，R1为10K--200K。

电源电压为8V。

单通道红外遥控电路在不需要多路控制的应用场合，可以使用由常规集成电路组成的单通道红外遥控电路。

这种遥控电路不需要使用较贵的专用编译码器，因此成本较低。

单通道红外遥控发射电路如图1所示。

在发射电路中使用了一片高速CMOS 型四重二输入“与非”门74HC00。

其中“与非”门3、4组成载波振荡器，振荡频率f0调在38kHz左右；“与非”门1、2组成低频振荡器，振荡频率f1不必精确调整。

f1 对f0进行调制，所以从“与非”门4输出的波形是断续的载波，这也是经红外发光二极管传送的波形。

几个关键点的波形如图2所示，图中B′波形是A点不加调制波形而直接接高电平时B点输出的波形。

由图2可以看出，当A点波形为高电平时，红外发光二极管发射载波；当A点波形为低电平时，红外发光二极管不发射载波。

这一停一发的频率就是低频振荡器频率f1。

在红外发射电路中为什么不采用价格低廉的低速CMOS四重二输入“与非”门CD4011，而采用价格较高的74HC00呢？主要是由于电源电压的限制。

红外发射器的外壳有多种多样，但电源一般都设计成3V，使用两节5号或7号电池作电源。

66572资料

April 1996NEC Electronics Inc.A10616EU1V0DS00CMOS-8LHD3.3-Volt, 0.5-Micron CMOS Gate ArraysPreliminary DescriptionNEC's CMOS-8LHD gate-array family combines cell-based-level densities with the fast time-to-market and low development costs of gate arrays. With a unique heterogeneous cell architecture, CMOS-8LHD provides the very dense logic and RAM capabilities required to build devices for fast computer and communications systems.NEC delivers high-speed, 0.5-micron, drawn gate length (Leff=0.35-micron), three-level metal, CMOS technology with an extensive family of macros. I/O macros include GTL, HSTL, and pECL. TTL CMOS I/Os are provided with 5-V tolerance for applications requiring interface to 5-V logic. PCI signaling standards are also supported,including 3.3-V, 66 MHz PCI. The technology is enhanced by a set of advanced features, including phase-locked loops, clock tree synthesis, and high-speed memory. The CMOS-8LHD gate-array family of 3.3-V devices consists of 12 masters, offered in densities of 75K raw gates to 1.123 million raw gates. Usable gates range from 45K to 674K used gates.The gate-array family is supported by NEC's OpenCAD ®design system, a mixture of popular third-party EDA tools,and proprietary NEC tools. NEC proprietary tools include the GALET floorplanner, which helps to reduce design time and improve design speed, and a clock tree synthesis tool that automatically builds a balanced-buffer clock tree to minimize on-chip clock skew.Figure 1. CMOS-8LHD Package Options: BGA & QFPTable 1. CMOS-8LHD Family Features and BenefitsCMOS-8LHD ApplicationsThe CMOS-8LHD family is ideal for use in personal computer systems, engineering workstations, and telecommunications switching and transmission systems, where extensive integration and high speeds are primary design goals. With power dissipation of 0.21 µW/MHz/gate, CMOS-8LHD is also suited for lower-power applications where high performance is required.OpenCAD is a registered trademark of NEC Electronics Inc.CMOS-8LHD2Cell-Based Array ArchitectureThe CMOS-8LHD gate-array family is built with the Cell-Based Array (CBA) architecture licensed from the Silicon Architects Group of Synopsys. CBA architecture uses two types of cells: compute cells and drive cells.This heterogeneous cell architecture enables very high-density design. Compute cells are used to optimize intramacro logic. Drive cells are optimized for intermacro interconnect. The two cell types are also used to build macros with up to three different power/performance/area points.CBA has a rich macrocell library that is optimized for synthesis. RAM blocks are efficiently created from the CBA architecture, using compute cells as memory cores, and sense amplifiers and drive cells as word and address predecoder drivers.As shown in Figure 2, CBA is divided into I/O and array regions. The I/O region contains input and output buffers. The array region contains the gates used to build logic, RAM blocks, and other design features.Power Rail ArchitectureCMOS-8LHD provides additional flexibility for mixedvoltage system designs. As shown in Figure 2, the arrays contain two power rails: a 3.3-V rail, and V DD2.The V DD2 rail is used for interfaces such as 5-V PCI buffers where a clamping diode allows protection for up to an 11-V voltage spike, per the PCI revision 2.1specification.Figure 2. CBA Layout and Cell ConfigurationThe V DD2 rail is separated into sections to give flexibility for including two or more buses requiring special I/O voltage on one device. Each section can operate as an independent voltage zone, and sections can be linked together to form common voltage zones.Packaging and TestNEC utilizes BIST test structures for RAM testing. NEC also offers advanced packaging solutions including Plastic Ball Grid Arrays (PBGA), Plastic Quad Flat Packs (PQFP), and Pin Grid Arrays (PGA). Please call your local NEC ASIC design center representative for a listing of available master/package combinations.PublicationsThis data sheet contains preliminary specifications for the CMOS-8LHD gate-array family. Additional infor-mation will be available in NEC's CMOS-8LHD Block Library and CMOS-8LHD Design Manual . Call your local NEC ASIC design center representative or the NEC literature line for additional ASIC design information; see the back of this data sheet for locations and phone numbers.Table 2. CMOS-8LHD Base Array Line-upDevice Raw Gates Used Gates (1)Total Pads66562750404502416466563997925987518866565125216751292126656617963210777925266568202400121440268665692681281608763086657029792017875232466571359744215845356665725008643005184206657362054437232646866575802240481344532(1) Actual gate utilization varies depending on circuit implementation.Utilization is 60% for 3LM.3CMOS-8LHDInput/Output CapacitanceV DD =V I =0-V; f =1 MHzTerminal Symbol Typ Max Unit Input C IN 1020pF Output C OUT 1020pF I/OC I/O1020pF(1)Values include package pin capacitancePower ConsumptionDescription Limits Unit Internal gate (1)0.21µW/MHz Input buffer 2.546µW/MHz Output buffer10.60µW/MHzAbsolute Maximum RatingsPower supply voltage, V DD –0.5 to +4.6-VInput voltage, V I3.3-V input buffer (at V I < V DD + 0.5-V)–0.5 to +4.6-V 3.3-V fail-safe input buffer (at V I < V DD + 0.5-V)–0.5 to +4.6-V 5 V-tolerant (at V I < V DD + 3.0-V)–0.5 to +4.6-V Output Voltage, V O3.3-V output buffer (at V O < V DD + 0.5-V)–0.5 to +4.6-V 5-V-tolerant output buffer (at V O < V DD + 3.0-V)–0.5 to +4.6-V 5-V open-drain output buffer (at V O < V DD + 3.0-V)–0.5 to +4.6-VLatch-up current, I LATCH >1 A (typ)Operating temperature, T OPT –40 to +85°C Storage temperature, T STG–65 to +150°C (1) Assumes 30% internal gate switching at one timeCaution: Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The device should not be operated outside the recommended operating conditions.Recommended Operating ConditionsV DD = 3.3-V ±0.165-V; T j = 0 to +100°C3.3-V Interface 5-V Interface5-V PCI 3.3-V PCIBlock BlockLevel LevelParameterSymbol Min Max Min Max Min Max Min Max Unit I/O power supply voltage V DD 3.0 3.6 3.0 3.6 3.0 5.5 3.0 3.6V Junction temperature T J 0+1000+1000+1000+100°C High-level input voltage V IH 2.0V DD 2.0 5.5 2.0V CC 0.5 V CCV CC V Low-level input voltage V IL 00.800.800.800.3 V CCV Positive trigger voltage V P 1.50 2.70 1.50 2.70————V Negative trigger voltage V N 0.60 1.60.60 1.6————V Hysteresis voltage V H 1.10 1.3 1.10 1.3————V Input rise/fall time t R , t F 0200020002000200ns Input rise/fall time, Schmittt R , t F1010————nsAC CharacteristicsV DD = 3.3-V ±0.3-V; T j = –40 to +125°C ParameterSymbol MinTypMax Unit Conditions Toggle frequency (F611)f TOG356MHzD-F/F; F/O = 2 mmDelay time2-input NAND (F322)t PD181ps F/O = 1; L = 0 mmt PD 186ps F/O = 2; L = typ (0.42 mm)Flip-flop (F611)t PD 573ps F/O = 1; L = 0 mm t PD 688ps F/O = 2; L = typ t SETUP 410ps —t HOLD 540ps —Input buffer (FI01)t PD 268ps F/O = 1; L = 0 mm t PD 312ps F/O = 2; L = typ Output buffer (9 mA) 3.3-V (FO01)t PD 1.316ns C L = 15 pF Output buffer (9 mA) 5-V-tolerant (FV01)t PD 1.228ns C L = 15 pF Output buffer (9 mA) 5-V-swing (FY01)t PD 1.517ns C L = 15 pF Output rise time (9 mA) (FO01)t R 1.347ns C L = 15 pF Output fall time (9 mA) (FO01)t F1.284nsC L = 15 pFCMOS-8LHD4(3)Rating is for only one output operating in this mode for less than 1 second.(4)Normal type buffer: I OH < I OL .(5)Balanced buffer: I OH = I OL .(6)Resistor is called 50ký to maintain consistency with previous families.Notes:(1)Static current consumption increases if an I/O block with on-chip pull-up/pull-down resistor or an oscillator is used. Call an NEC ASIC design center repre-sentative for assistance in calculation.(2)Leakage current is limited by tester capabilities. Specification listed representsthis measurement limitation. Actual values will be significantly lower.DC CharacteristicsV DD = 3.3-V ±0.165-V; T j = 0 to +100°C ParameterSymbol Min Typ Max Unit Conditions Quiescent current (1)µPD66578I DDS 2.0300µA V I = V DD or GND µPD66575, 66573, 66572I DDS 1.0300µA V I = V DD or GND Remaining mastersI DDS 0.5200µA V I = V DD or GND Off-state output leakage current3.3-V buffers, 3.3-V PCII OZ ±10µA V O = V DD or GND 5-V-tolerant buffers, 5-V PCI I OZ ±14µA V O = V DD or GND 5-V open-drainI OZ ±14µA V O = V DD or GND Output short circuit current (3)I OS –250mA V O = GND Input leakage current (2)5-V PCI I IH +70, –70µA V IN = 2.7-V, 0.5-V 3.3-V PCI I I ±10µA V IN = V DD or GND RegularI I ±10–5±10µA V I = V DD or GND 50 k Ω pull-up I I –180–40µA V I = GND 5 k Ω pull-up I I –1400–350mA V I = GND 50 k Ω pull-down I I 30160µA V I = V DDResistor values50 k Ω pull-up (6)R pu 2075k Ω5 k Ω pull-upR pu 2.68.6k Ω50 k Ω pull-down (6)R pu 22.5100k ΩInput clamp voltageV IC –1.2V I I = 18 mA Low-level output current (ALL buffer types)3 mA I OL 3mA V OL = 0.4-V 6 mA I OL 6mA V OL = 0.4-V 9 mA I OL 9mA V OL = 0.4-V 12 mA I OL 12mA V OL = 0.4-V 18 mA I OL 18mA V OL = 0.4-V 24 mAI OL 24mA V OL = 0.4-V High-level output current (5-V-tolerant block)3 mA I OH –3mA V OH = V DD –0.4-V 6 mA I OH –3mA V OH = V DD –0.4-V 9 mA I OH –3mA V OH = V DD –0.4-V 12 mA I OH –3mA V OH = V DD –0.4-V 18 mA I OH –4mA V OH = V DD –0.4-V 24 mAI OH –4mA V OH = V DD –0.4-V High-level output current (3.3-V interface block)3 mA I OH –3mA V OH = V DD –0.4-V 6 mA I OH –6mA V OH = V DD –0.4-V 9 mA I OH –9mA V OH = V DD –0.4-V 12 mA I OH –12mA V OH = V DD –0.4-V 18 mA I OH -18mA V OH = V DD –0.4-V 24 mAI OH -24mA V OH = V DD –0.4-V Output voltage (5-V PCI)High-level output voltage V OH 2.4mA I OH = 2 mALow-level output voltage V OL 0.55mA I OL = 3 mA, 6 mA Output voltage (3.3-V PCI)High-level output voltage V OH 0.9 V DDmA I OH = 500 µA Low-level output voltage V OL 0.1 V DDmA I OL = 1500 µA Low-level output voltageV OL 0.1V I OL = 0 mA High-level output voltage, 5-V TTL V OH V DD –0.2V I OL = 0 mA High-level output voltage, 3.3-VV OHV DD –0.1VI OH = 0 mACMOS-8LHD5CMOS-8LHD6Document No. A10616EU1V0DS00For literature, call toll-free 7 a.m. to 6 p.m. Pacific time: 1-800-366-9782or FAX your request to: 1-800-729-9288©1996 NEC Electronics Inc./Printed in U.S.A.NEC ASIC DESIGN CENTERSWEST•3033 Scott Boulevard Santa Clara, CA 95054TEL 408-588-5008FAX 408-588-5017•One Embassy Centre9020 S.W. Washington Square Road,Suite 400Tigard, OR 97223TEL 503-671-0177FAX 503-643-5911THIRD-PARTY DESIGN CENTERSSOUTH CENTRAL/SOUTHEAST•Koos Technical Services, Inc.385 Commerce Way, Suite 101Longwood, FL 32750TEL 407-260-8727FAX 407-260-6227•Integrated Silicon Systems Inc.2222 Chapel Hill Nelson Highway Durham, NC 27713TEL 919-361-5814FAX 919-361-2019•Applied Systems, Inc.1761 W. Hillsboro Blvd., Suite 328Deerfield Beach, FL 33442TEL 305-428-0534FAX 305-428-5906NEC Electronics Inc.CORPORATE HEADQUARTERS2880 Scott Boulevard P.O. Box 58062Santa Clara, CA 95052TEL 408-588-6000No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc. (NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALES ONLY. INCLUDING THE LIMITATION OF LIABILITY,WARRANTY, AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding informa-tion set forth herein or regarding the freedom of the described devices from patent infringement. NECEL assumes no responsibility for any errors that may appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems,aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. “Standard” quality grade devices are recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools,industrial robots, audio and visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, anti-disaster and anti-crime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the reliabilty requirements for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in life support devices or systems or in any application where failure could result in injury or death.If customers wish to use NECEL devices in applications not intended by NECEL, customer must contact the responsible NECEL sales people to determine NECEL’s willingness to support a given application.SOUTH CENTRAL/SOUTHEAST•16475 Dallas Parkway, Suite 380Dallas, TX 75248TEL 972-735-7444FAX 972-931-8680•Research Triangle Park2000 Regency Parkway, Suite 455Cary, NC 27511TEL 919-460-1890FAX 919-469-5926•Two Chasewood Park 20405 SH 249, Suite 580Houston, TX 77070TEL 713-320-0524FAX 713-320-0574NORTH CENTRAL/NORTHEAST•The Meadows, 2nd Floor 161 Worcester Road Framingham, MA 01701TEL 508-935-2200FAX 508-935-2234•Greenspoint Tower2800 W. Higgins Road, Suite 765Hoffman Estates, IL 60195TEL708-519-3945FAX 708-882-7564。

TI产品中文版说明书

Load (A)E f f i c i e n c y (%)0.00.51.0 1.52.06065707580859095100D008V INV OUTL1TLV62569AProduct Folder Order Now Technical Documents Tools &SoftwareSupport &CommunityTLV62568A ,TLV62569AZHCSI23B –APRIL 2018–REVISED MARCH 2020采用SOT563封装并具有强制PWM 的TLV6256xA 1A 、2A 降压转换器1特性•强制PWM 模式可减少输出电压纹波•效率高达95%•低R DS(ON)开关：100m Ω/60m Ω•输入电压范围为2.5V 至5.5V •可调输出电压范围为0.6V 至V IN •100%占空比，可实现超低压降• 1.5MHz 典型开关频率•电源正常输出•过流保护•内部软启动•热关断保护•采用SOT563封装•与TLV62568、TLV62569引脚对引脚兼容•借助WEBENCH ®电源设计器创建定制设计方案2应用•通用负载点(POL)电源•STB 和DVR •IP 网络摄像头•无线路由器•固态硬盘(SSD)–企业级3说明TLV62568A 、TLV62569A 器件是经过优化而具有高效率和紧凑型解决方案尺寸的同步降压型直流/直流转换器。

该器件集成了输出电流高达2A 的开关。

在整个负载范围内，该器件将以1.5MHz 开关频率在脉宽调制(PWM)模式下运行。

关断时，流耗减少至2μA 以下。

内部软启动电路可限制启动期间的浪涌电流。

此外，还内置了诸如输出过流保护、热关断保护和电源正常输出等其他特性。

该器件采用SOT563封装。

器件信息(1)器件型号封装封装尺寸（标称值）TLV62568ADRL SOT563(6)1.60mm x 1.60mmTLV62568APDRL TLV62569ADRL TLV62569APDRL(1)如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

pwscf说明书

User’s Guide for Quantum ESPRESSO(version4.2.0)Contents1Introduction31.1What can Quantum ESPRESSO do (4)1.2People (6)1.3Contacts (8)1.4Terms of use (9)2Installation92.1Download (9)2.2Prerequisites (10)2.3configure (11)2.3.1Manual conﬁguration (13)2.4Libraries (13)2.4.1If optimized libraries are not found (14)2.5Compilation (15)2.6Running examples (17)2.7Installation tricks and problems (19)2.7.1All architectures (19)2.7.2Cray XT machines (19)2.7.3IBM AIX (20)2.7.4Linux PC (20)2.7.5Linux PC clusters with MPI (22)2.7.6Intel Mac OS X (23)2.7.7SGI,Alpha (24)3Parallelism253.1Understanding Parallelism (25)3.2Running on parallel machines (25)3.3Parallelization levels (26)3.3.1Understanding parallel I/O (28)3.4Tricks and problems (29)4Using Quantum ESPRESSO314.1Input data (31)4.2Dataﬁles (32)4.3Format of arrays containing charge density,potential,etc (32)5Using PWscf335.1Electronic structure calculations (33)5.2Optimization and dynamics (35)5.3Nudged Elastic Band calculation (35)6Phonon calculations376.1Single-q calculation (37)6.2Calculation of interatomic force constants in real space (37)6.3Calculation of electron-phonon interaction coeﬃcients (38)6.4Distributed Phonon calculations (38)7Post-processing397.1Plotting selected quantities (39)7.2Band structure,Fermi surface (39)7.3Projection over atomic states,DOS (39)7.4Wannier functions (40)7.5Other tools (40)8Using CP408.1Reaching the electronic ground state (42)8.2Relax the system (43)8.3CP dynamics (45)8.4Advanced usage (47)8.4.1Self-interaction Correction (47)8.4.2ensemble-DFT (48)8.4.3Treatment of USPPs (50)9Performances519.1Execution time (51)9.2Memory requirements (52)9.3File space requirements (52)9.4Parallelization issues (52)10Troubleshooting5410.1pw.x problems (54)10.2PostProc (61)10.3ph.x errors (62)11Frequently Asked Questions(F AQ)6311.1General (63)11.2Installation (63)11.3Pseudopotentials (64)11.4Input data (65)11.5Parallel execution (66)11.6Frequent errors during execution (66)11.7Self Consistency (67)11.8Phonons (69)1IntroductionThis guide covers the installation and usage of Quantum ESPRESSO(opEn-Source Package for Research in Electronic Structure,Simulation,and Optimization),version4.2.0.The Quantum ESPRESSO distribution contains the following core packages for the cal-culation of electronic-structure properties within Density-Functional Theory(DFT),using a Plane-Wave(PW)basis set and pseudopotentials(PP):•PWscf(Plane-Wave Self-Consistent Field).•CP(Car-Parrinello).It also includes the following more specialized packages:•PHonon:phonons with Density-Functional Perturbation Theory.•PostProc:various utilities for data postprocessing.•PWcond:ballistic conductance.•GIPAW(Gauge-Independent Projector Augmented Waves):EPR g-tensor and NMR chem-ical shifts.•XSPECTRA:K-edge X-ray adsorption spectra.•vdW:(experimental)dynamic polarizability.•GWW:(experimental)GW calculation using Wannier functions.The following auxiliary codes are included as well:•PWgui:a Graphical User Interface,producing input dataﬁles for PWscf.•atomic:a program for atomic calculations and generation of pseudopotentials.•QHA:utilities for the calculation of projected density of states(PDOS)and of the free energy in the Quasi-Harmonic Approximation(to be used in conjunction with PHonon).•PlotPhon:phonon dispersion plotting utility(to be used in conjunction with PHonon).A copy of required external libraries are included:•iotk:an Input-Output ToolKit.•PMG:Multigrid solver for Poisson equation.•BLAS and LAPACKFinally,several additional packages that exploit data produced by Quantum ESPRESSO can be installed as plug-ins:•Wannier90:maximally localized Wannier functions(/),writ-ten by A.Mostoﬁ,J.Yates,Y.-S Lee.•WanT:quantum transport properties with Wannier functions.•YAMBO:optical excitations with Many-Body Perturbation Theory.This guide documents PWscf,CP,PHonon,PostProc.The remaining packages have separate documentation.The Quantum ESPRESSO codes work on many diﬀerent types of Unix machines,in-cluding parallel machines using both OpenMP and MPI(Message Passing Interface).Running Quantum ESPRESSO on Mac OS X and MS-Windows is also possible:see section2.2.Further documentation,beyond what is provided in this guide,can be found in:•the pw forum mailing list(pw forum@).You can subscribe to this list,browse and search its archives(links in /contacts.php).Only subscribed users can post.Please search the archives before posting:your question may have already been answered.•the Doc/directory of the Quantum ESPRESSO distribution,containing a detailed de-scription of input data for most codes inﬁles INPUT*.txt and INPUT*.html,plus and a few additional pdf documents;people who want to contribute to Quantum ESPRESSO should read the Developer Manual,developer man.pdf.•the Quantum ESPRESSO Wiki:/wiki/index.php/Main Page.This guide does not explain solid state physics and its computational methods.If you want to learn that,you should read a good textbook,such as e.g.the book by Richard Martin: Electronic Structure:Basic Theory and Practical Methods,Cambridge University Press(2004). See also the Reference Paper section in the Wiki.This guide assume that you know the basic Unix concepts(shell,execution path,directories etc.)and utilities.If you don’t,you will have a hard time running Quantum ESPRESSO.All trademarks mentioned in this guide belong to their respective owners.1.1What can Quantum ESPRESSO doPWscf can currently perform the following kinds of calculations:•ground-state energy and one-electron(Kohn-Sham)orbitals;•atomic forces,stresses,and structural optimization;•molecular dynamics on the ground-state Born-Oppenheimer surface,also with variable cell;•Nudged Elastic Band(NEB)and Fourier String Method Dynamics(SMD)for energy barriers and reaction paths;•macroscopic polarization andﬁnite electricﬁelds via the modern theory of polarization (Berry Phases).All of the above works for both insulators and metals,in any crystal structure,for many exchange-correlation(XC)functionals(including spin polarization,DFT+U,hybrid function-als),for norm-conserving(Hamann-Schluter-Chiang)PPs(NCPPs)in separable form or Ultra-soft(Vanderbilt)PPs(USPPs)or Projector Augmented Waves(PAW)method.Non-collinear magnetism and spin-orbit interactions are also implemented.An implementation ofﬁnite elec-tricﬁelds with a sawtooth potential in a supercell is also available.PHonon can perform the following types of calculations:•phonon frequencies and eigenvectors at a generic wave vector,using Density-Functional Perturbation Theory;•eﬀective charges and dielectric tensors;•electron-phonon interaction coeﬃcients for metals;•interatomic force constants in real space;•third-order anharmonic phonon lifetimes;•Infrared and Raman(nonresonant)cross section.PHonon can be used whenever PWscf can be used,with the exceptions of DFT+U and hybrid functionals.PAW is not implemented for higher-order response calculations.Calculations,in the Quasi-Harmonic approximations,of the vibrational free energy can be performed using the QHA package.PostProc can perform the following types of calculations:•Scanning Tunneling Microscopy(STM)images;•plots of Electron Localization Functions(ELF);•Density of States(DOS)and Projected DOS(PDOS);•L¨o wdin charges;•planar and spherical averages;plus interfacing with a number of graphical utilities and with external codes.CP can perform Car-Parrinello molecular dynamics,including variable-cell dynamics.1.2PeopleIn the following,the cited aﬃliation is either the current one or the one where the last known contribution was done.The maintenance and further development of the Quantum ESPRESSO distribution is promoted by the DEMOCRITOS National Simulation Center of IOM-CNR under the coor-dination of Paolo Giannozzi(Univ.Udine,Italy)and Layla Martin-Samos(Democritos)with the strong support of the CINECA National Supercomputing Center in Bologna under the responsibility of Carlo Cavazzoni.The PWscf package(which included PHonon and PostProc in earlier releases)was origi-nally developed by Stefano Baroni,Stefano de Gironcoli,Andrea Dal Corso(SISSA),Paolo Giannozzi,and many others.We quote in particular:•Matteo Cococcioni(Univ.Minnesota)for DFT+U implementation;•David Vanderbilt’s group at Rutgers for Berry’s phase calculations;•Ralph Gebauer(ICTP,Trieste)and Adriano Mosca Conte(SISSA,Trieste)for noncolinear magnetism;•Andrea Dal Corso for spin-orbit interactions;•Carlo Sbraccia(Princeton)for NEB,Strings method,for improvements to structural optimization and to many other parts;•Paolo Umari(Democritos)forﬁnite electricﬁelds;•Renata Wentzcovitch and collaborators(Univ.Minnesota)for variable-cell molecular dynamics;•Lorenzo Paulatto(Univ.Paris VI)for PAW implementation,built upon previous work by Guido Fratesi(ano Bicocca)and Riccardo Mazzarello(ETHZ-USI Lugano);•Ismaila Dabo(INRIA,Palaiseau)for electrostatics with free boundary conditions.For PHonon,we mention in particular:•Michele Lazzeri(Univ.Paris VI)for the2n+1code and Raman cross section calculation with2nd-order response;•Andrea Dal Corso for USPP,noncollinear,spin-orbit extensions to PHonon.For PostProc,we mention:•Andrea Benassi(SISSA)for the epsilon utility;•Norbert Nemec(U.Cambridge)for the pw2casino utility;•Dmitry Korotin(Inst.Met.Phys.Ekaterinburg)for the wannier ham utility.The CP package is based on the original code written by Roberto Car and Michele Parrinello. CP was developed by Alfredo Pasquarello(IRRMA,Lausanne),Kari Laasonen(Oulu),Andrea Trave,Roberto Car(Princeton),Nicola Marzari(Univ.Oxford),Paolo Giannozzi,and others. FPMD,later merged with CP,was developed by Carlo Cavazzoni,Gerardo Ballabio(CINECA), Sandro Scandolo(ICTP),Guido Chiarotti(SISSA),Paolo Focher,and others.We quote in particular:•Carlo Sbraccia(Princeton)for NEB;•Manu Sharma(Princeton)and Yudong Wu(Princeton)for maximally localized Wannier functions and dynamics with Wannier functions;•Paolo Umari(Democritos)forﬁnite electricﬁelds and conjugate gradients;•Paolo Umari and Ismaila Dabo for ensemble-DFT;•Xiaofei Wang(Princeton)for META-GGA;•The Autopilot feature was implemented by Targacept,Inc.Other packages in Quantum ESPRESSO:•PWcond was written by Alexander Smogunov(SISSA)and Andrea Dal Corso.For an introduction,see http://people.sissa.it/~smogunov/PWCOND/pwcond.html•GIPAW()was written by Davide Ceresoli(MIT),Ari Seitsonen (Univ.Zurich),Uwe Gerstmann,Francesco Mauri(Univ.Paris VI).•PWgui was written by Anton Kokalj(IJS Ljubljana)and is based on his GUIB concept (http://www-k3.ijs.si/kokalj/guib/).•atomic was written by Andrea Dal Corso and it is the result of many additions to the original code by Paolo Giannozzi and others.Lorenzo Paulatto wrote the PAW extension.•iotk(http://www.s3.infm.it/iotk)was written by Giovanni Bussi(SISSA).•XSPECTRA was written by Matteo Calandra(Univ.Paris VI)and collaborators.•VdW was contributed by Huy-Viet Nguyen(SISSA).•GWW was written by Paolo Umari and Geoﬀrey Stenuit(Democritos).•QHA amd PlotPhon were contributed by Eyvaz Isaev(Moscow Steel and Alloy Inst.and Linkoping and Uppsala Univ.).Other relevant contributions to Quantum ESPRESSO:•Andrea Ferretti(MIT)contributed the qexml and sumpdos utility,helped withﬁle formats and with various problems;•Hannu-Pekka Komsa(CSEA/Lausanne)contributed the HSE functional;•Dispersions interaction in the framework of DFT-D were contributed by Daniel Forrer (Padua Univ.)and Michele Pavone(Naples Univ.Federico II);•Filippo Spiga(ano Bicocca)contributed the mixed MPI-OpenMP paralleliza-tion;•The initial BlueGene porting was done by Costas Bekas and Alessandro Curioni(IBM Zurich);•Gerardo Ballabio wrote theﬁrst configure for Quantum ESPRESSO•Audrius Alkauskas(IRRMA),Uli Aschauer(Princeton),Simon Binnie(Univ.College London),Guido Fratesi,Axel Kohlmeyer(UPenn),Konstantin Kudin(Princeton),Sergey Lisenkov(Univ.Arkansas),Nicolas Mounet(MIT),William Parker(Ohio State Univ), Guido Roma(CEA),Gabriele Sclauzero(SISSA),Sylvie Stucki(IRRMA),Pascal Thibaudeau (CEA),Vittorio Zecca,Federico Zipoli(Princeton)answered questions on the mailing list, found bugs,helped in porting to new architectures,wrote some code.An alphabetical list of further contributors includes:Dario Alf`e,Alain Allouche,Francesco Antoniella,Francesca Baletto,Mauro Boero,Nicola Bonini,Claudia Bungaro,Paolo Cazzato, Gabriele Cipriani,Jiayu Dai,Cesar Da Silva,Alberto Debernardi,Gernot Deinzer,Yves Ferro, Martin Hilgeman,Yosuke Kanai,Nicolas Lacorne,Stephane Lefranc,Kurt Maeder,Andrea Marini,Pasquale Pavone,Mickael Profeta,Kurt Stokbro,Paul Tangney,Antonio Tilocca,Jaro Tobik,Malgorzata Wierzbowska,Silviu Zilberman,and let us apologize to everybody we have forgotten.This guide was mostly written by Paolo Giannozzi.Gerardo Ballabio and Carlo Cavazzoni wrote the section on CP.1.3ContactsThe web site for Quantum ESPRESSO is /.Releases and patches can be downloaded from this site or following the links contained in it.The main entry point for developers is the QE-forge web site:/.The recommended place where to ask questions about installation and usage of Quantum ESPRESSO,and to report bugs,is the pw forum mailing list:pw forum@.Here you can receive news about Quantum ESPRESSO and obtain help from the developers and from knowledgeable users.You have to be subscribed in order to post to the list.Please browse or search the archive–links are available in the”Contacts”page of the Quantum ESPRESSO web site,/contacts.php–before posting: many questions are asked over and over again.NOTA BENE:only messages that appear to come from the registered user’s e-mail address,in its exact form,will be accepted.Messages”waiting for moderator approval”are automatically deleted with no further processing(sorry,too much spam).In case of trouble,carefully check that your return e-mail is the correct one(i.e.the one you used to subscribe).Since pw forum averages∼10message a day,an alternative low-traﬃc mailing list,pw users@,is provided for those interested only in Quantum ESPRESSO-related news,such as e.g.announcements of new versions,tutorials,etc..You can subscribe(but not post)to this list from the Quantum ESPRESSO web site.If you need to contact the developers for speciﬁc questions about coding,proposals,oﬀersof help,etc.,send a message to the developers’mailing list:user q-e-developers,address.1.4Terms of useQuantum ESPRESSO is free software,released under the GNU General Public License. See /licenses/old-licenses/gpl-2.0.txt,or theﬁle License in the distribution).We shall greatly appreciate if scientiﬁc work done using this code will contain an explicit acknowledgment and the following reference:P.Giannozzi,S.Baroni,N.Bonini,M.Calandra,R.Car,C.Cavazzoni,D.Ceresoli,G.L.Chiarotti,M.Cococcioni,I.Dabo,A.Dal Corso,S.Fabris,G.Fratesi,S.deGironcoli,R.Gebauer,U.Gerstmann,C.Gougoussis,A.Kokalj,zzeri,L.Martin-Samos,N.Marzari,F.Mauri,R.Mazzarello,S.Paolini,A.Pasquarello,L.Paulatto, C.Sbraccia,S.Scandolo,G.Sclauzero, A.P.Seitsonen, A.Smo-gunov,P.Umari,R.M.Wentzcovitch,J.Phys.:Condens.Matter21,395502(2009),/abs/0906.2569Note the form Quantum ESPRESSO for textual citations of the code.Pseudopotentials should be cited as(for instance)[]We used the pseudopotentials C.pbe-rrjkus.UPF and O.pbe-vbc.UPF from.2Installation2.1DownloadPresently,Quantum ESPRESSO is only distributed in source form;some precompiled exe-cutables(binaryﬁles)are provided only for PWgui.Stable releases of the Quantum ESPRESSO source package(current version is4.2.0)can be downloaded from this URL:/download.php.Uncompress and unpack the core distribution using the command:tar zxvf espresso-X.Y.Z.tar.gz(a hyphen before”zxvf”is optional)where X.Y.Z stands for the version number.If your version of tar doesn’t recognize the”z”ﬂag:gunzip-c espresso-X.Y.Z.tar.gz|tar xvf-A directory espresso-X.Y.Z/will be created.Given the size of the complete distribution,you may need to download more packages and to unpack them following the same procedure(they will unpack into the same directory).Plug-ins should instead be downloaded into subdirectory plugin/archive but not unpacked or uncompressed:command make will take care of this during installation.Occasionally,patches for the current version,ﬁxing some errors and bugs,may be distributed as a”diﬀ”ﬁle.In order to install a patch(for instance):cd espresso-X.Y.Z/patch-p1</path/to/the/diff/file/patch-file.diffIf more than one patch is present,they should be applied in the correct order.Daily snapshots of the development version can be downloaded from the developers’site :follow the link”Quantum ESPRESSO”,then”SCM”.Beware:the develop-ment version is,well,under development:use at your own risk!The bravest may access the development version via anonymous CVS(Concurrent Version System):see the Developer Manual(Doc/developer man.pdf),section”Using CVS”.The Quantum ESPRESSO distribution contains several directories.Some of them are common to all packages:Modules/sourceﬁles for modules that are common to all programsinclude/ﬁles*.h included by fortran and C sourceﬁlesclib/external libraries written in Cflib/external libraries written in Fortraniotk/Input/Output Toolkitinstall/installation scripts and utilitiespseudo/pseudopotentialﬁles used by examplesupftools/converters to uniﬁed pseudopotential format(UPF)examples/sample input and outputﬁlesDoc/general documentationwhile others are speciﬁc to a single package:PW/PWscf:sourceﬁles for scf calculations(pw.x)pwtools/PWscf:sourceﬁles for miscellaneous analysis programstests/PWscf:automated testsPP/PostProc:sourceﬁles for post-processing of pw.x dataﬁlePH/PHonon:sourceﬁles for phonon calculations(ph.x)and analysisGamma/PHonon:sourceﬁles for Gamma-only phonon calculation(phcg.x)D3/PHonon:sourceﬁles for third-order derivative calculations(d3.x)PWCOND/PWcond:sourceﬁles for conductance calculations(pwcond.x)vdW/VdW:sourceﬁles for molecular polarizability calculation atﬁnite frequency CPV/CP:sourceﬁles for Car-Parrinello code(cp.x)atomic/atomic:sourceﬁles for the pseudopotential generation package(ld1.x) atomic doc/Documentation,tests and examples for atomicGUI/PWGui:Graphical User Interface2.2PrerequisitesTo install Quantum ESPRESSO from source,you needﬁrst of all a minimal Unix envi-ronment:basically,a command shell(e.g.,bash or tcsh)and the utilities make,awk,sed. MS-Windows users need to have Cygwin(a UNIX environment which runs under Windows) installed:see /.Note that the scripts contained in the distribution assume that the local language is set to the standard,i.e.”C”;other settings may break them. Use export LC ALL=C(sh/bash)or setenv LC ALL C(csh/tcsh)to prevent any problem when running scripts(including installation scripts).Second,you need C and Fortran-95compilers.For parallel execution,you will also need MPI libraries and a“parallel”(i.e.MPI-aware)compiler.For massively parallel machines,or for simple multicore parallelization,an OpenMP-aware compiler and libraries are also required.Big machines with specialized hardware(e.g.IBM SP,CRAY,etc)typically have a Fortran-95compiler with MPI and OpenMP libraries bundled with the software.Workstations or“commodity”machines,using PC hardware,may or may not have the needed software.If not,you need either to buy a commercial product(e.g Portland)or to install an open-source compiler like gfortran or g95.Note that several commercial compilers are available free of charge under some license for academic or personal usage(e.g.Intel,Sun).2.3configureTo install the Quantum ESPRESSO source package,run the configure script.This is ac-tually a wrapper to the true configure,located in the install/subdirectory.configure will(try to)detect compilers and libraries available on your machine,and set up things accordingly. Presently it is expected to work on most Linux32-and64-bit PCs(all Intel and AMD CPUs)and PC clusters,SGI Altix,IBM SP machines,NEC SX,Cray XT machines,Mac OS X,MS-Windows PCs.It may work with some assistance also on other architectures(see below).Instructions for the impatient:cd espresso-X.Y.Z/./configuremake allSymlinks to executable programs will be placed in the bin/subdirectory.Note that both Cand Fortran compilers must be in your execution path,as speciﬁed in the PATH environment variable.Additional instructions for CRAY XT,NEC SX,Linux PowerPC machines with xlf:./configure ARCH=crayxt4./configure ARCH=necsx./configure ARCH=ppc64-mnconfigure Generates the followingﬁles:install/make.sys compilation rules andﬂags(used by Makefile)install/configure.msg a report of the conﬁguration run(not needed for compilation)install/config.log detailed log of the conﬁguration run(may be needed for debugging) include/fft defs.h deﬁnes fortran variable for C pointer(used only by FFTW)include/c defs.h deﬁnes C to fortran calling conventionand a few more deﬁnitions used by CﬁlesNOTA BENE:unlike previous versions,configure no longer runs the makedeps.sh shell scriptthat updates dependencies.If you modify the sources,run./install/makedeps.sh or type make depend to updateﬁles make.depend in the various subdirectories.You should always be able to compile the Quantum ESPRESSO suite of programs without having to edit any of the generatedﬁles.However you may have to tune configure by specifying appropriate environment variables and/or command-line ually the tricky part is toget external libraries recognized and used:see Sec.2.4for details and hints.Environment variables may be set in any of these ways:export VARIABLE=value;./configure#sh,bash,kshsetenv VARIABLE value;./configure#csh,tcsh./configure VARIABLE=value#any shellSome environment variables that are relevant to configure are:ARCH label identifying the machine type(see below)F90,F77,CC names of Fortran95,Fortran77,and C compilersMPIF90name of parallel Fortran95compiler(using MPI)CPP sourceﬁle preprocessor(defaults to$CC-E)LD linker(defaults to$MPIF90)(C,F,F90,CPP,LD)FLAGS compilation/preprocessor/loaderﬂagsLIBDIRS extra directories where to search for librariesFor example,the following command line:./configure MPIF90=mpf90FFLAGS="-O2-assume byterecl"\CC=gcc CFLAGS=-O3LDFLAGS=-staticinstructs configure to use mpf90as Fortran95compiler withﬂags-O2-assume byterecl, gcc as C compiler withﬂags-O3,and to link withﬂag-static.Note that the value of FFLAGS must be quoted,because it contains spaces.NOTA BENE:do not pass compiler names with the leading path included.F90=f90xyz is ok,F90=/path/to/f90xyz is not.Do not use environmental variables with configure unless they are needed!try configure with no options as aﬁrst step.If your machine type is unknown to configure,you may use the ARCH variable to suggest an architecture among supported ones.Some large parallel machines using a front-end(e.g. Cray XT)will actually need it,or else configure will correctly recognize the front-end but not the specialized compilation environment of those machines.In some cases,cross-compilation requires to specify the target machine with the--host option.This feature has not been extensively tested,but we had at least one successful report(compilation for NEC SX6on a PC).Currently supported architectures are:ia32Intel32-bit machines(x86)running Linuxia64Intel64-bit(Itanium)running Linuxx8664Intel and AMD64-bit running Linux-see note belowaix IBM AIX machinessolaris PC’s running SUN-Solarissparc Sun SPARC machinescrayxt4Cray XT4/5machinesmacppc Apple PowerPC machines running Mac OS Xmac686Apple Intel machines running Mac OS Xcygwin MS-Windows PCs with Cygwinnecsx NEC SX-6and SX-8machinesppc64Linux PowerPC machines,64bitsppc64-mn as above,with IBM xlf compilerNote:x8664replaces amd64since v.4.1.Cray Unicos machines,SGI machines with MIPS architecture,HP-Compaq Alphas are no longer supported since v.4.2.0.Finally,configure recognizes the following command-line options:--enable-parallel compile for parallel execution if possible(default:yes)--enable-openmp compile for openmp execution if possible(default:no)--enable-shared use shared libraries if available(default:yes)--disable-wrappers disable C to fortran wrapper check(default:enabled)--enable-signals enable signal trapping(default:disabled)and the following optional packages:--with-internal-blas compile with internal BLAS(default:no)--with-internal-lapack compile with internal LAPACK(default:no)--with-scalapack use ScaLAPACK if available(default:yes)If you want to modify the configure script(advanced users only!),see the Developer Manual.2.3.1Manual conﬁgurationIf configure stops before the end,and you don’tﬁnd a way toﬁx it,you have to write working make.sys,include/fft defs.h and include/c defs.hﬁles.For the latter twoﬁles,follow the explanations in include/defs.h.README.If configure has run till the end,you should need only to edit make.sys.A few templates (each for a diﬀerent machine type)are provided in the install/directory:they have names of the form Make.system,where system is a string identifying the architecture and compiler.The template used by configure is also found there as make.sys.in and contains explanations of the meaning of the various variables.The diﬃcult part will be to locate libraries.Note that you will need to select appropriate preprocessingﬂags in conjunction with the desired or available libraries(e.g.you need to add-D FFTW)to DFLAGS if you want to link internal FFTW).For a correct choice of preprocessingﬂags,refer to the documentation in include/defs.h.README.NOTA BENE:If you change any settings(e.g.preprocessing,compilationﬂags)after a previous(successful or failed)compilation,you must run make clean before recompiling,unless you know exactly which routines are aﬀected by the changed settings and how to force their recompilation.2.4LibrariesQuantum ESPRESSO makes use of the following external libraries:•BLAS(/blas/)and•LAPACK(/lapack/)for linear algebra•FFTW(/)for Fast Fourier TransformsA copy of the needed routines is provided with the distribution.However,when available, optimized vendor-speciﬁc libraries should be used:this often yields huge performance gains. BLAS and LAPACK Quantum ESPRESSO can use the following architecture-speciﬁc replacements for BLAS and LAPACK:MKL for Intel Linux PCsACML for AMD Linux PCsESSL for IBM machinesSCSL for SGI AltixSUNperf for SunIf none of these is available,we suggest that you use the optimized ATLAS library:see /.Note that ATLAS is not a complete replacement for LAPACK:it contains all of the BLAS,plus the LU code,plus the full storage Cholesky code. Follow the instructions in the ATLAS distributions to produce a full LAPACK replacement.Sergei Lisenkov reported success and good performances with optimized BLAS by Kazushige Goto.They can be freely downloaded,but not redistributed.See the”GotoBLAS2”item at /tacc-projects/.FFT Quantum ESPRESSO has an internal copy of an old FFTW version,and it can use the following vendor-speciﬁc FFT libraries:IBM ESSLSGI SCSLSUN sunperfNEC ASLAMD ACMLconfigure willﬁrst search for vendor-speciﬁc FFT libraries;if none is found,it will search for an external FFTW v.3library;if none is found,it will fall back to the internal copy of FFTW.If you have recent versions of MKL installed,you may try the FFTW interface provided with MKL.You will have to compile them(only sources are distributed with the MKL library) and to modifyﬁle make.sys accordingly(MKL must be linked after the FFTW-MKL interface)MPI libraries MPI libraries are usually needed for parallel execution(unless you are happy with OpenMP multicore parallelization).In well-conﬁgured machines,configure shouldﬁnd the appropriate parallel compiler for you,and this shouldﬁnd the appropriate libraries.Since often this doesn’t happen,especially on PC clusters,see Sec.2.7.5.Other libraries Quantum ESPRESSO can use the MASS vector math library from IBM, if available(only on AIX).2.4.1If optimized libraries are not foundThe configure script attempts toﬁnd optimized libraries,but may fail if they have been in-stalled in non-standard places.You should examine theﬁnal value of BLAS LIBS,LAPACK LIBS, FFT LIBS,MPI LIBS(if needed),MASS LIBS(IBM only),either in the output of configure or in the generated make.sys,to check whether it found all the libraries that you intend to use.If some library was not found,you can specify a list of directories to search in the envi-ronment variable LIBDIRS,and rerun configure;directories in the list must be separated by spaces.For example:./configure LIBDIRS="/opt/intel/mkl70/lib/32/usr/lib/math"If this still fails,you may set some or all of the*LIBS variables manually and retry.For example:./configure BLAS_LIBS="-L/usr/lib/math-lf77blas-latlas_sse"Beware that in this case,configure will blindly accept the speciﬁed value,and won’t do any extra search.。

稳压管大全

简易开关电源稳压器(3A可调1.23V to 37V)
LM2576HVT-3.3
3.3V简易开关电源稳压器(3A)
LM2576HVT-5.0
5.0V简易开关电源稳压器(3A)
LM2576HVT-12
12V简易开关电源稳压器(3A)
LM2576HVT-15
15V简易开关电源稳压器(3A)
LM2576HVT-ADJ
简易开关电源稳压器(3A可调1.23V to 37V)
LM2930T-5.0
5.0V低压差稳压器
LM2930T-8.0
8.0V低压差稳压器
LM2931AZ-5.0
5.0V低压差稳压器(TO-92)
LM2931T-5.0
5.0V低压差稳压器
LM2931CT
3V to 29V低压差稳压器(TO-2205PIN)
通用型双运算放大器
HA17358/LM358P(TI)
LM380
音频功率放大器
NS[DATA]
LM386-1 NS[DATA]
音频放大器
NJM386DUTC386
LM386-3
音频放大器
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LM386-4
音频放大器
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LM3886
音频大功率放大器
NS[DATA]
LM3900
四运算放大器
LM133K(NS)
三端可调-1.2V to -37V稳压器(3.0A)
LM333K(NS)
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LM337K(NS)
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LM337T(NS)
三端可调-1.2V to -37V稳压器(1.5A)

W567S210中文资料

W567SXXX Data Sheet8-CHANNEL SPEECH+MELODY PROCESSOR(BandDirector TM Series)Publication Release Date: June 15, 2004Table of Contents-1. GENERAL DESCRIPTION.........................................................................................................22. FEATURES.................................................................................................................................33. PIN DESCRIPTION.....................................................................................................................44. BLOCK DIAGRAM......................................................................................................................55.ELECTRICAL CHARACTERISTICS...........................................................................................6 5.1 Absolute Maximum Ratings...............................................................................................6 5.2 D.C. Characteristics...........................................................................................................6 5.3 A.C. Characteristics...........................................................................................................7 6.TYPICAL APPLICATION CIRCUITS..........................................................................................8 6.1 W567S010~S030..............................................................................................................8 6.2 W567S040~S060..............................................................................................................9 6.3 W567S080~S341............................................................................................................10 6.4 W567S301/S341 with ADC Application...........................................................................11 7.REVISION HISTORY (12)W567SXXX1. GENERAL DESCRIPTIONThe W567Sxxx is a powerful microcontroller (uC) dedicated to speech and melody synthesis applications. With the help of the embedded 8-bit microprocessor & dedicated H/W, the W567Sxxx can synthesize 8-channel speech+melody simultaneously.The two channels of synthesized speech can be in different kinds of format, for example ADPCM and MDPCM. The W567Sxxx can provide 8-channel high-quality WinMelody TM , which can emulate the characteristics of musical instruments, such as piano and violin. The output of speech/melody channels are mixed together through the on-chip digital mixer to produce colorful effects. The mixer is further processed to drive dual speakers with stereo effects. With these hardware resources, the W567Sxxx is very suitable for high-quality and sophisticated scenario applications.The W567Sxxx is also capable of transmitting infrared (IR) signals with on-chip carrier generator. As a result, toys can be designed to interact with each other for more play values. A serial interface can be supported as external memory for memory expansion or content-updateable applications.Besides, the W567Sxxx is equipped with a 4-channel Analog-to-Digital Converter (ADC). With ADC, a toy can respond to environment conditions such as temperature or pressure via sensory devices. Therefore, toys with ADC can behave vividly than ever before.The W567Sxxx family contains several items with different playback duration as shown below: (@5-bit MDPCM algorithm, 6 KHz sampling rate)Item W567S010 W567S015 W567S020 W567S025 W567S030 W567S040*Duration 14 sec. 18 sec. 27 sec. 31 sec. 35 sec. 52 sec.Item W567S060 W567S080 W567S100 W567S120 W567S150 W567S170 Duration 60 sec. 104 sec. 116 sec. 129 sec. 163 sec. 197 sec.Item W567S210 W567S260 W567S301 W567S341Duration 232 sec. 265 sec. 300 sec. 334 sec.Note: *: The duration time is based on 5-bit MDPCM at 6 KHz sampling rate. The firmware library and timber library have been xcluded from user’s ROM space for the duration estimation.W567SXXXPublication Release Date: June 15, 20042. FEATURES• Wide range of operating voltage:− 8 MHz @ 3.6 volt ~ 5.5 volt − 4 MHz @ 2.4 volt ~ 5.5 volt• Power management:− 4 ~ 8 MHz system clocks, with Ring type− Stop mode for stopping all IC operations• Provides up to 8 inputs and 24 I/O pins• Current-type Digital-to-Analog Converter (DAC): − (8+2)-bit resolution with programmable output current− 2 speaker outputs for stereo applications• F/W speech synthesis with multiple format support: ADPCM/MDPCM/PCM • 2 speech synthesis 1 channels at programmable sample rate• 8 melody channels that can emulate characteristics of musical instruments • 8-input/10-bit-resolution Mixer can mix the speech and melody signals flexibly• Dynamic control of the channel assignment to the dual speaker output for stereo effects • Built-in IR carrier generation circuit for simplifying firmware IR application• 4-channel ADC interface (W567S301~S341) with maximum 4-KHz sampling rate and 6-biteffective resolution • Built-in 9 timers for speech/melody synthesis and general purpose applications • Built-in 10*7 multiplier• Built-in Watch-Dog Timer (WDT) and Low Voltage Reset (LVR)• Built-in 32KHz crystal oscillator with divider for time-keeping application in W567S080 ~ S341 • Built-in Serial Interface Manager (SIM) in W567S080 ~ S341 • Support PowerScript for developing codes in easy way • Full-fledged development system − Source-level ICE debugger− Event synchronization mechanism− Compatible with W566B/C & W588S system − User-friendly GUI environment• Available package form: (COB is essential)− W 567S010, S015, S020, S025, S030: LQFP48 − W 567S040, S060: QFP64 − W 567S080 ~ S120: LQFP80− W 567S150 ~ S341: LQFP1001More speech channels are available for 8-bit PCM format in the remaining melody channels.W567SXXX3. PIN DESCRIPTIONPIN NAMEI/OFUNCTIONRESETB InIC reset input, low active.XIN In 32 KHz crystal oscillator with divider for time-keeping application XOUTOut32 KHz crystal oscillator with divider for time-keeping applicationOSC InMain-clock oscillation input. Only Ring type is used. Connect to GND via theoscillation resistor.IP0[3:0] / IP0[7:4]In General input port with pull-high selection. Each 2 input pins can be programmed to generate interrupt request and used to release IC fromSTOP mode. IP0[3:0] are used as the input of ADC. IP0.0 is the input pin of channel 0 and IP0.3 is the input pin of channel 3, and so on.BP0[7:0] I/O General input/output pins. When used as output pin, it can be open–drain or CMOS type and it can sink 8mA for high-current applications. When used as input pin, there may have a pull-high option and generate interruptrequest to release IC from STOP mode.When BP0[7] is used as output pin, it can be the IR transmission carrier for IR applications.BP1[7:0]I/O General input/output pins. When used as output pin, it can be open–drainor CMOS type. When used as input pin, there may have a pull-high optionand generate interrupt request to release IC from STOP mode. When serial interface is enabled, BP1[6:4] are used as serial interface pins. BP2[7:0]I/OGeneral input/output pins. When used as output pin, it can be open–drain or CMOS type. When used as input pin, there may have a pull-high option and generate interrupt request to release IC from STOP mode.2VRB OutReference-bottom voltage of ADC. Theoretically, the converted codes 0 ~255 will be uniformly distributed between VRB and AVDD. Voltages below VRB will be mapped to code 0.2CIN In Capacitor input for ADC. 2COUT Out Capacitor output for ADC. 2AVDD Out ADC regulator output voltage. DAC0 Out Current type DAC speaker output 0. DAC1 Out Current type DAC speaker output 1. TEST In Test input, internally pulled low. Do not connect during normal operation. V DD Power Positive power supply for µP and peripherals. V SS Power Negative power supply for µP and peripherals. 3VDDOSC Power Positive power supply for oscillation. 3VSSOSC Power Negative power supply for oscillation. 2VDDA Power Positive power supply for ADC module. 2VSSA Power Negative power supply for ADC module.2 Only W567S301~S341 provides these pins for ADC application.3In order to get a stable oscillating frequency, W567S080~S341 provides these pins for power supply.W567SXXXPublication Release Date: June 15, 20044. BLOCK DIAGRAMDAC0DAC1or VRB CIN IP0[3:0]COUTW567SXXX5. ELECTRICAL CHARACTERISTICS5.1 Absolute Maximum RatingsPARAMETER RATINGUNIT Supply Voltage to Ground Potential -0.3 to +7.0 VD.C. Voltage on Any Pin to Ground Potential -0.3 to V DD +0.3 VOperating Temperature 0 to +70 °CStorage Temperature -55 to +150 °CNote: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.5.2 D.C. Characteristics(V DD−V SS = 4.5 V, F M = 8 MHz, Ta = 25°C, No Load unless otherwise specified)SPEC.PARAMETER SYM. TESTCONDITIONSMin. Typ. Max.UNITF SYS = 4 MHz 2.4 - 5.5 VOperating Voltage V DDF SYS = 8 MHz 3.6 - 5.5 VOperating Current I OP F SYS = F M, normaloperation- 15 20 mAStandby Current I SB STOPmode - 1 2 µA32KHz Crystal current I32K F OSC disable, No load, Wakeup frequency: 2Hz- 6 15 µAInput Low Voltage V IL All input pins V SS - 0.3V DD V Input High Voltage V IH All input pins 0.7 V DD - V DD VV OUT = 0.4V, all output pins except BP0 - - 4 mAOutput Low Current I OLV OUT = 0.4V, BP0 only - - 8 mA Output High Current I OH V OUT = 2.4V, all output pins -4 - - mADAC Full Scale Current I DAC V DD = 4.5V, RL = 100Ω-2.4-4.0-3.0-5.0-3.6-6.0mAADC Analog InputVoltageV AN V RB - AV DD V ADC Reference-BottomVoltageV RB I RB ≦ 6 mA 0.6 0.8 1.0 V ADC Input Impendence R ADC30 - - MΩOperation Current ofLow Voltage ResetI LVR V DD = 4.5V 60 uAAll input pins except RESETB 200 - - KΩPull High Resistance R INRESERB 100--KΩW567SXXXPublication Release Date: June 15, 2004 5.3 A.C. Characteristics(V DD -V SS = 4.5 V, F M = 8 MHz, Ta = 25°C; No Load unless otherwise specified)*: Typical ROSC value for each part number should refer to design guide.4AV DD is a fixed voltage, for example AV DD = 3.6V, 4.5V, or 5.5V.W567SXXX6. TYPICAL APPLICATION CIRCUITS6.1 W567S010~S030Notes:1. The typical value of Rosc is 150 K Ω for 8MHz and 300 K Ω for 4MHz and should be connected to GND (V SS ).2. Please refer to design guide to get typical Rosc value for each part number.3. The Rs value is suggested in 270Ω ~ 1K Ω to limit too large DAC output current flowing into transistor.4. The capacitor, 4.7µF, shunts between V DD and GND is necessary as power stability. But the value of capacitor isdepend on the application. 5. The above application circuits are for reference only. No warranty for mass production.W567SXXXPublication Release Date: June 15, 20046.2 W567S040~S060Notes:1.The typical value of Rosc is 160 K Ω for 8MHz and 330 K Ω for 4MHz and should be connected to GND (V SS ). 2. Please refer to design guide to get typical Rosc value for each part number.3. The Rs value is suggested in 270Ω ~ 1K Ω to limit too large DAC output current flowing into transistor.4. The capacitor, 4.7uF, shunts between V DD and GND is necessary as power stability. But the value of capacitor is depend on the application.5.The above application circuits are for reference only. No warranty for mass production.W567SXXX6.3 W567S080~S341Notes:1. The typical value of Rosc is 150 K Ω for 8MHz and 300 K Ω for 4MHz and should be connected to GND (V SS ).2. Please refer to design guide to get typical Rosc value for each part number.3. For W567S080~S341, VSSOSC should be connected to V SS ; and VDDOSC should be connected to V DD in PCB layout.4. The Rs value is suggested in 270Ω ~ 1K Ω to limit too large DAC output current flowing into transistor.5. The 10Ω and 0.1µF between V DD , VDDOSC and GND are optional to filter power noise.6. The capacitor, 4.7µF, shunts between V DD and GND is necessary as power stability. But the value of capacitor is depend on the application.7.The above application circuits are for reference only. No warranty for mass production.W567SXXXPublication Release Date: June 15, 2004- 11 -Revision A116.4 W567S301/S341 with ADC ApplicationNotes:1. The typical value of Rosc is 150 K Ω for 8MHz and 300 K Ω for 4MHz and should be connected to GND (V SS ).2. Please refer to design guide to get typical Rosc value for each part number.3. For W567S301~S341, VSSA and VSSOSC should be connected to V SS ; and VDDA and VDDOSC should beconnected to V DD in PCB layout.4. The Rs value is suggested in 270Ω ~ 1K Ω to limit too large DAC output current flowing into transistor.5. The 10Ω and 0.1µF between V DD , VDDOSC and GND are optional to filter power noise.6. The capacitor, 4.7µF, shunts between V DD and GND is necessary as power stability. But the value of capacitor isdepend on the application.7. The above application circuits are for reference only. No warranty for mass production.W567SXXX- 12 -7. REVISION HISTORYREVISION DATEMODIFICATIONSA1 April 2002 Preliminary release. A2July 11, 2002W567S020 created.2 speech channels for entire series. Wording modification. A3 July 31, 2002 Modify pin descriptionModify DC/AC electrical characteristics A4 Oct. 15, 2002 Remove SIM out of from W567S040 ~ S060Define ROSC value in AC ELECTRICAL CHARACTERI A5Nov. 15, 2002Page 2, provides up to 8 input pins Page 2, available packageA6 May 15, 2003 Add a table to show all W567Sxxx duration in page 1 Add PowerScript TM function in feature listUpdate available package Rename RTC as 32 KHz crystal Update application circuitA7 Sep 10, 2003 Change part number W567S300 as W567S301Change part number W567S340 as W567S341 Page 3, add Low Voltage Detect (LVD) feature A8 Oct. 15, 2003 Update application circuit and notes.A9 Nov 17, 2003 Rename VDD1 to VDDOSC in the Pin Description Update application circuit and notes.A10 March 16, 2004 Change the name Low-Voltage-Detect (LVD) to Low-Voltage-Reset(LVR).A11June 15, 2004Add the operation current of Low-Voltage-Reset.W567SXXXPublication Release Date: June 15, 2004- 13 -Revision A11HeadquartersNo. 4, Creation Rd. III,Science-Based Industrial Park,Hsinchu, Taiwan TEL: 886-3-5770066FAX: 886-3-5665577/Taipei Office TEL: 886-2-8177-7168FAX: 886-2-8751-3579Winbond Electronics Corporation America2727 North First Street, San Jose,CA 95134, U.S.A.TEL: 1-408-9436666FAX: 1-408-5441798Winbond Electronics (H.K.) Ltd.No. 378 Kwun Tong Rd., Kowloon, Hong Kong FAX: 852-********Unit 9-15, 22F, Millennium City, TEL: 852-********Please note that all data and specifications are subject to change without notice.All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.Winbond Electronics (Shanghai) Ltd.200336 ChinaFAX: 86-21-6236599827F, 2299 Yan An W. Rd. Shanghai, TEL: 86-21-62365999Winbond Electronics Corporation JapanShinyokohama Kohoku-ku, Yokohama, 222-0033FAX: 81-45-47818007F Daini-ueno BLDG, 3-7-18 TEL: 81-45-47818819F, No.480, Rueiguang Rd.,Neihu District, Taipei, 114,Taiwan, R.O.C.。

TEA5757自调谐器无线接器

TEA5757; TEA5759- -自调谐无线电接收器(STR)
概述：TEA5757；TEA5759为44脚AM/FM集成立体声无线电接收电路，应用新的调谐方式。无线电部分以TEA5712为基础。它具有调谐质量优良，无需IF-计数据器便可实现停止检测；对陶瓷滤波器的误差无严格要求。配合微控制器，可实现快速、低功率的预设模式、人工搜索、自动搜索及自动存储等操作特性。
10
AFO
AM/FM FM输出（输出阻抗标准：5kΩ）
32
AFC
450kHz LC电路
11
MPXI
立体声解Байду номын сангаас器输入（输入阻抗标准：150kΩ）
33
FM-IFI2
FMIF输入2（输入阻抗标准：330Ω）
12
LFI
环路滤波器输入
34
VSTAB（B）
内部稳定供电电压（B）
13
MUTE
静音输入
35
FM-IFO1
FMIF输出1（输出阻抗标准：330Ω）
14
AFLO
左通道输出（输出阻抗标准：4.3kΩ）
36
AM-IFI/O2
输入/输出至IF-振荡器（IFT）；输出：电流源
15
AFRO
右通道输出（输出阻抗标准：4.3kΩ）
37
FM-IFI1
FMIF输入1（输入阻抗标准：330Ω）
16
PILFIL
引导检波滤波器输入
在TCL **机型上测定
序号
符号
功能
直流电压（V）
序号
符号
功能
直流电压（V）
1
RIPPLE
纹波电容输入
23
VDDD
数字供电电压

mpc5674f 单片机参考手册说明书

MPC5674F MicrocontrollerReference ManualDevices Supported:MPC5674FMPC5673FMPC5674FRMRev. 7Feb 2015This page is intentionally left blank.MPC5674F Microcontroller Reference Manual, Rev. 7ii Freescale SemiconductorTable of ContentsChapter1Device Overview1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.1.1MPC5500 and MPC5600 Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41.2.1Critical Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41.2.2Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51.2.3Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51.2.4Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51.2.5Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-61.2.6Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-91.2.6.1 High-Performance e200z7 Core Processor . . . . . . . . . . . . . . . . . . . . . 1-91.2.6.2 Crossbar Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-101.2.6.3 Enhanced Direct Memory Access Controller (eDMA2) . . . . . . . . . . . . 1-101.2.6.4 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111.2.6.5 Frequency-Modulated PLL (FMPLL) . . . . . . . . . . . . . . . . . . . . . . . . . 1-121.2.6.6 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-121.2.6.7 System Integration Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-131.2.6.8 Error Correction Status Module (ECSM) . . . . . . . . . . . . . . . . . . . . . . 1-141.2.6.9 On-Chip Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-141.2.6.10 General-Purpose Static RAM (SRAM) . . . . . . . . . . . . . . . . . . . . . . . 1-151.2.6.11 Boot Assist Module (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-151.2.6.12 Enhanced Modular Input Output System (eMIOS) . . . . . . . . . . . . . . 1-151.2.6.13 Enhanced Timing Processor Unit (eTPU2) . . . . . . . . . . . . . . . . . . . . 1-161.2.6.14 Enhanced Queued Analog to Digital Converter (eQADC) . . . . . . . . 1-171.2.6.15 Deserial Serial Peripheral Interface Module (DSPI) . . . . . . . . . . . . . 1-181.2.6.16 Enhanced Serial Communication Interface Module (eSCI) . . . . . . . 1-191.2.6.17 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-201.2.6.18 Dual-Channel FlexRay Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-211.2.6.19 Nexus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-221.2.6.20 System Timer Module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-231.2.6.21 Software Watchdog Timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-231.2.6.22 Periodic Interrupt Timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-241.2.6.23 JTAG Controller (JTAGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-241.2.6.24 Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.3Developer Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25Chapter2Signal Descriptions2.1Pin Function Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1MPC5674F Microcontroller Reference Manual Rev. 7Freescale Semiconductor Table of Contents-i2.1.1Pad Configuration Register (PCR) PA Definition . . . . . . . . . . . . . . . . . . . . . . . 2-12.1.2LVDS Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2External Signal Descriptions, Pin Multiplexing, and Attributes . . . . . . . . . . . . . . . . . . . 2-3 2.3Detailed Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-552.3.1eTPU Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-552.3.2IRQ and GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-562.3.3eMIOS Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-572.3.4eQADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-582.3.5FlexRay Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-592.3.6FlexCAN Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-592.3.7eSCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-602.3.8DSPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-602.3.9EBI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-622.3.10Reset and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-642.3.11JTAG and Nexus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-642.3.12PMC and Power/Voltage Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66Chapter3Resets3.1Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2Reset Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23.3.1RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23.3.2RSTOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4FMPLL Lock Gating Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.5Reset Source Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33.5.1Power-on Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63.5.2External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63.5.3Loss of Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63.5.4Loss of Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73.5.5Core Watchdog Timer/Debug Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73.5.6JTAG Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73.5.7Software System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83.5.8Software External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.6Reset Registers in the SIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.7Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93.7.1Reset Configuration Half Word (RCHW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93.7.1.1 RCHW Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93.7.1.2 RCHW Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93.7.2Reset Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113.7.3Reset Weak Pull Up/Down Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11MPC5674F Microcontroller Reference Manual Rev. 7Table of Contents-ii Freescale SemiconductorChapter4Power Management Controller (PMC)4.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14.1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14.1.1.1 Features of the Analog Portion of PMC_SMPS . . . . . . . . . . . . . . . . . . 4-24.1.1.2 Features of the Digital Portion of PMC_SMPS . . . . . . . . . . . . . . . . . . . 4-24.1.2Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34.1.3PMC Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2External Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44.2.1Signals Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3Signals Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44.3.1VDDREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44.3.2VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54.3.3VDDSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54.3.4VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54.3.5REGCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54.3.6REGSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54.3.7VDD33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.4Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64.4.1Configuration Register (PMC_MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64.4.2Trimming Register (PMC_TRIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84.4.3Status Register (PMC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.5Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144.5.1PMC Internal 1.2V Voltage Regulator Selection . . . . . . . . . . . . . . . . . . . . . . . 4-154.5.2PMC Bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-164.5.3VDDREG LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-164.5.4 3.3V Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-164.5.5 3.3V VDDSYN LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-174.5.6 1.2V Voltage Regulator Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-184.5.7 1.2V VDD LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194.5.8Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-204.5.9Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-204.5.10PMC Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-204.5.11ADC Test Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4.6Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4.7Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-234.7.1Regulator Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-234.7.2Hardware Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24Chapter5Frequency Modulated Phase-Locked Loop (FMPLL)5.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15.1.1Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25.1.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2MPC5674F Microcontroller Reference Manual Rev. 7Freescale Semiconductor Table of Contents-iii5.1.3Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35.3.1Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35.3.2Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45.3.2.1 FMPLL Synthesizer Status Register (SYNSR) . . . . . . . . . . . . . . . . . . . 5-45.3.2.2 FMPLL Enhanced Synthesizer Control Register 1 (ESYNCR1) . . . . . . 5-65.3.2.3 FMPLL Enhanced Synthesizer Control Register 2 (ESYNCR2) . . . . . . 5-85.3.2.4 FMPLL Synthesizer FM Control Register(SYNFMCR) . . . . . . . . . . . . 5-11 5.4Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-135.4.1General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-135.4.2PLL Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-135.4.3Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-135.4.3.1 PLL Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-145.4.3.2 Loss-of-Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-155.4.3.3 PLL Normal Mode Without FM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-165.4.3.4 PLL Normal Mode With Frequency Modulation . . . . . . . . . . . . . . . . . 5-18 5.5Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-215.5.1Clock Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-215.5.1.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-215.5.1.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-215.5.2PLL Loss-of-Lock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-225.5.3PLL Loss-of-Clock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-225.6.1Loss-of-Lock Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-225.6.2Loss-of-Clock Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22Chapter6System Integration Unit (SIU)6.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16.1.1Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26.1.2Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36.1.3Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46.2.1Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46.2.1.1 Reset Input (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46.2.1.2 Reset Output (RSTOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56.2.1.3 General-Purpose I/O (GPIO n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56.2.1.4 Boot Configuration (BOOTCFG[0:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56.2.1.5 I/O Weak Pullup Reset Configuration (WKPCFG) . . . . . . . . . . . . . . . . 6-66.2.1.6 External Interrupt Request Input (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.3Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76.3.1Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106.3.1.1 MCU ID Register (SIU_MIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106.3.1.2 Reset Status Register (SIU_RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11MPC5674F Microcontroller Reference Manual Rev. 7Table of Contents-iv Freescale Semiconductor6.3.1.3 System Reset Control Register (SIU_SRCR) . . . . . . . . . . . . . . . . . . . 6-156.3.1.4 External Interrupt Status Register (SIU_EISR) . . . . . . . . . . . . . . . . . . 6-156.3.1.5 DMA/Interrupt Request Enable Register (SIU_DIRER) . . . . . . . . . . . 6-166.3.1.6 DMA/Interrupt Request Select Register (SIU_DIRSR) . . . . . . . . . . . . 6-176.3.1.7 Overrun Status Register (SIU_OSR) . . . . . . . . . . . . . . . . . . . . . . . . . 6-186.3.1.8 Overrun Request Enable Register (SIU_ORER) . . . . . . . . . . . . . . . . 6-196.3.1.9 IRQ Rising-Edge Event Enable Register (SIU_IREER) . . . . . . . . . . . 6-206.3.1.10 IRQ Falling-Edge Event Enable Register (SIU_IFEER) . . . . . . . . . . 6-216.3.1.11 IRQ Digital Filter Register (SIU_IDFR) . . . . . . . . . . . . . . . . . . . . . . . 6-226.3.1.12 IRQ Filtered Input Register (SIU_IFIR) . . . . . . . . . . . . . . . . . . . . . . . 6-226.3.1.13 Pad Configuration Registers (SIU_PCR) . . . . . . . . . . . . . . . . . . . . . 6-246.3.1.14 GPIO Pin Data Output Registers 0–512 (SIU_GPDO n) . . . . . . . . . . 6-406.3.1.15 GPIO Pin Data Input Registers 0–255 (SIU_GPDI n) . . . . . . . . . . . . 6-406.3.1.16 External IRQ Input Select Register (SIU_EIISR) . . . . . . . . . . . . . . . 6-416.3.1.17 DSPI Input Select Register (SIU_DISR) . . . . . . . . . . . . . . . . . . . . . . 6-436.3.1.18 eQADC Command FIFO Trigger Source Select - IMUX Select Registers(SIU_ISEL[4-7]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-466.3.1.19 eTPU Input Select Register (SIU_ISEL 8) . . . . . . . . . . . . . . . . . . . . 6-606.3.1.20 eQADC Advance Trigger Selection (SIU_ISEL9) . . . . . . . . . . . . . . . 6-616.3.1.21 Decimation Filter Register 1 (SIU_DECFIL1) . . . . . . . . . . . . . . . . . . 6-626.3.1.22 Decimation Filter Register 2 (SIU_DECFIL2) . . . . . . . . . . . . . . . . . . 6-646.3.1.23 Chip Configuration Register (SIU_CCR) . . . . . . . . . . . . . . . . . . . . . 6-656.3.1.24 External Clock Control Register (SIU_ECCR) . . . . . . . . . . . . . . . . . 6-666.3.1.25 Compare B Register High (SIU_CBRH) . . . . . . . . . . . . . . . . . . . . . . 6-686.3.1.26 Compare B Register Low (SIU_CBRL) . . . . . . . . . . . . . . . . . . . . . . . 6-686.3.1.27 System Clock Register (SIU_SYSDIV) . . . . . . . . . . . . . . . . . . . . . . . 6-696.3.1.28 Halt Register (SIU_HLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-696.3.1.29 Halt Acknowledge Register (SIU_HLTACK) . . . . . . . . . . . . . . . . . . . 6-716.3.1.30 Parallel GPIO Pin Data Output Register (SIU_PGPDO0 - SIU_PGPDO15)6-736.3.1.31 Parallel GPIO Pin Data Input Register (SIU_PGPDI0 - SIU_PGPDI15) 6-746.3.1.32 Masked Parallel GPIO Pin Data Output Register (SIU_MPGPDO0 -SIU_MPGPDO31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-746.3.1.33 SIU DSPI Serialization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-756.3.1.34 Serialized Output Signal Selection Registers for DSPI_D . . . . . . . . 6-836.3.1.35 GPIO Pin Data Input Registers (SIU_GPDI0_3 - SIU_GPDI508_511) -Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-85 6.4Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-866.4.1Pad Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-866.4.2Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-876.4.2.1 Reset Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-876.4.2.2 RESET Pin Glitch Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-876.4.3External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-876.4.4GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-90MPC5674F Microcontroller Reference Manual Rev. 7Freescale Semiconductor Table of Contents-v6.4.5.1 eQADC External Trigger Input Multiplexing . . . . . . . . . . . . . . . . . . . . 6-916.4.5.2 SIU External Interrupt Input Multiplexing . . . . . . . . . . . . . . . . . . . . . . 6-926.4.5.3 Multiplexed Inputs for DSPI Multiple Transfer Operation . . . . . . . . . . 6-92Chapter7System Information Module7.1SIM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17.1.1SIM Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1Chapter8Boot Assist Module (BAM)8.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.3Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18.3.1Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18.3.2Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28.3.3Internal Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28.3.4Serial Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28.3.5Development Bus Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.5Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38.5.1BAM Program Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38.5.2BAM Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48.5.3Reset Configuration Half Word (RCHW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-68.5.3.1 Application Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-88.5.4Internal Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-88.5.5Serial Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-88.5.5.1 CAN Controller Configuration in the Fixed Baud Rate Mode . . . . . . . 8-108.5.5.2 SCI Controller Configuration in Fixed Baud Rate Mode . . . . . . . . . . . 8-118.5.5.3 Serial Boot Mode Download Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 8-118.5.5.4 Download Protocol Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-128.5.5.5 Baud Rate Detection Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-148.5.5.6 CAN Baud Rate Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-148.5.6Booting from the Development Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-168.5.6.1 EBI Configuration for Separate Address and Data Development Bus BootMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-168.5.6.2 EBI Configuration for multiplexed Address and Data Development BusBoot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-178.5.7Enabling Debug of a Censored Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17Chapter9Interrupts and Interrupt Controller (INTC)9.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1MPC5674F Microcontroller Reference Manual Rev. 7Table of Contents-vi Freescale Semiconductor9.1.2Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29.1.3Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49.1.4Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59.1.4.1 Software Vector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59.1.4.2 Hardware Vector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.2External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.3Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-79.3.1Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-99.3.1.1 INTC Module Configuration Register (INTC_MCR) . . . . . . . . . . . . . . . 9-99.3.1.2 INTC Current Priority Register (INTC_CPR) . . . . . . . . . . . . . . . . . . . 9-109.3.1.3 INTC Interrupt Acknowledge Register (INTC_IACKR) . . . . . . . . . . . . 9-109.3.1.4 INTC End-of-Interrupt Register (INTC_EOIR) . . . . . . . . . . . . . . . . . . 9-119.3.1.5 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0–7) . . . . 9-129.3.1.6 INTC Priority Select Registers (INTC_PSR0–479) . . . . . . . . . . . . . . . 9-13 9.4Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-139.4.1Interrupt Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-139.4.1.1 Peripheral Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-319.4.1.2 Software configurable Interrupt Requests . . . . . . . . . . . . . . . . . . . . . 9-319.4.1.3 Unique Vector for Each Interrupt Request Source . . . . . . . . . . . . . . . 9-319.4.2Priority Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-319.4.2.1 Current Priority and Preemption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-329.4.2.2 LIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-339.4.3Details on Handshaking with Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-339.4.3.1 Software Vector Mode Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . 9-339.4.3.2 Hardware Vector Mode Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . 9-34 9.5Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-359.5.1Initialization Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-359.5.2Interrupt Exception Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-369.5.2.1 Software Vector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-369.5.2.2 Hardware Vector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-379.5.3ISR, RTOS, and Task Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-379.5.4Order of Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-389.5.5Priority Ceiling Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-399.5.5.1 Elevating Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-399.5.5.2 Ensuring Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-399.5.6Selecting Priorities According to Request Ratesand Deadlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-429.5.7Software configurable Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-429.5.7.1 Scheduling a Lower Priority Portion of an ISR . . . . . . . . . . . . . . . . . . 9-429.5.7.2 Scheduling an ISR on Another Processor . . . . . . . . . . . . . . . . . . . . . 9-439.5.8Lowering Priority Within an ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-439.5.9Negating an Interrupt Request Outside of its ISR . . . . . . . . . . . . . . . . . . . . . . 9-439.5.9.1 Negating an Interrupt Request as a Side Effect of an ISR . . . . . . . . . 9-439.5.9.2 Negating Multiple Interrupt Requests in One ISR . . . . . . . . . . . . . . . . 9-44MPC5674F Microcontroller Reference Manual Rev. 7Freescale Semiconductor Table of Contents-vii。

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该协议将为测量行业带来两个革命性的优点：该协议将为测量行业带来两个革命性的优点：对于坐标测量机用户，选择他们喜爱的软件配用其机器平台，将拥有极大的灵活性；对于测量机制造商，可快速地集成Renishaw未来的产品，使用户快速领略测量技术突破性进展。Renishaw一直处于这种高速发展的最前沿。
UCC2是一种高性能的多轴通用型控制器，适用于复杂的测量要求。由于采用了比先前UCC1系统性能更为强大的机器动态补偿技术、创新的扫描程序及更强大的数据处理性能，所以测量能力获得大幅提高。选择UCC2还可确保用户方便地升级Renishaw的最新技术。
UCC2控制器的标准配置包括Renishaw领先的SP25M扫描测头接口、4轴控制器、Renishaw测头技术的先进校正程序和对几何、温度和机器动态误差进行全面补偿的误差标测。如用户选用光学扫描的插卡，Renscan DC?将会带来额外的效益，坐标测量机在高速扫描时可达到低速扫描的精度水平，有助于大幅提高生产力。
对于UCC系列通用型坐标测量机控制器，Renishaw免费提供UCCassist?软件包，为用户提供了一系列的诊断工具，支持Renishaw的坐标测量机空间精度检测规(MCG)，进行自动误差检测和补偿。
对所有的UCC用户而言，该产品兼容新工业标准的I++DME协议的优点，为控制器兼容所有主流的软件包提供了一个交融的平台。尽管这项技术新发展的开发初衷是满足汽车行业主要用户的要求，但它的优势将使所有行业的测量机用户受益。
Renishaw新近推出了一系列新型控制器，为坐标测量机(CMM)用户提供了极为灵活的解决方案，从而引发了计量行业的一次小小的变革。该控制器为率先支持新工业标准的I++DME协议的产品之一，今后可使坐标测量机用户选择其喜爱的软件配用任何控制器。

ADCMP562中文资料

Figure 2. ADCMP561 16-Lead QSOP Figure 3. ADCMP562 20-Lead QSOP
are fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to VDD − 2 V. A latch input, which is included, permits tracking, track-and-hold, or sample-and-hold modes of operation. The latch input pins contain internal pull-ups that set the latch in tracking mode when left open.
A differential input stage permits consistent propagation delay with a wide variety of signals in the common-mode range from −2.0 V to +3.0 V. Outputs are complementary digital signals that
REVISION HISTORY
7/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Specification Table ....................................................... 4 Changes to Figure 14........................................................................ 9 Changes to Figure 21...................................................................... 12 Changes to Figure 23...................................................................... 13

详解铝电解电容器的参数

详解铝电解电容器的参数详解铝电解电容器的参数铝电解电容器的参数详解之一铝电解电容器的基本参数主要有电压、电容量、最高工作温度及寿命、漏电流和损耗因数，有的铝电解电容器，如开关电源输出滤波用的铝电解电容器还有额定纹波电流、ESR等参数。

电压铝电解电容器的电压指标主要有额定DC电压、额定浪涌电压、瞬间过压和反向电压，下面将逐一介绍。

1．反向电压钽电容是有极性电容器，通常不允许工作在反向电压。

在需要的地方，可通过连接一个二极管来防止反极性。

通常，采用导通电压约为0. 8V的二极管是允许的。

在短于Vs的时间内，小于或等于1.5V的反向电压也是可以承受的，但仅仅是短时间，绝不能是连续工作状态。

2．工作电压V OP工作电压是电容器在额定温度范围内所允许的连续工作的电压。

在整个工作温度范围内，电容器既可以在满额定电压（包括叠加的交流电压）下连续工作，也可以连续工作在0V与额定电压之间任何电压值。

在短时间内，电容器也可承受幅值不高于-1. 5V的反向电压。

反向电压的危害主要是反向电压将产生减薄氧化铝膜的电化学过程，从而不可逆地损坏铝电解电容器。

3．额定DC电压VR额定DC电压VR是电容器在额定温度范围内所允许的连续工作电压，它包括在电容器两电极间的直流电压和脉动电压或连续脉冲电压之和。

通常，钽电容的额定电压在电容器表面标明。

通常额定电压≤100V为“低压”铝电解电容器，而额定电压≥150V为“高压”铝电解电容器。

额定电压的标称电压为：3V、4V、6.3V、(7.5V)、10V、16V、25V、35V、(40V)、50V、63V、80V、100V、160V、200V、250V、300V、(315V)、350V、(385V)、400V、450V、500V、(550V)。

其中括号中的电压值为我国不常见的。

4．额定浪涌电压Vs额定浪涌电压Vs是铝电解电容器在短时间内能承受的电压值，其测试条件是：电容器工作在25℃，在不超过30s，两次间隔不小于5min。

FAIRCHILD FDMS5672 说明书

tmDecember 2007FDMS5672 N-Channel UltraFET Trench®MOSFET©2006 Fairchild Semiconductor CorporationFDMS5672 Rev.C21FDMS5672N-Channel UltraFET Trench® MOSFET60V, 22A, 11.5mΩFeaturesMax r DS(on) = 11.5mΩ at V GS = 10V, I D = 10.6AMax r DS(on) = 16.5mΩ at V GS = 6V, I D = 8ATyp Qg = 32nC at V GS = 10VLow Miller ChargeOptimized efficiency at high frequenciesRoHS CompliantGeneral DescriptionUItraFET devices combine characteristics that enablebenchmark efficiency in power conversion applications.Optimized for r DS(on), low ESR, low total and Miller gate charge,these devices are ideal for high frequency DC to DC converters.ApplicationDC - DC ConversionMOSFET Maximum Ratings TA= 25°C unless otherwise notedThermal CharacteristicsPackage Marking and Ordering InformationSymbol Parameter Ratings Units V DS Drain to Source Voltage60VV GS Gate to Source Voltage±20VI DDrain Current -Continuous (Package limited) T C = 25°C22A-Continuous (Silicon limited) T C = 25°C65-Continuous T A = 25°C (Note 1a)10.6-Pulsed60E AS Single Pulse Avalanche Energy (Note 3)337mJP DPower Dissipation T C = 25°C 78WPower Dissipation T A = 25°C (Note 1a) 2.5T J, T STG Operating and Storage Junction Temperature Range-55 to +150°CRθJC Thermal Resistance, Junction to Case 1.6°C/W RθJA Thermal Resistance, Junction to Ambient (Note 1a)50Device Marking Device Package Reel Size Tape Width Quantity FDMS5672FDMS5672Power 5613’’12mm3000 unitsGS S SPin 1Power 56 (Bottom view)DD D D43215678GSSSDDDD® MOSFETFDMS5672 2T J = 125°Cg FSForward TransconductanceV DS = 10V, I D = 10.6A26S Dynamic CharacteristicsC iss Input Capacitance V DS = 30V, V GS = 0V,f = 1MHz 21002800pF C oss Output Capacitance375500pF C rss Reverse Transfer Capacitance120180pF R gGate Resistancef = 1MHz1.2ΩSwitching Characteristicst d(on)Turn-On Delay Time V DD = 30V, I D = 10.6A V GS = 10V, R GEN = 6Ω1629ns t r Rise Time1731ns t d(off)Turn-Off Delay Time 2235ns t f Fall Time816ns Q g(TOT)Total Gate Charge at 10V V GS = 0V to 10VV DD = 30V I D = 10.6A3245nC Q gs Gate to Source Gate Charge 10nC Q gdGate to Drain “Miller” Charge8.3nCDrain-Source Diode CharacteristicsV SD Source to Drain Diode Forward Voltage V GS = 0V, I S = 10.6A (Note 2) 0.80 1.20V t rr Reverse Recovery Time I F = 10.6A, di/dt = 100A/µs3553ns Q rrReverse Recovery Charge4263nCNotes:1:R θJA is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R θJC is guaranteed by design while R θCA is determined by the user's board design.2:Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%.3:Starting T J = 25°C, L = 3mH, I AS = 15A, V DD = 60V, V GS = 10V.50°C/W when mounted on a 1 in 2 pad of 2 oz copper125°C/W when mounted on a minimum pad of 2 oz coppera. b.FDMS5672 Rev.C23FDMS5672 Rev.C24FDMS5672 Rev.C25® MOSFETFDMS5672 6FDMS5672 Rev. C27® MOSFET* EZSWITCH™ and FlashWriter ® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of Terms Fairchild Fairchild Semiconductor ®FACT Quiet Series™FACT ®FAST ®FastvCore™FlashWriter ® *MicroFET™MicroPak™MillerDrive™Motion-SPM™OPTOLOGIC ®OPTOPLANAR ®®RapidConfigure™SMART START™SPM ®STEALTH™SuperFET™SuperSOT™-3SuperSOT™-6SuperSOT™-8TinyWire™µSerDes™UHC ®Ultra FRFET™UniFET™VCX™tmDatasheet Identification Product Status DefinitionAdvance InformationFormative or In DesignThis datasheet contains the design specifications for product development. Specifications may change in any manner without notice.Preliminary First ProductionThis datasheet contains preliminary data; supplementary data will be pub-lished at a later date. Fairchild Semiconductor reserves the right to make。

DAC5672AIPFB资料

FEATURESAPPLICATIONSDESCRIPTIONDAC5672ASLAS528–SEPTEMBER 2007DUAL,14-BIT 275MSPS DIGITAL-TO-ANALOG CONVERTER•Package:48-Pin Thin-Quad Flat Pack (TQFP)•14-Bit Dual Transmit Digital-to-Analog Converter (DAC)•Cellular Base Transceiver Station Transmit •275MSPS Update Rate Channel•Single Supply:3V to 3.6V–CDMA:W-CDMA,CDMA2000,IS-95•High Spurious-Free Dynamic Range (SFDR):–TDMA:GSM,IS-136,EDGE/UWC-13684dBc at 5MHz•Medical/Test Instrumentation•High Third-Order Two-Tone Intermodulation •Arbitrary Waveform Generators (ARB)(IMD3):79dBc at 15.1MHz and 16.1MHz •Direct Digital Synthesis (DDS)•WCDMA Adjacent Channel Leakage Ratio •Cable Modem Termination System (CMTS)(ACLR):78dB at Baseband•WCDMA ACLR:73dB at 30.72MHz•Independent or Single Resistor Gain Control •Dual or Interleaved Data •On-Chip 1.2-V Reference •Low Power:330mW•Power-Down Mode:9mWThe DAC5672A is a monolithic,dual-channel,14-bit,high-speed DAC with on-chip voltage reference.Operating with update rates of up to 275MSPS,the DAC5672A offers exceptional dynamic performance,tight-gain,and offset matching characteristics that make it suitable in either I/Q baseband or direct IF communication applications.Each DAC has a high-impedance,differential-current output,suitable for single-ended or differential analog-output configurations.External resistors allow scaling the full-scale output current for each DAC separately or together,typically between 2mA and 20mA.An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage.Optionally,an external reference may be used.The DAC5672A has two,14-bit,parallel input ports with separate clocks and data latches.For flexibility,the DAC5672A also supports multiplexed data for each DAC on one port when operating in the interleaved mode.The DAC5672A has been specifically designed for a differential transformer-coupled output with a 50-Ωdoubly-terminated load.For a 20-mA full-scale output current,both a 4:1impedance ratio (resulting in an output power of 4dBm)and 1:1impedance ratio transformer (–2dBm output power)are supported.The DAC5672A is available in a 48-pin TQFP package.Pin compatibility between family members provides 12-bit (DAC5662)and 14-bit (DAC5672A)resolution.Furthermore,the DAC5672A is pin compatible to the DAC2904and AD9767dual DACs.The device is characterized for operation over the industrial temperature range of -40°C to 85°C.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright ©2007,Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.DA[13:0]DB[13:0]MODEGSETIOUTA1IOUTA2IOUTB1IOUTB2BIASJ_ABIASJ_BEXTIODVDD DGND AVDD AGNDSLEEPDAC5672ASLAS528–SEPTEMBER2007These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.FUNCTIONAL BLOCK DIAGRAMAVAILABLE OPTIONSPACKAGED DEVICEST A48-Pin TQFPDAC5672AIPFB-40°C to85°CDAC5672AIPFBR2Submit Documentation Feedback Copyright©2007,Texas Instruments IncorporatedProduct Folder Link(s):DAC5672ADEVICE INFORMATION131415DB0 (LSB)DB1DB2DB3DB4DB5DB6DB7DB8DB9DB10DB1136353433323130292827262516123456789101112DA13 (MSB)DA12DA11DA10DA9DA8DA7DA6DA5DA4DA3DA217181920A G N D 47464544434842I O U T A 1I O U T A 2B I A S J _A E X T I O G S E T B I A S J _B I O U T B 2D V D D D B 13 (M S B )D B 12D G N D D V D D W R T A /W R T I Q C L K A /C L K I Q C L K B /RE S E T I Q W R T B /S E L E C T I Q D G N D 403938412122232437D A 1S LE E PI O U T B 1M O D E A V D D D A 0 (L S B )Top View 48−Pin TQFP PFB PackageDAC5672ASLAS528–SEPTEMBER 2007TERMINAL FUNCTIONSTERMINALI/O DESCRIPTION NAME NO.AGND 38I Analog ground AVDD 47I Analog supply voltageBIASJ_A 44O Full-scale output current bias for DACA BIASJ_B 41O Full-scale output current bias for DACBCLKA/CLKIQ 18I Clock input for DACA,CLKIQ in interleaved mode CLKB/RESETIQ 19I Clock input for DACB,RESETIQ in interleaved mode DA[13:0]1-14I Data port A.DA13is MSB and DA0is LSB.DB[13:0]23-36I Data port B.DB13is MSB and DB0is LSB.DGND 15,21I Digital ground DVDD 16,22I Digital supply voltageEXTIO 43I/O Internal reference output (bypass with 0.1μF to AGND)or external reference input GSET 42I Gain-setting mode:H –1resistor,L –2resistors.Internal pullup.IOUTA146O DACA current output.Full-scale with all bits of DA high.IOUTA245O DACA complementary current output.Full-scale with all bits of DA low.IOUTB139O DACB current output.Full-scale with all bits of DB high.IOUTB240O DACB complementary current output.Full-scale with all bits of DB low.MODE 48I Mode Select:H –Dual Bus,L –Interleaved.Internal pullup.Sleep function control input:H –DAC in power-down mode,L –DAC in operating mode.SLEEP 37I Internal pulldown.WRTA/WRTIQ 17I Input write signal for PORT A (WRTIQ in interleaving mode)WRTB/SELECTIQ20IInput write signal for PORT B (SELECTIQ in interleaving mode)Copyright ©2007,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):DAC5672AABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICSDAC5672ASLAS528–SEPTEMBER 2007over T A (unless otherwise noted)(1)UNITAVDD (2)-0.5V to 4V Supply voltage rangeDVDD (3)-0.5V to 4V Voltage between AGND and DGND -0.5V to 0.5V Voltage between AVDD and DVDD-4V to 4V DA[13:0]and DB[13:0](3)-0.5V to DVDD +0.5V MODE,CLKA,CLKB,WRTA,WRTB (3)-0.5V to DVDD +0.5V Supply voltage rangeIOUTA1,IOUTA2,IOUTB1,IOUTB2(2)-1.0V to AVDD +0.5V EXTIO,BIASJ_A,BIASJ_B,SLEEP(2)-0.5V to AVDD +0.5VPeak input current (any input)20mA Peak total input current (all inputs)-30mA Operating free-air temperature range -40°C to 85°C Storage temperature range -65°C to 150°C(1)Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device.These are stress ratings only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions”is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)Measured with respect to AGND.(3)Measured with respect to DGND.over T A ,AVDD =DVDD =3.3V,I (OUTFS)=20mA,independent gain set mode (unless otherwise noted)PARAMETERTEST CONDITIONS MIN TYP MAX UNIT DC SpecificationsResolution14BitsDC Accuracy (1)INL Integral nonlinearity 1LSB =I (OUTFS)/214,T MIN to T MAX-4±1.14LSB DNLDifferential nonlinearity -3±0.753LSB Analog OutputOffset error Midscale value ±0.03%FSR Offset mismatch Midscale value ±0.03%FSR With external reference ±0.25%FSR Gain errorWith internal reference±0.25%FSR Minimum full-scale output current (2)2mA Maximum full-scale output current (2)20mAWith external reference -20.22%FSR Gain mismatchWith internal reference-20.22%FSR Output voltage compliance range (3)-11.25V R O Output resistance 300k ΩC OOutput capacitance 5pFReference OutputReference voltage 1.141.2 1.26V Reference output current(4)100nA(1)Measured differentially through 50Ωto AGND.(2)Nominal full-scale current,I (OUTFS),equals 32x the I (BIAS)current.(3)The lower limit of the output compliance is determined by the CMOS process.Exceeding this limit may result in transistor breakdown,resulting in reduced reliability of the DAC5672A device.The upper limit of the output compliance is determined by the load resistors and full-scale output current.Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.(4)Use an external buffer amplifier with high-impedance input to drive any external load.4Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):DAC5672AELECTRICAL CHARACTERISTICSDAC5672A SLAS528–SEPTEMBER2007ELECTRICAL CHARACTERISTICS(continued)over T A,AVDD=DVDD=3.3V,I(OUTFS)=20mA,independent gain set mode(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference InputV(EXTIO)Input voltage0.1 1.25VR I Input resistance1MΩSmall signal bandwidth300kHzC I Input capacitance100pF Temperature CoefficientsOffset drift2ppm ofFSR/°CWith external reference±20ppm ofFSR/°C Gain driftWith internal reference±40ppm ofFSR/°C Reference voltage drift±20ppm/°Cover T A,AVDD=DVDD=3.3V,I(OUTFS)=20mA,f DATA=200MSPS,f OUT=1MHz,independent gain set mode(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power SupplyAVDD Analog supply voltage3 3.3 3.6V DVDD Digital supply voltage3 3.3 3.6VIncluding output current through load7590mAresistorI(AVDD)Supply current,analogSleep mode with clock 2.56mASleep mode without clock 2.5mA2538mAI(DVDD)Supply current,digital Sleep mode with clock13.418mASleep mode without clock0.6mA330390Sleep mode with clock53Power dissipation mWSleep mode without clock9.2f DATA=275MSPS,f OUT=20MHz350APSRR Analog power supply rejection ratio-0.2-0.010.2%FSR/V DPSRR Digital power supply rejection ratio-0.200.2%FSR/V T A Operating free-air temperature-4085°CCopyright©2007,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):DAC5672AELECTRICAL CHARACTERISTICSDAC5672ASLAS528–SEPTEMBER 2007AC specifications over T A ,AVDD =DVDD =3.3V,I (OUTFS)=20mA,independent gain set mode,differential 1:1impedance ratio transformer coupled output,50-Ωdoubly terminated load (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXUNITAnalog Output f clk Maximum output update rate (1)275MSPS Output settling time to 0.1%t s Mid-scale transition20ns (DAC)Output rise time 10%to 90%t r 1.4ns (OUT)Output fall time 90%to 10%t f1.5ns (OUT)I (OUTFS)=20mA 55pA/√Hz Output noiseI (OUTFS)=2mA30pA/√HzAC Linearity (estimates based on measurements of preliminary parts)1st Nyquist zone,T A =25°C,f DATA =50MSPS,f OUT =1MHz,83I (OUTFS)=0dB1st Nyquist zone,T A =25°C,f DATA =50MSPS,f OUT =1MHz,80I (OUTFS)=-6dB1st Nyquist zone,T A =25°C,f DATA =50MSPS,f OUT =1MHz,79I (OUTFS)=-12dB1st Nyquist zone,T A =25°C,SFDRSpurious-free dynamic rangedBc84f DATA =100MSPS,f OUT =5MHz 1st Nyquist zone,T A =25°C,79f DATA =100MSPS,f OUT =20MHz 1st Nyquist zone,T MIN to T MAX ,6875f DATA =200MSPS,f OUT =20MHz 1st Nyquist zone,T A =25°C,72f DATA =200MSPS,f OUT =41MHz 1st Nyquist zone,T A =25°C,74f DATA =275MSPS,f OUT =20MHz1st Nyquist zone,T A =25°C,77dB f DATA =100MSPS,f OUT =5MHz SNRSignal-to-noise ratio1st Nyquist zone,T A =25°C,70dB f DATA =160MSPS,f OUT =20MHz W-CDMA signal with 3.84-MHz Bandwidth,75dB f DATA =61.44MSPS,IF =15.360MHzW-CDMA signal with 3.84-MHz Bandwidth,73dB f DATA =122.88MSPS,IF =30.72MHz ACLRAdjacent channel leakage ratioW-CDMA signal with 3.84-MHz Bandwidth,78dB f DATA =61.44MSPS,BasebandW-CDMA signal with 3.84-MHz Bandwidth,78dB f DATA =122.88MSPS,Baseband Each tone at -6dBFS,T A =25°C,f DATA =200MSPS,f OUT =45.4MHz and 65dBc 46.4MHzThird-order two-tone IMD3intermodulationEach tone at -6dBFS,T A =25°C,f DATA =100MSPS,f OUT =15.1MHz and 79dBc16.1MHz(1)Specified by design and bench characterization.Not production tested.6Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):DAC5672AELECTRICAL CHARACTERISTICS SWITCHING CHARACTERISTICSDAC5672A SLAS528–SEPTEMBER2007ELECTRICAL CHARACTERISTICS(continued)AC specifications over T A,AVDD=DVDD=3.3V,I(OUTFS)=20mA,independent gain set mode,differential1:1impedance ratio transformer coupled output,50-Ωdoubly terminated load(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITEach tone at-12dBFS,T A=25°Cf DATA=100MSPS,f OUT=15.6,15.8,16.2,79dBcand16.4MHzEach tone at-12dBFS,T A=25°CIMD Four-tone intermodulation f DATA=165MSPS,f OUT=68.8,69.6,71.2,61dBcand72.0MHzEach tone at-12dBFS,T A=25°Cf DATA=165MSPS73dBcf OUT=19.0,19.1,19.3,and19.4MHzT A=25°C,f DATA=165MSPSChannel isolation f OUT(CH1)=20MHz,f OUT(CH2)=2195dBcMHzDigital specifications over T A,AVDD=DVDD=3.3V,I OUTFS=20mA(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital InputV IH High-level input voltage2 3.3VV IL Low-level input voltage00.8VI IH High-level input current±50μAI IL Low-level input current±10μAI IH(GSET)High-level input current,GSET pin7μAI IL(GSET)Low-level input current,GSET pin-80μAI IH(MODE)High-level input current,MODE pin-30μAI IL(MODE)Low-level input current,MODE pin-80μAC I Input capacitance5pFDigital specifications over T A,AVDD=DVDD=3.3V,I OUTFS=20mA(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Timing-Dual Bus Modet su Input setup time1nst h Input hold time1nst LPH Input clock pulse high time1nst LAT Clock latency(WRTA/B to outputs)44clkt PD Propagation delay time 1.5ns Timing-Single Bus Interleaved Modet su Input setup time0.5nst h Input hold time0.5nst LAT Clock latency(WRTA/B to outputs)44clkt PD Propagation delay time 1.5nsCopyright©2007,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):DAC5672ATYPICAL CHARACTERISTICS−1.5−1.0−0.50.00.51.01.50200040006000800010000120001400016000Input CodeI N L − I n t e g r a l N o n l i n e a r i t y E r r o r − L S BG001−1.0−0.8−0.6−0.4−0.20.00.20.40.60.81.00200040006000800010000120001400016000Input CodeD N L − D i f f e r e n t i a l N o n l i n e a r i t yE r r o r − L SBG002DAC5672ASLAS528–SEPTEMBER 2007INTEGRAL NONLINEARITYvsINPUT CODEFigure 1.DIFFERENTIAL NONLINEARITYvsINPUT CODEFigure 2.8Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):DAC5672A6065707580859095100048121620f out − Output Frequency − MHzS F D R − S p u r i o u s -F r e e D y n a m i c R a n g e − d B cG0036065707580859095100051015202530f out − Output Frequency − MHzS F D R − S p u r i o u s -F r e e D y n a m i c R a n g e − d B cG004606570758085909510005101520253035f out − Output Frequency − MHzS F D R − S p u r i o u s -F r e e D y n a m i c R a n g e − d B cG0056065707580859095100051015202530354045505560f out − Output Frequency − MHzS F D R − S p u r i o u s -F r e e D y n a m i c R a n g e − d B cG006DAC5672ASLAS528–SEPTEMBER 2007TYPICAL CHARACTERISTICS (continued)SPURIOUS-FREE DYNAMIC RANGESPURIOUS-FREE DYNAMIC RANGEvsvsOUTPUT FREQUENCYOUTPUT FREQUENCYFigure 3.Figure 4.SPURIOUS-FREE DYNAMIC RANGESPURIOUS-FREE DYNAMIC RANGEvsvsOUTPUT FREQUENCYOUTPUT FREQUENCYFigure 5.Figure 6.Copyright ©2007,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):DAC5672Af − Frequency − MHz−100−80−60−40−2000.07.815.623.431.239.0P o w e r − d B mG007f − Frequency − MHz−100−80−60−40−200.016.533.049.566.082.5P o w e r − d B mG008f out1 − Output Frequency − MHz606570758085909505101520253035T w o -T o n e I M D 3 − d B cG009f out1 − Output Frequency − MHz5055606570758085909510001020304050T w o -T o n e I M D 3 − d BcG010DAC5672ASLAS528–SEPTEMBER 2007TYPICAL CHARACTERISTICS (continued)Figure 7.Figure 8.TWO-TONE IMD3TWO-TONE IMD3vsvsOUTPUT FREQUENCYOUTPUT FREQUENCYFigure 9.Figure 10.10Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):DAC5672Af − Frequency − MHz −110−90−70−50−30−1019.019.520.020.521.021.522.0P o w e r − d B mG011f − Frequency − MHz−110−90−70−50−30−1029.029.530.030.531.031.532.0P o w e r − d BmG012−120−100−80−60−40−20P o w e r − d Bmf − Frequency − MHzP o w e r − d B m−120−100−80−60−40−207.610.112.615.117.620.122.6G014TWO-TONE SPECTRUMTWO-TONE SPECTRUMFigure 11.Figure 12.POWER POWER vsvsFREQUENCYFREQUENCYFigure 13.Figure 14.P o w e r − d B m−120−100−80−60−40−20f − Frequency − MHzP o w e r − d B m−120−100−80−60−40−2023.025.528.030.533.035.538.0G016Digital Inputs and TimingDigital InputsInternal Digital InPOWER POWER vsvsFREQUENCYFREQUENCYFigure 16.The data input ports of the DAC5672A accept a standard positive coding with data bits DA13and DB13being the most significant bits (MSB).The converter outputs support a clock rate of up to 275MSPS.The best performance is typically achieved with a symmetric duty cycle for write and clock;however,the duty cycle may vary as long as the timing specifications are met.Similarly,the setup and hold times may be chosen within their specified limits.All digital inputs of the DAC5672A are CMOS compatible.Figure 17and Figure 18show schematics of the equivalent CMOS digital inputs of the DAC5672A.The 14-bit digital data input follows the offset positive binary coding scheme.The DAC5672A is designed to operate with a digital supply (DVDD)of 3V to 3.6V.Figure 17.CMOS/TTL Digital Equivalent Input With Internal Pulldown ResistorInternal Digital InInput InterfacesDual-Bus Data Interface and TimingFigure 18.CMOS/TTL Digital Equivalent Input With Internal Pullup ResistorThe DAC5672A features two operating modes selected by the MODE pin,as shown in Table 1.•For dual-bus input mode,the device essentially consists of two separate DACs.Each DAC has its own separate data input bus,clock input,and data write signal (data latch-in).•In single-bus interleaved mode,the data must be presented interleaved at the A-channel input bus.The B-channel input bus is not used in this mode.The clock and write input are now shared by both DACs.Table 1.Operating ModesMODE Pin MODE pin connected to DGNDMODE pin connected to DVDDBus inputSingle-bus interleaved mode,clock and write input equal for both DACsDual-bus mode,DACs operate independentlyIn dual-bus mode,the MODE pin is connected to DVDD.The two converter channels within the DAC5672A consist of two independent,14-bit,parallel data ports.Each DAC channel is controlled by its own set of write (WRTA,WRTB)and clock (CLKA,CLKB)lines.The WRTA/B lines control the channel input latches and the CLKA/B lines control the DAC latches.The data is first loaded into the input latch by a rising edge of the WRTA/B line.The internal data transfer requires a correct sequence of write and clock inputs,since essentially two clock domains having equal periods (but possibly different phases)are input to the DAC5672A.This is defined by a minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs.This essentially implies that the rising edge of CLKA/B must occur at the same time or before the rising edge of the WRTA/B signal.A minimum delay of 2ns must be maintained if the rising edge of the clock occurs after the rising edge of the write.Note that these conditions are satisfied when the clock and write inputs are connected externally.Note that all specifications were measured with the WRTA/B and CLKA/B lines connected together.DA[13:0]/DB[13:0]WRTA/WRTBCLKA/CLKBIOUTorIOUTFigure19.Dual-Bus Mode OperationSingle-Bus Interleaved Data Interface and TimingIn single-bus interleaved mode,the MODE pin is connected to DGND.Figure20shows the timing diagram.In interleaved mode,the A-and B-channels share the write input clock(CLKIQ and internal CLKDACIQ).Multiplexing logic directs the input word at the A-channel input bus to either the A-channel input latch(SELECTIQ is high)or to the B-channel input latch(SELECTIQ is low).When SELECTIQ is high,the data value in the B-channel latch is retained by presenting the latch output data to its input again.When SELECTIQ is low,the data value in the A-channel latch is retained by presenting the latch output data to its input.In interleaved mode,the A-channel input data rate is twice the update rate of the DAC core.As in dual-bus mode,it is important to maintain a correct sequence of write and clock inputs.The edge-triggered flip-flops latch the A-and B-channel input words on the rising edge of the write input(WRTIQ).This data is presented to the A-and B-DAC latches on the following falling edge of the write inputs.The DAC5672A clock input is divided by a factor of two before it is presented to the DAC latches.Correct pairing of the A-and B-channel data is done by RESETIQ.In interleaved mode,the clock input CLKIQ is divided by two,which would translate to a non-deterministic relation between the rising edges of the CLKIQ and CLKDACIQ.RESETIQ ensures,however,that the correct position of the rising edge of CLKDACIQ with respect to the data at the input of the DAC latch is determined.CLKDACIQ is disabled(low)when RESETIQ is high.SELECTIQWRTIQCLKIQRESETIQIOUTorIOUTFigure20.Single-Bus Interleaved Mode OperationAPPLICATION INFORMATIONTheory of OperationDAC Transfer FunctionI OUTFS +I OUT1)I OUT2(1)I OUT1+IOUTFS ǒCode16384Ǔ(2)I OUT2+I OUTFS ǒ16383*Code 16384Ǔ(3)I OUTFS +32 I REF +32 VREF RSET (4)V OUT1+I OUT1 R LOAD (5)V OUT2+I OUT2 R LOAD (6)The architecture of the DAC5672A uses a current steering technique to enable fast switching and high update rate.The core element within the monolithic DAC is an array of segmented current sources that are designed to deliver a full-scale output current of up to 20mA.An internal decoder addresses the differential current switches each time the DAC is updated and a corresponding output current is formed by steering all currents to either output summing node,IOUT1or IOUT2.The complementary outputs deliver a differential output signal,which improves the dynamic performance through reduction of even-order harmonics,common-mode signals (noise),and double the peak-to-peak output signal swing by a factor of two,as compared to single-ended operation.The segmented architecture results in a significant reduction of the glitch energy and improves the dynamic performance (SFDR)and DNL.The current outputs maintain a very high output impedance of greater than 300k Ω.When pin 42(GSET)is high (simultaneous gain set mode),the full-scale output current for both DACs is determined by the ratio of the internal reference voltage (1.2V)and an external resistor (R SET )connected to BIASJ_A.When GSET is low (independent gain set mode),the full-scale output current for each DAC is determined by the ratio of the internal reference voltage (1.2V)and separate external resistors (R SET )connected to BIASJ_A and BIASJ_B.The resulting I REF is internally multiplied by a factor of 32to produce an effective DAC output current that can range from 2mA to 20mA,depending on the value of R SET .The DAC5672A is split into a digital and an analog portion,each of which is powered through its own supply pin.The digital section includes edge-triggered input latches and the decoder logic,while the analog section comprises both the current source array with its associated switches,and the reference circuitry.Each of the DACs in the DAC5672A has a set of complementary current outputs,IOUT1and IOUT2.The full-scale output current,I OUTFS ,is the summation of the two complementary output currents:The individual output currents depend on the DAC code and can be expressed as:where Code is the decimal representation of the DAC data input word.Additionally,I (OUTFS)is a function of thereference current I REF ,which is determined by the reference voltage and the external setting resistor (R SET ).In most cases,the complementary outputs drive resistive loads or a terminated transformer.A signal voltagedevelops at each output according to:The value of the load resistance is limited by the output compliance specification of the DAC5672A.To maintainspecified linearity performance,the voltage for IOUT1and IOUT2must not exceed the maximum allowable compliance range.V OUTDIFF +V OUT1*V OUT2(7)V OUTDIFF +(2 Code *16383)16384 I OUTFS R LOAD (8)Analog OutputsOutput ConfigurationsThe total differential output voltage is:The DAC5672A provides two complementary current outputs,IOUT1and IOUT2.The simplified circuit of theanalog output stage representing the differential topology is shown in Figure 21.The output impedance of IOUT1and IOUT2results from the parallel combination of the differential with the current sources and associated parasitic capacitances.Figure 21.Analog OutputsThe signal voltage swing that may develop at the two outputs,IOUT1and IOUT2,is limited by a negative and positive compliance.The negative limit of –1V is given by the breakdown voltage of the CMOS process and exceeding it compromises the reliability of the DAC5672A (or even causes permanent damage).With the full-scale output set to 20mA,the positive compliance equals 1.2V.Note that the compliance range decreases to about 1V for a selected output current of I (OUTFS)=2mA.Care must be taken that the configuration of DAC5672A does not exceed the compliance range to avoid degradation of the distortion performance and integral linearity.Best distortion performance is typically achieved with the maximum full-scale output signal limited to approximately 0.5V PP .This is the case for a 50-Ωdoubly-terminated load and a 20-mA full-scale output current.A variety of loads can be adapted to the output of the DAC5672A by selecting a suitable transformer while maintaining optimum voltage levels at IOUT1and IOUT2.Furthermore,using the differential output configuration in combination with a transformer is instrumental for achieving excellent distortion mon-mode errors,such as even-order harmonics or noise,can be substantially reduced.This is particularly the case with high output frequencies.For those applications requiring the optimum distortion and noise performance,it is recommended to select a full-scale output of 20mA.A lower full-scale range of 2mA may be considered for applications that require low power consumption,but can tolerate a slight reduction in performance level.The current outputs of the DAC5672A allow for a variety of configurations.As mentioned previously,using the converter’s differential outputs yield the best dynamic performance.Such a differential output circuit may consist of an RF transformer or a differential amplifier configuration.The transformer configuration is ideal for most applications with ac coupling,while op amps are suitable for a dc-coupled configuration.。

DSP56721资料

Freescale Semiconductor Data Sheet: Technical DataFreescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.DSP56720 / DSP56721DSP56720144-Pin LQFP 20 mm x 20 mm 0.5 mm pitchDSP5672180-Pin LQFP 14 mm x 14 mm 0.65 mm pitch 144-Pin LQFP 20 mm x 20 mm 0.5 mm pitchOrdering Information Device Device Marking or Operating TemperatureRangeLQFP Package DSP56720DSP A56720AG 20 mm x 20 mm DSPB56720AG 20 mm x 20 mm DSP56720DSP A56721AG 20 mm x 20 mm DSPB56721AG 20 mm x 20 mm DSP A56721AF 14 mm x 14 mm DSPB56721AF14 mm x 14 mmDocument Number: DSP56720Rev.1, 12/2007The Symphony DSP56720/DSP56721 Multi-Core Audio Processors are part of the DSP5672x family of programmable CMOS DSPs, designed using multiple DSP56300 24-bit cores.The DSP56720/DSP56721 devices are intended forautomotive, consumer, and professional audio applications that require high performance for audio processing. Inaddition, the DSP56720 is ideally suited for applications that need the capability to expand memory off-chip or to interface to external parallel peripherals. Potential applications include A/V receivers, HD-DVD and Blu-Ray players, caraudio/amplifiers, and professional recording equipment. The DSP56720/DSP56721 devices excel at audio processing for automotive and consumer audio applications requiring high MIPs. Higher MIPs and memory requirements are driven by the new high-definition audio standards (Dolby Digital+, Dolby TrueHD, DTS-HD, for example) and the desire to process multiple audio streams.In addition, DSP56720/DSP56721 devices are optimal for the professional audio market requiring audio recording, signal processing, and digital audio synthesis.The DSP56720/DSP56721 processors provide a wealth of on-chip audio processing functions, via a plug and play software architecture system that supports audio decoding algorithms, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, among others. TheDSP56720/DSP56721 devices also support various matrix decoders and sound field processing algorithms.With two DSP56300 cores, a single DSP56720 or DSP56721 device can replace dual-DSP designs, saving costs while meeting high MIPs requirements. Legacy peripherals from the previous DSP5636x/7x families are included, as well as a variety of new modules. Included among the new modules are an Asynchronous Sample Rate Converter (ASRC), Inter-CoreCommunication (ICC), an External Memory Controller (EMC) to support SDRAM, and a Sony/Philips Digital Interface (S/PDIF).The DSP56720/DSP56721 offer 200 million instructions per second (MIPs) per core using an internal 200MHz clock.The DSP56720/DSP56721 are high density CMOS devices with 3.3V inputs and outputs.The DSP56720 device is slightly different than the DSP56721 device—the DSP56720 includes an external memory interface while the DSP56721 device does not. The DSP56720 block diagram is shown in Figure 1; the DSP56721 block diagram is shown in Figure 2.Symphony TM DSP56720 / DSP56721 Multi-Core Audio ProcessorsTable of Contents1Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.1Pinout for DSP56720 144-Pin Plastic LQFP Package . .41.2Pinout for DSP56721 80-Pin Plastic LQFP Package . . .61.3Pinout for DSP56721 144-Pin Plastic LQFP Package . .71.4Pin Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82.1Chip-Level Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .82.1.1Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .82.1.2Thermal Characteristics. . . . . . . . . . . . . . . . . . .102.1.3Power Requirements. . . . . . . . . . . . . . . . . . . . .102.1.4DC Electrical Characteristics. . . . . . . . . . . . . . .112.1.5AC Electrical Characteristics. . . . . . . . . . . . . . .122.1.6Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . .122.1.7External Clock Operation. . . . . . . . . . . . . . . . . .132.1.8Reset, Stop, Mode Select, and Interrupt Timing142.2Module-Level Specifications. . . . . . . . . . . . . . . . . . . . .172.2.1Serial Host Interface (SHI) SPI Protocol Timing182.2.2Serial Host Interface (SHI) I2C Protocol Timing.242.2.3Programming the SHI I2C Serial Clock . . . . . . 262.2.4Enhanced Serial Audio Interface (ESAI) Timing272.2.5Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 322.2.6GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 322.2.7JT AG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 332.2.8Watchdog Timer Timing. . . . . . . . . . . . . . . . . . 352.2.9Host Data Interface (HDI24) Timing. . . . . . . . . 352.2.10S/PDIF Timing . . . . . . . . . . . . . . . . . . . . . . . . . 422.2.11EMC Timing (DSP56720 only). . . . . . . . . . . . . 43 3Functional Description and Application Information . . . . . . . 48 4Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . 48 5Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.180-Pin Package Outline Drawing. . . . . . . . . . . . . . . . . 486.2144-Pin Package Outline Drawing. . . . . . . . . . . . . . . . 51 7Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 1. DSP56720 Block DiagramFigure 2. DSP56721 Block DiagramS H IT E CE S A IE S A I _1W D TG P I OS H I _1T E C _1E S A I _2E S A I _3W D T _1G P I OPCU / AGU / ALUDMA OnCEOnCEPCU / AGU / ALUDMAOn-Chip MemoryP X YOn-Chip MemoryP X YDSP Core-0E M CS /P D I FG P I OASRCArbiter 8Arbiters 0–72 JTAGsShared Memory 8K Blocks 0–7 (64K total)MODA1, MODB1,MODC1, MODD1MODA0, MODB0,MODC0, MODD0JT AGEXT AL/XTALDSP Core-1C h i p C o n f i gArbiter 9CGM Shared Bus 0Shared Bus 1S H IT I M E RE S A IE S A I _1W D TG P I OH D I 24S H I _1T I M E R _1E S A I _2E S A I _3W D T _1G P I OH D I 24_1PCU / AGU / ALUDMA OnCEOnCEPCU / AGU / ALUDMAOn-Chip MemoryPXYOn-Chip MemoryPXYDSP Core-0S P D I FG P I OASRCArbiter 8Arbiters 0–72 JTAGsShared Memory 8K Blocks 0–7 (64K total)MODA1, MODB1,MODC1, MODD1MODA0, MODB0,MODC0, MODD0JT AGHDI24EXT AL/XTALDSP Core-1C h i p C o n f i gCGM Shared Bus 0Shared Bus 11Pin AssignmentsDSP56720 devices are available in one package type; DSP56721 devices are available in two package types. For the pin assignments of a specific device in a specific package, please see sections 1.2–1.1.Table1. Pin Assignments by PackageDevice Package SeeDSP56720144-pin plastic LQFP Figure3on page5DSP5672180-pin plastic LQFP Figure4on page6144-pin plastic LQFP Figure5on page7For more detailed information about signals, refer to the DSP56720/DSP56721 Reference Manual (DSP56720RM).1.1Pinout for DSP56720 144-Pin Plastic LQFP PackageFor the pinout of the DSP56720 144-pin plastic LQFP package, see Figure3.Figure 3. DSP56720 144-Pin Package Pinout108IO_GND 107IO_VDD 106WDT105104TDO 103TDI 102TCK 101TMS100SDO2_1/SDI3_199SDO3_1/SDI2_198SDO4_1/SDI1_197SDO5_1/SDI0_196CORE_GND 95CORE_VDD 94FSR 93SCKR 92HCKR 91SCKT 90FST 89HCKT88SDO2/SDI387SDO3/SDI286SDO4/SDI185SDO5/SDI084SPDIFOUT183SPDIFIN182IO_GND 81IO_VDD 80EXTAL 79XTAL78PLLP_GND 77PLLD_GND 76PLLD_VDD 75PLLA_GND 74PLLA_VDD 73PLLP_VDDL S Y N C _I N 37L S Y N C _O U T 38L A D 2339L A D 2240L A D 2141L A D 2042L A D 1943L A D 1844 L A D 17 45C O R E _V D D 46C O R E _G N D 47I O _V D D 48I O _G N D 49L A D 1650L A D 1551L A D 1452L A D 1353L A D 1254L A D 1155L A D 1056L A D 957I O _V D D 58I O _G N D 59C O R E _V D D 60C O R E _G N D 61L A D 862L A D 763L A D 664L A D 565L A D 466L A D 367L A D 268L A D 169L A D 070I O _G N D 71I O _V D D 72CORE_VDD 1CORE_GND2LALE 3LCS04LCS15LCS26LCS37LCS48LCS59LCS610LCS711IO_VDD 12IO_GND 13CORE_VDD 14CORE_GND15LWE 1617LGPL518LSDA1019LCKE 20LCLK 21LBCTL 22LSDWE 23LSDCAS 2425LA026LA127LA228IO_VDD 29IO_GND 30PLLP1_GND 31PLLP1_VDD 32PLLD1_GND 33PLLD1_VDD 34PLLA1_GND 35PLLA1_VDD 36144S C A N 143M O D A 0/I R Q A 142M O D B 0/I R Q B 141M O D C 0/P L O C K 140M O D D 0/P G 1139F S R _3138S C K R _3137H C K R _3136S C K T _3135F S T _3134H C K T _3133I O _G N D 132I O _V D D 131C O R E _G N D 130C O R E _V D D 129M O D A 1/I R Q C 128M O D B 1/I R Q D 127M O D C 1/N M I _1126M O D D 1/P G 2125S D O 2_2/S D I 3_2124S D O 3_2/S D I 2_2123S D O 4_2/S D I 1_2122S D O 5_2/S D I 0_2121S D O 2_3/S D I 3_3120S D O 3_3/S D I 2_3119S D O 4_3/S D I 1_3118S D O 5_3/S D I 0_3117S S /H A 2116H R E Q /P H 4115S C K /S C L 114M O S I /H A 0113M I S O /S D A 112S S _1/H A 2_1111R E S E T 110C O R E _G N D 109C O R E _VD DDSP56720144-Pin1.2Pinout for DSP56721 80-Pin Plastic LQFP PackageFor the pinout of the DSP56721 80-pin plastic LQFP package, see Figure 4.Figure 4. DSP56721 80-Pin Package60WDT 59PINIT/NMI 58TDO 57TDI 56TCK 55TMS 54CORE_GND 53CORE_VDD 52SDO4/SDI151SDO5/SDI050IO_GND 49IO_VDD 48EXTAL 47XTAL 46PLLP_GND 45PLLD_GND 44PLLD_VDD 43PLLA_GND 42PLLA_VDD 41PLLP_VDDF S T _321H C K T _322S D O 2_1/S D I 3_123S D O 3_1/S D I 2_124C O R E _VD D25C O R E _G N D26S D O 4_1/S D I 1_127S D O 5_1/S D I 0_128F S R29S C K R30H C K R31S C K T32I O _V D D33I O _G N D34C O R E _VD D35C O R E _G N D36F S T37H C K T38S D O 2/S D I 339S D O 3/S D I 240SDO2_3/SDI3_31SDO3_3/SDI2_32SDO4_3/SDI1_33SDO5_3/SDI0_34IO_VDD 5IO_GND 6CORE_VDD 7CORE_GND8SPDIFIN1/SDO2_2/SDI3_29SPDIFOUT1/SDO3_2/SDI2_210SDO4_2/SDI1_211SDO5_2/SDI0_212FSR_313SCKR_314SCKT_315GND 16GND 17GND 18GND 19GND2080S C A N79M O D A 0I R Q A78M O D B 0I R Q B77M O D C 0/P L O C K76I O _G N D75I O _V D D74C O R E _G N D73C O R E _VD D72M O D A 1I R Q C71M O D B 1I R Q D70M O D C 1/N M I _169S S /H A 268H R E Q /P H 467S C K /S C L66M O S I /H A 065M I S O /S D A64S S _1/H A 2_163R E S E T62C O R E _G ND 61C O R E _VD DDSP5672180-Pin1.3Pinout for DSP56721 144-Pin Plastic LQFP PackageFor the pinout of the DSP56721 144-pin plastic LQFP package, see Figure 5.Figure 5. DSP56721 144-Pin Package Pinout1.4Pin MultiplexingMany pins are multiplexed. For more about pin multiplexing, refer to the DSP56720/DSP56721 Reference Manual (DSP56720RM).108IO_GND 107IO_VDD 106WDT105PIINT/NMI 104TDO 103TDI 102TCK 101TMS 100SCKR_199FSR_198SCKT_197FST_196SDO0_195SDO1_194IO_GND 93IO_VDD 92CORE_GND 91CORE_VDD 90SDO089SDO188SDO4/SDI187SDO5/SDI086SPDIFOUT1/H12/HAD1285SPDIFIN1/H8/HAD884HACK/HRRQ 83HOREQ/HTRQ 82IO_GND 81IO_VDD 80EXTAL 79XTAL78PLLP_GND 77PLLD_GND 76PLLD_VDD 75PLLA_GND 74PLLA_VDD 73PLLP_VDDH A S /H A 037H A 1/H A 838H A 2/H A 938H R W /H R D 40H D S /H W R 41H C S /H A 1042I O _V D D 43I O _G N D 44F S T _345H C K T _346S D O 2_1/S D I 3_147S D O 3_1/S D I 2_148C O R E _V D D 49C O R E _G N D 50S D O 4_1/S D I 1_151S D O 5_1/S D I 0_152F S R 53S C K R 54H C K R 55S C K T 56I O _V D D 57I O _G N D 58C O R E _V D D 59C O R E _G N D 60F S T 61H C K T 62S D O 2/S D I 363S D O 3/S D I 264I O _G N D 65I O _V D D 66H 0/H A D 067H 1/H A D 168H 2/H A D 269H 3/H A D 370H 4/H A D 471H 5/H A D 572TIO0/H15/HAD151PG18/HDI_SEL2IO_GND3TIO0_1/H18/HAD184CORE_VDD 5CORE_GND 6SDO2_3/SDI3_37SDO3_3/SDI2_38SDO4_3/SDI1_39SDO5_3/SDI0_310IO_VDD 11IO_GND 12CORE_VDD 13CORE_GND 14SDO2_2/SDI3_215SDO3_2/SDI2_216SDO4_2/SDI1_217SDO5_2/SDI0_218HCKR_319FSR_320SCKR_321SCKT_322IO_VDD 23IO_GND 24H6/HAD625H7/HAD726SPDIFIN2/H9/HAD927SPDIFIN3/H10/HAD1028SPDIFIN4/H11/HAD1129SPDIFOUT2/H13/HAD1330SPLOCK/H14/HAD1431GND 32GND 33GND 34GND 35GND 36144S C A N 143M O D A 0/I R Q A 142M O D B 0/I R Q B 141M O D C 0/P L O C K 140M O D D 0/P G 1139I O _G N D 138I O _V D D 137C O R E _G N D 136C O R E _V D D 135M O D A 1/I R Q C 134M O D B 1/I R Q D 133M O D C 1N M I _1132M O D D 1/P G 2131F S R _2130S C K R _2129S C K T _2128F S T _2127S D O 0_2126S D O 1_2125I O _G N D 124I O _V D D 123S D O 0_3122S D O 1_3121S S /H A 2120H R E Q /P H 4119S C K /S C L 118M O S I /H A 0117M I S O /S D A 116S S _1/H A 2_1115H R E Q _1/P H 4_1114S C K _1/S C L _1113M O S I _1/H A 0_1112M I S O _1/S D A _1111R E S E T 110C O R E _G N D 109C O R E _VD DDSP56721144-Pin2Electrical CharacteristicsFor electrical characteristics, see Table2.Table2. Electrical CharacteristicsFor SeeSection2.1, “Chip-Level Conditions”on page8Section2.2, “Module-Level Specifications”on page172.1Chip-Level ConditionsFor a summary of chip-level conditions in this section, see Table3.Table3. Chip-Level ConditionsFor SeeSection2.1.1, “Maximum Ratings”on page8Section2.1.2, “Thermal Characteristics”on page10Section2.1.3, “Power Requirements”on page10Section2.1.4, “DC Electrical Characteristics”on page11Section2.1.5, “AC Electrical Characteristics”on page12Section2.1.6, “Internal Clocks”on page12Section2.1.7, “External Clock Operation”on page13Section2.1.8, “Reset, Stop, Mode Select, and Interrupt Timing”on page142.1.1Maximum RatingsFor maximum ratings, see Table4.CAUTIONThis device contains circuitry protecting against damage due to high static voltage orelectrical fields. However, normal precautions should be taken to avoid exceedingmaximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulledto an appropriate logic voltage level (for example, either GND or V DD). The suggestedvalue for a pull-up or pull-down resistor is 4.7kΩ.NOTEIn the calculation of timing requirements, adding a maximum value of one specification toa minimum value of another specification does not yield a reasonable sum. A maximumspecification is calculated using a worst case variation of process parameter values in onedirection. The minimum specification is calculated using the worst case for the sameparameters in the opposite direction. Therefore, a “maximum” value for a specification willnever occur in the same device that has a “minimum” value for another specification;adding a maximum to a minimum represents a condition that can never exist.Table4. Maximum RatingsRating1Symbol Value1, 2Unit Supply Voltage V CORE_VDD,V PLLD_VDD-0.3 to + 1.26VV PLLP_VDD,V IO_VDD,V PLLA_VDD,-0.3 to + 4.0V Maximum CORE_VDD power supply ramp time4Tr10ms Input Voltage per pin excluding VDD and GND V IN GND -0.3 to 5.5V V Current drain per pin excluding V DD and GND(Except for pads listed below)I12mA LSYNC_OUT I lsync_out16mA LCLK I lclk16mA LALE I ale16mA TDO I JT AG24mA Operating temperature range3T J-40 to +125°C Storage temperature T STG-65 to +150°C ESD protected voltage (Human Body Model)–2000VESD protected voltage (Charged Device) •All pins•Corner pins –500750VNotes:1.GND = 0 V, T J = -40°C to 125°C, CL = 50pF2.Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond themaximum rating may affect device reliability or cause permanent damage to the device.3.Operating temperature qualified for consumer applications. T J = T A + q JA x Power. Variables used wereCore Current = 900mA, I/O Current = 200mA, Core Voltage = 1.1 V, I/O Voltage = 3.6 V, T A = 105°C.4.If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly, causing erroneousoperation.2.1.2Thermal CharacteristicsFor thermal characteristics, see Table 5.2.1.3Power RequirementsTo prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode as shown in Figure 6, connected between the DSP56720/DSP56721 IO_VDD and Core_VDD power pins.Figure 6. Prevent High Current Conditions by Using External Schottky DiodeIf an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead of Core_VDD, as shown in Figure 7.Figure 7. Prevent High Current Conditions by Applying IO_VDD Before Core_VDDFor correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10ms, as shown in Figure 8.Table 5. Thermal CharacteristicsCharacteristicBoard Type SymbolLQFP Values UnitNatural Convection, Junction-to-ambient thermal resistance 1,2Single layer board (1s)R θJA or θJA 57 for 80 QFP 49 for 144 QFP °C/W Four layer board (2s2p)44 for 80 QFP 40 for 144 QFP°C/W Junction-to-case thermal resistance 3–R θJC or θJC 10 for 80 QFP9 for 144 QFP°C/WNotes:1.Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.2.Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.3.Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).IO_VDDCore_VDDExternal Schottky DiodeCore_VDDIO_VDDFigure 8. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD2.1.4DC Electrical CharacteristicsFor DC electrical characteristics, see Table 6.Table 6. DC Electrical CharacteristicsCharacteristicsSymbol Min Typ Max Unit Supply voltages•Core (Core_VDD)•PLL (PLLD_VDD, PLLD1_VDD)V DD0.91.01.1VSupply voltages •I/O (IO_VDD)•PLL (PLLP_VDD, PLLP1_VDD) •PLL (PLLA_VDD, PLLA1_VDD)V DDIO3.14 3.3 3.46VInput high voltageV IH2.0–V IO_VDD+2VVNote:To avoid a high current condition and possible system damage, all 3.3 volt supplies must rise before the 1.0 voltsupplies rise.Input low voltage V IL -0.3–0.8V Input leakage currentI IN ––±84μA Clock pin Input Capacitance (EXTAL)C IN 18pF High impedance (off-state) input current (@ 3.3V or 0V)I TSI -10–10μA Output high voltage I OH = -12mALSYNC_OUT , LALE, LCLK Pins I OH = -16mA, TDO Pin I OH = -24mAV OH2.4––VOutput low voltage I OL = 12mALSYNC_OUT , LALE, LCLK Pins I OL = 16mA, TDO Pins I OL = 24mAV OL––0.4VCore_VDD Tr must be < 10 ms0 V1.0VTr2.1.5AC Electrical CharacteristicsThe timing waveforms shown in the AC electrical characteristics section are tested with a V IL maximum of 0.8V and a V IHminimum of 2.0V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal’s transition. DSP56720/DSP56721 output levels are measured with the production test machine V OL and V OH reference levels set at 0.4V and 2.4V , respectively.2.1.6Internal ClocksInternal clock characteristics are listed in Table 7.Internal supply current 1 (core only) at internal clock of 200MHz•In Normal mode I CCI –190 780 mA •In Wait mode I CCW –90 680mA •In Stop mode 2I CCS –50 640mA Input capacitance C IN––10pFNotes:1.The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with V CORE_VDD = 1.0V , V DD_IO = 3.3V at T J = 25°C. Maximum internal supply current is measured with V CORE_VDD = 1.10V , V IO_VDD) = 3.6V at T J = 125°C.2.In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float).Table 7. Internal ClocksNo.CharacteristicsSymbol Min Typ Max Unit Condition1Comparison Frequency Fref 2–8MHzFref = Fin/NR2Input Clock Frequency Fin Max = 200MHz3PLL VCO Frequency Fvco 200–400MHz Fvco = (Fin * NF)/NR 4Output Clock Frequency [1] •with PLL enabled •with PLL disabled Fout25––200200MHzFout= Fvco/NO Fout = Fin5Duty Cycle–405060%Fvco=200MHz – 400MHzNotes:Fin = External frequency, NF = Multiplication Factor, NR = Predivision Factor, NO = Output DividerTable 6. DC Electrical Characteristics (Continued)CharacteristicsSymbol Min Typ Max Unit2.1.7External Clock OperationThe DSP56720/DSP56721 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see the example in Figure 9.Figure 9. Using the On-Chip OscillatorIf the DSP56720/DSP56721 system clock is an externally supplied square wave voltage source, it is connected to EXTAL (Figure 10). When the external square wave source is connected to EXTAL, the XTAL pin is not used.Figure 10. External Clock TimingTable 8. Clock OperationNo.CharacteristicsSymbolMinMaxUnits1EXTAL input high 1(40% to 60% duty cycle) •Crystal oscillator •Square wave inputEth16.672.5100infnsXT ALEXT ALSuggested component values:Fosc = 24.576 MHz R = 1 M ±10%C (EXTAL)= 18 pF Calculations are for a 5 – 30 MHz crystal with the following parameters:• Shunt capacitance (C 0) of 10 pF – 12 pF • Series resistance 40 Ohm C (XTAL) = 18 pF• Drive level of 10 μWRXT AL1CCEXTALV ILV IHMidpointNote:The midpoint is 0.5 (V IH + V IL ).ETHETLETC2312.1.8Reset, Stop, Mode Select, and Interrupt TimingFor reset, stop, mode select, and interrupt timing, see Table 9.2EXTAL input low 1(40% to 60% duty cycle) •Crystal oscillator •Square wave input Etl16.672.5100inf ns3EXTAL cycle time •With PLL disabled •With PLL enabled Etc 533.3inf 500ns4Instruction cycle time •With PLL disabled •With PLL enabledTc 5.005.00inf 5120nsNotes:1.Measured at 50% of the input transition.2.The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met.3.A valid clock signal must be applied to the EXT AL pin within 3ms of the DSP56720/DSP56721 being powered up.Table 9. Reset, Stop, Mode Select, and Interrupt Timing ParametersNo.CharacteristicsExpressionMin Max Unit 10Delay from RESET assertion to all pins at reset value 3––11ns 11Required RESET duration 4•Power on, external clock generator, PLL disabled •Power on, external clock generator, PLL enabled 2 x T C 2 x T C1010––ns ns 13Syn reset deassert delay time •Minimum2× T C 10–ns •Maximum (PLL enabled)(2x T C )+T LOCK200–us 14Mode select setup time –10.0–ns 15Mode select hold time–10.0–ns 16Minimum edge-triggered interrupt request assertion width –4–ns 17Minimum edge-triggered interrupt request deassertion width –4–ns 18Delay from interrupt trigger to interrupt code execution10 × T C + 454–nsTable 8. Clock Operation (Continued)No.CharacteristicsSymbolMinMaxUnits19Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)1, 2, 3•PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0)(128K × T C) 655–μs •PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 = 1)25 × T C125–ns •PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 = 0)(128K x T C ) + T LOCK 855–μs •PLL is not active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) (25 x T C ) + T LOCK 200–μs 20•Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion togeneral-purpose transfer output valid caused by first interrupt instruction execution 110 x T C + 3.8–53.8ns21Interrupt Requests Rate 1•ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_112 x T C –60.0ns •DMA8 x T C –40.0ns•IRQ, NMI (edge trigger)8 x T C –40.0ns•IRQ (level trigger)12 x T C –60.0ns 22DMA Requests Rate•Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1 6 x T C –30.0ns •Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_17 x T C –35.0ns •Timer, Timer_1 2 x T C –10.0ns•IRQ, NMI (edge trigger)3 x T C–15.0nsNotes:1.When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.2.For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined by the OMR Bit 6 settings.For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200μs. 3.Periodically sampled and not 100% tested.4.RESET duration is measured during the time in which RESET is asserted, V DD is valid, and the EXT AL input is active and valid. When V DD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration.Table 9. Reset, Stop, Mode Select, and Interrupt Timing ParametersNo.CharacteristicsExpressionMinMaxUnitFigure 11. Reset Timing DiagramFigure 12. External Fast Interrupt Timing DiagramV IHRESETAll Pins101113Reset Valuea) First Interrupt Instruction ExecutionGeneral PurposeI/OIRQA, IRQB,IRQC, IRQD,NMI,NMI_1b) General Purpose I/OIRQA, IRQB,IRQC, IRQD,NMI,NMI_1181920Figure 13. External Interrupt Timing Diagram (Negative Edge-Triggered)Figure 14. MODE Select Set-Up and Hold Timing Diagram2.2Module-Level SpecificationsFor a summary of the module-level specifications in this section, see Table 10.Table 10. Module-Level SpecificationsForSee Section 2.2.1, “Serial Host Interface (SHI) SPI Protocol Timing ”on page 18Section 2.2.2, “Serial Host Interface (SHI) I 2C Protocol Timing ”on page 24Section 2.2.3, “Programming the SHI I 2C Serial Clock ”on page 26Section 2.2.4, “Enhanced Serial Audio Interface (ESAI) Timing ”on page 27Section 2.2.5, “Timer Timing ”on page 32Section 2.2.6, “GPIO Timing ”on page 32Section 2.2.7, “JT AG Timing ”on page 33Section 2.2.8, “Watchdog Timer Timing ”on page 35Section 2.2.9, “Host Data Interface (HDI24) Timing ”on page 35Section 2.2.10, “S/PDIF Timing ”on page 42Section 2.2.11, “EMC Timing (DSP56720 only)”on page 43IRQA, IRQB,IRQC, IRQD,NMI,NMI_1IRQA, IRQB,IRQC, IRQD,NMI,NMI_11617RESETMODA, MODB,MODC, MODD,PINITV IHIRQC,IRQD, NMIV IH V IH 1415V ILV IL。

2SC5654资料

Transistors1Publication date: February 2003SJC00187BEDDirective (EU 2002/95/EC).Request for your special attention and precautions in using the technical information andsemiconductors described in this book(1)If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws andregulations of the exporting country, especially, those with regard to security export control, must be observed.(2)The technical information described in this book is intended only to show the main characteristics and application circuit examplesof the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book.(3)The products described in this book are intended to be used for standard applications or general electronic equipment (such as officeequipment, communications equipment, measuring instruments and household appliances).Consult our sales staff in advance for information on the following applications:– Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the prod-ucts may directly jeopardize life or harm the human body.– Any applications other than the standard applications intended.(4)The products and product specifications described in this book are subject to change without notice for modification and/or im-provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements.(5)When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment.Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.(6)Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7)This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of MatsushitaElectric Industrial Co., Ltd.。

音调解码器567详解

在图 14 中的电路有双音解码器的作用。在二个输入输入信号中有任一个出现时，都可激励出一个信号输出。图中，二个音调开关是由是一个信号源激励的，而其输出则由一个 CD4001B 型 CMOS 门集成块来进行或非处理。图 15 所示为二个 567 音调开关并行联接，其作用有中一个相对带宽为 24%的单个音调开关。在此电路中，IC1 音调开关的工作频率设计成比 IC2 音调开关的工作频率高 1.12 倍。因此，它们的转接频带是叠合的。
BW＝1070 BW 的单位为中心频率的百分数（%），而且，Vi≤200mVRMS。式中 Vi 的单位为 V-RMS，C2 的单位为 uF。通过试探和误差处理来选择 C2，一开始可选择 C2 的值为 C1 的 2 倍。随后可增加 C2 的值以减小带宽，也可减小 C2 的值以增加带宽。检测带宽的对称性所谓检测整容的对称性就是测量此带宽与中心频率的对称程度。对称性的定义如下：（fmax＋fmin－2f0）/2f 这时 fmax 和 fmin 是相应于所检测频带二边沿的频率。如果一个音调开关的中心频率为 100KHz，而带宽为 10KHz，频带的边沿频率对称于 95KHz 和 105KHz，这样，其对称性为 0%。但是，如果其频带相当不对称，边沿频率为 100KHz 和 110KHz，其对称值增加到 5%。如果需要，可以用微调电位器 R2 和 47KΩ 的电阻 R4 在 567 的引脚 2 上加一外偏微调电压，以使对称值减至 0，如图 13 所示。将电位器的中间滑动触点向上移则中心频率降低，向下移则中心频率升高。硅二极管 D1 和 D2 用作温度补偿。音调开关设计以图 3 所示的典型电路为基础，很容易设计出实用的音调开关。频率控制元件电阻 R1 和电容 C1 各值的选定可利用图 6 的诺模图。电容 C2 容量的选择可以上述讨论为基础，由实验确定。一开始可用其容量为 C1 的两倍的电容，然后，若有需要可调整其值，以给出所要求的信号带宽。如果对于频带的对称性要求严格，可如图 13 所示，加一对称性调整级。

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FEATURES•Auto Selection Multi-Mode Single Ended or Low Voltage Differential Termination•2.7V to 5.25V Operation •Differential Failsafe Bias•Built-in SPI-3Mode Change Filter/Delay•Meets SCSI-1, SCSI-2, Ultra2 (SPI-2LVD) and Ultra3/Ultra160 Standards •Supports Active Negation •3pF Channel CapacitanceMultimode(LVD/SE) SCSI 9 Line TerminatorDESCRIPTIONThe UCC5672Multi-Mode Low Voltage Differential and Single Ended Ter-minator is both a single ended terminator and a low voltage differential ter-minator for the transition to the next generation SCSI Parallel Interface (SPI-3).The low voltage differential is a requirement for the higher speeds at a reasonable cost and is the only way to have adequate skew budgets.The automatic mode select/change feature switches the terminator be-tween Single Ended or LVD SCSI Termination,depending on the bus mode.If the bus is in High Voltage Differential Mode,the terminator lines transition into a High Impedance state.The UCC5672is SPI-3,SPI-2,and SCSI-2compliant.This device is of-fered in a 28pin TSSOP package to minimize the footprint.The UCC5672is also available in a 36 pin MWP package.ABSOLUTE MAXIMUM RATINGSTRMPWR Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 5V Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C Junction Temperature. . . . . . . . . . . . . . . . . . .–55°C to +150°C Lead Temperature (Soldering, 10sec.). . . . . . . . . . . . .+300°CAll voltages are with respect to GND.Currents are positive into,negative out of the specified terminal.Consult Packaging Sec-tion of the Databook for thermal limitations and considerations of packages.RECOMMENDED OPERATING CONDITIONSTRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . .2.7V to 5.25VCONNECTION DIAGRAMELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for T A=T J= 0°C to 70°C,ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for T A =T J = 0°C to 70°C,TRMPWR = 2.7V to 5.25V.PARAMETERTEST CONDITIONSMINTYPMAX UNITSTime Delay/Filter Section Mode Change DelayA new mode change can start any time after a previous mode change has been detected.(Note4 )100180300msNote 1:Guaranteed by design.Not 100% tested in production.Note 2:()()Z VI I CM V V V V CM CM =−+−120606...;Where VCM = Voltage measured with L+ tied to L– and zero current applied;Note 3:VL X = Output voltage for each terminator minus output pin (L1– through L9–) with each pin unloaded.IL X = Output current for each terminator minus output pin (L1– through L9–) with the minus output pin forced to 0.2V .Note 4:Noise on DIFFB will not cause a false mode change.The time delay is that same for a change from any mode to any other mode.Within 300ms after power is applied the mode is defined by the voltage of DIFFB.PIN DESCRIPTIONSDIFFB:Input pin for the comparators that select SE,LVD SCSI,or HIPD modes of operation.This pin should be decoupled with a 0.1µF capacitor to ground and then coupled to the DIFSENS pin through a 20k Ωresistor.DIFSENS:Connects to the Diff Sense line of the SCSI bus.The bus mode is controlled by the voltage level on this pin.DISCNCT:Input pin used to shut down the terminator if the terminator is not connected at the end of the bus.Connect this pin to ground to activate the terminator or open pin to disable the terminator.HS/GND:Heat sink ground pins.These should be con-nected to large ground area PC board traces to increase the power dissipation capability.GND:Power Supply return.L1–thru L9–:Termination lines.These are the active lines in SE mode and are the negative lines for LVD SCSI mode.In HIPD mode,these lines are high imped-ance.L1+thru L9+:Termination lines.These lines switch to ground in SE mode and are the positive lines for LVD SCSI mode.In HIPD mode,these lines are high imped-ance.REG:Regulator bypass pin,must be connected to a 4.7 F capacitor to ground.TRMPWR:2.7V to 5.25V power input pin.Bypass near the terminators with a 4.7 F capacitor to ground.All SCSI buses require a termination network at each end to function properly.Specific termination require-ments differ,depending on which types of SCSI devices are present on the bus.The UCC5672is used in multi-mode active termination applications,where single ended (SE)and low voltage differential (LVD)SCSI devices might coexist.The UCC5672has both SE and LVD SCSI termination net-works integrated into a single monolithic component.The correct termination network is automatically determined by the SCSI bus "DIFSENS" signal.The SCSI bus DIFSENS signal line is used to identify which types of SCSI devices are present on the bus.On power-up,the UCC5672DIFSENS drivers will try to de-liver 1.3V to the DIFSENS line.If only LVD SCSI devices are present,the DIFSENS line will be successfully driven to 1.3V and the terminators will configure for LVD SCSI operation.If any single ended devices are present,they will present a short to ground on the DIFSENS line,sig-naling the UCC5672(s)to configure into the SE mode,accommodating the SE devices.Or,if any high voltage differential (HVD)SCSI devices are present,the DIFSENS line is pulled high and the terminator will enter a high impedance state,effectively disconnecting from the bus.The DIFSENS line is monitored by each terminator through a 50Hz noise filter at the DIFFB input pin.A set of comparators detect and select the appropriate termi-APPLICATION INFORMATIONnation for the bus as follows.If the DIFSENS signal is below0.5V,the termination network is set for single ended.Between0.7V and1.9V,the termination network switches to LVD SCSI,and above2.4V indicates HVD SCSI,causing the terminators to disconnect from the bus.These thresholds accommodate differences in ground potential that can occur with long lines.Three UCC5672multi-mode parts are required at each end of the bus to terminate27(18data,plus9control) lines.Each part includes a DIFSENS driver,but only one is necessary to drive the line.The DIFFB inputs on all three parts are connected together,allowing them to share the same50Hz noise filter.This multi-mode termi-nator operates in full specification down to 2.7V TRMPWR voltage.This accommodates 3.3V systems,APPLICATION INFORMATION (cont.)UNITRODE CORPORA TION7 CONTINENT AL BLVD.• MERRIMACK, NH 03054TEL.(603) 424-2410 • FAX (603) 424-3460with allowance for the 3.3V supply tolerance (+/-10%),a unidirectional fusing device and cable drop.In 3.3V TRMPWR systems,the UCC3918is recommended in place of the fuse and diode.The UCC3918's lower volt-age drop allows additional margin over the fuse and di-ode, for the far end terminator.Layout is critical for Ultra2and Ultra3/Ultra160systems.The SPI-2standard for capacitance loading is 10pF max-imum from each positive and negative signal line to ground,and a maximum of 5pF between the positive and negative signal lines of each pair is allowed.These maxi-mum capacitances apply to differential bus termination circuitry that is not part of a SCSI device,(e.g.a cable terminator).If the termination circuitry is included as part of a SCSI device,(e.g.,a host adaptor,disk or tape drive),then the corresponding requirements are 30pF maximum from each positive and negative signal line to ground and 15pF maximum between the positive and negative signal lines of each pair.The SPI-2standard for capacitance balance of each pair and balance between pairs is more stringent.The stan-dard is 0.75pF maximum difference from the positive and negative signal lines of each pair to ground.An additional requirement is a maximum difference of 2pF when com-paring pair to pair.These requirements apply to differen-tial bus termination circuitry that is not part of a SCSI device.If the termination circuitry is included as part of a device,then the corresponding balance requirements are 2.25pF maximum difference within a pair,and 3pF from pair to pair.Feed-throughs,through-hole connections,and etch lengths need to be carefully balanced.Standard multi-layer power and ground plane spacing add about1pF to each plane.Each feed-through will add about 2.5pF to 3.5pF.Enlarging the clearance holes on both power and ground planes will reduce the capacitance.Similarly,opening up the power and ground planes under the connector will reduce the capacitance for through-hole connector applications.Capacitance will also be affected by components,in close proximity,above and below the circuit board.Unitrode multi-mode terminators are designed with very tight balance,typically 0.1pF between pins in a pair and 0.3pF between pairs.At each L+pin,a ground driver drives the pin to ground,while in single ended mode.The ground driver is specially designed to not effect the ca-pacitive balance of the bus when the device is in LVD SCSI or disconnect mode.Multi-layer boards need to adhere to the 120Ωimped-ance standard,including the connectors and feed-throughs.This is normally done on the outer layers with 4mil etch and 4mil spacing between runs within a pair,and a minimum of 8mil spacing to the adjacent pairs to reduce crosstalk.Microstrip technology is normally too low of impedance and should not be used.It is designed for 50Ωrather than 120Ωdifferential systems.Careful consideration must be given to the issue of heat manage-ment.A multi-mode terminator,operating in SE mode,will dissipate as much as 130mW of instantaneous power per active line with TRMPWR =5.25V .The UCC5672is offered in a 28pin TSSOP .This package includes two heat sink ground pins.These heat sink/ground pins are directly connected to the die mount paddle under the die and conduct heat from the die to reduce the junction tem-perature.Both of the HS/GND pins need to be connected to etch area or four feed-through per pin connecting to the ground plane layer on a multi-layer board.APPLICATION INFORMATION (cont.)。