Integrated circuit yield and quality analysis meth

专利名称：Integrated circuit yield and quality analysis
methods and systems
发明人：Rajski, Janusz,Chen, Gang,Keim,
Martin,Tamarapalli, Nagesh,Tang,
Huaxing,Sharma, Manish
申请号：EP11156468.8
申请日：20050906
公开号：EP2372588A1
公开日：
20111005
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专利附图：
摘要：Methods, apparatus, and systems for testing, analyzing, and improving
integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, design defect extraction rules are derived at least partially from a set of design manufacturing rules. Potential defects are extracted from a representation of an integrated circuit layout using the design defect extraction rules. Circuit test stimuli applied during one or more circuit tests are determined. Test responses resulting from the applied circuit tests are evaluated to identify integrated circuits that fail and to identify the occurrence in the failing integrated circuits of one or more potential types of defects associated with the applied circuit tests.; Information concerning the repetitive identification in the failing integrated circuits of the occurrence of potential types of defects is collected and analyzed to determine the likelihood of potential types of defects being present in integrated circuits manufactured in accordance with the layout.
申请人：Mentor Graphics Corporation
地址：8005 S.W. Boeckman Drive Wilsonville, OR 97070-7777 US
国籍：US
代理机构：Wallin, Nicholas James
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