数字电路英文版 第七单元 医学课件教学提纲

? OLMC Output logic marcocell. The programmable output logic in a GAL.
? PAL Programmable array logic. A PLD with a programmable AND array and a fixed OR array.
? Buffer A circuit that prevents loading of an input or output.
? Cell A fused cross point of a row and columnn in a PLD.
? Complier Software that translates from high-level language that uses words or symbols, such as HDL , into low-level machine language (1s and 0s).
? Documentation file The information from a computer that documents the final design after the input file has been processed.
? E2CMOS Electrically earsable CMOS ( EECMOS). The circuit technology used for the reprogrammable cells in GAL.
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§7.1 PLD ARRAYS AND CLASSIFICATIONS
Programmable logic devices (PLDs) are used in many applications to replace SSI and MSI circuits; they save space and reduce the actual number and cost of devices in a given design.
? Software Computer programs; programs that instruct a computer what to do in order to carry out a given set of tasks.
? Synthesis The software process of converting a circuit description to a standard JEDEC file for PLD programming.
KEY TERMS
? ABEL Advanced Bollean Expression Language. A software compiler language for PLD programming; a type of hardware description language (HDL).
? Tristate output buffer A logic circuit having three output states: HIGH, LOW, and high impedance (open).
? ZIF socket Zero insertion force socket. A type of socket used in most programmers that accepts a PLD package.
? Architecture The internal functional arrangement of the elements that give a device its particular operating characteristics.
? Array In a PLD, a matrix formed by rows of product-term lines and columns of input lines with a programmable cell at each junction.
? PLA Programmable logic array. A PLD with a programmable AND and OR array.
? PLD Programmable logic device.
? Programmer An instrument that programs PLD using a JEDEC file downloaded from a computer running HDL software.
最新数字电路英文版 -第七单元医学课件
JEDEC file ( 标准数据格式文件 ) OLMC (输出逻辑宏单元 ) PAL ( 可编程阵列逻辑 ) PLA ( 可编程逻辑阵列) PLD ( 可编程逻辑器件 ) Programmer ( 编程器 ) PROM ( 可编程只读存储器 ) Software ( 软件 ) Synthesis ( 综合 ) Tristate output buffer ( 三态输出缓冲器 ) ZIF socked ( 不用力插座 )
? Fuse The programmaf PLDs; also called a fusible link.
? GAL Generic array logic. A PLD with a reprogrammable AND array, a fixed OR array, and programmable output logic macrocells.
? Input file The information entered in a computer that describes logic design using a PLD programming language such as HDL.
? Input/Output (I/O) A terminal of a device that can be used as either an input or as an output.