PSC_v41_20050303

– Want to add flexibility & headroom to your platform services – Concerned about time-to-market to add programmability
3. Implemented an NPU solution, but:
10G
Programmable Headroom
SDRAM SDRAM
SDRAM
SDRAM
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© IDT CONFIDENTIAL
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Accelerated Thinking
TM
IL-PSC Offload by Application
NPU or ASIC/FPGA
• Ethernet Bridging • VLAN • IPv4 • IPv6 • MPLS • SLA Enforcement
IL-PSC: Functional View
Internal Tables & Statistics Database Aging Acceleration
Search Engines
SPI 4.2 Input (400 MHz)
Packet Assembly
Recursive Packet Parser
Accelerated Thinking
TM
பைடு நூலகம்
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Data Flow Diagram
Packet In
Packet Rx Port
Control Plane In
Packet Memory Packet Parser Search Control Packet Editor
Inexpensive Programmable Line Rate Offload for Complex Packet Classification and Header Processing
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Accelerated Thinking
Packet Out
Accelerated Thinking
TM
PSC Linecard Architectures
TCAM SRAM SRAM
Classifier
ASIC / FPGA / NPU
MAC / Framer
Fabric
6/18/2014
PHY PHY PHY
TM
CostReduction
Issues
– – – – – Doesn't scale Not inherently secure No Direct QoS support Not Resilient Disruptive
Solutions
– Stacked VLANs / MPLS / VPLS for Scalability – Prioritization for CoS / QoS – Data tunneling for security – Programmability for Timeto-Market improvement
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Associated Data SDRAM (333 MHz) PAGE 11
External Stats SDRAM (333 MHz)
Accelerated Thinking
SPI 4.2 Output (400 MHz)
TM
Expansion
15 Mpps 82 Byte Packets
• Integrated Search Engines for Classification, Filtering Support • Recursive Search Capability
– Build and recursively apply up to 4 keys per packet @ line rate
Meter it ?
Count it ?
Traffic Manager
Typical Packet Processing Functionality PSC Functionality Partial PSC Functionality
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Packet / Result Out
Packet Tx Port
Search Result Up to 4x Key: 32 - 320 bits Handle Assoc. Data (up to 256 bits)
Payload
Payload
Handle (Index) Assoc. Data
10G Classification 10G ACL Filtering Policing State Processing Packet Editing Customer Differentiation <10G Congestion Avoidance Shaping <10G
SDRAM SDRAM TCAM
Recursive Search Control
Packet Editor
Processor Array (x 64 Threads) Packet Insertion Extraction
External Tables & Statistics I/F
Packet Buffer
PCI Interface (32 x 66 MHz)
– Transition to an NPU is risky, expensive – Want a simple, fast, inexpensive programming environment
2. Modifying an existing FPGA / ASIC solution, but:
Packet Processing Features
Typical resource budgets per packet for Ethernet applications are shown in this table
Function
Exact Match searches (<= 128 bit) TCAM searches (<= 160 bit) Assoc. Data reads OR writes (120 bit) Max. Associated Data writes (120 bit) Off-chip Stats counter updates Local SRAM accesses (128 bit) Packet modifications (1-16 Byte updates) Max. latency budget (usec) @ 300MHz 10 GbE
• User-defined, programmable per-packet modification
– Optimized for en/de-encapsulation and tags (VLAN / MPLS etc.) – ~60M modifications per second (up to 4 per packet) at line rate
Intelligent Transport
Aggregation
Reduced CAPEX / OPEX
Equipment Convergence
Market Disruption Increased Use of Ethernet / IP
Increased Services
Service Price Reductions
Packet Input Search Engines
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External Memory
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• Statistics • Associated Data
Packet / Result Output
Accelerated Thinking
TM
TM
PSC in Packet Processing Flow
What is it ? Who sent it ? What do I do with it?
(Classification) Forward it ?
(includes validation)
Packet In
Modify it ?
Traffic Manager
<10G • Port-based QoS • Class-based QoS • Flow-based QoS <10G
10G
NPU or ASIC/FPGA
PSC
10G • Ethernet Bridging • VLAN • VPLS • Q-in-Q 10G • IPv4 • IPv6 • MPLS • SLA Enforcement • Port-based QoS • Class-based QoS • Flow-based QoS
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10G
6/18/2014
© IDT CONFIDENTIAL
Accelerated Thinking
TM
IL-PSC Packet Processing Features
• 10 Gbps (uni-directional) Offload Co-Processor
– Targeting 15M packets per second (15M PPS)