FPGA可编程逻辑器件芯片XC2V1500-4FFG896I中文规格书

Figure 52: ODT_SINGLE
X22491-041519 The ODT attribute uses the following syntax in the XDC file:
set_property ODT value [get_ports port_name]
Values can be RTT_40, RTT_48, and RTT_60 for termination values of 40Ω, 48Ω, or 60Ω, respectively. RTT_40 is the default ODT setting.
For source termination, Versal devices provide calibrated output impedance control.
Figure 53: Controlled Output Termination
X21641-092418
Values can be RDRV_40, RDRV_48, and RDRV_60 for termination values of 40Ω, 48Ω, or 60Ω, respectively.
set_property OUTPUT_IMPEDANCE value [get_ports port_name]
Chapter 4: XP IOB Resources
DCITERMDISABLE
Bidirectional primitives that use ODT (SPLIT or SINGLE) internal termination have a DCITERMDISABLE port that allows you to disable internal input termination.Asserting this port High can help save power during long periods of IDLE time on an interface. Differential Termination Attribute
In addition to calibrated impedance, a fixed precision 100Ω differential input impedance block is available in XP IOB input pairs to support LVDS15 and MIPI_DPHY. For both LVDS15 and
MIPI_DPHY, the bank must be powered at the VCCO level (1.5V for LVDS15 or 1.2V for
MPI_DPHY) to use the differential impedance block.
The DIFF_TERM_ADV attribute can be set to TERM_100 or TERM_NONE (default) to enable internal 100Ω termination. It uses the following syntax in the XDC file:
set_property DIFF_TERM_ADV [get_ports port_name]
XP IOB Level Hold and Bias Features
The XP IOB provides several weak hold and biasing features in Versal devices. These features are designed to provide a known level to a pin that is not actively driven.
PULLUP, PULLDOWN, KEEPER
All XP IOB pins can enable a weak internal PULLUP bias to V CCO, a weak internal PULLDOWN to GND, or a weak internal KEEPER circuit that both pulls up to V CCO or pulls down to GND, based on the last driven pin voltage. The PULLTYPE attribute can be set to NONE, PULLUP, PULLDOWN, or KEEPER using the following syntax in the XDC file:
set_property PULLTYPE value [get_ports port_name]
DQS_BIAS, DC_BIAS, and AC Coupling
DQS_BIAS
DQS_BIAS behaves as a logic 0 holding mechanism for undriven pins in pseudo-differential buffers (for example: DIFF_HSTL or DIFF_SSTL) by weakly pulling the P-side of the buffer to GND and the N-side of the buffer to V CCO. This allows an IDLE link to maintain a fixed logic level when a driver and termination are disabled on the link. The left circuit in the following figure shows DQS_BIAS behavior on pseudo-differential links.
The allowed values for the DQS_BIAS attribute for applicable I/O standards are TRUE and FALSE (DEFAULT) and are enabled using the following syntax:
set_property DQS_BIAS TRUE|FALSE [get_ports port_name]
DC_BIAS
DC_BIAS provides an internal bias to both P and N pins used as an input in scenarios where an AC coupled differential signal needs to be re-biased such that the LVDS15 receiver specifications are met. The DC_BIAS feature creates a bias through an equivalent voltage divider network to the bank's V CCO. The DC_BIAS attribute can be added to the XDC:
set_property DC_BIAS DC_BIAS_0|DC_BIAS_1|DC_BIAS_2|DC_BIAS_3 [get_ports
port_name]
The DC_BIAS_1 setting provides the equivalent to 192 Ω at 20% V CCO. In a 1.5V bank, the combination of DIFF_TERM_ADV and DC_BIAS_1 provide an appropriate termination and bias for an AC coupled LVDS link without the need for bias or termination components on the PCB. DC_BIAS_2 provides the equivalent of 48Ω to 20% V CCO, but is not recommended for use with AC coupling due to a higher current draw caused by the voltage divider used to generate the equivalent 48Ω voltage divider. DC_BIAS_3 provides a 50Ω to GND bias which has very limited practical use as a bias network. With a LVDS15 IOSTANDARD used in a 1.5V bank, the combination of DC_BIAS_1 and DIFF_TERM_ADV provide both a bias and termination appropriate for many differential signals that require AC coupling. Because DC_BIAS can corrupt a weaker driver, it should not be used when the IOB is configured as an output or bidirectional. Table 91: DC_BIAS Levels Explained
DC_BIAS Attribute Description
DC_BIAS_0No Bias
DC_BIAS_1192Ω to 20% V CCO. Suitable for AC coupling applications
needing a weaker bias. DIFF_TERM_ADV or equivalent
external 100Ω termination should be used with DC_BIAS_1.
DIFF_TERM_ADV is only available in a 1.5V V CCO
DC_BIAS_248Ω to 20% V CCO. Provides a strong bias and termination.
DC_BIAS_2 should not be used with DIFF_TERM_ADV.
DC_BIAS_350Ω to GND. Care must be taken to ensure that GND biased
signal does not violate input lower levels outlined in the
data sheet.。