2019年-basicCMOSanalogicdesignLecture13designofOp-amps-PPT精选文档
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Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
design process of op-amps (cont.)
2. Requirements:
1) gain 2) gain bandwidth 2) 3) settling time 4) slew rate 5) Input common mode range (ICMR) 6) Common mode rejection ratio (CMRR) 7) power-supply rejection ratio (PSRR) 8) output-voltage swing 9)output resistance 10) Offset 11) noise 12) power dissipation 13) layout area
Useful relationships :
R out
2 N P I SS
A V g m 1 R out
3 dB 1 / R out C L
V IC (max) V DD V SG 3 V TN 1
V IC (min) V SS V DS 5 ( sat ) V GS 1 , 2
or modify the circuit (choose a different topology); 3) design W3/L3 (W4/L4) to satisfy the upper ICMR; 4) design W1/L1 (W2/L2) to satisfy the gain; 5) design W5/L5 to satisfy the lower ICMR; 6) Iterate where necessary
EIS Soochow University
ZRHP Z1
gm6 CC
600 Phase margin requires that gm6=2.2(CL/CC)
if all other roots are >=10GB
ICMR Vin max VDD
I5
3
VT03 (max) VT1(min)
Micro-electronics Departsity
CMOS Analog IC Design
Design example(cont.)
3.Design of a two stage op-amp 1) Block diagram of a general two stage op-amp and a realization:
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design example(cont.)
3. Design of a two stage op-amp (cont.)
Design procedure
1).choose the smallest device length that will keep the channel modulation parameter constant and give good matching for current mirrors;
SR I SS / C L
Pdiss V DD V SS I D
Where ID is all DC currents
following from VDD to VSS
Micro-electronics Department
EIS Soochow University
CMOS Analog IC Design
CMOS Analog IC Design
design process of op-amps
1.Boundary conditions and requirements definition
2.decide on a suitable configuration
3.determine the type of compensation needed to meet the specifications
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design example(cont.)
1. Design of a CMOS differential amplifier with a current-mirror load(cont.)
ICMR VinminVSS
I5
1
VT1(max)VDS5(sat)
VDS(sat)
2IDS
CMOS Analog IC Design
Design example(cont.)
3. Design of a two stage op-amp (cont.) 3) Specifications of the amplifier for the design:
2) From the desired phase margin, choose the minimum value for CC ; that is ,for a 600 phase margin we sue the following relationship this assumes that z>=10GB,
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design example
1. Design of a CMOS differential amplifier with a current-mirror load
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
CMOS Analog IC Design
the characterizations of op-amps
Op-amplifiers will be characterized by the following properties:
Design example(cont.)
1.Design of a CMOS differential amplifier with a current-mirror load (cont.)
design procedure: 1)pick ISS to satisfy the slew rate knowing CL or the power dissipation; 2) check to see if Rout will satisfy the frequency response(f-3dB) ,if not change ISS
SR
I5 CC
I7
I 5 , C L
CC
A V 1
g m1 g ds 2 g ds 4
2 g m1 I5 2 4
A V 2
gm6 g ds 6 g ds 7
gm6 I6 6 7
GB g m 1 CC
Mp iocut ro-eleCgcLtm r6onics Department
• large-signal voltage transfer characteristics • large-signal voltage swing limitations • small-signal ,frequency independent performance
----- gain, input resistance, output resistance • small-signal, frequency response • other properties ----- noise, power dissipation, etc.
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design example(cont.)
3. Design of a two stage op-amp (cont.)
2) Pertinent equations for the design:
CMOS Analog IC Design
Lecture 12 Design of Op Amps
Micro-electronics Department EIS Soochow University
index
1. the characterizations of op-amps 2. Design hierarchy of op-amps 3. design process steps of op-amps 4. design examples 5.physical design 6. Simulation and measurement 7.references
4.design device sizes for proper DC,AC and transient performance
5.simulation, redesign and optimization
6.physical design (layout) and fabrication
7. test and measurement
Design considerations:
Constraints
specifications
Power supply
small-signal gain
Technology Temperature
frequency response(CL) ICMR
slew rate (CL) power dissipation
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design hierarchy of op-amps
Micro-electronics Department EIS Soochow University
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design example(cont.)
2.Design of a simple cascode amplifier pertinent design equations for design of a simple cascode amplifier
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
design process of op-amps (cont.)
1.Boundary conditions:
1). Process specifications (VT , K/, Cox ,etc) 2). Supply voltage and range 3). Supply current and range 4) operating temperature and range
• gain at DC, AV(0) • gain-bandwidth , GB • phase margin (or settling time) • input common-mode range, ICMR • load capacitance, CL • slew rate ,SR • output voltage swing • power dissipation, Pdiss
CC>0.22CL;
3) Determine the minimum value for the tail current (I5) from the largest of the two values:
CMOS Analog IC Design
design process of op-amps (cont.)
2. Requirements:
1) gain 2) gain bandwidth 2) 3) settling time 4) slew rate 5) Input common mode range (ICMR) 6) Common mode rejection ratio (CMRR) 7) power-supply rejection ratio (PSRR) 8) output-voltage swing 9)output resistance 10) Offset 11) noise 12) power dissipation 13) layout area
Useful relationships :
R out
2 N P I SS
A V g m 1 R out
3 dB 1 / R out C L
V IC (max) V DD V SG 3 V TN 1
V IC (min) V SS V DS 5 ( sat ) V GS 1 , 2
or modify the circuit (choose a different topology); 3) design W3/L3 (W4/L4) to satisfy the upper ICMR; 4) design W1/L1 (W2/L2) to satisfy the gain; 5) design W5/L5 to satisfy the lower ICMR; 6) Iterate where necessary
EIS Soochow University
ZRHP Z1
gm6 CC
600 Phase margin requires that gm6=2.2(CL/CC)
if all other roots are >=10GB
ICMR Vin max VDD
I5
3
VT03 (max) VT1(min)
Micro-electronics Departsity
CMOS Analog IC Design
Design example(cont.)
3.Design of a two stage op-amp 1) Block diagram of a general two stage op-amp and a realization:
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design example(cont.)
3. Design of a two stage op-amp (cont.)
Design procedure
1).choose the smallest device length that will keep the channel modulation parameter constant and give good matching for current mirrors;
SR I SS / C L
Pdiss V DD V SS I D
Where ID is all DC currents
following from VDD to VSS
Micro-electronics Department
EIS Soochow University
CMOS Analog IC Design
CMOS Analog IC Design
design process of op-amps
1.Boundary conditions and requirements definition
2.decide on a suitable configuration
3.determine the type of compensation needed to meet the specifications
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design example(cont.)
1. Design of a CMOS differential amplifier with a current-mirror load(cont.)
ICMR VinminVSS
I5
1
VT1(max)VDS5(sat)
VDS(sat)
2IDS
CMOS Analog IC Design
Design example(cont.)
3. Design of a two stage op-amp (cont.) 3) Specifications of the amplifier for the design:
2) From the desired phase margin, choose the minimum value for CC ; that is ,for a 600 phase margin we sue the following relationship this assumes that z>=10GB,
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design example
1. Design of a CMOS differential amplifier with a current-mirror load
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
CMOS Analog IC Design
the characterizations of op-amps
Op-amplifiers will be characterized by the following properties:
Design example(cont.)
1.Design of a CMOS differential amplifier with a current-mirror load (cont.)
design procedure: 1)pick ISS to satisfy the slew rate knowing CL or the power dissipation; 2) check to see if Rout will satisfy the frequency response(f-3dB) ,if not change ISS
SR
I5 CC
I7
I 5 , C L
CC
A V 1
g m1 g ds 2 g ds 4
2 g m1 I5 2 4
A V 2
gm6 g ds 6 g ds 7
gm6 I6 6 7
GB g m 1 CC
Mp iocut ro-eleCgcLtm r6onics Department
• large-signal voltage transfer characteristics • large-signal voltage swing limitations • small-signal ,frequency independent performance
----- gain, input resistance, output resistance • small-signal, frequency response • other properties ----- noise, power dissipation, etc.
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design example(cont.)
3. Design of a two stage op-amp (cont.)
2) Pertinent equations for the design:
CMOS Analog IC Design
Lecture 12 Design of Op Amps
Micro-electronics Department EIS Soochow University
index
1. the characterizations of op-amps 2. Design hierarchy of op-amps 3. design process steps of op-amps 4. design examples 5.physical design 6. Simulation and measurement 7.references
4.design device sizes for proper DC,AC and transient performance
5.simulation, redesign and optimization
6.physical design (layout) and fabrication
7. test and measurement
Design considerations:
Constraints
specifications
Power supply
small-signal gain
Technology Temperature
frequency response(CL) ICMR
slew rate (CL) power dissipation
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design hierarchy of op-amps
Micro-electronics Department EIS Soochow University
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
Design example(cont.)
2.Design of a simple cascode amplifier pertinent design equations for design of a simple cascode amplifier
Micro-electronics Department EIS Soochow University
CMOS Analog IC Design
design process of op-amps (cont.)
1.Boundary conditions:
1). Process specifications (VT , K/, Cox ,etc) 2). Supply voltage and range 3). Supply current and range 4) operating temperature and range
• gain at DC, AV(0) • gain-bandwidth , GB • phase margin (or settling time) • input common-mode range, ICMR • load capacitance, CL • slew rate ,SR • output voltage swing • power dissipation, Pdiss
CC>0.22CL;
3) Determine the minimum value for the tail current (I5) from the largest of the two values: