88E1111 数据手册(中文)-第一部分

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88E1111-SFP-RefDsgn-Schematics-Rev-1-0new

88E1111-SFP-RefDsgn-Schematics-Rev-1-0new
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EM111单相能源分析仪操作手册说明书

EM111单相能源分析仪操作手册说明书

Energy Management Energy Analyzer Type EM111Product descriptionSingle-phaseenergy analyzer with backlit LCD display with integrated touch keypad. Particularly indicated for active energy metering and for cost allocation inapplications up to 32 A (direct connection) or up to 300 A (CT connection) or up to 600 A (333 mV current sensor), with dual tariffmanagement availability. It can measure• Single phase energy analyzer• Class 1 (kWh) according to EN62053-21• Class B (kWh) according to EN50470-3• Accuracy ±0.5% RDG (current/voltage)• Current measurement via 333 mV current sensor up to 600 A (MV5)• Current measurement via CT up to 300 A (AV5)• Rated primary current: 32 A (AV7, AV8)• Max primary current: 45 A (AV7, AV8)• Max cable cross section: 6 mm 2• Backlit LCD display with integrated touch key-pad • Energy readout on display: 7 digit • Variable readout on display: 4 digit• Energy measurement: kWh and kvarh (imported/exported); kWh+ by 2 tariffs• System variables, kW, kvar, V, A, PF, Hz, kWdmd, kWdmd peak • Self power supply• Dimensions: 1-DIN module • Protection degree (front): IP51• Pulse output (by open collector PNP)• RS485 Modbus port • M-Bus port• Digital input (for tariff management)• Easy connection or wrong current direction detection • Compliant with the international accuracy standard IEC/EN62053-21, and the IEC/EN61557-12 performance requirements (active power and active energy).• Certified according to MID Directive (option PF only): see “how to order” belowimported and exported energy or be programmed to sum them into an unique totalizer. Housing for DIN-rail mounting, with IP51 front degree protection. The meteris provided with pulse output proportional to the active energy being measured, RS485 Modbus port or M-Bus port.Certified according to MID Directive, Module Band Module D of Annex II, for legal metrology relevant to active electrical energy meters (see Annex V, MI003, of MID). Can be used for fiscal (legal) metrology.Type SelectionRange codeAV8: 230VLN AC - 5(45)A(Direct connection up to 32 A)Power supply X:Self power supplyOutput O1: pulse output S1: RS485 Modbus port M1:M-Bus portSystem 1:1-phase 2-wireOption PF:Certified according to MID Directive. Can be used for fiscal (legal) metrology.Measurement A:The power is always integrated (both in case of positive imported and negative exported power) and the total energy meter is certified according to MID. Operating temperature: from –25 to +55°C/from –13 to +131°FB:Only the total positive energy meter is certified according to MID. Operating temperature: from –25 to +55°C/from –13 to +131°FA70: The power is always integrated (both in case of positive imported and negativeexported power) and the total energy meter is certified according to MID. Operating temperature: from –25 to +70°C/from –13 to +158°F B70: Only the total positive energy meter is certified according to MID. Operatingtemperature: from –25 to +70°C/from –13 to +158°FEM111Not certified according to MID Directive. Cannot be used for fiscal (legal) metrology.Type SelectionRange codeAV8:230VLN ac - 5(45)A(Direct connection upto 32 A)AV7:120VLN ac - 5(45)A (Direct connectionup to 32 A). Availableon request (MOQ 100pcs)AV5:230VLN ac - 5(6)A(CT connection), S1output onlyMV5:230VLN ac - 333 mV(current sensor con-nection), S1 outputonlyPower supplyX:Self power supplyOutputO1:pulse outputS1:RS485 Modbus portM1:M-Bus port System1:1-phase 2-wireOption X:noneEM111Input specificationsEM111Output specificationsDigital input specificationsDigital inputsFree of voltage contact FunctionTariff management (switch between t1-t2)Number of inputs 1 Contact measurement voltage 5 V Input impedance 1kohm Contact resistance ≤ 1kohm, close contact ≥ 100kohm, open contactOverloadIn case a voltage iserroneously applied to the digital input, the input is not damaged up to 30 V ac/dc.EM111General specificationsPower supply specificationsPower supplyself power supplyPower consumption≤ 1.0W, ≤ 8VAEM111Insulation (for 1 minute) between inputs and outputsEM111MID compliance (PF option only)Accuracy (according to EN62053-21 and EN62053-23) - AV5 modelkWh,accuracy (RDG) depending on the currentClass 1 accuracy limits (Active energy)5(6)A Start-up current: 10mA +1.5%+1%0%-1%-1.5%PF=10.25A(I min )0.5A(I tr )5A(I n )6A(I max )0.5A(I tr )5A(I n )6A(I max )PF=L0.5or C0.8(0,1I ref )(0,1I ref )(0.05I ref )kvarh,accuracy (RDG) depending on the currentClass 2 accuracy limits (Reactive energy)5(6)A Start-up current: 10mAError+2.5%+2%0%-2%-2.5%sin j =10.25A0.5A 5A(In)6A(I max )1A5A(In)6A(I max )sin j =0.5(0.1In)(0.25In)0.5A(0.05In)(0.1In)ErrorEM111Accuracy (according to EN50470-3 and EN62053-23) - A V7/A V8 modelkWh,accuracy (RDG) depending on the currentClass 1 accuracy limits (Active energy)5(45)A Start-up current: 20mA Percentage error limits for class index B+1.5%+1%0%-1%-1.5%PF=10.25A(I min )0.5A(I tr )5A(I n )45A(I max )0.5A(I tr )5A(I n )45A(I max )PF=L0.5or C0.8(0,1I ref )(0,1I ref )0.05A(I ref )kvarh,accuracy (RDG) depending on the currentClass 2 accuracy limits (Reactive energy)5(45)A Start-up current: 20mAError+2.5%+2%0%-2%-2.5%sin j =10.25A0.5A 5A(Ib)45A(I max )1A5A(Ib)45A(I max )sin j =0.5(0.1Ib)(0.25Ib)0.5A(0.05Ib)(0.1Ib)Display pagesX= availableMeasurement accuracy according to IEC/EN61557-12 (MID versions)Active powerPerformance class 1Active energyPerformance class 2EM111List of available menusNote: after the confirmation of a new parameter value, the value is stored in the memory without the need to exit the programming mode.EM111Additional available information on the display (*)(*) can be reached by pressing simultaneously the 2 touch keysEM111Specification are subject to change without notice EM111 DS 01092111AV7, AV8 wiring diagramsAV5 wiring diagramsMV5 wiring diagramsEM111Specification are subject to change without notice EM111 DS 01092112Input/output communicationEM111Specification are subject to change without notice EM111 DS 01092113Front panel description1. DisplayBacklit LCD display with touch key-pad. Upper part: enter2. LEDLED proportional to kWh reading3. Serial number and MID dataArea reserved to serial number and MID-relevant data in PF versionsDimensions (mm)。

EN1111(中文版).pdf卫浴龙头---混合调温阀芯

EN1111(中文版).pdf卫浴龙头---混合调温阀芯

阀芯温度控制装置应有以下识别信息: --刻度或符号 --和/或颜色(冷水蓝色,热水红色) 调温龙头必须清晰地在热水进水口用红色标记,冷水进水口用蓝色标记.可互相转换的供水装置不用作标记.
7 材质
7.1 化学及卫生特征 人类使用的与水接触的材料,温度到 90℃,对人休健康无危害.不得对人类用水造成污染,以致影响食物的质量, 外观,气味或味觉. 在条款 1 推荐的正确操作极限内,材料对龙头在使用中的操作不会造成负面影响.受压部件必须符合表 1 规定的使 用极限. 不完全耐腐蚀的材料表面须另外保护. 7.2 表面状况及涂层质量 表面镀铬及镍-铬材料,需满足 EN248 要求.
尺寸必须保证龙头安装在厚度 1-18mm 的支撑
上,并与供水连接
24(最大)
35(最大). 用于浴缸
龙头底座后面突出部分,从 A 直径中轴线量起
32(最大). 用于面盆,妇洗器及水槽
8.2.2.1 连接接头尺寸(见草图 4 及表 5) 如果接头机加后,要求接入管子,其尺寸应符合表 5 要求(例类型 1 或类型 2)
3 定义 该标准中,以下定义适合: 调温阀芯:是指带有一个或多个出水口,能自动混合冷热水并控制混合水达到用者选择的温度,最小到最大流 量可由同一控制装置或由单独的流量控制装置来完成.
4 分类 分类包括以下类型的调温龙头: 类型 1---单把控制:调温阀芯流量及温度由一个控制装置来完成. 类型 2---双把控制:调温阀芯流量及温度由两个单独的控制装置来完成. 类型 3---单独间接控制:调温阀芯由一个单独的,设定好的流量及温度调节装置,来控制流量及温度,有关闭装 置. 类型 4---无流量控制装置的调温阀芯. 类型 5---其它:带特殊控制装置的调温阀芯.
表 5—连接接头尺寸

中文EN 1111

中文EN 1111

英国标准BS EN1111:1999卫浴龙头-低压恒温混合阀(PN10)-总体技术规范这份欧洲标准EN 1111:1998具有英国标准的作用ICS91.140.70未经BSI 许可,不可拷贝,除非拷贝法许可BSI国家标准的前言这份英国标准是EN1111:1998的英语版本.在准备工作中,英国的参与是技术委员会B/504,水供给,委托小组委员会B/504/8,终端管件,它负责于:-援助理解此文的询问者;-给予欧洲委员会在解释上,或更改建议上可靠的询问,保持英国的关心受到通知;-监控相关的国际和欧洲发展,并在英国公布.描述委员会的组织清单可在秘书处获得.交叉-参考本文献内的增补国际或欧洲出版物的英国标准可在题为“国际标准信件索引”下的BSI标准目录中找到,或通过使用BSI标准电子目录中的“寻找工具.”英国标准不支持包括一个合同中所有需要的条款.英国标准的使用者对他们正确的用途负责.遵守英国标准本身不是授予豁免法律义务.页数概要这份文件由一页前封面,一页内部前封面,EN题目页,第2到35页,和一页后封面组成.自从出版发行以来的修正修正号日期受影响的文章这份英国标准在房屋和建筑工程委员会的指导下准备起来,在标准委员会的授权下发行,并在1999年3月15日生效.BSI 英国标准协会BSI是负责准备英国标准的独立国家机构.它提出欧洲和国际水平英国方面的标准.它与皇家宪章相合并.修订英国标准通过修正或修订更新.英国标准的用者要确保他们拥有最新的修正或版本.改进我们产品和服务的质量是BSI不变的目标.如果有人在使用英国标准时,发现不精确或含糊不清的地方,并告知技术委员会的秘书处,我们将感激不尽,身份可在内部前封面找到.电话:0181 996 9000.传真:0181 996 7400.BSI向成员提供称为PLUS个人的更新服务,其可确保订户自动收到最新版本的标准.购买标准订购所有的BSI,国际和国外标准出版物,都应写信到客服部.电话:0181 996 9001.传真:0181 996 7001.除另有规定外,作为对订购国际标准的回馈,供应这些标准BSI的增补内容是BSI的政策,这些增补内容以被出版成英国标准.有关标准的信息BSI通过其图书馆和对出口服务的技术援助提供广泛的有关国家,欧洲和国际标准的信息.各种BSI电子信息服务也有提供,给出其所有产品和服务的细节.联系信息中心.电话:0181 996 7111.传真:0181 996 7048.订购的BSI成员要跟上标准发展的日期,并可收到标准购买价的折扣.这些细节和其他利益联系成员管理中心.电话:0181 996 7002.传真:0181 996 7001.版权版权存在于所有的BSI出版物中.在英国,BSI也持有国际标准机构出版物的版权.除了版权,设计和专利法案1988下的许可之外,没有其他的摘要可复制,储存于恢复体系,或以任何的形式或手段转发电子,复印,录音或其他的方式事先没有得到BSI的书面许可.在增补标准的过程中,这并不排除免费使用需要的细节,如符号,和尺寸,类型或级别命名.如果这些细节用于其他目的而非增补,那么,必须获得BSI预先的书面许可.如果取得许可,条款需要包括皇家付款或一个许可证同意.细节和通知可从版权经理处获得. 电话:0181 996 7070.英语版本卫浴水龙头低恒温混合阀(PN10) 总体技术规范这份欧洲标准有CEN在1998年5月7日批准.CEN成员要遵守CEN/CENELEC国际管制,该国际管制复制条件使得这份欧洲标准在没有更变的情况下有国家标准的地位.最新的有关这国家标准的列表和著书目录的参考可从秘书中心处或CEN的成员处取得.这份欧洲标准有三种官方版本(英语,法语,德语).任何在CEN成员的义务下翻译成另外一种语言的版本并通知到秘书中心处,具有同官方版本相同的地位.CEN成员是澳大利亚,比利时,智利,丹麦,芬兰,法国,德国,希腊,冰岛,爱尔兰,意大利,卢森堡公国,荷兰,挪威,葡萄牙,西班牙,瑞典,瑞士和英国的国家标准机构.CEN欧洲标准化组织EN 1111:1998前言这份欧洲标准经技术委员会CEN/TC164,水供给,由AFNOR举行的秘书会议准备.这份欧洲标准应给予国家标准的地位,要么通过同一文章的出版,要么通过背书,最近是在1998年十一月,在其上,与国家标准冲突的应被撤消.根据CEN/CENELEC国际管制,下列国家的国家标准组织要增补这份欧洲标准:澳大利亚,比利时,智利,丹麦,芬兰,法国,德国,希腊,冰岛,爱尔兰,意大利,卢森堡公国,荷兰,挪威,葡萄牙,西班牙,瑞典,瑞士和英国.目录页码前言 2简介 41 范围 42 标准的参考 43 定义 54 分类 55 命名 56 标识-识别 56.1 标识 56.2 识别 57 材料 57.1化学和卫生特性 57.2暴露的表面状况和涂层质量 58尺寸特性 68.1图纸的总评注 68.2固定于水平表面的恒温混合阀 68.3固定于垂直表面的恒温混合阀16 8.4水出口体的尺寸18 8.5特例199防漏的特性20 9.1总则20 9.2测试方法20 9.3恒温混合阀闭塞物逆流和闭塞物的防漏性. 20 9.4恒温混合阀闭塞物的防漏性-热和冷水之间的交叉流. 20 9.5恒温混合阀闭塞物顺流的防漏性20EN 1111:19989.6恒温混合阀人工分流器的防漏性21 9.7带有自动返回的恒温混合阀分流器的防漏性21 9.8要求概要21 10水压操作特性21 10.1总则21 10.2测试方法21 10.3器械21 10.4安装和开始设置程序24 10.5流率的测量24 10.6敏感性25 10.7冷水失败的安全测试26 10.8带有变化入口压力的温度稳定测试26 10.9带有变化入口温度的温度稳定测试27 11压力下的机械性能27 11.1总则27 11.2器械27 11.3恒温混合阀闭塞物逆流机械性能的测试-闭塞物在关闭的位置27 11.4恒温混合阀闭塞物顺流机械性能的测试-闭塞物在开启的位置27 12机械耐久特性28 12.1总则28 12.2恒温阀流率控制设备的耐久(寿命)测试28 12.3分流器的机械耐久性28 12.4旋转嘴的机械耐久性29 13操作控制的扭力抵抗特性30 13.1总则30 13.2测试方法30 14声学特性30 14.1总则30 14.2程序31 14.3要求31 15对饮用水污染的保护31 附件A(提供信息的)压力释放三通的例子32 附件B(提供信息的)声学分类(例子) 33 附件C(提供信息的)防漏性测试的概要34附件D(提供信息的)参考书目35EN 1111:1998简介有关本标准含盖产品所引起的人类消费水质量潜在的反作用.1)在没有限制的条件下,在EU或欧洲自由贸易地域的成员国内,本标准不提供关于产品是否可用的信息.2)应当注意,在等候采用能证实的欧洲标准时,现存的有关产品使用和/或特性的国家管制保持有效.这份欧洲标准描述了:-尺寸,防漏性,机械和水压性能,恒温混合阀需要符合的机械耐久性和声学特性;-测试这些特性的程序.它适用于:-在盥洗室(厕所,浴室等)和厨房中卫浴设备上使用的恒温混合阀.-表1所示的压力和温度条件下使用的PN10恒温混合阀.这份标准考虑到在”家”用中供给一个单独出水口或少数出水口的低压恒温混合阀的使用(例如一个阀,控制一个淋浴,浴缸,面盆,妇洗器).它不包括专为供给大量出水口而设的阀门(例如社会公共机构的用途).表1-恒温混合阀使用的条件使用界限正确操作的推荐界限动压最小0,05MPa 0,1MPa≤P≤0,5MPa(0,5 bar) (1bar≤P≤5bar)静压最大1Mpa(10bar) -热水温T≤90。

88E111调试心得

88E111调试心得

回想调试88E1111芯片时,遇到不少的心酸,花掉不少的money,从目前实现的UDP数据传输,ICMP ping包,ARP包,与大家一起分享一下,也许是受到调试时遇问题发帖求助,到热心网友的帮助的感慨吧;1、芯片Package:我选择的为《117-Pin TFBGA Package》,建议没有调试过以太网的不要选择BGA封装,最好选择PQFP封装,调试过硬件会懂得;2、硬件配置:通过芯片CONFIG[6:0]这7个引脚与外部信号相连接,得到不同的结果,例如传输速率、光线、以太网接口等,通过与外界不同管脚的连接也影响着寄存器,他们分别可以与VSS、LED_TX、LED_RX、LED_DUPLEX、LED_LINK1000、LED_LINK100、LED_LINK10、VDDO连接,依次代表3位从000到111的值;对于CONFIG[6:0]分别对应3位,每位都具有自己的含义,详见下datasheet P65;我选择的千兆以太网的配置为:CONFIG[0]--VSS,CONFIG[1]-- LED_RX,CONFIG[2]-- LED_LINK100,CONFIG[3]-- VSS,CONFIG[4]-- VDDO,CONFIG[5]-- VDDO,CONFIG[6]-- VSS,对照上面以PHY地址为例,有PHYADR为10000b,也可参照手册实例P64;3、MAC接口:通过上一步硬件配置知HWCFG_MODE[3:0]为1111,实际应该先确定传输速率、模式,再选择HWCFG_MODE[3:0]对应的值,参考手册P48,当选定此值时可知为GMII/MII to copper,接下来可以参照P48 GMII MAC接口图;在此不给我实际的原理图,真是有原因的,我原来做硬件时候就是参照别人的图纸做的,做回来的板子有部分好用,部分不好用,由于采用BGA封装,当时就以为是芯片没有焊接好(没用专用BGA焊接机),做了几种板子之后发现奇怪的现象,数据只能读,不能写,其他的一切都正常,猜想过板子使用发热、焊接内部助焊剂没有清洗干净等等,其实就是自己没有看手册,太相信别人的原理图,受先入为主的思想,认为只要好使过的板子原理就没有问题,如果以后遇到调试硬件问题,一定要回答datasheet中寻求答案,大神们早都知道的东西,可我在调试以太网给我上了深深一课,这也就是不给我画好板子原理图的原因,别给大家误导了!一切都得从根本出发!!!4、上拉电阻:一定要注意一些引脚需要上拉电阻,例如:MIC、MDIO、RESET 等引脚;5、电源地信号:88E1111有两种不同的电源2.5V、1.2V,对于2.5V需要区分不同的地方的供电,参照datasheet P73,我只把数字2.5V与模拟2.5V用磁珠分开,将地采用铺地的方式链接到一起;6、以太网网线接口:有的带有变压器,有的没有,这样就需要外加芯片转换,在两者直接转换时一定要对应好引脚,否则在做好硬件后,最起码的LINK都链接不上的。

EN1111使用规范

EN1111使用规范

EN1111:1998使用规范一,产品的适用条件该规范适用于公称压力为10bar的家用恒温龙头,具体的适用条件见下表:使用极限被推荐的使用条件动压最小0.05MPa(0.5bar)0.1MPa≤P≤0.5MPa 1bar≤P≤5bar静压最大1MPa(10bar)热水温度T≤90℃55℃≤T≤65℃冷水温度T≤25℃二,分类恒温龙头根据控制方式可以分为如下5种产品:1.单控恒温龙头:一个控制装置,同时控制温度和流量。

2.双控恒温龙头:两个独立的控制装置,分别控制流量和温度。

3.按照顺序单控恒温龙头:一个控制装置,装有预设顺序程序,带有切断(shut-off)装置。

4.无流量控制装置恒温龙头:不带流量控制装置。

5.特殊控制装置恒温龙头:使用特殊的控制装置。

6.三,设计构造和普通龙头一样,恒温龙头也是从名义尺寸、本体类型,出水口类型、用途、安装方式、流量等级、噪音等级来进行设计,定义其构造。

四,打标和标识符合该标准的恒温龙头应该永久并清晰的打上制造商的名字或标志,流量等级和噪音等级;带有温度控制的恒温龙头还得打上冷热标识,可以是红蓝标识,字母标识等等。

五,表面处理表面处理需满足EN248要求。

六,尺寸尺寸要求包括进水口尺寸要求,出水口尺寸要求,安装尺寸要求,具体见EN1111:1998第8章节。

七,密封特性密封性要求--阀及阀芯上游:出水口打开,阀芯关闭,施加1.6±0.5MPa的压力60±5s,本体及阀芯不能出现泄漏。

密封性要求--交叉水流:将龙头的一个进水口和测试设备连接,然后打开出水口,关闭阀芯,施加0.4±0.02MPa的水压60+5s,测试中,出水边和不连接的进水边都不能出现泄漏。

密封性要求--阀芯下游:出水口关闭,阀芯打开,施加0.4±0.02MPa的水压60+5s,不能出现泄漏;重复测试,施加0.02±0.005MPa的压力60+5s,密封性要求--手动分水器:1.将混合阀连接到测试线路上,并处于使用位置,将分水器放于浴盆位置上,浴盆出水口人为关闭,花洒出水口打开,施以静水压0.2±0.02MPa60±5s;检查花洒出水口的密封性;2.逐渐降低静压至0.02±0.005MPa持续60±5s,检查花洒出水口的密封性。

CS8900A中文数据手册 中文部分翻译

CS8900A中文数据手册 中文部分翻译

Байду номын сангаас 目录
4.10.11 I/O 模式下轮询 CS8900A....................................................................... 15 5.2 基本接收操作........................................................................................................ 17
5.2.1.1 数据包................................................................................................ 17 5.2.1.2 帧........................................................................................................ 17 5.2.1.3 传送.................................................................................................... 18 5.2.2 接收配置...................................................................................................... 18 5.2.2.1 配置物理接口.................................................................................... 19

CE88中文资料

CE88中文资料

Page 1 of 29X14 PECL J-LEAD CLOCK- PB FREE COMPLIANT (SEE PAGE TWO FOR PART NUMBERING SCHEME)" APPROVALSRALTRON CUSTOMER Eng. approval, date: RONEN 3/20/03 Name (please print):Sales approval, date: Title (please print):Created by, date: RONEN 3/20/03 Signature, date:Revision:" MECHANICAL SPECIFICATION" ELECTRICAL SPECIFICATIONPARAMETERSYMBOL CONDITIONS VALUE UNITFrequency, nom fo - 70.000~250.0 MHz Supply voltage, nom. Vcc Vcc±5%3.3VDC 5.0VDC VSupply current, max. (excluding load) Is Vcc=+3.3VDC/+5.0VDCTa=+25°C, 50Ω to Vcc-2.0VDC load100 mAPECL output level VOH / VOL Vcc=+3.3VDC/+5.0VDC load=50Ω to Vcc-2.0VDC 2.275 / 1.68 3.975/3.38 V Duty cycleDC load=50Ω to Vcc-2.0VDC / @50%Vcc, Ta=+25°C 40…60 OR 45…55 % Rise- / fall time, max. tr / tf 20%~80% Vout, 80%~20% Vout, max 0.100…1.0 (see note A) nsJitter, rms, max.J 1σ, Fj=12KHz…20MHz1.0 ps Overall freq. stability, max. ∆f/fcIncluding operating temperature, ±5% load & supply variations, calibration @+25°C, and 10 year agingSEE PART NUMBER GENERATION TABLE ppm Enable option En Pin 2=Low, Vcc-1.620 (max.) Enabled - Disable option DisPin 2=High, Vcc-1.025 (min.) Pin 4 will assume a fixed level of logic “0”, and pin 5 will assume a fixed level of logic“1”-Operating temperature range Ta -SEE PART NUMBER GENERATION TABLE °C Storage temperature range T(stg) --55…+90 °C Absolute voltage rangeVcc(abs)Non-destructive, DC-0.5…+7.0V3/20/03 marketing-rfq, clockNOTE A: RISE AND FALL TIME VALUES (tr/tf) ARE FREQUENCY DEPENDENT.Page 2 of 2PART NUMBER EXAMPLE:CE8950A-LZ-155.520-T-C-EL。

(完整版)88E111调试心得

(完整版)88E111调试心得

回想调试88E1111芯片时,遇到不少的心酸,花掉不少的money,从目前实现的UDP数据传输,ICMP ping包,ARP包,与大家一起分享一下,也许是受到调试时遇问题发帖求助,到热心网友的帮助的感慨吧;1、芯片Package:我选择的为《117-Pin TFBGA Package》,建议没有调试过以太网的不要选择BGA封装,最好选择PQFP封装,调试过硬件会懂得;2、硬件配置:通过芯片CONFIG[6:0]这7个引脚与外部信号相连接,得到不同的结果,例如传输速率、光线、以太网接口等,通过与外界不同管脚的连接也影响着寄存器,他们分别可以与VSS、LED_TX、LED_RX、LED_DUPLEX、LED_LINK1000、LED_LINK100、LED_LINK10、VDDO连接,依次代表3位从000到111的值;对于CONFIG[6:0]分别对应3位,每位都具有自己的含义,详见下datasheet P65;我选择的千兆以太网的配置为:CONFIG[0]--VSS,CONFIG[1]-- LED_RX,CONFIG[2]-- LED_LINK100,CONFIG[3]-- VSS,CONFIG[4]-- VDDO,CONFIG[5]-- VDDO,CONFIG[6]-- VSS,对照上面以PHY地址为例,有PHYADR为10000b,也可参照手册实例P64;3、MAC接口:通过上一步硬件配置知HWCFG_MODE[3:0]为1111,实际应该先确定传输速率、模式,再选择HWCFG_MODE[3:0]对应的值,参考手册P48,当选定此值时可知为GMII/MII to copper,接下来可以参照P48 GMII MAC接口图;在此不给我实际的原理图,真是有原因的,我原来做硬件时候就是参照别人的图纸做的,做回来的板子有部分好用,部分不好用,由于采用BGA封装,当时就以为是芯片没有焊接好(没用专用BGA焊接机),做了几种板子之后发现奇怪的现象,数据只能读,不能写,其他的一切都正常,猜想过板子使用发热、焊接内部助焊剂没有清洗干净等等,其实就是自己没有看手册,太相信别人的原理图,受先入为主的思想,认为只要好使过的板子原理就没有问题,如果以后遇到调试硬件问题,一定要回答datasheet中寻求答案,大神们早都知道的东西,可我在调试以太网给我上了深深一课,这也就是不给我画好板子原理图的原因,别给大家误导了!一切都得从根本出发!!!4、上拉电阻:一定要注意一些引脚需要上拉电阻,例如:MIC、MDIO、RESET 等引脚;5、电源地信号:88E1111有两种不同的电源2.5V、1.2V,对于2.5V需要区分不同的地方的供电,参照datasheet P73,我只把数字2.5V与模拟2.5V用磁珠分开,将地采用铺地的方式链接到一起;6、以太网网线接口:有的带有变压器,有的没有,这样就需要外加芯片转换,在两者直接转换时一定要对应好引脚,否则在做好硬件后,最起码的LINK都链接不上的。

基于FPGA与88E1111的千兆以太网设计

基于FPGA与88E1111的千兆以太网设计

基于FPGA与88E1111的千兆以太网设计转自XILINX电子创新网随着通信技术的发展,千兆以太网因在传输中具备高带宽和高速率的特点,成为高速传输设备的首选。

基于Xilinx FPGA的嵌入式系统设计整合了一系列的知识产权(IP)核使其功能强大,从而使得利用FPGA进行嵌入式串行千兆以太网开发成为可能。

本设计使用Xilinx公司65nm工艺级别的Virtex5FXT系列芯片,满足嵌入式系统设计所应具备的高性能、高密度、低功耗和低成本的要求。

V5Hard TEMAC模块提供了专用的以太网功能,并通过FPGA内部高速串行收发器GTX和Marvell公司的88E1111物理层接口芯片相连,完成串行千兆以太网的接口功能。

物理层接口芯片支持MII、GMII、RGMII 和SGMII四种以太网接口模式。

相对GMII接口而言,SGMII接口的I/O端口数目少,便于PCB布线,并且数据信号以差分对的形式出现,有利于保证信号完整性[1]。

本文将FPGA内嵌PowerPC硬核处理器、Xilinx精简嵌入式操作系统Xilkernel,以及相应的外设IP Core相结合,完成嵌入式串行千兆以太网的设计。

1总体设计系统硬件平台中选用Xilinx公司的Virtex5FX70t作为主控芯片,它集成了PowerPC440处理器模块和高速RocketIO GTX收发器。

外部存储器采用Micron公司的128M×16位DDR SDRAM芯片MT47H128M16HG 31T,为程序运行提供空间。

在网络芯片方面有两种方案可供选择,即单物理层芯片方案和物理层加MAC层集成于同一芯片方案[2]。

PHY加MAC于一体的方案易于编程,但不利于控制,基于这方面的考虑,采用Marvell公司的88E1111单物理层接口芯片作为解决方案,该芯片支持10BASET、100BASETX和1000BASET以太网协议。

本系统硬件由Virtex5FX70t芯片、88E1111PHY 芯片、DDRII芯片、8个拨码开关(8DIPS)、8个LED灯和RJ45接口构成,其连接框图如图1所示。

AX88180_M88E1111_RGMII_REFERENCE_SCHEMATIC_V142

AX88180_M88E1111_RGMII_REFERENCE_SCHEMATIC_V142

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
LD0 LD2 LD4 LD6 LD8 LD10 LD12 LD14 LD16 LD18 LD20 LD22 LD24 LD26 LD28 LD30
AX88180 GPIO1
Unmount R66: Little-endian Mount R66: Big-endian
R66 NC,4.7K
C
Optional
AX88180 Power Circuit and By-pass Capacitors *Note2-8
VCC 5H + C2 100u/16V C3 0.1u LT1084 3.3
CSN
GND
LCLK GND RESET GND O E_IN
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
WEN
GND LD1 LD3 LD5 LD7 LD9 LD11 LD13 LD15 LD17 LD19 LD21 LD23 LD25 LD27 LD29 LD31
*Note2-6 *Note2-7
R14 330 D1 LED R 1 2
93C56 EEPROM
*Note2-5
VCC33
5V ---> 3.3V
U3
Optional
U2
3
VIN
TAB/OUT VOUT ADJ/GND
4 2 1

PXIE-8881 用户手册说明书

PXIE-8881 用户手册说明书

SPECIFICA TIONSPXIe-8881Note Specifications are subject to change without notice.Caution Using the PXIe-8881 controller in a manner not described in this usermanual can impair the protection the controller provides.Note The PXIe-8881 requires a chassis with 82 W per slot cooling capacity.FeaturesFront Panel DimensionsThe following figure shows the front panel layout and dimensions of the PXIe-8881.Dimensions are in inches (millimeters).Figure 1. PXIe-8881 Front Panel Layout and Dimensions0.000 in. (0.00 mm)0.000 i n . (0.00 m m 0.480 in. (12.20 mm)2.573 in. (65.35 mm) 2.917 in. (74.10 mm)0.542 in. (13.76 mm)0.293 in. (7.44 mm)2.259 i n . (57.39 m m )1.815 i n . (46.10 m m )1.218 i n . (30.93 m m )0.531 i n . (13.49 m m )2.187 i n . (55.54 m m 2.160 i n . (54.87 m m 1.825 i n . (46.37 m m 1.641 i n . (41.69 m m 1.491 i n . (37.87 m m 1.307 i n . (33.19 m m 1.156 i n . (29.37 m m 0.534 i n . (13.57 m m 2 | | PXIe-8881 SpecificationsElectricalNote Does not include any attached devices.Note The PXIe-8881 requires a chassis with 82 W per slot cooling capacity.Note Power delivered to external loads through USB or Thunderbolt 3 ports shouldbe included in system power budgets that include this controller module andperipheral modules.PhysicalBoard dimensions Four-wide 3U PXI Express moduleSlot requirements One system slot plus three controller expansionslotsPXIe-8881 Specifications| © National Instruments Corporation| 3Compatibility Fully compatible with PXI ExpressSpecification 1.0Weight 1.6 kg (3.5 lb) typical EnvironmentalMaximum altitude2000 m (800 mbar) (at 25 °C ambient) withchassis fans on HighPollution Degree2Indoor use only.Operating EnvironmentCaution The operating temperature must not be exceeded, even when used in achassis with a higher temperature range.Ambient temperature range1, 20 °C to 55 °C (Tested in accordance withIEC-60068-2-1 and IEC-60068-2-2. MeetsMIL-PRF-28800F Class 3 low temperaturelimit and MIL-PRF-28800F Class 2 hightemperature limit.)Relative humidity range10% to 90%, noncondensing (Tested inaccordance with IEC-60068-2-78.) Storage EnvironmentAmbient temperature range-40 °C to 71 °C (Tested in accordance withIEC 60068-2-1 and IEC 60068-2-2. MeetsMIL-PRF-28800F Class 3 limits.)Relative humidity range5% to 95%, noncondensing (Tested inaccordance with IEC 60068-2-78.) 1The PXIe-8881 requires a chassis with 82 W per slot cooling capacity.2Processor may throttle if operating at maximum workloads at an ambient temperature above 40 °C. 4| | PXIe-8881 SpecificationsShock and VibrationOperating shock30 g peak, half-sine, 11 ms pulse (Tested inaccordance with IEC 60068-2-27. MeetsMIL-PRF-28800F Class 2 limits.)Random vibrationOperating 5 Hz to 500 Hz, 0.3 g rms (with solid-state harddrive)Nonoperating 5 Hz to 500 Hz, 2.4 g rms (Tested in accordancewith IEC 60068-2-64. Nonoperating testprofile exceeds the requirements ofMIL-PRF-28800F, Class 3.)SafetyThis product is designed to meet the requirements of the following standards of safety for information technology equipment:•IEC 61010-1, EN 61010-1•UL 61010-1, CSA C22.2 No. 61010-1Note For UL and other safety certifications, refer to the product label or theProduct Certifications and Declarations section. Electromagnetic CompatibilityThis product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:•EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity•EN 55011 (CISPR 11): Group 1, Class A emissions•EN 55022 (CISPR 22): Class A emissions•EN 55024 (CISPR 24): Immunity•AS/NZS CISPR 11: Group 1, Class A emissions•AS/NZS CISPR 22: Class A emissions•FCC 47 CFR Part 15B: Class A emissions•ICES-001: Class A emissionsNote In the United States (per FCC 47 CFR), Class A equipment is intended foruse in commercial, light-industrial, and heavy-industrial locations. In Europe,Canada, Australia and New Zealand (per CISPR 11) Class A equipment is intendedfor use only in heavy-industrial locations.PXIe-8881 Specifications| © National Instruments Corporation| 5Note Group 1 equipment (per CISPR 11) is any industrial, scientific, or medicalequipment that does not intentionally generate radio frequency energy for thetreatment of material or inspection/analysis purposes.Note For EMC declarations and certifications, and additional information, refer tothe Product Certifications and Declarations section.CE ComplianceThis product meets the essential requirements of applicable European Directives, as follows:•2014/35/EU; Low-V oltage Directive (safety)•2014/30/EU; Electromagnetic Compatibility Directive (EMC)•2011/65/EU; Restriction of Hazardous Substances (RoHS)•2014/53/EU; Radio Equipment Directive (RED)•2014/34/EU; Potentially Explosive Atmospheres (ATEX)Product Certifications and DeclarationsRefer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for NI products, visit / product-certifications, search by model number, and click the appropriate link. Environmental ManagementNI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.For additional environmental information, refer to the Commitment to the Environment web page at /environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.Waste Electrical and Electronic Equipment (WEEE)EU Customers At the end of the product life cycle, all NI products must bedisposed of according to local laws and regulations. For more information abouthow to recycle NI products in your region, visit /environment/weee. Battery Replacement and DisposalBattery Directive This product contains a long-life coin cell battery. If you needto replace it, use the Return Material Authorization (RMA) process or contact anauthorized NI service representative. For more information about compliance withthe EU Battery Directive 2006/66/EC about Batteries and Accumulators and WasteBatteries and Accumulators, visit /environment/batterydirective.6| | PXIe-8881 Specifications电子信息产品污染控制管理办法(中国RoHS)e NI符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。

88E1111-B2-BAB1C000_千兆网口

88E1111-B2-BAB1C000_千兆网口

Marvell.Moving Forward FasterDoc. No. MV-S105540-00, Rev. --March 4, 2009Document Classification: Proprietary Information88E1111 Product BriefIntegrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDocument ConventionsNote: Provides related information or information of special importance.Caution: Indicates potential damage to hardware or software, or loss of data.Warning: Indicates a risk of personal injury.Document StatusAdvance Information This document contains design specifications for initial product development. Specifications may change without notice. Contact Marvell Field Application Engineers for more information.Preliminary InformationThis document contains preliminary data, and a revision of this document will be published at a later date. Specifications may change without notice. Contact Marvell Field Application Engineers for more information.Final Information This document contains specifications on a product that is in final release. Specifications may change without notice. Contact Marvell Field Application Engineers for more information.Doc Status: AdvanceTechnical Publications: 1.00For more information, visit our website at: DisclaimerNo part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications.With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2;2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and,3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML").At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information.Copyright © 2009. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners.88E1111 Product BriefIntegrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDoc. No. MV-S105540-00 Rev. -- Copyright © 2009 Marvell Page 2Document Classification: Proprietary InformationMarch 4, 2009, Advance88E1111 Product BriefIntegrated 10/100/1000 Ultra Gigabit Ethernet TransceiverCopyright © 2009 MarvellDoc. No. MV-S105540-00, Rev. --March 4, 2009, AdvanceDocument Classification: Proprietary InformationPage 3O VERVIEWThe Alaska ® Ultra 88E1111 Gigabit Ethernet Trans-ceiver is a physical layer device for Ethernet1000BASE-T, 100BASE-TX, and 10BASE-T applica-tions. It is manufactured using standard digital CMOS process and contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT 5 unshielded twisted pair.The 88E1111 device incorporates the Marvell Virtual Cable Tester ® (VCT™) feature, which uses TimeDomain Reflectometry (TDR) technology for the remote identification of potential cable malfunctions, thus reducing equipment returns and service calls. Using VCT, the Alaska 88E1111 device detects and reports potential cabling issues such as pair swaps, pair polar-ity and excessive pair skew. The device will also detect cable opens, shorts or any impedance mismatch in the cable and report accurately within one meter the dis-tance to the fault.The 88E1111 device supports the Gigabit Media Inde-pendent Interface (GMII), Reduced GMII (RGMII), Serial Gigabit Media Independent Interface (SGMII), the Ten-Bit Interface (TBI), and Reduced TBI (RTBI) for direct connection to a MAC/Switch port.The 88E1111 device incorporates an optional 1.25 GHz SERDES (Serializer/Deserializer). The serial interface may be connected directly to a fiber-optic transceiver for 1000BASE-T/1000BASE-X media conversion appli-cations. Additionally, the 88E1111 device may be used to implement 1000BASE-T Gigabit Interface Converter (GBIC) or Small Form Factor Pluggable (SFP) modules.The 88E1111 device uses advanced mixed-signal pro-cessing to perform equalization, echo and crosstalk cancellation, data recovery, and error correction at a gigabit per second data rate. The device achievesrobust performance in noisy environments with very low power dissipation.The 88E1111 device is offered in three different pack-age options including a 117-Pin TFBGA, a 96-pin BCC featuring a body size of only 9 x 9 mm, and a 128 PQFP package.F EATURES•10/100/1000BASE-T IEEE 802.3 compliant •Supports GMII, TBI, reduced pin count GMII(RGMII), reduced pin count TBI (RTBI), and serial GMII (SGMII) interfaces•Integrated 1.25 GHz SERDES for 1000BASE-X fiber applications •Four RGMII timing modes•Energy Detect and Energy Detect+ low power modes•Three loopback modes for diagnostics•“Downshift” mode for two-pair cable installations •Fully integrated digital adaptive equalizers, echo cancellers, and crosstalk cancellers •Advanced digital baseline wander correction •Automatic MDI/MDIX crossover at all speeds of operation•Automatic polarity correction•IEEE 802.3u compliant Auto-Negotiation•Software programmable LED modes including LED testing•Automatic detection of fiber or copper operation •Supports IEEE 1149.1 JTAG•Two-Wire Serial Interface (TWSI) and MDC/MDIO •CRC checker, packet counter •Packet generation •Virtual Cable Tester (VCT)•Auto-Calibration for MAC Interface outputs •Requires only two supplies: 2.5V and 1.0V (with 1.2V option for the 1.0V supply)•I/Os are 3.3V tolerant•Low power dissipation Pave = 0.75W •117-Pin TFBGA, 96-Pin BCC, and 128 PQFP package options•117-Pin TFBGA and 96-Pin BCC packages avail-able in Commercial or Industrial grade •RoHS 6/6 compliant packages available88E1111 Product BriefIntegrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDoc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell Page 4Document Classification: Proprietary InformationMarch 4, 2009, Advance88E1111 Device used in Copper Application88E1111 Device used in Fiber Application88E1111 RGMII/GMII MAC to SGMII MAC ConversionTable of Contents1.1117-Pin TFBGA Package (6)1.2 96-Pin BCC Package (7)1.3128-Pin PQFP Package (8)1.4Pin Description (9)1.4.1Pin Type Definitions (9)1.5I/O State at Various Test or Reset Modes (33)1.6117-Pin TFBGA Pin Assignment List - Alphabetical by Signal Name (34)1.796-Pin BCC Pin Assignment List - Alphabetical by Signal Name (36)1.8128-Pin PQFP Pin Assignment List - Alphabetical by Signal Name (38)2.1117-pin TFBGA Package (40)2.296-pin BCC Package - Top View (42)2.396-Pin BCC Package - Bottom View (43)2.4128-Pin PQFP Package (44)3.1Ordering Part Numbers and Package Markings (45)3.1.1RoHS 5/6 Compliant Marking Examples (46)3.1.2RoHS 6/6 Compliant Marking Examples (49)Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --March 4, 2009, Advance Document Classification: Proprietary Information Page 588E1111 Product BriefIntegrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDoc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell Page 6Document Classification: Proprietary InformationMarch 4, 2009, AdvanceSection 1. Signal DescriptionThe 88E1111 device is a 10/100/1000BASE-T/1000BASE-X Gigabit Ethernet transceiver.1.1117-Pin TFBGA PackageFigure 1:88E1111 Device 117-Pin TFBGA Package (Top View)Figure 2:Pin A1 Location123456789A RXD5RXD6S_IN+S_IN-S_CLK+S_CLK-S_OUT+S_OUT-LED_LINK1000AB RX_DV RXD0RXD3VDDO CRS COL AVDD LED_LINK100VDDOHBC RX_CLK VDDO RXD2RXD4RXD7DVDD DVDD LED_LINK10LED_RX CD TX_CLK RX_ER RXD1VSS VSS VSS DVDD CONFIG[0]LED_TX DE TX_EN GTX_CLK DVDD VSS VSS VSS DVDD LED_DUPLEX CONFIG[1]EF TXD0TX_ER DVDD VSS VSS VSS VDDOH CONFIG[2]CONFIG[4]FG NC TXD1TXD2VSS VSS VSS CONFIG[3]CONFIG[6]CONFIG[5]GH TXD4TXD3TXD5VSS VSS VSS VSSC SEL_FREQ XTAL1HJ TXD6TXD7DVDD VSS VSS VSS DVDD VDDOHXTAL2JK VDDO 125CLK RESETn VSS VSS VSS NC TDO VDDOX KL INTn VDDOX MDC COMA VSS VSS TDI TMS TCK LM MDIO RSET AVDD AVDD HSDAC+HSDAC-AVDD AVDD TRSTn MN MDI[0]+MDI[0]-MDI[1]+MDI[1]-AVDD MDI[2]+MDI[2]-MDI[3]+MDI[3]-N12345678988E1111-BABSignal Description96-Pin BCC Package1.2 96-Pin BCC PackageFigure 3:88E1111 Device 96-Pin BCC Package (Top View)88E1111 - CAACopyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --March 4, 2009, Advance Document Classification: Proprietary Information Page 788E1111 Product BriefIntegrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDoc. No. MV-S105540-00, Rev. --Copyright © 2009 Marvell Page 8Document Classification: Proprietary InformationMarch 4, 2009, Advance1.3128-Pin PQFP PackageFigure 4:88E1111 Device 128-Pin PQFP Package (Top View)78910111213141516171819202122232425262728293031323388E1111 - RCJTop ViewR X _C L K R X _E R V S S T X _C L K V D D O D V D D T X _E R G T X _C L K V S S T X _E N D V D D T X D 0T X D 1T X D 2V S S V S S D V D D T X D 3T X D 4T X D 5D V D D T X D 6T X D 7V D D O 125C L K I N T n M D I OSignal DescriptionPin Description1.4Pin Description1.4.1Pin Type DefinitionsPin Type DefinitionH Input with hysteresisI/O Input and outputI Input onlyO Output onlyPU Internal pull upPD Internal pull downD Open drain outputZ Tri-state outputmA DC sink capabilityCopyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --March 4, 2009, Advance Document Classification: Proprietary Information Page 988E1111 Product BriefIntegrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDoc. No. MV-S105540-00, Rev. --Copyright © 2009 Marvell Page 10Document Classification: Proprietary InformationMarch 4, 2009, AdvanceTable 1:Media Dependent Interface117-TFBGA Pin #96-BCC Pin #128-PQFP Pin #Pin Name Pin TypeDescriptionN1N229314142MDI[0]+MDI[0]-I/O, DMedia Dependent Interface[0].In 1000BASE-T mode in MDI configuration, MDI[0]± correspond to BI_DA±.In MDIX configuration, MDI[0]± correspond to BI_DB±.In 100BASE-TX and 10BASE-T modes in MDI configuration, MDI[0]± are used for the transmit pair. In MDIX configuration, MDI[0]± are used for the receive pair. MDI[0]± should be tied to ground if not used.N3N433344647MDI[1]+MDI[1]-I/O, D Media Dependent Interface[1].In 1000BASE-T mode in MDI configuration, MDI[1]± correspond to BI_DB±.In MDIX configuration, MDI[1]± correspond to BI_DA±.In 100BASE-TX and 10BASE-T modes in MDI configuration, MDI[1]± are used for the receive pair. In MDIX configuration, MDI[1]± are used for the transmit pair.MDI[1]± should be tied to ground if not used.N6 N739415657MDI[2]+MDI[2]-I/O, D Media Dependent Interface[2].In 1000BASE-T mode in MDI configuration,MDI[2]±correspond to BI_DC±.In MDIX configuration, MDI[2]± correspondsto BI_DD±.In 100BASE-TX and 10BASE-T modes,MDI[2]±are not used.MDI[2]± should be tied to ground if not used.N8 N942436162MDI[3]+MDI[3]-I/O, D Media Dependent Interface[3].In 1000BASE-T mode in MDI configuration,MDI[3]± correspond to BI_DD±.In MDIX configuration, MDI[3]± correspondto BI_DC±.In 100BASE-TX and 10BASE-T modes,MDI[3]± are not used.MDI[3]± should be tied to ground if not used.Table 1:Media Dependent Interface (Continued)117-TFBGA Pin #96-BCCPin #128-PQFPPin #Pin Name PinTypeDescriptionCopyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --Integrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDoc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell The GMII interface supports both 1000BASE-T and 1000BASE-X modes of operation. The GMII interface pins are also used for the TBI interface. See Table 3 for TBI pin definitions. The MAC interface pins are 3.3V tolerant. Table 2:GMII/MII Interfaces117-TFBGA Pin #96-BCC Pin #128-PQFP Pin #Pin Name PinTypeDescriptionE2814GTX_CLKIGMII Transmit Clock. GTX_CLK provides a 125 MHz clock reference for TX_EN, TX_ER, and TXD[7:0]. This clock can be stopped when the device is in 10/100BASE-T modes, and also during Auto-Negotiation.D1410TX_CLK O, ZMII Transmit Clock. TX_CLK provides a 25 MHz clock reference for TX_EN, TX_ER, and TXD[3:0] in 100BASE-TX mode, and a 2.5 MHz clock reference in 10BASE-T mode.TX_CLK provides a 25 MHz, 2.5 MHz, or 0 MHz clock during 1000 Mbps Good Link, Auto-Negotiation, and Link Lost statesdepending on the setting of register 20.6:4.The 2.5 MHz clock is the default rate, which may be programmed to another frequency by writing to register 20.6:4.E1916TX_EN IGMII and MII Transmit Enable. In GMII/MII mode when TX_EN is asserted, data on TXD[7:0] along with TX_ER is encoded and transmitted onto the cable.TX_EN is synchronous to GTX_CLK, and synchronous to TX_CLK in 100BASE-TX and 10BASE-T modes.F2713TX_ER IGMII and MII Transmit Error. In GMII/MII mode when TX_ER and TX_EN are both asserted, the transmit error symbol is trans-mitted onto the cable. When TX_ER is asserted with TX_EN de-asserted, carrier extension symbol is transmitted onto the cable.TX_ER is synchronous to GTX_CLK, and synchronous to TX_CLK in 100BASE-TX and 10BASE-T modes.Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --J2J1H3H1H2G3G2F120191817161412112928262524201918TXD[7]TXD[6]TXD[5]TXD[4]TXD[3]/TXD[3]TXD[2]/TXD[2]TXD[1]/TXD[1]TXD[0]/TXD[0]IGMII and MII Transmit Data. In GMII mode, TXD[7:0] present the data byte to be trans-mitted onto the cable in 1000BASE-T mode. In MII mode, TXD[3:0] present the data nib-ble to be transmitted onto the cable in 100BASE-TX and 10BASE-T modes. TXD[7:4] are ignored in these modes, but should be driven either high or low. These pins must not float.TXD[7:0] are synchronous to GTX_CLK, and synchronous to TX_CLK in 100BASE-TX and 10BASE-T modes.Inputs TXD[7:4] should be tied low if not used (e.g., RGMII mode).C127RX_CLK O, ZGMII and MII Receive Clock. RX_CLK pro-vides a 125 MHz clock reference for RX_DV, RX_ER, and RXD[7:0] in 1000BASE-T mode, a 25 MHz clock reference in100BASE-TX mode, and a 2.5 MHz clock reference in 10BASE-T mode.TX_TCLK comes from the RX_CLK pins used in jitter testing. Refer to Register 9 for jitter test modes.B1944RX_DV O, ZGMII and MII Receive Data Valid. When RX_DV is asserted, data received on the cable is decoded and presented on RXD[7:0] and RX_ER.RX_DV is synchronous to RX_CLK.D238RX_ER O, ZGMII and MII Receive Error. When RX_ER and RX_DV are both asserted, the signals indicate an error symbol is detected on the cable.When RX_ER is asserted with RX_DV de-asserted, a false carrier or carrier extension symbol is detected on the cable. RX_ER is synchronous to RX_CLK.Table 2:GMII/MII Interfaces (Continued)117-TFBGA Pin #96-BCC Pin #128-PQFP Pin #Pin Name Pin TypeDescriptionIntegrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDoc. No. MV-S105540-00, Rev. --Copyright © 2009 Marvell C5A2A1C4B3C3D3B286878990919392951201211231241251261283RXD[7]RXD[6]RXD[5]RXD[4]RXD[3]/RXD[3]RXD[2]/RXD[2]RXD[1]/RXD[1]RXD[0]/RXD[0]O, ZGMII and MII Receive Data. Symbolsreceived on the cable are decoded and pre-sented on RXD[7:0] in 1000BASE-T mode. In MII mode, RXD[3:0] are used in100BASE-TX and 10BASE-T modes. In MII mode, RXD[7:4] are driven low. RXD[7:0] is synchronous to RX_CLK.B584115CRSO, ZGMII and MII Carrier Sense. CRS asserts when the receive medium is non-idle. In half-duplex mode, CRS is also asserted during transmission. CRS assertion during half-duplex transmit can be disabled by program-ming register 16.11 to 0.CRS is asynchronous to RX_CLK, GTX_CLK, and TX_CLK.B683114COL O, ZGMII and MII Collision. In 10/100/1000BASE-T full-duplex modes, COL is always low. In 10/100/1000BASE-T half-duplex modes, COL asserts only when both the transmit and receive media are non-idle. In 10BASE-T half-duplex mode, COL is asserted to indicate signal quality error(SQE). SQE can be disabled by clearing reg-ister 16.2 to zero.COL is asynchronous to RX_CLK, GTX_CLK, and TX_CLK.Table 2:GMII/MII Interfaces (Continued)117-TFBGA Pin #96-BCC Pin #128-PQFP Pin #Pin Name Pin TypeDescriptionThe TBI interface supports 1000BASE-T mode of operation. The TBI interface uses the same pins as the GMII interface. The MAC interface pins are 3.3V tolerant.Table 3:TBI Interface117-TFBGA Pin #96-BCCPin #128-PQFPPin #Pin Name PinTypeDescriptionE2814GTX_CLK/TBI_TXCLK I TBI Transmit Clock. In TBI mode, GTX_CLKis used as TBI_TXCLK. TBI_TXCLK is a 125MHz transmit clock.TBI_TXCLK provides a 125 MHz clock refer-ence for TX_EN, TX_ER, and TXD[7:0].D1410TX_CLK/RCLK1O, Z TBI 62.5 MHz Receive Clock- even codegroup. In TBI mode, TX_CLK is used asRCLK1.J2 J1 H3 H1 H2 G3 G2 F120191817161412112928262524201918TXD[7]TXD[6]TXD[5]TXD[4]TXD[3]TXD[2]TXD[1]TXD[0]I TBI Transmit Data. TXD[7:0] presents thedata byte to be transmitted onto the cable.TXD[9:0] are synchronous to GTX_CLK.Inputs TXD[7:4] should be tied low if notused (e.g., RTBI mode).E1916TX_EN/TXD8I TBI Transmit Data. In TBI mode, TX_EN isused as TXD8.TXD[9:0] are synchronous to GTX_CLK.F2713TX_ER/TXD9I TBI Transmit Data. In TBI mode, TX_ER isused as TXD9.TXD[9:0] are synchronous to GTX_CLK.TX_ER should be tied low if not used (e.g.,RTBI mode).C127RX_CLK/RCLK0O, Z TBI 62.5 MHz Receive Clock- odd code group. In the TBI mode, RX_CLK is usedas RCLK0.C5 A2 A1 C4 B3 C3 D3 B286878990919392951201211231241251261283RXD[7]RXD[6]RXD[5]RXD[4]RXD[3]RXD[2]RXD[1]RXD[0]O, Z TBI Receive Data code group [7:0]. In theTBI mode, RXD[7:0] present the data byte tobe transmitted to the MAC. Symbolsreceived on the cable are decoded and pre-sented on RXD[7:0].RXD[7:0] are synchronous to RCLK0 andRCLK1.B1944RX_DV/RXD8O, Z TBI Receive Data code group bit 8. In the TBI mode, RX_DV is used as RXD8.RXD[9:0] are synchronous to RCLK0 andRCLK1.Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --Integrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDoc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell D238RX_ER/RXD9O, ZTBI Receive Data code group bit 9. In the TBI mode, RX_ER is used as RXD9. RXD[9:0] are synchronous to RCLK0 and RCLK1.B584115CRS/COMMA O, Z TBI Valid Comma Detect. In the TBI mode, CRS is used as COMMA.B683114COL/LPBKITBI Mode Loopback. In the TBI mode, COL is used to indicate loopback on the TBI. When a “0 - 1" transition is sampled on this pin, bit 0.14 is set to 1.When a “1 - 0" is sampled on this pin, bit 0.14 is reset to 0.If this feature is not used, the COL pinshould be driven low on the board. This pin should not be left floating in TBI mode.Table 3:TBI Interface (Continued)117-TFBGA Pin #96-BCC Pin #128-PQFP Pin #Pin Name PinTypeDescriptionThe RGMII interface supports 10/100/1000BASE-T and 1000BASE-X modes of operation.The RGMII interface pins are also used for the RTBI interface. See Table5 for RTBI pin definitions. The MAC interface pins are 3.3V tolerant.Table 4:RGMII Interface117-TFBGA Pin #96-BCCPin #128-PQFPPin #Pin Name PinTypeDescriptionE2814GTX_CLK/TXC I RGMII Transmit Clock provides a 125 MHz,25 MHz, or 2.5 MHz reference clock with ±50 ppm tolerance depending on speed. InRGMII mode, GTX_CLK is used as TXC.H2 G3 G2 F11614121124201918TXD[3]/TD[3]TXD[2]/TD[2]TXD[1]/TD[1]TXD[0]/TD[0]I RGMII Transmit Data. In RGMII mode,TXD[3:0] are used as TD[3:0].In RGMII mode, TXD[3:0] run at double datarate with bits [3:0] presented on the risingedge of GTX_CLK, and bits [7:4] presentedon the falling edge of GTX_CLK. In thismode, TXD[7:4] are ignored.In RGMII 10/100BASE-T modes, the trans-mit data nibble is presented on TXD[3:0] onthe rising edge of GTX_CLK.E1916TX_EN/TX_CTL I RGMII Transmit Control. In RGMII mode,TX_EN is used as TX_CTL. TX_EN is pre-sented on the rising edge of GTX_CLK.A logical derivative of TX_EN and TX_ER ispresented on the falling edge of GTX_CLK.C127RX_CLK/RXC O, Z RGMII Receive Clock provides a 125 MHz,25 MHz, or 2.5 MHz reference clock with ±50 ppm tolerance derived from the receiveddata stream depending on speed. In RGMIImode, RX_CLK is used as RXC.B1944RX_DV/RX_CTL O, Z RGMII Receive Control. In RGMII mode,RX_DV is used as RX_CTL. RX_DV is pre-sented on the rising edge of RX_CLK.A logical derivative of RX_DV and RX_ER ispresented on the falling edge of RX_CLK.B3 C3 D3 B2919392951251261283RXD[3]/RD[3]RXD[2]/RD[2]RXD[1]/RD[1]RXD[0]/RD[0]O, Z RGMII Receive Data. In RGMII mode,RXD[3:0] are used as RD[3:0]. In RGMIImode, RXD[3:0] run at double data rate withbits [3:0] presented on the rising edge ofRX_CLK, and bits [7:4] presented on the fall-ing edge of RX_CLK. In this mode, RXD[7:4]are ignored.In RGMII 10/100BASE-T modes, the receivedata nibble is presented on RXD[3:0] on therising edge of RX_CLK.RXD[3:0] are synchronous to RX_CLK.Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --Integrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDoc. No. MV-S105540-00, Rev. -- Copyright © 2009 Marvell The RTBI interface supports 1000BASE-T mode of operation. The RTBI interface uses the same pins as the RGMII interface. The MAC interface pins are 3.3V tolerant. Table 5:RTBI Interface117-TFBGA Pin #96-BCC Pin #128-PQFP Pin #Pin Name PinTypeDescriptionE2814GTX _CLK/TXC IRGMII Transmit Clock provides a 125 MHz reference clock with ± 50 ppm tolerance. In RTBI mode, GTX_CLK is used as TXC. H2G3G2F11614121124201918TXD[3]/TD[3]TXD[2]/TD[2]TXD[1]/TD[1]TXD[0]/TD[0]IRTBI Transmit Data.In RTBI mode, TXD[3:0] are used asTD[3:0]. TD[3:0] run at double data rate with bits [3:0] presented on the rising edge of GTX_CLK, and bits [8:5] presented on the falling edge of GTX_CLK. In this mode, TXD[7:4] are ignored.E1916TX_EN/TD4_TD9IRTBI Transmit Data.In RTBI mode, TX_EN is used as TD4_TD9. TD4_TD9 runs at a double data rate with bit 4 presented on the rising edge of GTX_CLK, and bit 9 presented on the falling edge of GTX_CLK.C127RX_CLK/RXCO, ZRTBI Receive Clock provides a 125 MHz ref-erence clock with ± 50 ppm tolerance derived from the received data stream. In RTBI mode, RX_CLK is used as RXC.B3C3D3B2919392951251261283RXD[3]/RD[3]RXD[2]/RD[2]RXD[1]/RD[1]RXD[0]/RD[0]O, ZRTBI Receive Data.In RTBI mode, RXD[3:0] are used as RD[3:0]. RD[3:0] runs at double data rate with bits [3:0] presented on the rising edge of RX_CLK, and bits [8:5] presented on the fall-ing edge of RX_CLK. In this mode, RXD[7:4] are ignored.B1944RX_DV/RD4_RD9O, ZRTBI Receive Data.In RTBI mode, RX_DV is used asRD4_RD9. RD4_RD9 runs at a double data rate with bit 4 presented on the rising edge of RX_CLK, and bit 9 presented on the fall-ing edge of RX_CLK.Table 6:SGMII Interface117-TFBGA Pin #96-BCCPin #128-PQFPPin #Pin Name PinTypeDescriptionA3 A48281113112S_IN+S_IN-I SGMII Transmit Data. 1.25 GBaud input -Positive and Negative.Input impedance on the S_IN± pins may beprogrammed for 50 ohm or 75 ohm imped-ance by setting register 26.6. The inputimpedance default setting is determined bythe 75/50 OHM configuration pin.A5 A67980110109S_CLK+S_CLK-I/O SGMII 625 MHz Receive Clock.For Serial Interface modes(HWCFG_MODE[3:0] = 1x00) the S_CLK±pins become Signal Detect± (SD±) inputs.A7 A87775107105S_OUT+S_OUT-O, Z SGMII Receive Data. 1.25 GBaud output -Positive and Negative.Output impedance on the S_OUT± pins maybe programmed for 50 ohm or 75 ohmimpedance by setting register 26.5. Outputamplitude can be adjusted via register26.2:0. The output impedance default settingis determined by the 75/50 OHM configura-tion pin.Copyright © 2009 Marvell Doc. No. MV-S105540-00, Rev. --Integrated 10/100/1000 Ultra Gigabit Ethernet TransceiverDoc. No. MV-S105540-00, Rev. --Copyright © 2009 Marvell Table 7: 1.25 GHz Serial High Speed Interface117-TFBGA Pin #96-BCC Pin #128-PQFP Pin #Pin Name Pin TypeDescriptionA3A48281113112S_IN+S_IN-I1.25 GHz input - Positive and Negative. When this interface is used as a MAC inter-face, the MAC transmitter’s positive output connects to the S_IN+. The MAC transmit-ter’s negative output connects to the S_IN-. When this interface is used as a fiber inter-face, the fiber-optic transceiver’s positive output connects to the S_IN+. The fiber-optic transceiver’s negative output connects to the S_IN-.Input impedance on the S_IN± pins may be programmed for 50 ohm or 75 ohm imped-ance by setting register 26.6. The input impedance default setting is determined by the 75/50 OHM configuration pin.A5A67980110109S_CLK+/SD+S_CLK-/SD-I Signal Detect input.For Serial Interface modes the S_CLK± pins become Signal Detect± (SD±) inputs.A7A87775107105S_OUT+S_OUT-O, Z1.25 GHz output − Positive and Negative. When this interface is used as a MAC inter-face, S_OUT+ connects to the MACreceiver’s positive input. S_OUT- connects to the MAC receiver’s negative input. When this interface is used as a fiber inter-face, S_OUT+ connects to the fiber-optic transceiver’s positive input. S_OUT- con-nects to the fiber-optic transceiver’s negative input.Output impedance on the S_OUT± pins may be programmed for 50 ohm or 75 ohm impedance by setting register 26.5. Output amplitude can be adjusted via register26.2:0. The output impedance default setting is determined by the 75/50 OHM configura-tion pin.B391125RXD[3]O, ZSerial MAC interface Copper Link Status[1] connection.1 = Copper link up 0 = Copper link down。

EC11 资料

EC11 资料

Chattiring t1,t3≤5mS.Bounce t2≤3mS.Detent feeling has to remains Contact resistance 200ΩMax all items is shall be for 1.5H,After which measurements shall be made.all items is shall be all items is shall be Application time of soldering iron:within 3S solder shall cover75% minimum of the surface being immersed.所有项应满足初期规格。

be subjected to standard atmospheric conditions Specifications in clause 所有项应满足初期规格温度40±2℃,湿度90~95%的恒温恒湿槽中放置96±4atmospheric conditions for 1.5H,After which 温度-40±3℃的恒温箱中放置96±4小时,then the encoder.shall be subjected to standard satisfied.mechanical abnormality.不得有绝缘体的破损、变形、Electrical characteristics 常温、常湿放置1.5小时后测试.The encoder shall be stored at a temperature of -40±3℃for 96±4H in a thermostatic chamber.And 所有项应满足初期规格。

Specifications in clause 小时后,在常温、常湿中放置1.5小时后测试. The 温度85±3℃的恒温箱中放置96±4小时,satisfied.in a thermostatic chamber.And the encoder shall with relative humidity of 90% to95% for96±4H encoder shall be stored at temperature of40 ±2℃ Specifications in clause 85±3℃for 96±4H in a thermostatic chamber.And The encoder shall be stored at a temperature of satisfied.then the encoder.shall be subjected to standard 常温、常湿放置1.5小时后测试.atmospheric conditions for 1.5H,After which 温度300℃以下,时间3秒以内.端子在260℃±5℃温度的焊锡槽内浸锡3秒±0.5秒.measurements shall be made. 预热:基板表面温度100℃以下,时间1分钟以内.Printed wiring board:single-sided copper clad 焊接:温度260±5℃或以下,时间3秒以内.Preheating:1.Surface temperature of board:100℃. heator less 2.Preheating time:within 1 minute.shall be satisfied No 接触无异常.Soldering:Solder temperature:260±5℃ or less Bit temperature of soldering iron:300℃less than Immersion time:within 3S 手焊 Manual soldering. 7-6.焊锡性浸渍面须有75%以上焊锡附着at 260℃for 3S±0.5S.Solderability The terminals shall be immersed into solder bath A new uniform coating of EC11 REVERSE DIRECTION SERIES SPECIFICATION600~1000cycles/H without electrical load,after with 在无负荷条件下轴以600~1000周/小时速度回转,端子间接触阻抗200Ω以下■在力矩≤100gf.cm时30,000±200周 7-3.耐热性 7-2.耐湿性 Damp heatmeasurements shall be made.Resistance Cold7-4.低温特性一日连续5000~8000次.laminate board with thickness of 1.6mm.使用基板:t=1.6mm的单面覆铜板.槽焊 Dip soldering.7-5.焊锡耐热性 to Soldering Dry heat7 耐久性能 Endurance CharacteristicsRotationallifeCONDITIONSITEM条件(5000 to 8000 continuous cycles for 24 hours.)7-1.回转寿命项目振荡 t1,t3≤5mS.突跳 t2≤3mS.SPECIFICATIONS15,000±200cycles per above 100gf.cm.规格The shaft of encoder shall be rotated at a speed of measurements shall be made.尚余有轻微定位感.30,000±200cycles per below 100gf.cm.□在力矩>100gf.cm时15,000±200周.≤100mΩ100mΩor lessPush 1Kgf to the shaft of encoder in the axial4-1.按压寿命 Push-life修订 Revision日期 Date 经 办 Designed审 核 Check批 准 Approved初始发行2011-1-4版本 VERSION:A0≤10mS10mS or less 在端子和安装板间施加AC300V电压1分钟A voltage of300V AC shall be applied for 1 minute 用DC 5V 1mA 电压测定.which a voltage of 250V DC is applied between Rated voltage:DC 5VNote:The following specification is only suitable for the one type with switch construction of RE11 encoder series.1.额定值 Rating2-1.接触电阻 2.电气性能 Electrical Characteristics条件规格1-2.最大额定电流 (阻抗负载)Measurement shall be made under the condition 在端子和安装板间施加电压 250V DC.100MΩ 以上100MΩ Min SPECIFICATIONSMaximum operating current (resistive load):10mA MaxITEMCONDITIONS1-1.额定电压推动开关部分Push Switch Portion备注:以下规格适用于RE11编码器带开关系列.项目不得有绝缘破坏Without arcing or breakdown.3 机械性能 M echanical Characteristicsbetween individual terminals and bushing and plank.EC11 REVERSE DIRECTION SERIES SPECIFICATION4 耐久性能 Endurance Characteristicsfore of switch Single pole and single throw (push ON)单极单投(按压ON)接点数Switch circuit and ■0.5±0.3 mm □1.5±0.5 mm3-2.开关动作力 Operation 500±200gf Push static load to the shaft in the axial directionTravel of switchVoltage test at DC 5V 1mA.2-2.绝缘阻抗 Insulation number of pulse individual terminals and bushing and plank.以1秒钟1往返(OFF-ON-OFF)按压动作.Shaft shall be push at 1 cycles/s(OFF-ON-OFF) resistance Contact 2-3.振荡 Bouncing resistance 3-1.开关电路 2-4.耐电压 Dielectric strength 在轴端,沿轴向施加的按压力.3-3.开关移动量的速度按压。

LINEAR AN88-1 数据手册

LINEAR AN88-1 数据手册

AN88-1AN88-2on a number of factors but the main requirement is that it must handle the input ripple current produced by the DC/DC converter. The input ripple current is usually in the range of 1A to 2A. Therefore, the required capacitors would be either one 10µF to 22µF ceramic capacitor, two to three 22µF tantalum capacitors or one to two 22µF OS-CON capacitors.Turning On the SwitchWhen switch SW1 in Figure 1 is turned on, the mayhem starts. Since the wall adapter is already plugged in, there is 24V across its low impedance output capacitor. On the other hand, the input capacitor C IN is at 0V potential. What happens from t = 0s is pretty basic. The applied input voltage will cause current to flow through L OUT . C IN will begin charging and the voltage across C IN will ramp up toward the 24V input voltage. Once the voltage across C IN has reached the output voltage of the wall adapter, the energy stored in L OUT will raise the voltage across C IN further above 24V. The voltage across C IN will eventually reach its peak and will then fall back to 24V. The voltage across C IN may ring for some time around the 24V value.The actual waveform will depend on the circuit elements.If you intend to run this circuit simulation, keep in mind that the real-life circuit elements are very seldom linear under transient conditions. For example, the capacitors may undergo a change of capacitance (Y5V ceramic capacitors will loose 80% of the initial capacitance under rated input voltage). Also, the ESR of input capacitors will depend on the rise time of the waveform. The inductance of EMI-suppressing inductors may also drop during tran-sients due to the saturation of the magnetic material.Testing a Portable ApplicationInput voltage transients with typical values of C IN and L OUT used in notebook computer applications are shown in Fig-ure 2. Figure 2 shows input voltage transients for C IN val-ues of 10µF and 22µF with L OUT values of 1µH and 10µH.The top waveform shows the worst-case transient, with a 10µF capacitor and 1µH inductor. The voltage across C IN peaks at 57.2V with a 24V DC input. The DC/DC converter may not survive repeated exposure to 57.2V.The waveform with 10µF and 10µH (trace R2) looks a bit better. The peak is still around 50V. The flat part of the waveform R2 following the peak indicates that the synchronous MOSFET M1, inside of the DC/DC converter in Figure 1, is avalanching and taking the energy hit. Traces R3 and R4 peak at around 41V and are for a 22µF capacitor with 1µH and 10µH inductors, respectively.Figure 2. Input Voltage Transients Across Ceramic CapacitorsTable 1. Peak Voltages of Waveforms In Figure 2TRACE L IN (µH)C IN (µF)V IN PEAK (V)CH111057.2R2101050R312241R4102241Input Voltage Transients with Different Input Elements Different types of input capacitors will result in different transient voltage waveforms, as shown in Figure 3. The reference waveform for 22µF capacitor and 1µH inductor is shown in the top trace (R1); it peaks at 40.8V.The waveform R2 in Figure 3 shows what happens when a transient voltage suppressor is added across the input.The input voltage transient is clamped but not eliminated.It is very hard to set the voltage transient’s breakdown voltage low enough to protect the DC/DC converter and far enough from the operating DC level of the input source (24V). The transient voltage suppressor P6KE30A that was used was too close to starting to conduct at 24V.AN88-3Unfortunately, using a transient voltage suppressor with a higher voltage rating would not provide a sufficiently low clamping voltage.The waveforms R3 and R4 are with a 22µF, 35V AVX TPS type tantalum capacitor and a 22µF, 30V Sanyo OS-CON capacitor, respectively. With these two capacitors, the transients have been brought to manageable levels. How-ever, these capacitors are bigger than the ceramic capaci-tors and more than one capacitor is required in order to meet the input ripple current requirements.Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.actually required. A critically damped circuit will rise nicely to the input voltage without voltage overshoots or ringing.To keep the input filter design small, it is desirable to use ceramic capacitors because of their high ripple current ratings and low ESR. To start the design, the minimum value of the input capacitor must first be determined. In the example, it has been determined that a 22µF, 35V ceramic capacitor should be sufficient. The input tran-sients generated with this capacitor are shown in the top trace of Figure 4. Clearly, there will be a problem if components that are rated for 30V are used.To obtain optimum transient characteristic, the input circuit has to be damped. The waveform R2 shows what happens when another 22µF ceramic capacitor with a 0.5Ω resistor in series is added. The input voltage tran-sient is now nicely leveled off at 30V.Critical damping can also be achieved by adding a capaci-tor of a type that already has high ESR (on the order of 0.5Ω). The waveform R3 shows the transient response when a 22µF, 35V TPS type tantalum capacitor from AVX is added across the input.Figure 3. Input Transients with Different Input Components Table 2. Peak Voltages of Waveforms In Figure 3TRACE C IN (µF)CAPACITOR TYPEV IN PEAK (V)R122Ceramic 40.8R222Ceramic 32with 30V TVS R322AVX, TPS 33Tantalum R422Sanyo OS-CON35Optimizing Input CapacitorsWaveforms in Figure 3 show how input transients vary with the type of input capacitors used.Optimizing the input capacitors requires clear under-standing of what is happening during transients. Just as in an ordinary resonant RLC circuit, the circuit in Figure 1may have an underdamped, critically damped or overdamped transient response.Because of the objective to minimize the size of input filter circuit, the resulting circuit is usually an underdamped resonant tank. However, a critically damped circuit isFigure 4. Optimizing Input Circuit Waveforms for Reduced Peak VoltageTable 3. Peak Voltages of Waveforms In Figure 4 with 22µF Input Ceramic Capacitor and Added SnubberTRACE SNUBBER TYPEV IN PEAK (V)R1None40.8R222µF Ceramic + 0.5Ω In Series 30R322µF Tantalum AVX, TPS Series33R430V TVS, P6KE30A 35Ch147µF, 35V Aluminum 25Electrolytic CapacitorAN88-4an88f LT/TP 0301 4K • PRINTED IN USA© LINEAR TECHNOLOGY CORPORA TION 2001Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 q FAX: (408) 434-0507 q The waveform R4 shows the input voltage transient with a 30V transient voltage suppressor for comparison.Finally, an ideal waveform shown in Figure 4, bottom trace (Ch1) is achieved. It also turns out that this is the least expensive solution. The circuit uses a 47µF, 35V alumi-num electrolytic capacitor from Sanyo (35CV47AXA). This capacitor has just the right value of capacitance and ESR to provide critical damping of the 22µF ceramic capacitor in conjunction with the 1µH of input inductance. The 35CV47AXA has an ESR value of 0.44Ω and an RMS current rating of 230mA. Clearly, this capacitor could not be used alone in an application with 1A to 2A of RMS ripplecurrent without the 22µF ceramic capacitor. An additional benefit is that this capacitor is very small, measuring just 6.3mm by 6mm.ConclusionInput voltage transients are a design issue that should not be ignored. Design solutions for preventing input voltage transients can be very simple and effective. If the solution is properly applied, input capacitors can be minimized and both cost and size minimized without sacrificing performance.。

诺亚舟 CE88 电子辞典 说明书

诺亚舟 CE88 电子辞典 说明书

前 言承蒙惠购本公司产品,本公司将竭诚为您提供完善的服务。

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目 录一 基本使用说明 (1)1.1 使用注意事项 (1)1.2 机身简介 (2)1.3 按键功能说明 (2)1.4 屏幕指示说明 (5)1.5 输入法简介 (6)全拼输入法 (6)双拼输入法 (7)五笔输入法 (7)英文输入法 (8)数字输入法 (8)1.6 基本使用简介 (8)电源 (8)功能热键 (9)菜单的选择与浏览 (9)离开某项功能 (10)系统复位 (10)与PC通讯 (10)二 小新英汉词典功能 (11)普通查询 (11)顺序查询 (14)模糊查询 (15)三 简明汉英词典功能 (15)普通查询 (16)模糊查询 (17)四 记事功能 (18)4.1 名片盒 (18)名片输入 (18)名片查询 (20)名片删除 (21)名片修改 (21)4.2 备忘录 (22)4.3 提醒 (24)4.4 理财簿 (25)4.5 课程表 (26)五 时间功能 (28)六 计算 (28)6.1 普通计算 (28)6.2 常用换算 (30)6.2.1 单位换算 (30)6.2.2 汇率换算 (31)6.2.3 进制换算 (33)6.2.4 增值税计算 (33)6.2.5 房地产按揭 (34)七 资料 (34)7.1 学科知识 (34)7.2 英语园地 (35)不规则动词 (35)分类词库 (35)常用会话 (35)精品欣赏 (35)趣味英语 (36)谚语集锦 (36)常见英美姓名 (36)7.3 生活手册 (36)7.4 旅游指南 (36)7.5 文学鉴赏 (36)八 学习功能 (36)8.1 词汇学习 (36)8.2 巩固复习 (39)8.3 单元测试 (40)8.4 成绩图表 (40)8.5 学习设置 (42)九 娱乐 (42)9.1 俄罗斯方块 (42)9.2 搬运工 (43)9.3 猜单词 (43)9.4 围棋教室 (44)9.5 拼图游戏 (46)9.6 逻辑推数 (47)9.7 休闲时空 (48)十 系统 (49)10.1 系统参数设置 (49)时间设置 (49)时间方式设置 (49)密码设置 (49)自动关机设置 (51)亮度调节 (52)按键声音设置 (53)闹铃设置 (53)倒数计时 (53)10.2 资料管理 (54)10.3 开机设置 (54)10.4 网络传输 (55)十一 产品规格 (57)附录a: 双拼输入法代码表 (58)附录b: 五笔字型键盘字根总图 (59)附录c: 简易故障排除方法 (60)一.基本使用说明1. 1使用注意事项● 不要擅自对本机进行拆卸。

BK1086-88E数据手册v1.2

BK1086-88E数据手册v1.2
2.1 FM 接收器 .......................................................................................................... 3 2.2 AM 接收器 ......................................................................................................... 3 2.3 接口总线............................................................................................................. 4
RDS
DSP
AUTO
0/90
TUNE
DPLL
APLL
REG
BK1086/88E
LOUT
DAC
DAC
ROUT
GPIO
SDIO SCLK VIO
图 1 功能框图
2.1 FM接收器
FM接收器采用了可减少外围器件数量 的数字低中频架构,内部集成了支持 全世界调频广播频段(64-108MHz) 的低噪声放大器(LNA),可以控制 LNA的增益从而优化灵敏度和抑制大 干扰信号的自动增益控制器 (AGC),可把射频信号转换为低中 频信号的镜像抑制混频器。混频器的 输出通过一个可编程增益控制放大器 (PGA)来放大,然后由一个高分辨 率的模数转换器(ADC)转换成数字 信号。一个音频数字信号处理器 (DSP)完成了频道选择、FM解调、 立体声多路解码器和输出音频信号的 功能。多路解码器可自动从立体声转 换成单声道解码,从而限制了输出噪 声。
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88E1111数据手册Integrated 10/100/1000 Ultra Gigabit EthernetTransceiverYounger.li2013/1/12一.概览88E1111吉比特以太网收发器是一个物理层器件,用于1000BASE-T、100BASE-TX和10BASE-T类型的以太网,它是使用标准数字CMOS工艺制造,并且包含所有所需的有源电路来实现物理层功能,以便在标准的CAT-5类非屏蔽双绞线上发送和接收数据。

88E1111器件集成了Marvell的虚拟电缆测试仪®(VCT™)功能,虚拟电缆测试仪®使用了时域反射计(TDR)技术,它可以远程识别潜在的电缆故障。

从而减少设备的回厂调试和服务的次数。

使用VCT,Alaska的88E1111器件可以检测并报告潜在的布线问题,诸如线对交换反掉了、线对儿极性和过多的线对歪斜。

器件还可以在电缆上检测电缆断开、短路或任何的阻抗不匹配,以及准确报告在一米以内距离的故障。

88E1111支持用于直接连接到MAC/Switch接口的吉比特介质无关接口(GMII)、精简的GMII(RGMII)、串行吉比特介质无关接口(SGMII)、10比特接口(TBI)、精简的10比特接口(RTBI)。

88E1111器件集成了一个可选的1.25GHz的SERDES接口(串行器/解串器),这个串行接口可直接连接到光纤收发器,用于1000BASE-T/1000BASE-X介质转换的应用。

此外,88E1111可以被用于实现1000BASE -T千兆接口转换器(GBIC)或小型可插拔(SFP)模块。

88E1111器件采用了先进的混合信号进程来均衡执行、消除回声合传音、数据恢复和错误校正。

该器件具有强劲的性能,运行在高噪的环境中时也会消耗非常低的功耗。

88E1111器件提供三种不同的封装选项,包括:117引脚的TFBGA封装、整体尺寸只有9mm×9mm的96引脚的BCC封装和128引脚的PQFP封装。

二.特点●10/100/1000BASE-T 兼容IEEE 802.3●支持GMII、TBI、RGMII、RTBI、SGMII接口●集成用于1000BASE-X光纤应用的1.25GHz的SERDES接口●四种RGMII时序模式●能量检测和能量检测+低功耗模式●用于诊断的三种环回模式●用于两对电缆装置的“下移”模式●完全集成的数字自适应均衡器,回声消除器和串音消除器●先进的数字基线漂移校正●在所有的运行速率下都可以实现自动MDI/MDIX交叉●自动极性校正●兼容IEEE 802.3u的自动协商●包括LED测试的软件可编程LED模式●自动检测光纤或铜线工作模式●支持IEEE 1149.1 JTAG●两线串行接口(TWSI)和MDC/MDIO●CRC检查和包计数器●数据包生成●虚拟电缆测试(VCT)●MAC接口输出的自动校准●只需要两个电源:2.5V和1.0V(也可以不用1.0V,而使用1.2V)●I/O可以为3.3V●低功耗●0.13微●可选三●117引●可选R耗,只有0.75微米数字CMO三种封装:11脚的TFBGA封oHS6/6兼容88E15WOS工艺7引脚的TFB封装和96引容包装88E111188E11111111 RGMII/BGA封装、9引脚的BCC封1在电口方面1在光口方面/GMII MAC96引脚的BC封装有商业级面的应用面的应用到SGMII MACC封装和128和工业级转换8 PQFP封装目 录一. 信号描述 (1)1.1 117引脚的TFBGA封装 (1)1.2 96引脚的BBC封装 (2)1.3 128引脚的PQFP封装 (3)1.4 引脚描述 (3)1.4.1引脚类型描述 (3)1.5 在各种测试或复位模式下I/O口状态 (13)1.6 TFBGA-117封装引脚分配列表 (14)1.7 BCC-96封装引脚分配列表 (15)1.8 PQFP-128封装引脚分配列表 (16)二. 功能描述 (17)2.1 88E1111器件的接口描述 (17)2.1.1 介质接口 (17)2.1.2 MAC接口 (18)2.2 MAC接口 (19)2.2.1 千兆网介质无关接口(GMII/MII) (19)2.2.2 10位接口 (20)2.2.3 简化管脚数的GMII(RGMII) (21)2.2.4简化管脚数的TBI(RTBI) (22)2.2.5 SGMII接口 (23)2.2.6 串行MAC接口 (24)2.3 88E1111器件的运行模式 (25)2.3.1 用于铜介质的运行模式 (25)2.3.2 光纤接口的运行模式 (27)2.3.3 GMII/MII到SGMII模式和RGMII到SGMII模式 (27)一1.一. 信号88E1111是1 117引脚号描述 一个10/100脚的TFB 图1:88E10/1000BASE-T BGA 封装1111器件的图2:T/1000BASE-装117引脚的:引脚A1的-X 的吉比特TFBGA 封装的位置 以太网收发器(顶视图)器器件。

图3:888E1111器件的的96引脚的的BBC封装(顶视图)1.41.44 引脚描4.1引脚引HI/I O PU PD D Z mA 图4:88E 描述 脚类型描引脚类型 /O U D AE1111器件的述描述带迟输入输入输出内部内部开漏三态DC 吸的128引脚的述 迟滞的输入入输出 入 出 部上拉 部下拉 漏输出 态输出 吸收能力的PQFP 封装(顶视图)表1:介质相关接口GMII接口支持1000BASE-T和1000BASE-X两种运行模式,GMII接口引脚是与TBI接口引脚复用的。

表3为TBI接口引脚的定义,MAC接口引脚的工作电压是3.3V容限的,详细参见“数字引脚”。

表2:GMII/MII接口表2:GMII/MII接口(续)TBI接口支持1000BASE-T模式。

TBI接口的引脚是与GMII接口引脚复用的,MAC接口引脚的工作电压是3.3V容限的,详细参见“数字引脚”。

表3:TBI接口RGMII接口支持10/100/1000BASE-T和1000BASE-X模式,RGMII接口引脚是和RTBI接口引脚复用的,详见表5中关于RTBI引脚的定义。

MAC接口引脚的工作电压是3.3V容限的,详细参见“数字引脚”。

表4:RGMII接口RTBI接口支持1000BASE-T模式,RTBI接口引脚是与RGMII接口引脚复用的,MAC接口引脚的工作电压是3.3V容限的,详细参见“数字引脚”。

表5:RGMII接口表6:SGMII接口表7:1.25GHz串行高速接口表8:管理接口和中断表9:两线串行接口表10:LED接口表10:LED接口(续)表11:JTAG接口表12:JTAG接口表13:测试表14:控制和参考表15:电源和地1.5 在各种测试或复位模式下I/O口状态1.6TFBGA-117封装引脚分配列表引脚标号 引脚名 引脚标号 引脚名 引脚标号 引脚名 A1 RXD5 E4 VSS J7 DVDDA2 RXD6 E5 VSS J8 VDDOHA3 S_IN+ E6 VSS J9 XTAL2A4 S_IN E7 DVDD K1 VDDOA5 S_CLK+ E8 LED_DUPLEX K2 125CLKA6 S_CLK E9 CONFIG[1] K3 RESETnA7 S_OUT+ F1 TXD0 K4 VSSA8 S_OUT- F2 TX_ER K5 VSSA9 LED_LINK1000 F3 DVDD K6 VSSB1 RX_DV F4 VSS K7 NCB2 RXD0 F5 VSS K8 TDOB3 RXD3 F6 VSS K9 VDDOXB4 VDDO F7 VDDOH L1 INTnB5 CRS F8 CONFIG[2] L2 VDDOXB6 COL F9 CONFIG[4] L3 MDCB7 AVDD G1 NC L4 COMAB8 LED_LINK100 G2 TXD1 L5 VSSB9 VDDOH G3 TXD2 L6 VSSC1 RX_CLK G4 VSS L7 TDIC2 VDDO G5 VSS L8 TMSC3 RXD2 G6 VSS L9 TCKC4 RXD4 G7 CONFIG[3] M1 MDIOC5 RXD7 G8 CONFIG[6] M2 RSETC6 DVDD G9 CONFIG[5] M3 AVDDC7 DVDD H1 TXD4 M4 AVDDC8 LED_LINK10 H2 TXD3 M5 HSDAC+C9 LED_RX H3 TXD5 M6 HSDAC-D1 TX_CLK H4 VSS M7 AVDDD2 RX_ER H5 VSS M8 AVDDD3 RXD1 H6 VSS M9 TRSTnD4 VSS H7 VSSC N1 MDI[0]+D5 VSS H8 SEL_FREQ N2 MDI[0]-D6 VSS H9 XTAL1 N3 MDI[1]+D7 DVDD J1 TXD6 N4 MDI[1]-D8 CONFIG[0] J2 TXD7 N5 AVDDD9 LED_TX J3 DVDD N6 MDI[2]+E1 TX_EN J4 VSS N7 MDI[2]-E2 GTX_CLK J5 VSS N8 MDI[3]+E3 DVDD J6 VSS N9 MDI[3]-1.7BCC-96封装引脚分配列表引脚标号 引脚名 引脚标号 引脚名 引脚标号 引脚名1 DVDD 33 MDI[1]+ 65 CONFIG[0]2 RX_CLK 34 MDI[1]- 66 VDDOH3 RX_ER 35 AVDD 67 DVDD4 TX_CLK 36 AVDD 68 LED_TX5 VDDO 37 HSDAC+ 69 LED_RX6 DVDD 38 HSDAC- 70 LED_DUPLEX7 TX_ER 39 MDI[2]+ 71 DVDD8 GTX_CLK 40 AVDD 72 VDDOH9 TX_EN 41 MDI[2]- 73 LED_LINK100010 DVDD 42 MDI[3]+ 74 LED_LINK10011 TXD0 43 MDI[3]- 75 S_OUT-12 TXD1 44 TDI 76 LED_LINK1013 NC 45 AVDD 77 S_OUT+14 TXD2 46 TMS 78 AVDD15 DVDD 47 TRSTn 79 S_CLK+16 TXD3 48 VDDOX 80 S_CLK-17 TXD4 49 TCK 81 S_IN18 TXD5 50 TDO 82 S_IN+19 TXD6 51 NC 83 COL20 TXD7 52 VDDOH 84 CRS21 VDDO 53 VSSC 85 DVDD22 125CLK 54 XTAL2 86 RXD723 INTn 55 XTAL1 87 RXD624 MDIO 56 SEL_FREQ 88 VDDO25 MDC 57 DVDD 89 RXD526 VDDOX 58 CONFIG[6] 90 RXD427 COMA 59 CONFIG[5] 91 RXD328 RESETn 60 CONFIG[4] 92 RXD129 MDI[0]+ 61 CONFIG[3] 93 RXD230 RSET 62 DVDD 94 RX_DV31 MDI[0]- 63 CONFIG[2] 95 RXD032 AVDD 64 CONFIG[1] 96 VDDO0 VSS1.8PQFP-128封装引脚分配列表引脚标号 引脚名 引脚标号 引脚名 引脚标号引脚名 引脚标号 引脚名1 VSS 33 MDIO 65 VSS 97 VDDOH2 DVDD 34 VDDOX 66 VSS 98 LED_LINK10003 RXD0 35 MDC 67 TDI 99 LED_LINK1004 RX_DV 36 RESETn 68 TRSTn 100 LED_LINK105 VDDO 37 COMA 69 TMS 101 VSS6 DVDD 38 VSS 70 TCK 102 VSS7 RX_CLK 39 RSET 71 VDDOX 103 VSS8 RX_ER 40 VSS 72 TDO 104 AVDD9 VSS 41 MDI[0]+ 73 VDDOH 105 S_OUT-10 TX_CLK 42 MDI[0]- 74 VSSC 106 VSS11 VDDO 43 VSS 75 XTAL2 107 S_OUT+12 DVDD 44 AVDD 76 XTAL1 108 VSS13 TX_ER 45 VSS 77 SEL_FREQ 109 S_CLK-14 GTX_CLK 46 MDI[1]+ 78 DVDD 110 S_CLK+15 VSS 47 MDI[1]- 79 CONFIG[6] 111 VSS16 TX_EN 48 VSS 80 CONFIG[5] 112 S_IN-17 DVDD 49 AVDD 81 CONFIG[4] 113 S_IN+18 TXD0 50 NC 82 CONFIG[3] 114 COL19 TXD1 51 VSS 83 VSS 115 CRS20 TXD2 52 AVDD 84 VSS 116 VSS21 VSS 53 HSDAC+ 85 DVDD 117 DVDD22 VSS 54 HSDAC- 86 CONFIG[2] 118 DVDD23 DVDD 55 VSS 87 CONFIG[1] 119 VSS24 TXD3 56 MDI[2]+ 88 CONFIG[0] 120 RXD725 TXD4 57 MDI[2]- 89 VDDOH 121 RXD626 TXD5 58 VSS 90 DVDD 122 VDDO27 DVDD 59 AVDD 91 LED_TX 123 RXD528 TXD6 60 VSS 92 LED_RX 124 RXD429 TXD7 61 MDI[3]+ 93 VSS 125 RXD330 VDDO 62 MDI[3]- 94 VSS 126 RXD231 125CLK 63 VSS 95 LED_DUPLEX 127 VSS32 INTn 64 AVDD 96 DVDD 128 RXD1二质接码子2.2.2.1 100B 阻, 见“2.1 GMII 阻抗存器SERD二. 功能88E1111是图5显示了接入层的更全子层和物理介1 88E1188E1111器1.1 介质1.1.1 铜介铜介质接口BASE-TX 和1并且通过以5类(CAT5“Alaska Ult 1.1.2 光光缆连接到I 或RGMII 接SERDES 接口抗。

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