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8051微控制器硬件手册及应用注释说明书

1API Program ExamplesReferences•Atmel 8051 Microcontrollers Hardware Manual1. IntroductionThis Application Note provides to customers C program examples for Api usages.24365A–80C51–07/0434365A–80C51–07/042. API for Standard C512.1 flash_eeprom_api.c/*C************************************************************************ NAME: flash_eeprom_api.c*-------------------------------------------------------------------------* Copyright (c) 2004 Atmel.*-------------------------------------------------------------------------* RELEASE:* REVISION: 1.0*-------------------------------------------------------------------------* PURPOSE:* Read/Write flash* CAUTTION : add #define ONCHIP_EEPROM for on-chip eeprom products* (defined by default in the standard delivery)**************************************************************************//*_____ I N C L U D E - F I L E S _______________________________________*/#include "reg_C51.h"/*_____ D E C L A R A T I O N ___________________________________________*/#define ONCHIP_EEPROM //define it only for on-chip eeprom products/*---- API for FLASH access --------------------------------------------*//*************************************************************************/#define __api_rd_code_byte(address) (*((unsigned char code*) (address)))unsigned char__api_wr_code_byte(int , unsigned char)small;unsigned char__api_wr_code_page(int , int, unsigned char)small;/*---- API for EEPROM access -------------------------------------------*//*************************************************************************/#ifdef ONCHIP_EEPROMvoid __api_wr_eeprom_byte(unsigned int adr, unsigned char value);unsigned char __api_rd_eeprom_byte(unsigned int adr);#endif/*_____ G L O B A L S ___________________________________________________*/sfr16 DPTR = 0x82;/*_____ L O C A L S _____________________________________________________*/#define MSK_AUXR1_ENBOOT0x20#define MSK_AUXR_M00x20#define MAP_BOOT AUXR1 |= MSK_AUXR1_ENBOOT;#define UNMAP_BOOTAUXR1 &= ~MSK_AUXR1_ENBOOT;/*_____ EXTERNAL - F U N C T I O N S - D E C L A R A T I O N ____________*/extern void ASM_MOV_R1_A(void);extern void __API_FLASH_ENTRY_POINT(void);/*F************************************************************************ NAME: __api_wr_code_byte*-------------------------------------------------------------------------* PARAMS:* int address : address to program* unsigned char value : data to write* unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* Program data byte in Flash memory**************************************************************************/unsigned char __api_wr_code_byte (int address, unsigned char value) small{bit ea_save;ea_save = EA;EA = 0;DPTR = address;ACC = 0x02;ASM_MOV_R1_A();ACC = value;MAP_BOOT;__API_FLASH_ENTRY_POINT();UNMAP_BOOT;EA = ea_save; // restore interrupt statereturn (ACC);}/*F************************************************************************ NAME: __api_wr_code_page*-------------------------------------------------------------------------* PARAMS:* int add_flash : address of the first byte to program in the Flash* int add_xram : address in XRAM of the first data to program* unsigned char nb_data : number of bytes to program*unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* Program until 128 Datas in Flash memory.* Number of bytes to program is limited such as the Flash write remains in a* single 128 bytes page.**************************************************************************/unsigned char __api_wr_code_page (int add_flash, int add_xram, unsigned charnb_data) small{unsigned char save_auxr1;bit ea_save;44365A–80C51–07/0454365A–80C51–07/04ea_save = EA;EA = 0;save_auxr1 = AUXR1;AUXR1 &= ~0x01; // Set DPTR=DPTR0DPTR = add_flash;AUXR1++; // DPTR = DPTR1DPTR = add_xram;ACC = 0x09;ASM_MOV_R1_A();ACC = nb_data;AUXR1 &= ~0x01; // Set DPTR = DPTR0MAP_BOOT__API_FLASH_ENTRY_POINT();UNMAP_BOOT;AUXR1 = save_auxr1;EA = ea_save; // restore interrupt statereturn (ACC);}/*F************************************************************************ NAME: __api_rd_eeprom_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int adr: The EEDATA memory location to read* return: value*-------------------------------------------------------------------------* PURPOSE:* This function reads one byte in the on-chip EEPROM data.*-------------------------------------------------------------------------* EXAMPLE:* val=__api_rd_eeprom_byte(128);*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_rd_eeprom_byte(unsigned int adr){unsigned char val;bit ea_save;while (EECON&1);//Eeprom_busy()ea_save=EA;EA=0;EECON |= 0x02;//Enable eeprom data;val=*(unsigned char xdata*)adr;EECON &= ~0x02;//Disable eeprom data;EA=ea_save;return val;}/*F************************************************************************ NAME: __api_wr_eeprom_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int adr: The EEDATA memory location to read* unsigned char value: The data byte to write* return: none*-------------------------------------------------------------------------* PURPOSE:* This function writes one byte in the on-chip EEPROM data.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/void __api_wr_eeprom_byte(unsigned int adr, unsigned char value){bit ea_save;while(EECON & 0x01);// wait bit busyea_save=EA;EA=0;EECON |= 0x02;//Enable eeprom data*(unsigned char xdata*)adr=value;EECON &= ~0x02;//Disable eeprom dataEA=ea_save;}64365A–80C51–07/0474365A–80C51–07/042.2 flash_lib.a51NAME FLASH_LIB;;*A51********************************************************************; FILE_NAME : FLASH_LIB.a51 ;------------------------------------------------------------------------ ;------------------------------------------------------------------------; FILE_PURPOSE: low level function for API;************************************************************************USING 0PUBLIC ASM_MOV_R1_APUBLIC __API_FLASH_ENTRY_POINTAUXR1 EQU0A2hSTART SEGMENT CODERSEG START;************************************************************************; FUNCTION_NAME: ASM_MOV_A_R1;************************************************************************ASM_MOV_R1_A:Mov R1, ARet;************************************************************************; FUNCTION_NAME: __API_FLASH_ENTRY_POINT;************************************************************************__API_FLASH_ENTRY_POINT:PUSHAR2PUSHAR4PUSHAR6LCALL 0FFF0hPOPAR6POPAR4POPAR2RetEND3. API for USB products3.1 flash_eeprom_api.c/*C************************************************************************ NAME: flash_eeprom_api.c*-------------------------------------------------------------------------* Copyright (c) 2004 Atmel.*-------------------------------------------------------------------------* RELEASE:* REVISION:*-------------------------------------------------------------------------* PURPOSE:* This file contains whole of functions to access AT89C5131 Flash and* EEPROM and AT89C51SND1.* CAUTTION : add #define ONCHIP_EEPROM for on-chip eeprom products* (defined by default in the standard delivery)**************************************************************************//*_____ I N C L U D E S _________________________________________________*/#include "reg_C51.h"/*_____ D E F I N I T I O N _____________________________________________*/#define ONCHIP_EEPROM //define it only for build-in eeprom chipsunsigned char data api_command _at_ 0x1C;unsigned char data api_value _at_ 0x1D;#define MSK_AUXR1_ENBOOT 0x20#define MAP_BOOT AUXR1 |= MSK_AUXR1_ENBOOT;#define UNMAP_BOOT AUXR1 &= ~MSK_AUXR1_ENBOOT;#define __API_FLASH_ENTRY_POINT (*((const void(code*)(void)) 0xFFC0 ))/*_____ D E C L A R A T I O N ___________________________________________*//*---- API for FLASH access --------------------------------------------*//*************************************************************************/unsigned char __api_rd_code_byte (unsigned char code * pt_address);unsigned char __api_wr_code_byte (unsigned char xdata* , unsigned char);unsigned char __api_wr_code_page (unsigned char xdata* pt_code,unsigned char xdata* pt_xram,unsigned char nb_data);/*---- API for EEPROM access -------------------------------------------*//*************************************************************************/#ifdef ONCHIP_EEPROMunsigned char __api_rd_eeprom_byte(unsigned char xdata *);unsigned char __api_wr_eeprom_byte(unsigned char xdata *, unsigned char);#endif84365A–80C51–07/0494365A–80C51–07/04/*F************************************************************************ NAME: __api_rd_code_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int address : address in flash memory to read* return:* unsigned char device : read value*-------------------------------------------------------------------------* PURPOSE:* This function allows to read a flash memory byte.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_rd_code_byte (unsigned char code * pt_address){return(*pt_address);}/*F************************************************************************ NAME: __api_wr_code_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int address : address to program* unsigned char value : data to write* return:* unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* This function allows to program data byte in Flash memory.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_wr_code_byte (unsigned char xdata * pt_address, unsigned char value){bit ea_save;ea_save = EA;EA = 0;api_command = 0x0D; //_COMMAND_WR_CODE_BYTE;FCON = 0x08;*pt_address = value;MAP_BOOT;__API_FLASH_ENTRY_POINT();UNMAP_BOOT;EA = ea_save; // restore interrupt statereturn(api_value);}/*F************************************************************************ NAME: __api_wr_code_page*-------------------------------------------------------------------------* PARAMS:* unsigned int add_flash : address of the first byte to program* in the Flash* unsigned int add_xram : address in XRAM of the first data to program* unsigned char nb_data : number of bytes to program* return:* unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* This function allows to program until 128 Datas in Flash memory.* Number of bytes to program is limited such as the Flash write remains* in a single 128 bytes page.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:* This function used Dual Data Pointer DPTR0&1. At the end of this* function.* DPTR = DPTR0.*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_wr_code_page (unsigned char xdata * pt_code,unsigned char xdata * pt_xram,unsigned char nb_data){unsigned char data i, temp, temp_nb_data;bit ea_save;unsigned int data add_pt_code, add_pt_xram;add_pt_xram = pt_xram;add_pt_code = pt_code;temp_nb_data = nb_data;104365A–80C51–07/04114365A–80C51–07/04ea_save = EA;EA = 0;api_command = 0x0D;for (i=0 ; i< temp_nb_data; i++,add_pt_xram++,add_pt_code++){temp = *(unsigned char xdata *)add_pt_xram;FCON = 0x08;*(unsigned char xdata *)add_pt_code = temp;FCON = 0x00;}MAP_BOOT;__API_FLASH_ENTRY_POINT();UNMAP_BOOT;EA = ea_save; // restore interrupt statereturn(api_value);}#ifdef ONCHIP_EEPROM/*F************************************************************************ NAME: api_rd_eeprom*-------------------------------------------------------------------------* PARAMS:* unsigned char xdata *address : address to read* return:*-------------------------------------------------------------------------* PURPOSE:* This function allows to read a byte in Eeprom.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS: The EEPROM mustn't be busy to perform the read access.* eeprom status :(EECON & 0x01)=1 busy, =0 free**************************************************************************/unsigned char __api_rd_eeprom_byte(unsigned char xdata *address){unsigned char val;bit ea_save;ea_save = EA;EA = 0;EECON = 0x02;val = *address;EECON = 0x00;EA = ea_save;return (val);}/*F************************************************************************ NAME: api_wr_eeprom_byte*-------------------------------------------------------------------------* PARAMS:* unsigned char xdata* address : address to read* unsigned char value : data to write* return:*-------------------------------------------------------------------------* PURPOSE:* This function allows to program a byte in Eeprom.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS: The EEPROM mustn't be busy to perform the read access.* eeprom status :(EECON & 0x01)=1 busy, =0 free**************************************************************************/unsigned char __api_wr_eeprom_byte (unsigned char xdata *address,unsigned char value){bit ea_save;while(EECON & 0x01);// wait bit busyea_save = EA;EA = 0;EECON = 0x02;*address = value;/* addr is a pointer to external data mem */EECON = 0x50;EECON = 0xA0;EA = ea_save;return (1);}#endif124365A–80C51–07/04134365A–80C51–07/044. Example4.1 test_api.c/*C*********************************************************************** NAME: test_api.c*------------------------------------------------------------------------* Copyright (c) 2004 Atmel.*------------------------------------------------------------------------* RELEASE:* REVISION: 1.0*------------------------------------------------------------------------* PURPOSE: usage example of flash_eeprom_api.c*************************************************************************//*_____ I N C L U D E S ________________________________________________*/#include "flash_eeprom_api.c"/*F************************************************************************ NAME: main*-------------------------------------------------------------------------* PARAMS:*-------------------------------------------------------------------------* PURPOSE: usage example of flash_eeprom_api.c*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:*************************************************************************/void main (void){int adress;char i=0;char data_tmp;/* write code page example */for(adress=0x0000;adress<0x007F;adress++){/* write 0x55 between 0x0000 and 0x007F of xram */*((unsigned char xdata*) adress)=0x55;}/* copy xram page to flash at 0x1100 */__api_wr_code_page(0x1100,0x0000,0x7F);/* write code byte example */i=0;for(adress=0x1000;adress<0x1006;adress++){/* write "ABCDEF" at 0x1000 */__api_wr_code_byte(adress,0x41+i++);}/* read and write code byte example */for(adress=0x1000;adress<0x1006;adress++){/* copy 0x1000-0x1006 to 0x1010-0x1016 in flash memory */data_tmp = __api_rd_code_byte(adress);__api_wr_code_byte(adress+0x0010,data_tmp);}#ifdef ONCHIP_EEPROM/* write eeprom byte example */i=0;for (adress=0x000;adress<0x400;adress++) /* write 1Ko of eeprom */{/* write a byte, write time = 10ms to 20ms */__api_wr_eeprom_byte(adress,i++);}/* read eeprom byte example */for (adress=0x000;adress<0x400;adress++){/* copy previous writed data from eeprom to flash at 0x1200 */data_tmp=__api_rd_eeprom_byte(adress);__api_wr_code_byte(0x1200+adress,data_tmp);}#endifwhile(1); /* endless */}144365A–80C51–07/04154365A–80C51–07/044.2 SFR Register Definition/*H**************************************************************************** NAME: AT89C51XD2.h*----------------------------------------------------------------------------* PURPOSE: SFR Description file for AT89C51xD2 products* ON KEIL compiler*****************************************************************************/#define Sfr(x, y) sfr x = y#define Sbit(x, y, z) sbit x = y^z#define Sfr16(x,y) sfr16 x = y/*----------------------------------------*//* Include file for 8051 SFR Definitions *//*----------------------------------------*//* BYTE Register */Sfr (P0 , 0x80);Sbit (P0_7 , 0x80, 7);Sbit (P0_6 , 0x80, 6);Sbit (P0_5 , 0x80, 5);Sbit (P0_4 , 0x80, 4);Sbit (P0_3 , 0x80, 3);Sbit (P0_2 , 0x80, 2);Sbit (P0_1 , 0x80, 1);Sbit (P0_0 , 0x80, 0);Sfr (P1 , 0x90);Sbit (P1_7 , 0x90, 7);Sbit (P1_6 , 0x90, 6);Sbit (P1_5 , 0x90, 5);Sbit (P1_4 , 0x90, 4);Sbit (P1_3 , 0x90, 3);Sbit (P1_2 , 0x90, 2);Sbit (P1_1 , 0x90, 1);Sbit (P1_0 , 0x90, 0);Sfr (P2 , 0xA0);Sbit (P2_7 , 0xA0, 7);Sbit (P2_6 , 0xA0, 6);Sbit (P2_5 , 0xA0, 5);Sbit (P2_4 , 0xA0, 4);Sbit (P2_3 , 0xA0, 3);Sbit (P2_1 , 0xA0, 1);Sbit (P2_0 , 0xA0, 0);Sfr (P3 , 0xB0);Sbit (P3_7 , 0xB0, 7);Sbit (P3_6 , 0xB0, 6);Sbit (P3_5 , 0xB0, 5);Sbit (P3_4 , 0xB0, 4);Sbit (P3_3 , 0xB0, 3);Sbit (P3_2 , 0xB0, 2);Sbit (P3_1 , 0xB0, 1);Sbit (P3_0 , 0xB0, 0);Sbit (RD , 0xB0, 7);Sbit (WR , 0xB0, 6);Sbit (T1 , 0xB0, 5);Sbit (T0 , 0xB0, 4);Sbit (INT1 , 0xB0, 3);Sbit (INT0 , 0xB0, 2);Sbit (TXD , 0xB0, 1);Sbit (RXD , 0xB0, 0);Sfr (P4 , 0xC0);Sbit (P4_7 , 0xC0, 7);Sbit (P4_6 , 0xC0, 6);Sbit (P4_5 , 0xC0, 5);Sbit (P4_4 , 0xC0, 4);Sbit (P4_3 , 0xC0, 3);Sbit (P4_2 , 0xC0, 2);Sbit (P4_1 , 0xC0, 1);Sbit (P4_0 , 0xC0, 0);Sfr (P5 , 0xE8);Sbit (P5_7 , 0xE8, 7);Sbit (P5_6 , 0xE8, 6);Sbit (P5_5 , 0xE8, 5);Sbit (P5_4 , 0xE8, 4);Sbit (P5_3 , 0xE8, 3);Sbit (P5_2 , 0xE8, 2);Sbit (P5_1 , 0xE8, 1);Sbit (P5_0 , 0xE8, 0);Sfr (PSW , 0xD0);Sbit (CY , 0xD0 , 7);Sbit (AC , 0xD0 , 6);164365A–80C51–07/04174365A–80C51–07/04Sbit (RS1 , 0xD0 , 4);Sbit (RS0 , 0xD0 , 3);Sbit (OV , 0xD0 , 2);Sbit (UD , 0xD0 , 1);Sbit (P , 0xD0 , 0);Sfr (ACC , 0xE0);Sfr (B , 0xF0);Sfr (SP , 0x81);Sfr (DPL , 0x82);Sfr (DPH , 0x83);Sfr (PCON , 0x87);Sfr (CKCON0 , 0x8F);Sfr (CKCON1 , 0xAF);/*------------------ TIMERS registers ---------------------*/Sfr (TCON , 0x88);Sbit (TF1 , 0x88, 7);Sbit (TR1 , 0x88, 6);Sbit (TF0 , 0x88, 5);Sbit (TR0 , 0x88, 4);Sbit (IE1 , 0x88, 3);Sbit (IT1 , 0x88, 2);Sbit (IE0 , 0x88, 1);Sbit (IT0 , 0x88, 0);Sfr (TMOD , 0x89);Sfr (T2CON , 0xC8);Sbit (TF2 , 0xC8, 7);Sbit (EXF2 , 0xC8, 6);Sbit (RCLK , 0xC8, 5);Sbit (TCLK , 0xC8, 4);Sbit (EXEN2 , 0xC8, 3);Sbit (TR2 , 0xC8, 2);Sbit (C_T2 , 0xC8, 1);Sbit (CP_RL2, 0xC8, 0);Sfr (T2MOD , 0xC9);Sfr (TL0 , 0x8A);Sfr (TL1 , 0x8B);Sfr (TL2 , 0xCC);Sfr (TH0 , 0x8C);Sfr (TH1 , 0x8D);Sfr (TH2 , 0xCD);Sfr (RCAP2L , 0xCA);Sfr (RCAP2H , 0xCB);Sfr (WDTRST , 0xA6);/*------------------- UART registers ------------------------*/Sfr (SCON , 0x98);Sbit (SM0 , 0x98, 7);Sbit (FE , 0x98, 7);Sbit (SM1 , 0x98, 6);Sbit (SM2 , 0x98, 5);Sbit (REN , 0x98, 4);Sbit (TB8 , 0x98, 3);Sbit (RB8 , 0x98, 2);Sbit (TI , 0x98, 1);Sbit (RI , 0x98, 0);Sfr (SBUF , 0x99);Sfr (SADEN , 0xB9);Sfr (SADDR , 0xA9);/*-------------------- Internal Baud Rate Generator --------*/Sfr (BRL , 0x9A);Sfr (BDRCON , 0x9B);/*-------------------- IT registers -----------------------*/Sfr (IEN0 , 0xA8);Sfr (IEN1 , 0xB1);Sfr (IPH0 , 0xB7);Sfr (IPH1 , 0xB3);Sfr (IPL0 , 0xB8);Sfr (IPL1 , 0xB2);/* IEN0 */Sbit (EA , 0xA8, 7);Sbit (EC , 0xA8, 6);Sbit (ET2 , 0xA8, 5);Sbit (ES , 0xA8, 4);Sbit (ET1 , 0xA8, 3);Sbit (EX1 , 0xA8, 2);Sbit (ET0 , 0xA8, 1);Sbit (EX0 , 0xA8, 0);/*--------------------- PCA registers -----------------------------*/Sfr (CCON , 0xD8);Sfr (CMOD , 0xD9);Sfr (CH , 0xF9);184365A–80C51–07/04194365A–80C51–07/04Sfr (CCAP0H , 0xFA);Sfr (CCAP0L , 0xEA);Sfr (CCAPM0 , 0xDA);Sfr (CCAP1H , 0xFB);Sfr (CCAP1L , 0xEB);Sfr (CCAPM1 , 0xDB);Sfr (CCAP2H , 0xFC);Sfr (CCAP2L , 0xEC);Sfr (CCAPM2 , 0xDC);Sfr (CCAP3H , 0xFD);Sfr (CCAP3L , 0xED);Sfr (CCAPM3 , 0xDD);Sfr (CCAP4H , 0xFE);Sfr (CCAP4L , 0xEE);Sfr (CCAPM4 , 0xDE);/* CCON */Sbit (CF , 0xD8, 7);Sbit (CR , 0xD8, 6);Sbit (CCF4 , 0xD8, 4);Sbit (CCF3 , 0xD8, 3);Sbit (CCF2 , 0xD8, 2);Sbit (CCF1 , 0xD8, 1);Sbit (CCF0 , 0xD8, 0);/*------------------ T W I registers ------------------------------*/Sfr ( SSCON , 0x93);Sfr ( SSCS , 0x94);Sfr ( SSDAT , 0x95);Sfr ( SSADR , 0x96);Sfr ( PI2, 0xF8);Sbit (PI2_1 , 0xF8, 1);Sbit (PI2_0 , 0xF8, 0);/*-------------------- OSC control registers ----------------------*/Sfr ( CKSEL , 0x85 );Sfr ( OSCCON , 0x86 );Sfr ( CKRL , 0x97 );/*-------------------- Keyboard control registers -----------------*/Sfr ( KBLS , 0x9C );Sfr ( KBE , 0x9D );Sfr ( KBF , 0x9E );/*-------------------- SPI ---------------------- -----------------*/Sfr ( SPCON, 0xC3 );Sfr ( SPSTA, 0xC4 );Sfr ( SPDAT, 0xC5 );/*------ Misc ----------------------------------------------------*/Sfr( AUXR , 0x8E);Sfr ( AUXR1, 0xA2);Sfr ( FCON, 0xD1);/*------ E data --------------------------------------------------*/Sfr ( EECON, 0xD2 );204365A–80C51–07/04Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80e-mail********************Web Site4365A–80C51–07/04/xM©Atmel Corporation 2004. All rights reserved. Atmel, the Atmel logo, andcombinations thereof are registered trademarks of Atmel Corporation or its subsidiaries. Windows ® Windows 98™, Windows XP ™, and Windows 2000™ are trademarks and/ore registered trademark of Microsoft Corporation. Other terms and product names in this document may be the trademarks of others.。

片机基础知识：8051特点、结构与扩展

“微控制器”的称谓更能反映单片机的本质。
4、单片机的发展趋势
（1）低功耗CMOS化
80C51就采用了HMOS(即高密度金属氧化物半导体工艺) 和CHMOS(互补高密度金属氧化物半导体工艺)。更适合于在要求低功耗象电池供电的应用场合。
（2）微型单片化
要求体积小、重量轻、具有多种封装形式，其中 SMD(表面封装)越来越受欢迎，使得由单片机构成的系统正朝微型化方向发展。
（3）8051的指令部件
程序计数器PC：是一个16位的计数器，其内容是下一条待执行指令的地址，寻址范围是64KB。
➢RS1，RS0 = 1 0 则选择了工作寄存器组 2 区 R0～R7分别代表10H ～17H单元。
➢RS1，RS0 = 1 1 则选择了工作寄存器组 3 区 R0～R7分别代表18H ～1FH单元。
PSW.7 PSW.6 PSW.5
CY AC F0 RS1 RS0 OV
PSW.0
P
▼OV (PSW.2)溢出标志位。
（1）8051的时钟时钟电路是计算机的心脏，控制着计算机的工作节奏。
通常外接一个晶振两个电容
30±10pfx2
XTAL1 XTAL2
也可以由 XTAL1 端接入外部时钟，此时应将 XTAL2 接地：
外部时钟
XTAL1 XTAL2
1～12MHz（MCS-51） 4～24MHz（Atmel89C）
MCS51单片机和8051、8031、89C51等的关系
这一系列单片机包括了好些品种，如8031，8051， 8751，8032，8052，8752等，其中8051是最早最典型的产品，该系列其它单片机都是在8051的基础上进行功能的增、减、改变而来的，所以人们习惯于用8051来称呼 MCS51系列单片机，而8031是前些年在我国最流行的单片机，所以很多场合会看到8031的名称。

单片机芯片资料速查

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4、(EA)/Vpp（31脚）
EA端接高电平时，CPU取指令从片内程序存贮器自动顺延至片外程序存贮器。 EA端接低电平时，CPU仅从片外程序存贮器取指令。该引脚有复用功能，Vpp为片内程序存贮器编程时的编程电压。
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返回引脚图
4、输入/输出引脚P0、P1、P2和P3口
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P3口的第二功能
P3.0（10脚）： RXD（串行口输入端） P3.1（11脚）： TXD（串行口输出端） P3.2（12脚）： /INT0（外部中断0输入端） P3.3（13脚）： /INT1（外部中断1输入端） P3.4（14脚）： T0（定时器/计数器0外部输入端） P3.5（15脚）： T1（定时器/计数器1外部输入端） P3.6（16脚）： /WR（片外数据存贮器写选通信号输出端） P3.7（17脚）： /RD（片外数据存贮器读选通信号输出端
时钟电路引脚Vss接
地
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST/Vpd RXD/P3.0 TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 Vss
1
40
2
地址锁存信号端。访问片外存贮器时，ALE作低八位地址的锁存控制信号。平时不访问片外存贮器时，该端以六分之一的时钟振荡频率固定输出脉冲。 ALE端负载驱动能力为8个TTL门电路。该引脚有复用功能，为片内程序存贮器编程（固化）的编
程脉冲输入。
3、PSEN（29脚）
片外程序存贮器读选通信号端。负载能力为 8个TTL门电路。

单片机8051寄存器

P3为两用端口：┏━━━┯━━━┯━━━━━━━━━━━━━┓┃P3.0│RXD │串行口通讯输入┃┃P3.1│TXD │串行口通讯输出┃┃P3.2│INT0 │外部中断0 ┃┃P3.3│INT1 │外部中断1 ┃┃P3.4│T0 │定时器/计数器0┃┃P3.5│T1 │定时器/计数器1 ┃┃P3.6│WR │外部随机存取器的写入信号┃┃P3.7│RD │外部随机存取器的读取信号┃┗━━━┷━━━┷━━━━━━━━━━━━━┛-------------------------------------------------------------------------8051程序设计只读存储器特殊地址┏━━━━━━━┯━━━━━━━┯━━━━━━━┓┃名称│中断源│向量位置┃┠───────┼───────┼───────┨┃系统重置│RESET │00H ┃┃外部中断0 │INT0 │03H ┃┃定时器0中断│TIMER0 │0BH ┃┃外部中断1 │INT1 │13H ┃┃定时器1中断│TIMER1 │1BH ┃┃串行口中断│UART │23H ┃┗━━━━━━━┷━━━━━━━┷━━━━━━━┛-------------------------------------------------------------------------8051特殊功能寄存器┏━━━┯━━━━━━━━━━━┯━━━━━━━┓┃名称│用途│地址┃┠───┼───────────┼───────┨┃*ACC │累加器B │E0H ┃┃*B │寄存器B │F0H ┃┃*PSW │程序状态字│D0H ┃┃SP │堆栈指计│81H ┃┃DPTR │数据指计(DPH,DPL) │83H,82H ┃┃P0 │I/O端口0 │80H ┃┃P1 │I/O端口1 │90H ┃┃P2 │I/O端口2 │A0H ┃┃P3 │I/O端口3 │B0H ┃┃*IP │中断优先顺序控制│B8H ┃┃*IE │中断使能控制│A8H ┃┃TMOD │计时器模式控制│89H ┃┃*TCON │计时器控制│88H ┃┃TH0 │计时器0高字节寄存器│8CH ┃┃TL0 │计时器0低字节寄存器│8AH ┃┃TH1 │计时器1高字节寄存器│8DH ┃┃TL1 │计时器1低字节寄存器│8BH ┃┃*SCON │串行端口控制│98H ┃┃SBUF │串行端口数据缓冲器│99H ┃┃PCON │电源控制│87H ┃┗━━━┷━━━━━━━━━━━┷━━━━━━━┛*:表示位可寻址程序状态寄存器PSW (D0H)┏━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━━━━━┓┃PSW │CY │AC │F0 │RS1 │RS0 │OV │USR │P ┃┃D0H │D7H │D6H │D5H │D4H │D3H │D2H │D1H │D0H ┃┠───┼───┼───┼───┼───┼───┼───┼───┼───────┨┃地址│D7 │D6 │D5 │D4 │D3 │D2 │D1 │D0 ┃┠───┼───┴───┴───┴───┴───┴───┴───┴───────┨┃CY │进位标志位A最高位A7：0,无进位或借位；1,有进位或借位┃┃AC │辅助进位标志位A低4位A3向高4位A4:0,无进位或借位；1,有进位或借位┃┃F0 │通用标志位通用标志位，可任意设定┃┃RS1 │寄存器组选择位高位┃┃RS0 │寄存器组选择位低位00，0组；01，1组；10，2组；11，3组┃┃OV │溢出标志位0，无溢出；1，有溢出┃┃USR │用户定义标志位用户定义标志位，可任意设定┃┃P │奇偶标志位0，A中1的个数为偶数；1，A中1的个数为奇数┃┗━━━┷━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┛中断优先级寄存器IP (B8H)┏━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┓┃IP │/ │/ │/ │PS │PT1 │PX1 │PT0 │PX0 ┃┃B8H │/ │/ │/ │BCH │BBH │BAH │B9H │B8H ┃┠───┼───┼───┼───┼───┼───┼───┼───┼───┨┃地址│D7 │D6 │D5 │D4 │D3 │D2 │D1 │D0┃┠───┼───┴───┴───┴───┴───┴───┴───┴───┨┃IP │中断优先级寄存器┃┃/ │保留┃┃PS │串行通信中断优先级0，低优先级；1，高优先级┃┃PT1 │T1中断优先级0，低优先级；1，高优先级┃┃PX1 │/INT1优先级0，低优先级；1，高优先级┃┗━━━┷━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━┛-------------------------------------------------------------------------8051内部控制寄存器只有6个：┏━━━┯━━━━━━━┯━━━━━━━━━━━┓┃1. │IE,IP │寄存器用于中断控制┃┃2. │TMOD,TCON │寄存器计时/计数器用┃┃3. │SCON │寄存器串行口传输控制┃┃4. │PCON │寄存器省电模式操作┃┗━━━┷━━━━━━━┷━━━━━━━━━━━┛-------------------------------------------------------------------------IE中断允许控制寄存器（可位寻址）┏━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┓┃B7 │B6 │B5 │B4 │B3 │B2 │B1 │B0 ┃┠───┼───┼───┼───┼───┼───┼───┼───┨┃EA │- │ET2 │ES │ET1 │EX1 │ET0 │EX0 ┃┗━━━┷━━━┷━━━┷━━━┷━━━┷━━━┷━━━┷━━━┛EA(IE.7): 当EA=0时停止所有的中断位（禁止中断）当EA=1时各个中断的产生由个别允许位来决定IE.6: 保留位ET2(IE.5): 允许计时器2的中断（8052使用)ES(IE.4): 允许串行口的中断ET1(IE.3): 允许计时器1的中断EX1(IE.2): 允许外部中断1的中断ET0(IE.1): 允许计时器0的中断EX0(IE.0): 允许外部中断0的中断-------------------------------------------------------------------------IP中断优先次序寄存器（可位寻址）┏━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┓┃B7 │B6 │B5 │B4 │B3 │B2 │B1 │B0 ┃┠───┼───┼───┼───┼───┼───┼───┼───┨┃- │- │PT2 │PS │PT1 │PX1 │PT0 │PX0 ┃┗━━━┷━━━┷━━━┷━━━┷━━━┷━━━┷━━━┷━━━┛PT2(IP.5): 设定计时器2的优先次序（8052使用）PS(IP.4): 设定串行口的优先次序PT1(IP.3): 设定计时器1的优先次序PX1(IP.2): 设定外部中断1的优先次序PT0(IP.1): 设定计时器0的优先次序PX0(IP.0): 设定外部中断0的优先次序-------------------------------------------------------------------------TMOD计时器模式控制寄存器（不可位寻址）┏━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┯━━━┓┃B7 │B6 │B5 │B4 │B3 │B2 │B1 │B0 ┃┠───┼───┼───┼───┼───┼───┼───┼───┨┃GATE │C/T │M1 │M0 │GATE │C/T │M1 │M0 ┃┗━━━┷━━━┷━━━┷━━━┷━━━┷━━━┷━━━┷━━━┛GATE: 计时器工作门控制，当GATE=1时，INT0与INT1引脚为高电位，同时TCON中的TR0或TR1控制位1时，计时/计数器0或1才会工作。

8051单片机的基本结构及工作原理 _2013

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2FH
7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F
7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06
7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05
TH0 TL0

◦ MOV 8CH,#01H ;为TH0赋值 ◦ MOV 8AH,#20H ；为TL0赋值

串行数据缓冲器SBUF：它是专门用来存放发送或接收的数据，实际上它是两个独立的寄存器。尽管在SFR中的 RAM地址只是99H,但根据指令“发送”或“接收”两种不同的操作,有两个独立的缓存存在，硬件会自动的区分, 将数据送如对应的缓冲单元。 MOV SBUF，A ；A→SBUF （引发串口通信）
78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
字节地址
20H
07
返回上一次

位寻址区内的地址是位地址。共有00-7FH（共128个位）；要区分字节地址和位地址这两个不同的地址概念： MOV A， 20H ；将RAM的20单元内容送累加器A； MOV C ，20H ；将RAM位寻址区中20H位送CY中。
7FH
SP
60H
61H 60H
08H 07H
改变堆栈位置示意图
注意：FILO（ First In Last Out）

并行端口P0-P3：80H、90H、A0H、B0H。
如:
MOV 80H,A ；将累加器中的数据送到P0口输出 MOV A,90H ；将P1口的数据输入到累加器A中

8051_芯片手册

8051芯片手册目录1 NL06F86 芯片概述 (1)1.1结构框图 (1)1.2NL06F86 性能 (1)1.3外设连接示意图 (4)1.4管脚定义 (5)1.5NL06F86 最小系统 (18)1.6部分管脚的配臵电路 (18)2 内存映射 (20)3 CPU内核 (23)3.1概述 (23)3.2CPU编程模型 (24)3.3处理器寻址方式 (28)3.4CPU指令集 (32)3.5MMU和Cache (48)4 外设功能 (61)4.1 功能综述 (61)4.2 所有寄存器列表 (62)4.3 外设使用说明 (71)4.4 编程实例 (71)5 程序起动描述 (73)6 存储器控制器 (74)6.2 寄存器表 (74)6.3 寄存器功能描述 (74)6.4 模块管脚描述 (76)6.5 典型电路 (80)6.6 编程实例 (81)7 中断控制器 (83)7.1 功能综述 (83)7.2 寄存器表 (84)7.3 寄存器功能描述 (84)7.4 编程实例 (86)8 定时器 (88)8.1 功能综述 (88)8.2 寄存器表 (88)8.3 寄存器功能描述 (89)8.4 编程实例 (90)9 通用I/O (91)9.1 功能综述 (91)9.2 寄存器表 (91)9.3 寄存器功能描述 (93)9.4 编程实例 (96)10 HW控制器 (98)10.1 功能综述 (98)10.2 寄存器表 (98)10.4 编程实例 (99)11 以太网MAC控制器 (100)11.1 功能综述 (100)11.2 寄存器表 (100)11.3 寄存器功能描述 (101)11.4 模块管脚描述 (106)11.5 典型电路 (107)11.6 编程实例 (107)12 通用异步收发器UARTs (112)12.1 功能综述 (112)12.2 UART寄存器表 (112)12.3 寄存器功能描述 (113)12.4 模块管脚描述 (117)12.5 编程实例 (118)13 I2C总线接口 (122)13.1 功能综述 (122)13.2 寄存器表 (122)13.3 寄存器功能描述 (122)13.4 时序波形图 (123)13.5 模块管脚描述 (125)13.6 典型电路 (125)13.7 编程实例 (126)14 低速外设接口 (128)14.2 寄存器表 (128)14.3 寄存器功能描述 (128)14.4 模块管脚描述 (130)14.5 典型电路 (131)14.6 编程实例 (132)15 显示接口 (134)15.1 功能总述 (134)15.2 寄存器表 (134)15.3 寄存器功能描述 (136)15.4 模块管脚描述 (143)15.5 典型电路 (144)15.6 编程实例 (145)16 磁卡接口 (149)16.1 功能综述 (149)16.2 寄存器表 (149)16.3 寄存器功能描述 (149)16.4 模块管脚描述 (151)16.5 编程实例 (151)17 IC卡接口 (153)17.1 功能综述 (153)17.2 寄存器表 (153)17.3 寄存器功能描述 (154)17.4 模块管脚描述 (156)17.6 编程实例 (157)18 打印机接口 (159)18.1 功能综述 (159)18.2 寄存器表 (159)18.3 寄存器功能描述 (159)18.4 模块管脚描述 (161)18.5 典型电路 (162)18.6 编程实例 (162)19 PC键盘接口 (164)19.1 功能综述 (164)19.2 寄存器表 (164)19.3 寄存器功能描述 (164)19.4 模块管脚描述 (165)19.5 数据格式和时序图 (166)19.6 典型电路 (166)19.7 编程实例 (167)20 PWM接口 (169)20.1 功能综述 (169)20.2 寄存器表 (169)20.3 寄存器功能描述 (170)20.4 模块管脚描述 (171)20.5 典型电路 (171)20.6 编程实例 (172)21 蜂鸣器 (173)21.1 功能综述 (173)21.2 寄存器表 (173)21.3 寄存器功能描述 (173)21.4 模块管脚描述 (174)21.5 典型电路 (174)21.6 编程实例 (175)22 DES控制器 (176)22.1 功能综述 (176)22.2 寄存器表 (176)22.3 寄存器功能描述 (176)22.4 编程实例 (177)23 封装尺寸 (179)1. 8051 芯片概述8051微控制器属于MCS-51系列，自其1980年由Inter公司设计以来，由于其完善的指令集，在嵌入式系统应用中占有很大的市场。

8051单片机

Pm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3FEATURES• Single Power Supply Operation - Low voltage range: 2.7 V - 3.6 V• Memory Organization- Pm25LD010C: 128K x 8 (1 Mbit) - Pm25LD020C: 256K x 8 (2 Mbit)• Cost Effective Sector/Block Architecture - 1Mb : Uniform 4KByte sectors / Four uniform32KByte blocks- 2Mb : Uniform 4KByte sectors / Four uniform64KByte blocks• Low standby current 1uA (Typ)• Serial Peripheral Interface (SPI) Compatible - Supports single- or dual-output - Supports SPI Modes 0 and 3- Maximum 33 MHz clock rate for normal read - Maximum 100 MHz clock rate for fast read• Page Program (up to 256 Bytes) Operation - Typical 2 ms per page program• Sector, Block or Chip Erase Operation - Maximum 10ms sector, block or chip erase• Low Power Consumption- Typical 10 mA active read current - Typical 15 mA program/erase current• Hardware Write Protection- Protect and unprotect the device from write operation by Write Protect (WP#) Pin• Software Write Protection- The Block Protect (BP2, BP1, BP0) bits allow partial or entire memory to be configured as read-only• High Product Endurance- Guaranteed 200,000 program/erase cycles per single sector- Minimum 20 years data retention• Industrial Standard Pin-out and Package - 8-pin 150mil SOIC- 8-pin 208mil SOIC for Pm25LD040 - 8-pin 300mil PDIP for Pm25LD040 - 8-contact WSON - 8-pin TSSOP- Lead-free (Pb-free), halogen-free packageGENERAL DESCRIPTIONThe Pm25LD010C/020C are 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging from 2.7 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers.The Pm25LD010C/020C are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with allrecognized command codes and operations. The dual-output fast read operation provides and effective serial data rate of 200MHz.The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte blocks.(Pm25LD020C is uniform 4 KByte sectors or uniform 64 KByte).The Pm25LD010C/020C are manufactured on pFLASH™’s advanced non-volatile technology. The devices are offered in 8-pin SOIC 150mil, 8-contact WSON and 8-pin TSSOP. The devices operate at wide temperatures between -40°C to +105°C.1 Mbit /2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface Output SPI Bus InterfacePm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3PRODUCT ORDERING INFORMATIONPm25LDxxxC - S C EEnvironmental AttributeE = Lead-free (Pb-free) and Halogen- free packageTemperature RangeC = Commercial Grade (-40°C to +105°C)Package TypeS = 8-pin SOIC 150mil (8S) B = 8-pin SOIC 208mil (8B) P = 8-pin PDIP 300 mil (8P) K = 8-contact WSON (8K)pFlash Device Number Pm25LD010C/020CPart Number Operating Frequency (MHz) PackageTemperature RangePm25LD010C-SCE Pm25LD020C-SCE 1008S150mil SOICPm25LD010C-KCE Pm25LD020C-KCE 1008K WSON (Back Side Metal) Pm25LD010C-DCE Pm25LD020C-DCE1008-pin TSSOPCommercial Grade (-40o C to +105o C)Pm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3CONNECTION DIAGRAMSHOLD#SCK SIOSO GNDWP#CE#Vcc HOLD#SCK SIOSO GNDWP#CE#PIN DESCRIPTIONSSYMBOL TYPE DESCRIPTIONCE#INPUT Chip Enable: CE# low activates the devices internal circuitries for device operation. CE# high deselects the devices and switches intostandby mode to reduce the power consumption. When a device is not selected, data will not be accepted via the serial input pin (SlO), and the serial output pin (SO) will remain in a high impedance state.SCK INPUT Serial Data ClockSIO INPUT/OUTPUTSerial Data Input/Output SO OUTPUT Serial Data Output GND Ground Vcc Device Power Supply WP#INPUT Write Protect: A hardware program/erase protection for all or part of amemory array. When the WP# pin is low, memory array write-protection depends on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is high, the devices are not write-protected.HOLD#INPUT Hold: Pause serial communication by the master device without resettingthe serial sequence.CE# SOHOLD#SCKSIOSIOVcc 8-Pin SOIC8-Contact WSON8-Pin TSSOP8-Pin PDIPPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3BLOCK DIAGRAMSIOPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3SPI MODES DESCRIPTIONMultiple Pm25LD010C/020C devices can beconnected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 1. The devices support either of two SPI modes:Mode 0 (0, 0) Mode 3 (1, 1)The difference between these two modes is the clock polarity when the SPI master is in Stand-by mode: the serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure 2. For both modes, the input data is latched on the rising edge of Serial Clock (SCK), and the output data is available from the falling edge of SCK.Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)Figure 2. SPI Modes SupportedMSbMSbSCKSCKSOSIOInput mode Mode 0 (0, 0) Mode 3 (1, 1)Pm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3SYSTEM CONFIGURATIONThe Pm25LD010C/020C devices are designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers. The devices have two superset features that can be enabled through specific software instructions and the Configuration Register:Table 1-1. Block/Sector Addresses of Pm25LD010C/020CMemory DensityBlock No.Block Size (KBytes) Sector No. SectorSize (KBytes)Address Range Sector 0 4 000000h - 000FFFh Sector 14 001000h - 001FFFh: : :Block 064Sector 15 4 00F000h - 00FFFFh Sector 16 4 010000h - 010FFFh Sector 174 011000h - 011FFFh: : :Block 1 64 Sector 314 01F000h - 01FFFFh: : : : :2 MbitBlock 364:4030000h – 03FFFFhPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3REGISTERS (CONTINUED)STATUS REGISTERRefer to Tables 5 and 6 for Status Register Format and Status Register Bit Definitions.The BP0, BP1, BP2, and SRWD are volatile memory cells that can be written by a Write Status Register(WRSR) instruction. The default value of the BP2, BP1, BP0 were set to “0” and SRWD bits was set to “0” at factory. Once a “0” or “1”is written, it will not bechanged by device power-up or power-down, and can only be altered by the next WRSR instruction. The Status Register can be read by the Read StatusRegister (RDSR). Refer to Table 10 for Instruction Set.The function of Status Register bits are described as follows:WIP bit : The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a program or erase operation. When the WIP bit is “0”, the device is ready for a write status register, program or erase operation. When the WIP bit is “1”, the device is busy.WEL bit : The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the WEL is “0”, the write enable latch is disabled, and all write operations, including write status register, page program, sector erase, block and chip erase operations are inhibited. When the WEL bit is “1”, write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each write register, program and erase instruction must be preceded by a WREN instruction. The WEL bit can be reset by a WriteDisable (WRDI) instruction. It will automatically be the reset after the completion of a write instruction.BP2, BP1, BP0 bits : The Block Protection (BP2, BP1, BP0) bits are used to define the portion of the memory area to be protected. Refer to Tables 7, 8 and 9 for the Block Write Protection bit settings. When a defined combination of BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any program or erase operation to that area will be inhibited. Note: a Chip Erase (CHIP_ER) instruction is executedsuccessfully only if all the Block Protection Bits are set as “0”s.SRWD bit : The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#) signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not write-protected. When the SRWD is set to “1” and the WP# is pulled low (V IL ), the volatile bits of Status Register (SRWD, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to “1” and WP# is pulled high (V IH ), the Status Register can be changed by a WRSR instruction.Table 5. Status Register FormatBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRWD1ReservedBP2BP1 BP0 WEL WIP Default (flash bit) 0 0Pm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3REGISTERS (CONTINUED)Table 6. Status Register Bit Definition BitNameDefinitionRead- /Write Non-Volatile bit Bit 0 WIP Write In Progress Bit:"0" indicates the device is ready"1" indicates a write cycle is in progress and the device is busy R No Bit 1WEL Write Enable Latch:"0" indicates the device is not write enabled"1" indicates the device is write enabled (default)R/W No Bit 2 BP0 Bit 3 BP1 Bit 4 BP2 Block Protection Bit: (See Table 7 and Table 8 for details) "0" indicates the specific blocks are not write-protected (default) "1" indicates the specific blocks are write-protected R/W Yes Bits 5 - 6 N/A Reserved: Always "0"sN/A Bit 7 SRWD Status Register Write Disable: (See Table 9 for details)"0" indicates the Status Register is not write-protected (default)"1" indicates the Status Register is write-protectedR/WYesTable 8. Block Write Protect Bits for Pm25LD010C/020CPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3REGISTERS (CONTINUED)PROTECTION MODEThe Pm25LD010C/020C have two types of write-protection mechanisms: hardware and software. These are used to prevent irrelevant operation in a possibly noisy environment and protect the data integrity.HARDWARE WRITE-PROTECTIONThe devices provide two hardware write-protection features:a. When inputting a program, erase or write status register instruction, the number of clock pulse ischecked to determine whether it is a multiple of eight before the executing. Any incomplete instruction command sequence will be ignored.b. The Write Protection (WP#) pin provides ahardware write protection method for BP2, BP1, BP0 and SRWD in the Status Register. Refer to the STATUS REGISTER description.c. Write inhibit is 2.1V, all write sequence will beignored when Vcc drop to 2.1V and lowerSOFTWARE WRITE PROTECTIONThe Pm25LD010C/020C also provides two software write protection features:a. Before the execution of any program, erase or write status register instruction, the Write Enable Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled first, the program, erase or write register instruction will be ignored.b. The Block Protection (BP2, BP1, BP0) bits allow part or the whole memory area to be write-protected. Table 9. Hardware Write Protection on Status RegisterSRWD WP#Status Register 0Low Writable 1 Low Protected 0 High Writable 1HighWritablePm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3DEVICE OPERATIONThe Pm25LD010C/020C utilize an 8-bit instructionregister. Refer to Table 10 Instruction Set for details of the Instructions and Instruction Codes. All instructions, addresses, and data are shifted in with the mostsignificant bit (MSB) first on Serial Data Input (SI). The input data on SI is latched on the rising edge of Serial Clock (SCK) after Chip Enable (CE#) is driven low (V IL ). Every instruction sequence starts with a one-byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes,depending on the type of instruction. CE# must bedriven high (V IH ) after the last bit of the instruction sequence has been shifted in.The timing for each instruction is illustrated in the following operational descriptions.Table 10. Instruction SetInstruction NameHexCodeOperationCommand Cycle Maximum FrequencyRDIDABh Read Manufacturer and Product ID4 Bytes 100 MHz JEDEC ID READ 9Fh Read Manufacturer and Product ID by JEDEC ID Command1 Byte 100 MHz RDMDID 90h Read Manufacturer and Device ID 4 Bytes 100 MHz WREN 06h Write Enable 1 Byte 100 MHz WRDI 04h Write Disable1 Byte 100 MHz RDSR 05h Read Status Register 1 Byte 100 MHz WRSR 01h Write Status Register2 Bytes 100 MHz READ03h Read Data Bytes from Memory at Normal Read Mode 4 Bytes 33 MHz FAST_READ 0Bh Read Data Bytes from Memory at Fast Read Mode 5 Bytes 100 MHz FRDO3Bh Fast Read Dual Output5 Bytes 100 MHz PAGE_ PROG 02h Page Program Data Bytes Into Memory 4 Bytes + 256B 100 MHz SECTOR_ER D7h/20h Sector Erase 4 Bytes 100 MHz BLOCK_ER D8h Block Erase 4 Bytes 100 MHz CHIP_ERC7h/60hChip Erase1 Byte100 MHzHOLD OPERATIONHOLD# is used in conjunction with CE# to select the Pm25LD010C/020C. When the devices are selected and a serial sequence is underway, HOLD# can be used to pause the serialcommunication with the master device withoutresetting the serial sequence. To pause, HOLD# isbrought low while the SCK signal is low. To resume serial communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to SlO will be ignored while SO is in the high impedance state.Pm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3DEVICE OPERATION (CONTINUED)RDID COMMAND (READ PRODUCT IDENTIFICATION) OPERATIONThe Read Product Identification (RDID) instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not same as RDID or JEDEC ID instruction. It’s not recommended to use for newdesign. For new design, please use RDID or JEDEC ID instruction.The RDES instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising edge of SCK. Then the Device ID is shifted out on SO with the MSB first, each bit been shifted out during the falling edge of SCK. The RDES instruction is ended byCE# goes high. The Device ID outputs repeatedly if continuously send the additional clock cycles on SCK while CE# is at low.Table 11. Product IdentificationProduct Identification Data First Byte 9Dh Manufacturer ID Second Byte 7Fh Device ID:Device ID 1Device ID 2Pm25LD010C 10h21hPm25LD020C 11h22hFigure 3. Read Product Identification SequenceSCKCE#SI SOPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3DEVICE OPERATION (CONTINUED)JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID) OPERATIONThe JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to Table 11 Product Identification for pFlash Manufacturer ID and Device ID. After the JEDEC ID READ command is input, the second Manufacturer ID (7Fh) is shifted out on SO with the MSB first, followed by the first Manufacturer ID (9Dh) and the Device ID (22h, in the case of the Pm25LD020C), each bit shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID is shifted out, the Manufacturer ID and Device ID will loop until CE# is pulled high.Figure 4. Read Product Identification by JEDEC ID READ SequenceSCKCE#SISOPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3DEVICE OPERATION (CONTINUED)RDMDID COMMAND (READ DEVICE MANUFACTURER AND DEVICE ID) OPERATIONThe RDMDID instruction allows the user to read the manufacturer and product ID of devices. Refer to Table 11 Product Identification for pFlash Manufacturer ID and Device ID. The RDMDID command is input, followed by a 24-bit address pointing to an ID table. The table contains the first Manufacturer ID (9Dh) andthe Device ID (22h, in the case of the Pm25LD020C), and is shifted out on SO with the MSB first, each bit shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID is shifted out, the Manufacturer ID and Device ID will loop until CE# is pulled high.Figure 5. Read Product Identification by RDMDID READ SequencePm25LD010C/ 020CChingis Technology Corp. DRAFT Date: November, 2009, Rev: 0.3Pm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3DEVICE OPERATION (CONTINUED)WRITE ENABLE OPERATIONThe Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit of the Pm25LD010C/020C is reset to the write –protected state after power-up. The WEL bit must be writeenabled before any write operation, including sector, block erase, chip erase, page program and write status register operations. The WEL bit will be reset to the write-protect state automatically upon completion of a write operation. The WREN instruction is required before any above operation is executed.Figure 6. Write Enable SequenceWRDI COMMAND (WRITE DISABLE) OPERATIONThe Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI instruction is not required after the execution of a write instruction, since the WEL bit is automatically reset.Figure 7. Write Disable SequenceSIOSIOPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3DEVICE OPERATION (CONTINUED)RDSR COMMAND (READ STATUS REGISTER) OPERATIONThe Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a program, erase or write status register operation, all other instructions will be ignored except the RDSR instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of Status Register.Figure 8. Read Status Register SequenceWRSR COMMAND (WRITE STATUS REGISTER) OPERATIONThe Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and status register write protection features by writing “0”s or “1” s into the volatile BP2, BP1, BP0 and SRWD bits.Figure 9. Write Status Register SequenceSIOSIOPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3READ COMMAND (READ DATA) OPERATIONThe Read Data (READ) instruction is used to read memory data of a Pm25LD010C/020C under normal mode running up to 33 MHz.The READ instruction code is transmitted via the SlO line, followed by three address bytes (A23 - A0) of the first memory location to be read. A total of 24 address bits are shifted in, but only A MS (most significantaddress) - A0 are decoded. The remaining bits (A23 – A MS ) are ignored. The first byte addressed can be at any memory location. Upon completion, any data on the Sl will be ignored. Refer to Table 12 for the related Address Key.The first byte data (D7 - D0) addressed is then shifted out on the SO line, MSb first. A single byte of data, or up to the whole memory array, can be read out in one READ instruction. The address is automaticallyincremented after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (V IH ) after the data comes out. When the highest address of the devices is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read in one continuous READ instruction.Table 12. Address KeyAddress Pm25LD020CPm25LD010C A N (A MS – A 0) A17 - A0 A16 - A0 Don't Care BitsA23 – A18A23 – A17Figure 12. Read Data SequenceSIOPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3DEVICE OPERATION (CONTINUED)FAST_READ COMMAND (FAST READ DATA) OPERATIONThe FAST_READ instruction is used to read memory data at up to a 100 MHz clock. The FAST_READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO line, with each bit shifted out at a maximum frequency f CT , during the falling edge of SCK. The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FAST_READ instruction. The FAST_READ instruction is terminated by driving CE# high (V IH ).Figure 13. Fast Read Data SequenceSIOSIOPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3DEVICE OPERATION (CONTINUED)FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATIONThe FRDO instruction is used to read memory data on two output pins each at up to a 100 MHz clock. The FRDO instruction code is followed by threeaddress bytes (A23 - A0) and a dummy byte (8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO and SIO lines, with each pair of bits shifted out at a maximum frequency f CT , during the falling edge of SCK. The first bit (MSb) is output on SO, while simultaneously the second bit is output on SIO.The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FRDO instruction. FRDO instruction is terminated by driving CE# high (V IH).Figure 14. Fast Read Dual-Output Sequence123456789101128293031...INSTRUCTION = 0011 1011b (23)22213213 - BYTE ADDRESSCE#SCKSIOSO HIGH IMPEDANCE3233343536373839404142434445464748765432107654321076CE#SCKSIOSOHIGH IMPEDANCEDATA OUT 1DATA OUT 2Pm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3DEVICE OPERATION (CONTINUED)PAGE_PROG COMMAND (PAGE PROGRAM) OPERATIONThe Page Program (PAGE_PROG) instruction allows up to 256 bytes data to be programmed into memory in a single operation. The destination of the memory to be programmed must be outside the protected memoryarea set by the Block Protection (BP2, BP1, BP0) bits. A PAGE_PROG instruction which attempts to program into a page that is write-protected will be ignored.Before the execution of PAGE_PROG instruction, the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.The PAGE_PROG instruction code, three addressbytes and program data (1 to 256 bytes) are input via the SlO line. Program operation will start immediately after the CE# is brought high, otherwise thePAGE_PROG instruction will not be executed. Theinternal control logic automatically handles the programming voltages and timing. During a program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of theprogram operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation hascompleted.If more than 256 bytes data are sent to a device, theaddress counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The starting byte can be anywhere within the page.When the end of the page is reached, the address will wrap around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other bytes on the same page will remainunchanged. Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s. A byte cannot be reprogrammed without firsterasing the whole sector or block.Figure 15. Page Program SequenceSIOPm25LD010C/ 020CChingis Technology Corp.DRAFT Date: November, 2009, Rev: 0.3DEVICE OPERATION (CONTINUED)ERASE OPERATIONThe memory array of the Pm25LD010C is organized into uniform 4 KByte sectors or 32 KByte uniform blocks (a block consists of eight adjacent sectors). Pm25LD020C is organized into uniform 4 KBytesectors or 64 KByte uniform blocks (a block consists of sixteen adjacent sectors)Before a byte can be reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to “1”). In order to erase the devices, there are three erase instructions available: Sector Erase(SECTOR_ER), Block Erase (BLOCK_ER) and Chip Erase (CHIP_ER). A sector erase operation allows any individual sector to be erased without affecting the data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the whole memory array of a device. A sector erase, block erase or chip erase operation can be executed prior to any programming operation.SECTOR_ER COMMAND (SECTOR ERASE) OPERATIONA SECTOR_ER instruction erases a 4 KByte sector Before the execution of a SECTOR_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is reset automatically after the completion of sector an erase operation.A SECTOR_ER instruction is entered, after CE# ispulled low to select the device and stays low during the entire instruction sequence The SECTOR_ERinstruction code, and three address bytes are input via SI. Erase operation will start immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 14 for Sector Erase Sequence.During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction. The progress or completion of the erase operation can be determined by reading the WIP bit in the Status Register using a RDSR instruction. If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been completed.BLOCK_ER COMMAND (BLOCK ERASE) OPERATIONA Block Erase (BLOCK_ER) instruction erases a 64 KByte block of the Pm25LD010C/020C. Before the execution of a BLOCK_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the completion of a block erase operation.The BLOCK_ER instruction code and three address bytes are input via SI. Erase operation will startimmediately after the CE# is pulled high, otherwise the BLOCK_ER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 15 for Block Erase Sequence.CHIP_ER COMMAND (CHIP ERASE) OPERATIONA Chip Erase (CHIP_ER) instruction erases the entire memory array of a Pm25LD010C/020C. Before the execution of CHIP_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after completion of a chip erase operation.The CHIP_ER instruction code is input via the SI. Erase operation will start immediately after CE# ispulled high, otherwise the CHIP_ER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 16 for Chip Erase Sequence.。

8051单片机内部结构和功能基本概念

2021/6/7
与T2相关的6个SFR 没有列出
FFH 00H
用户RAM区（堆栈、数据缓冲）
（30H-FFH）
位寻址区（位地址00H-7FH）
（20H-2FH）
第3组通用寄存器（18H-1FH）
第2组通用寄存器（10H-17H）
第1组通用寄存器（08H-0FH）
第0组通用寄存器（00H-07H）
有四个物理上相互独立的存储空间，其配置如图2-6所示：
片外ROM
片内RAM
片外RAM/I/O口
128B SFR
256B
8KB 片202内1/6/R7 OM
说明
❖ 用户使用的角度上看，存储空间分为三类：片内外统一编址的64K字节的ROM； 256字节片内RAM； 64K字节片外RAM或I/O口地址空间
2021/6/7
用于存放用户数据和做堆栈用
可以直接对位进行寻址（共16 个单元，128个位）
用于存放操作数及中间结果。由于它们的功能预先不作规定，因此称为通用寄存器，也叫工作寄存器。任一时刻，CPU只能使用一组工作寄存器。（由PSW的RS0 和RS1决定）
内部RAM 的三个区域
(1) 工作寄存器（00H～1FH)
程序存储器用来存放程序和常数，分为片内和片外两部分，其中8051内部有4kB的ROM，地址范围是 0000H-0FFFH，片外用16位地址线扩充64kB的 ROM，两者统一编址。（从片内还是从片外取指取决于EA引脚。）
特殊单元： 0000H-0002H（开机复位单元） 3个 0003H-000AH（INT0中断地址区） 8个 000BH-0012H（T/C0中断地址区） 8个 0013H-001AH（INT1中断地址区） 8个 001BH-0022H（T/C0中断地址区） 8个 0023H-002AH（串行口中断地址区） 8个

8051课件

广州周立功单片机发展有限公司Tel：(020)38730976 38730977 Fax：38730925 目录第1章8051体系结构 (1)1.1 8051单片机概述 (1)1.1.1 嵌入式系统与单片机 (1)1.1.2 8051单片机及发展历史 (1)1.1.3 8051封装和管脚功能 (2)1.1.4 8051最小系统电路 (4)1.2 8051的并行扩展 (6)1.2.1 并行总线 (6)1.2.2 外部程序存储器扩展 (8)1.2.3 外部数据存储器扩展 (8)1.2.4 地址译码 (9)1.2.5 并行扩展I/O (9)1.3 8051的内部结构 (10)1.3.1 存储器组织 (10)1.3.2 8051处理器 (14)1.3.3 片内外设资源 (17)1.4 8051的指令集 (17)1.4.1 寻址模式 (18)1.4.2 指令集 (20)i 广州周立功单片机发展有限公司Tel：(020)38730976 38730977 Fax：38730925 第1章8051体系结构1.1 8051单片机概述1.1.1 嵌入式系统与单片机国内普遍认同的嵌入式系统（Embedded System）定义为：以应用为中心，以计算机技术为基础，软硬件可裁剪，适应应用系统对功能、可靠性、成本、体积、功耗等严格要求的专用计算机系统。

可以这样认为，嵌入式系统是一种专用的计算机系统，作为装置或设备的一部分。

通常，嵌入式系统是一个控制程序存储在ROM中的嵌入式处理器控制板。

在嵌入式系统里硬件和软件是高度融合在一起的。

单片机，即微控制器（Microcontroller），是指集成在一颗芯片上以嵌入式应用为目的的完整计算机系统。

单片机属于嵌入式处理器的一大类（另外还有DSP、FPGA等）。

在历史上，有一种被称作单板机的嵌入式系统，在同一块电路板上集成CPU（中央处理器）、ROM（只读的程序存储器）、RAM（随机访问的数据存储器）、时钟及各类外部设备。

8051单片机_课件_概述

……
3）十六进制数：有0~ 9 ，A,B,C,D,E,F 共十六个不同的符号。逢十六进位。用下脚标 “H” 表示十六进制数。例：327 H = 3×162+2×161+7×160 = 807D 3AB . 11H = 3×162+A×161+B×160+1×161+1×16-2 =939 . 0664 D
方法2：加法 X-Y = [ [ X-Y]补]补 = [ [X]补+[-Y]补]补 =[ [52]补+[ -38]补]补 =[ 14 ]补 =14 [52]补： 00110100
ቤተ መጻሕፍቲ ባይዱ
[-38]补：+） 1 1 0 1 1 0 1 0
100001110
自然丢失计算机在做算术运算时，必需检查溢出，以防止发生错误
3、数的符号表示
机器数与真值
机器只认识二进制数：0、1，这是因为电路状态只有两种情况如：电路的通、断；高电平、低电平；可用0、1表示。在机器中，这种0、1、0、1的表现形式称为机器数。机器数分为无符号数、带符号数。
无符号数如：00000001、10010011、01010010、 …… 等等，范围：00H ~ FFH。
（4）补码的运算当X≥0时，[X]补= [X]反=[X]原 [ [X]补]补 = [X]原 [X]补+ [Y]补 = [ X+Y ]补 [ X-Y ]补= [ X+（-Y）]补
例：已知 X=52 Y=38 求X-Y
方法1：减法： X-Y = 52-38 =14 00110100 -） 0 0 1 0 0 1 1 0 00001110
00011000
+）0 0 0 0 0 0 1 1 00011011 结果的低四位是非BCD码（错）

例说8051第1章轻松看8051

例说８０５１
1-18
MCS-51系列
• 无ROM型 • Mask ROM型
2019/12/4
例说８０５１
1-19
MCS-51系列
• EPROM型 • EEPROM型
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例说８０５１
1-20
8051系统的开发流程
开始
硬件设计
设计电路制作目标板
软件设计编辑源程序编写、汇编、连接调试 /仿真
例说８０５１
1-17
MCS-51系列
51类
52类
型号
8031
8051
8751
89C51
8032
8052
8752
89C52
形式
无ROM
Mask ROM
EP ROM
EEP ROM
无ROM
Mask ROM
EP ROM
EEP ROM
ROM
RAM
定时器/ 计数器
内部0K 外部64K
内部4K Bytes 外部最大64K Bytes
2019/12/4
例说８０５１
1-2
微型计算机与单片机
• 微型计算机系统包括中央处理单元(CPU)、存储器(Memory)及输入/输出单元(I/O)三大部分。
• 单片微型计算机就是把中央处理单元、存储器、输入/输出端口等，全部放置在一块芯片里。
2019/12/4
例说８０５１
1-3
8051基本知识
Kbytes。 • 四个可位寻址的8位输入/输出口，即P0、P1、P2及P3。 • 两个16位定时器/计数器。 • 一个全双工串行口，即UART。 • 五个中断源，即INT0、INT1、T0、T1、RXD或TXD。 • 111条指令。

8051简介

80518051通道0驱动器通道2驱动器ram地址ram通道0锁romepromb寄存器程序地址寄存器缓冲器pc递增器程序计数器pc数据指针dptrccgnd17堆栈指针spacctmppsw通道3锁存器通道1锁存器通道1驱动器通道3驱动器tmpscontmodpcontcontl0th1th0tl1iesbuftxrxip中断串行口和定时器逻辑振荡器37rstalepsenxtalalu5v控制逻辑cpu即中央处理器是单片机的核心部件它完成各种运算和控制操作cpu由运算器和控制器两部分组成
8051单片机基本结构
8051单片机的特点
8051单片机可分为无ROM型和ROM型两种无ROM型的芯片，为8031） ROM型芯片又分为EPROM型（典型芯片为 8751）、FLASH型（典型芯片为89C51）、掩膜ROM型（典型芯片为8051 ）、一次性可编程ROM（One Time Programming,简称OTP）的芯片（典型芯片为97C51）。
（2）控制器
控制器包括程序计数器PC、指令寄存器、指令译码器、数据指针DPTR、堆栈指针SP、缓冲器以及定时与控制电路等。控制电路完成指挥控制工作，协调单片机各部分正常工作。程序计数器PC：当一条指令按PC所指向的地址从程序存储器中取出之后，PC的值会自动增量，即指向下一条指令。堆栈指针SP：用来指示堆栈的起始地址。80C51单片机的堆栈位于片内RAM中，而且属于“上长型”堆栈，复位后SP被初始化为07H，使得堆栈实际上由08H单元开始。指令译码器：当指令送入指令译码器后，由译码器对该指令进行译码，CPU根据译码器输出的电平信号使定时控制电路产生执行该指令所需要的各种控制信号。数据指针寄存器DRTR：它是一个16位寄存器，由高位字节DPH 和低位字节DPL组成，用来存放16位数据存储器的地址，以便对片外64kB的数据RAM区进行读写操作。

8051封装与引脚PPT课件

EA ALE PSEN
上电时：RST上的高电平必须保持10ms以上才能保证有效复位，由于振荡器需要一定的起振时间。
7
单片机的引脚及功能
P1. 0 1
40
P1.1 2
39
P1.2 3
38
P1.3 4
37
P1.4 5 8031 36
P1.5 6 8051 35
P1.6 7
34
P1.7 8 8751 33
（二）8051封装与引脚
两种封装形式：40个引脚， HMOS工艺制造的芯片采用双列直插式封装（DIP）。
P0.3(AD3) P0.2(AD2) P0.1(AD1)
P0.0(AD0) 43
VCC 44
P1.0 1 P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1.6 7 P1.7 8 RES 9
2021/3/10
25
P3口各位的第二功能
2021/3/10
26
共同的心声
一起帮助孩子更好学习，一起帮助孩子健康成长。
RXD 10
TXD 11 IT0 12 IT1 13 T0 14
T1 15 WR 16 RD 17
X2 18
X1 19 VSS 20
P10 P11 P12 P13 P14 P15 P16 P17 RESET P30 P31 P32 P33 P34 P35 P36 P37
X2 X1 VSS
VDD P00
当该引脚接高电平时，CPU访问片内EPROM/ROM并执行片内程序存储器中的指令，但当PC值超过 EA 0FFFH（片内ROM为4KB）时，将自动转向执行片外ROM中的程序。
当该引脚接低电平时，CPU只访问片外EPROM/ROM并执行外部程序存储器中的程序。

DP80390CPU_03中文资料

DP80390CPU is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.
CPU FEATURES
♦ Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet
♦ Synthesis scripts ♦ Example application ♦ Technical support
◊ IP Core implementation support ◊ 3 months maintenance
元器件交易网
DP80390CPU
Pipelined High Performance 8-bit Microcontroller ver 3.10
OVERVIEW
DP80390CPU is an ultra high performance, speed optimized soft core of a singlechip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU.

8051 基本引脚

8051 基本资料如下：□8051 主要特性□8051 引脚说明□8051 中断服务常式的进入点□8051 特殊目的寄存器□8051 内部控制寄存器at89c51 为ATMEL 所生产的可电气烧录清洗的8051 相容单芯片，其内部程序代码容量为4KB8051主要功能列举如下：□ 为一般控制应用的8 位单芯片□ 晶片内部具时钟振荡器（传统最高工作频率可至12MHz）□ 内部程式存储器（ROM）为4KB□ 内部数据存储器（RAM）为128B□ 外部程序存储器可扩充至64KB□ 外部数据存储器可扩充至64KB□ 32 条双向输入输出线，且每条均可以单独做I/O 的控制□ 5 个中断向量源□ 2 组独立的16 位定时器□ 1 个全多工串行通信端口□ 8751 及8752 单芯片具有数据保密的功能□ 单芯片提供位逻辑运算指令□VCC8051 电源正端输入，接+5V。

□VSS电源地端。

□XTAL1单芯片系统时钟的反相放大器输入端。

□XTAL2系统时钟的反相放大器输出端，一般在设计上只要在XTAL1 和XTAL2 上接上一只石英振荡晶体系统就可以动作了，此外可以在两引脚与地之间加入一20PF 的小电容，可以使系统更稳定，避免噪声干扰而死机。

□RESET8051的重置引脚，高电平动作，当要对晶片重置时，只要对此引脚电平提升至高电平并保持两个机器周期以上的时间，8051便能完成系统重置的各项动作，使得内部特殊功能寄存器之内容均被设成已知状态，并且至地址0000H处开始读入程序代码而执行程序。

□EA/Vpp"EA"为英文"External Access"的缩写，表示存取外部程序代码之意，低电平动作，也就是说当此引脚接低电平后，系统会取用外部的程序代码（存于外部EPROM中）来执行程序。

因此在8031及8032中，EA引脚必须接低电平，因为其内部无程序存储器空间。

如果是使用8751 内部程序空间时，此引脚要接成高电平。

8051接口概论

①串行数据线（MISO、MOSI）主机输入／从机输出数据线（MISO）和主机输出／
从机输入数据线（MOSI），用于串行数据的发送和接收。数据发送时．先传送MSB（高位），后传送LSB（低位）。
在SPI设置为主机方式时，MISO线是从机数据输入线，MOSI是主机数据输出线；在SPI设置为从机方式时， MISO线是从机数据输出线，MOSI是从机数据输入线。
对于一个完整的SPI系统，串行数据和串行时钟之间有四种极性和相位关系，如图8－5所示，以适应不同的外围器件特性。主机和从机器件之间的传送定时关系必须相同。
③在从从机机选方择式（时S，S脚）是输入端，用于使能SPI从机进行数据传送；在主机方式时，SS 一般由外部置为高电平。
通过SPI可以扩展各种I/O功能，包括：A／D、D／A、实时时钟、RAM、EEPROM及并行输入／输#4 芯片地址分配为8000H～9FFFH，共8K。
(A15=1，A14=0，A13=0) #5 芯片地址分配为A000H～BFFFH，共8K。
(A15=1，A14=0，A13=1
#6 芯片地址分配为C000H～DFFFH，共8K。 (A15=1，A14=1，A13=0)
3/8译码器74LS138的管脚见图8–3。 ·G1、G2A 、G2B ：使能端。当G1=1，G2A = G2B =0时，芯片使能。
·C、B、A：译码器输入，高电平有效。
·Y ：译码器输出，低电平有效。正常情况下，只有一根
输出是低电平，其余输出都是高电平。这样，当译码器输出作
为单片微机应用系统中外扩芯片的片选控制线时，保证每次读或写时只选中一个芯片。
8.1.1外部并行扩展原理
单片微机是通过芯片的引脚进行系统扩展的。

第2章 8051单片机及增强型8051内核

单片机原理及应用 2.2.2 MSC1211单片机的内部结构
2019/3/7
12:03:26
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单片机原理及应用 2.2.3 增强型8051内核 1、4个时钟的指令周期
标准 8051 的一个机器周期是 12 个时钟周期，而 MSC1211 是 4 个时钟周期。因此，在同样的外部时钟频率下执行同样的代码，其指令执行速度要比 8051 快 1.5 ～ 3 倍。这样当用户在较低的外部时钟频率下运行 MSC1211 时，与原来使用标准 8051 内核来比较，不仅降低了系统噪声和电源功耗，而且提高了处理能力。
2019/3/7
12:03:26
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单片机原理及应用
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12:03:26
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单片机原理及应用
特殊功能寄存器地址映象表（一）
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单片机原理及应用
特殊功能寄存器地址映象表（二）
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12:03:26
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单片机原理及应用
3、用户标志F1
程序状态字的第1位（PSW.1）在8051基本内核中保留不用，在8051增强型内核中是用户标志1（F1），该位也是由用户定义的一个状态标志。
回顾PSW的内容
D7
CY
2019/3/7
D6
AC
D5
F0
D4
RS1
20/30
D3
RS0
D2
OV
D1
F1
D0
P
12:03:26
单片机原理及应用 4、双数据指针DPTR0和DPTR1