GS8322V36GB-225中文资料
GS8322V36GB-150中文资料
PreliminaryGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)2M x 18, 1M x 36, 512K x 7236Mb S/DCD Sync Burst SRAMs250 MHz –133 MHz1.8 V V DD 1.8 V I/O119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 1.8 V +10%/–10% core power supply • 1.8 V +10%/–10% core power supply • 1.8 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications• JEDEC-standard 119-, 165-, and 209-bump BGA package • Pb-Free packages availableFunctional DescriptionApplicationsThe GS8322V18/36/72 is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count ineither linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM inPipeline mode, activating the rising-edge-triggered Data Output Register.SCD and DCD Pipelined ReadsThe GS8322V18/36/72 is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Parameter Synopsis-250-225-200-166-150-133UnitPipeline 3-1-1-1KQ t KQ (x72)tCycle 3.04.0 3.04.4 3.05.0 3.56.0 3.86.7 4.07.5ns ns Curr (x18)Curr (x36)Curr (x72)285350440265320410245295370220260320210240300185215265mA mA mA Flow Through 2-1-1-1t KQ tCycle 6.56.57.07.07.57.58.08.08.58.58.58.5ns ns Curr (x18)Curr (x36)Curr (x72)205235315195225295185210265175200255165190240155175230mA mA mAGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)209-Bump BGA—x72 Common I/O—Top View (Package C)1234567891011A DQ G DQ G A E2ADSP ADSC ADV E3A DQB DQ B AB DQ G DQ G BC BG NC BW A BB BF DQ B DQ B BC DQ G DQ G BH BD NC E1NC BE BA DQ B DQ B CD DQ G DQ G V SS NC NC G GW NC V SS DQ B DQ B DE DQP G DQP C V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPF DQP B EF DQ C DQ C V SS V SS V SS ZQ V SS V SS V SS DQ F DQ F FG DQ C DQ C V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQ F DQ F GH DQ C DQ C V SS V SS V SS MCL V SS V SS V SS DQ F DQ F H J DQ C DQ C V DDQ V DDQ V DD MCL V DD V DDQ V DDQ DQ F DQ F J K NC NC CK NC V SS MCL V SS NC NC NC NC K L DQ H DQ H V DDQ V DDQ V DD FT V DD V DDQ V DDQ DQ A DQ A L M DQ H DQ H V SS V SS V SS MCL V SS V SS V SS DQ A DQ A M N DQ H DQ H V DDQ V DDQ V DD SCD V DD V DDQ V DDQ DQ A DQ A N P DQ H DQ H V SS V SS V SS ZZ V SS V SS V SS DQ A DQ A P R DQP D DQP H V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQP A DQP E R T DQ D DQ D V SS NC NC LBO NC NC V SS DQ E DQ E T U DQ D DQ D NC A A A A A A DQ E DQ E U V DQ D DQ D A A A A1A A A DQ E DQ E V W DQ D DQ D TMS TDI A A0A TDO TCK DQ E DQ E W11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V72 209-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset Inputs.An IAddress InputsDQ A DQ B DQ C DQ D DQ E DQ F DQ G DQ H I/O Data Input and Output pinsB A , B B I Byte Write Enable for DQ A , DQ B I/Os; active low BC ,BD I Byte Write Enable for DQ C , DQ D I/Os; active low BE , BF , BG ,B HI Byte Write Enable for DQ E , DQ F , DQ G , DQ H I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowSCD I Single Cycle Deselect/Dual Cycle Deselect Mode ControlMCH IMust Connect High MCL Must Connect Low BW I Byte Enable; active lowZQ I FLXDrive Output Impedance Control(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCKIScan Test ClockGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V72 209-Bump BGA Pin Description (Continued)SymbolTypeDescriptionGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)165-Bump BGA—x18 Commom I/O—Top View (Package E)1234567891011A NC A E1BB NC E3BW ADSC ADV A A AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQPB SCD V DDQ V SS NC A NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)165-Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3BW ADSC ADV A NC A B NC A E2BD BA CK GW G ADSP A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD SCD V DDQ V SS NC A NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A A P RLBOAAATMSA0TCKAAAAR11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch(Package E)GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V18/36 165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active low (x36 Version)NC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSPI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect LowSCD —Single Cycle Deselect/Dual Cyle Deselect Mode ControlV DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)119-Bump BGA—x36 Common I/O—Top View1234567A V DDQ A A ADSP A A V DDQ A B NC A A ADSC A A NC B C NC A A V DD A A NC C D DQ DQP V SS ZQ V SS DQP B DQ B D E DQ DQ V SS E1V SS DQ B DQ B E F V DDQ DQ V SS G V SS DQ B V DDQ F G DQ DQ BC ADV BB DQ B DQ B G H DQ DQ V SS GW V SS DQ B DQ B H J V DDQ V DD NC V DD NC V DD V DDQ J K DQ D DQ D V SS CK V SS DQ A DQ A K L DQ D DQ D BD SCD BA DQ A DQ A L M V DDQ DQ D V SS BW V SS DQ A V DDQ M N DQ D DQ D V SS A1V SS DQ A DQ A N P DQ D DQP D V SS A0V SS DQP A DQ A P R NC A LBO V DD FT A NC R T NC NC A A A A ZZ T UV DDQTMSTDITCKTDONCV DDQU7 x 17 Bump BGA—14 x 22 mm 2 Body—1.27 mm Bump PitchC C C C C C2C C CGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)119-Bump BGA—x18 Common I/O—Top View1234567A V DDQ A A ADSP A A V DDQ AB NC A A ADSC A A NC BC NC A A V DD A A NC CD DQ B NC V SS ZQ V SS DQP A NC DE NC DQ B V SS E1V SS NC DQ A EF V DDQ NC V SSG V SS DQ A V DDQ FG NC DQ B BB ADV NC NC DQ A GH DQ B NC V SS GW V SS DQ A NC HJ V DDQ V DD NC V DD NC V DD V DDQ JK NC DQ B V SS CK V SS NC DQ A KL DQ B NC NC SCD BA DQ A NC LM V DDQ DQ B V SS BW V SS NC V DDQ MN DQ B NC V SS A1V SS DQ A NC NP NC DQP B V SS A0V SS NC DQ A PR NC A LBO V DD FT A NC RT NC A A A A A ZZ TU V DDQ TMS TDI TCK TDO NC V DDQ U7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V18/36 119-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])SCD I Single Cycle Deselect/Dual Cyle Deselect Mode ControlTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock V DD I Core power supply V SS I I/O and Core Ground V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)A1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx93636Note: Only x36 version shown for simplicity.SCD3636B AB BB CB DGS8322V18/36 Block DiagramMode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Note:There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.The burst counter wraps to initial state on the 5th clock.The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110I nterleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4Write all bytesLXXXXX1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Synchronous Truth TableOperationAddress UsedState Diagram Key 5E 1ADSPADSCADVW 3DQ 4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CWH X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend BurstCurrentHXHHTDNotes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)First WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Simplified State Diagram with GAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 3.6V V DDQ Voltage in V DDQ Pins –0.5 to 3.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 3.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 3.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD 1.6 1.82.0V 1.8 V V DDQ I/O Supply VoltageV DDQ1.61.82.0VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)DQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 100 uA FT, SCD, and ZQ Input Current I IN2V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL–100 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V—Output Low VoltageV OL1I OL = 4 mA, V DD = 1.6 V—0.4 VGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 72)P i p e l i n eI D DI D D Q380604006035060370603205034050280403004026040280402353025530m AF l o w T h r o u g hI D DI D D Q275402854025540265402353024530225302353021030220302102022020m A(x 36)P i p e l i n eI D DI D D Q300503205027545295452554027540225352453521030230301902521025m AF l o w T h r o u g hI D DI D D Q210252202520025210251902020020180201902017020180201601517015m A(x 18)P i p e l i n eI D DI D D Q260252802524025260252252024520200202202019020210201701519015m AF l o w T h r o u g hI D DI D D Q190152001518015190151701518015160151701515015160151401515015m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 608060806080608060806080m AF l o w T h r o u g hI S B608060806080608060806080m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D100115951109010585100851008095m AF l o w T h r o u g hI D D85100851008095809575907085m AN o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .AC Electrical CharacteristicsParameterSymbol-250-225-200-166-150-133UnitMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxPipelineClock Cycle Time tKC 4.0— 4.4— 5.0— 6.0— 6.7—7.5—ns Clock to Output Valid (x18/x36)tKQ — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns Clock to Output Valid (x72)tKQ — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.2— 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.3—0.4—0.5—0.5—0.5—ns Flow ThroughClock Cycle Time tKC 6.5—7.0—7.5—8.0—8.5—8.5—ns Clock to Output ValidtKQ — 6.5—7.0—7.5—8.0—8.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5— 1.5— 1.5— 1.5— 1.7—2—ns Clock to Output in High-Z (x18/x36)tHZ 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns Clock to Output in High-Z (x72)tHZ 1 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid (x18/x36)tOE — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns G to Output Valid(x72)tOE — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z (x18/x36)tOHZ 1— 2.5— 2.7— 3.0— 3.0— 3.0— 3.0ns G to output in High-Z (x72)tOHZ 1— 3.0— 3.0— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—nsGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Pipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL tKH Single Write Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Flow Through Mode Timing (SCD)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQd。
3GPP_36.212-860(中文)
3GPP TS 36.212 V8.6.0 (2009-03)Technical Specification3rd Generation Partnership Project;Technical Specification Group Radio Access Network;Evolved Universal Terrestrial Radio Access (E-UTRA);Multiplexing and channel coding(Release 8)The present document has been developed within the 3rd Generation Partnership Project (3GPP TM) and may be further elaborated for the purposes of 3GPP. The present document has not been subject to any approval process by the 3GPP Organizational Partners and shall not be implemented.This Specification is provided for future development work within 3GPP only. The Organizational Partners accept no liability for any use of this Specification. Specifications and reports for implementation of the 3GPP TM system should be obtained via the 3GPP Organizational Partners’ Publications Offices.Keywords<keyword[, keyword]>3GPPPostal address3GPP support office address650 Route des Lucioles – Sophia AntipolisValbonne – FranceTel. : +33 4 92 94 42 00 Fax : +33 4 93 65 47 16InternetCopyright NotificationNo part may be reproduced except as authorized by written permission.The copyright and the foregoing restriction extend to reproduction in all media.© 2009, 3GPP Organizational Partners (ARIB, ATIS, CCSA, ETSI, TTA, TTC).All rights reserved.UMTS™ is a Trade Mark of ETSI registered for the benefit of its members3GPP™ is a Trade Mark of ETSI registered for the benefit of its Members and of the 3GPP Organizational PartnersLTE™ is a Trade Mark of ETSI currently being registered for the benefit of i ts Members and of the 3GPP Organizational Partners GSM® and the GSM logo are registered and owned by the GSM AssociationContentsForeword (5)1Scope (6)2References (6)3Definitions, symbols and abbreviations (6)3.1 Definitions (6)3.2Symbols (6)3.3 Abbreviations (7)4Mapping to physical channels (7)4.1Uplink (7)4.2Downlink (8)5Channel coding, multiplexing and interleaving (8)5.1Generic procedures (8)5.1.1CRC calculation (8)5.1.2Code block segmentation and code block CRC attachment (9)5.1.3Channel coding (10)5.1.3.1Tail biting convolutional coding (11)5.1.3.2Turbo coding (12)5.1.3.2.1Turbo encoder (12)5.1.3.2.2Trellis termination for turbo encoder (13)5.1.3.2.3Turbo code internal interleaver (13)5.1.4Rate matching (15)5.1.4.1Rate matching for turbo coded transport channels (15)5.1.4.1.1Sub-block interleaver (15)5.1.4.1.2Bit collection, selection and transmission (16)5.1.4.2Rate matching for convolutionally coded transport channels and control information (18)5.1.4.2.1Sub-block interleaver (18)5.1.4.2.2Bit collection, selection and transmission (19)5.1.5Code block concatenation (20)5.2Uplink transport channels and control information (20)5.2.1Random access channel (20)5.2.2Uplink shared channel (20)5.2.2.1Transport block CRC attachment (21)5.2.2.2Code block segmentation and code block CRC attachment (22)5.2.2.3Channel coding of UL-SCH (22)5.2.2.4Rate matching (22)5.2.2.5Code block concatenation (22)5.2.2.6 Channel coding of control information (22)5.2.2.6.1Channel quality information formats for wideband CQI reports (27)5.2.2.6.2Channel quality information formats for higher layer configured subband CQI reports (28)5.2.2.6.3Channel quality information formats for UE selected subband CQI reports (28)5.2.2.6.4Channel coding for CQI/PMI information in PUSCH (29)5.2.2.7 Data and control multiplexing (30)5.2.2.8 Channel interleaver (31)5.2.3Uplink control information on PUCCH (33)5.2.3.1Channel coding for UCI HARQ-ACK (33)5.2.3.2Channel coding for UCI scheduling request (33)5.2.3.3Channel coding for UCI channel quality information (33)5.2.3.3.1Channel quality information formats for wideband reports (34)5.2.3.3.2Channel quality information formats for UE-selected sub-band reports (35)5.2.3.4Channel coding for UCI channel quality information and HARQ-ACK (36)5.2.4Uplink control information on PUSCH without UL-SCH data (37)5.2.4.1 Channel coding of control information (37)5.2.4.2 Control information mapping (38)5.2.4.3 Channel interleaver (38)5.3Downlink transport channels and control information (38)5.3.1Broadcast channel (38)5.3.1.1Transport block CRC attachment (39)5.3.1.2Channel coding (39)5.3.1.3 Rate matching (40)5.3.2Downlink shared channel, Paging channel and Multicast channel (40)5.3.2.1Transport block CRC attachment (41)5.3.2.2Code block segmentation and code block CRC attachment (41)5.3.2.3Channel coding (41)5.3.2.4Rate matching (41)5.3.2.5Code block concatenation (41)5.3.3Downlink control information (42)5.3.3.1DCI formats (42)5.3.3.1.1Format 0 (42)5.3.3.1.2Format 1 (43)5.3.3.1.3Format 1A (44)5.3.3.1.3A Format 1B (46)5.3.3.1.4Format 1C (47)5.3.3.1.4A Format 1D (47)5.3.3.1.5Format 2 (48)5.3.3.1.5A Format 2A (52)5.3.3.1.6Format 3 (54)5.3.3.1.7Format 3A (54)5.3.3.2CRC attachment (55)5.3.3.3Channel coding (55)5.3.3.4Rate matching (55)5.3.4Control format indicator (55)5.3.4.1Channel coding (56)5.3.5HARQ indicator (56)5.3.5.1Channel coding (56)Annex A (informative): Change history (58)ForewordThis Technical Specification has been produced by the 3rd Generation Partnership Project (3GPP).The contents of the present document are subject to continuing work within the TSG and may change following formal TSG approval. Should the TSG modify the contents of the present document, it will be re-released by the TSG with an identifying change of release date and an increase in version number as follows:Version x.y.zwhere:x the first digit:1 presented to TSG for information;2 presented to TSG for approval;3 or greater indicates TSG approved document under change control.Y the second digit is incremented for all changes of substance, i.e. technical enhancements, corrections, updates, etc.z the third digit is incremented when editorial only changes have been incorporated in the document.1 ScopeThe present document specifies the coding, multiplexing and mapping to physical channels for E-UTRA.2 ReferencesThe following documents contain provisions which, through reference in this text, constitute provisions of the present document.•References are either specific (identified by date of publication, edition number, version number, etc.) or non-specific.•For a specific reference, subsequent revisions do not apply.•For a non-specific reference, the latest version applies. In the case of a reference to a 3GPP document (includinga GSM document), a non-specific reference implicitly refers to the latest version of that document in the sameRelease as the present document.[1] 3GPP TR 21.905: "Vocabulary for 3GPP Specifications".[2] 3GPP TS 36.211: "Evolved Universal Terrestrial Radio Access (E-UTRA); Physical channels andmodulation".[3] 3GPP TS 36.213: "Evolved Universal Terrestrial Radio Access (E-UTRA); Physical layerprocedures".[4] 3GPP TS 36.306: "Evolved Universal Terrestrial Radio Access (E-UTRA); User Equipment (UE)radio access capabilities".[5] 3GPP TS36.321, “Evolved Universal Terrestrial Radio Access (E-UTRA); Medium AccessControl (MAC) protocol specification”3 Definitions, symbols and abbreviations3.1 DefinitionsFor the purposes of the present document, the terms and definitions given in [1] and the following apply. A term defined in the present document takes precedence over the definition of the same term, if any, in [1].Definition format<defined term>: <definition>.3.2 SymbolsFor the purposes of the present document, the following symbols apply:DLN Downlink bandwidth configuration, expressed in number of resource blocks [2] RBULN Uplink bandwidth configuration, expressed in number of resource blocks [2] RBPUSCHN Number of SC-FDMA symbols carrying PUSCH in a subframesy m bPUSCH-initialN Number of SC-FDMA symbols carrying PUSCH in the initial PUSCH transmission subframe symbULN Number of SC-FDMA symbols in an uplink slotsy m bN Number of SC-FDMA symbols used for SRS transmission in a subframe (0 or 1).SRS3.3 AbbreviationsFor the purposes of the present document, the following abbreviations apply:BCH Broadcast channelCFI Control Format IndicatorCP Cyclic PrefixDCI Downlink Control InformationDL-SCH Downlink Shared channelFDD Frequency Division DuplexingHI HARQ indicatorMCH Multicast channelPBCH Physical Broadcast channelPCFICH Physical Control Format Indicator channelPCH Paging channelPDCCH Physical Downlink Control channelPDSCH Physical Downlink Shared channelPHICH Physical HARQ indicator channelPMCH Physical Multicast channelPMI Precoding Matrix IndicatorPRACH Physical Random Access channelPUCCH Physical Uplink Control channelPUSCH Physical Uplink Shared channelRACH Random Access channelRI Rank IndicationSRS Sounding Reference SignalTDD Time Division DuplexingTPMI Transmitted Precoding Matrix IndicatorUCI U plink Control InformationUL-SCH Uplink Shared channel4 物理信道映射4.1 上行表4.1-1给出了上行传输信道和相应的物理信道间的映射关系。
LM832中文资料
TL H 5176LM832Dynamic Noise Reduction SystemDNRAugust 1989LM832Dynamic Noise Reduction System DNRGeneral DescriptionThe LM832is a stereo noise reduction circuit for use with audio playback systems The DNR system is noncomple-mentary meaning it does not require encoded source mate-rial The system is compatible with virtually all prerecorded tapes and FM broadcasts Psychoacoustic masking and an adaptive bandwidth scheme allow the DNR to achieve 10dB of noise reduction DNR can save circuit board space and cost because of the few additional components re-quiredThe LM832is optimized for low voltage operation with input levels around 30mVrmsFor higher input levels use the LM1894DNR is a registered trademark of National Semiconductor CorporationThe DNR system is licensed to National Semiconductor Corp under U S patent 3 678 416and 3 753 159A trademark and licensing agreement is required for the use of this productFeaturesY Low voltage battery operationY Non-complementary noise reduction ‘‘single ended’’Y Low cost external components no critical matching Y Compatible with all prerecorded tapes and FM Y10dB effective tape noise reduction CCIR ARM weightedY Wide supply range 1 5V to 9V Y 150mVrms input overload Y No royalty requirementsYCascade connection for 17dB noise reductionApplicationsY Headphone stereo Y Microcassette players Y Radio cassette playersYAutomotive radio tape playersApplication CircuitOrder Number LM832M See NS Package M14A Order Number LM832N See NS Package N14ATL H 5176–1FIGURE 1 Component Hook-up for Stereo DNR SystemC 1995National Semiconductor Corporation RRD-B30M115 Printed in U S AAbsolute Maximum RatingsIf Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage10V Power Dissipation(Note1)1 2W Input Voltage1 7Vpp Storage Temperature b65to a150 C Operating Temperature(Note1)b40to a85 Soldering InformationY Dual-In-Line PackageSoldering(10seconds)260 C Y Small Outline PackageVapor Phase(60seconds)215 CInfrared(15seconds)220 C See AN-450‘‘Surface Mounting Methods and Their Effects on Products Reliability’’for other methods of soldering sur-face mount devices ’’DC Electrical Characteristics T A e25 C V CC e3 0VSymbol Parameter Conditions Min Typ Max Units V OP Operating Voltage Supply Voltage for Normal Operation1 53 09 0VI CC(1)Supply Current(1)Pin9to GND0 1m F BW e Min Note22 54 0mA I CC(2)Supply Current(2)DC GND Pin9with2k BW e Max Note25 08 0mA V IN(1)Input Voltage(1)Pin2 Pin130 200 360 5VV IN(2)Input Voltage(2)Pin60 500 650 8VV IN(3)Input Voltage(3)Pin90 500 650 8VV OUT(1)Output Voltage(1)Pin4 Pin110 200 350 50VV OUT(2)Output Voltage(2)Pin5Stereo Mode0 150 280 40VV OUT(3)Output Voltage(3)Pin5Monaural Mode DC Ground Pin140 100 200 30VV OUT(4)Output Voltage(4)Pin80 250 400 60VV OUT(5)Output Voltage(5)Pin10BW e Max Note21 001 271 50VV OUT(6)Output Voltage(6)Pin10BW e Min Note20 500 650 75VV OS Output DC Shift Pin4 PIN11 Change BW Min to Max1 03 0mVAC Electrical CharacteristicsSymbol Parameter Conditions Min Typ Max Units MAIN SIGNAL PATH(Note3)A V Voltage Gain V IN e30mVrms f e1kHz BW e Max Note2b1 00 0a1 0dBC B Channel Balance V IN e30mVrms f e1kHz BW e Max Note2b1 00a1 0dB f MIN Min Bandwidth0 1m F between Pin9-GND60010001500Hz f MAX Max Bandwidth DC Ground Pin9with2k243046kHz THD Distortion V IN e30mVrms f e1kHz BW e Max Note20 070 5% MV IN Max Input Voltage THD e3% f e1kHz BW e Max Note2120150mVrms S N Signal to Noise REF e30mVrms BW e Max CCIR ARM6068dB Z IN Input Impedance Pin2 Pin13142026k X C S Channel Separation Ref e30mVrms f e1kHz BW e Max Note24068dB P SRR P SRR V RIPPLE e50mVrms f e100Hz4055dB CONTROL PATHA V sum(1)Summing Amp Gain(1)V IN e30mVrms at R and L f e1kHz b3 0b1 50 0dB A V sum(2)Summing Amp Gain(2)DC Ground Pin14 f e1kHz b9 0b6 0b3 0dB A V1st Gain Amp Gain Pin6to Pin8253035dB Z IN1st Input Impedance Pin6284052k X A VPKD Peak Detector Gain AC In DC Out Pin9to Pin10253035V V Z INPKD Input Impedance Pin95008001100XV RPKD Output DC Change Pin10 Change BW Min to Max0 50 620 8V Note1 For operation in ambient temperature above25 C the device must be derated based on a150 C maximum junction temperature and a thermal resistance junction to ambient as follows LM832N b90 c w LM832M-115 c wNote2 To force the DNR system into maximum bandwidth connect a2k resistor from pin9to GND AC ground pin9or pin6to select minimum bandwidth To change minimum and maximum bandwidth see Application HintsNote3 The maximum noise reduction CCIR ARM weighted is about14dB This is accomplished by changing the bandwidth from maximum to minimum In actual operation minimum bandwidth is not selected a nominal minimum bandwidth of about2kHz gives10dB of noise reduction See Application Hints2External Component Guide(See Figure1)Recom-EffectP N mended PurposeSmaller Larger RemarksValueC110m F Power supply Poor supply Better supply Do not use lessdecoupling rejection rejection than10m FC2 C111m F Input coupling Increases Reduces DC voltage at pin2capacitor frequency of low-frequency of low-and pin13is0 35Vfrequency roll-off frequency roll-offf e12q C2R INC3 C1022nF for Stereo Establishment of Min Bandwidth Bandwidth See Note4 15nF for mono and Max Bandwidth becomes wider becomes narrowerC4 C81m F Output coupling Increases Reduces DC voltage at pin4capacitor frequency of low-frequency of low-and pin11is0 35Vfrequency roll-off frequency roll-offf e12q C4R LOADWorks with R1and R2Some high frequency Bandwidth mayto set one of the low-program material increase dueC50 1m F frequency corners may be attenuated to low-frequency f e12q C5(R1a R2)e1 6kHzin control path inputs causing‘‘Breathing’’See Note4 Works with inputresistance of pin6C6820pF to set one of the Same as Same as f e12q C6R PIN6e4 8kHzlow-frequency above abovecorners in the See Note4 control pathWorks with inputresistance of pin9Same as Same asC739nF to form part of above above f e12q C7R PIN7e4 8kHzcontrol pathfrequency weighing See Note4C91m F Sets attack time Reduces attack Increases attack See Note4and decay time and decay timeThis voltage Sensitivity should be set for R1 R2R1a R2e1k X divider sets maximum noise reduction control path and minimum audiblesensitivity frequency program effecton highR3 2k X Sets gain amp load Loads gain amp Max bandwidthwhen DNR is OFF output may will be reducedcause distortionNote4 The values of the control path filter components(C5 C6 C7 C9 R1 R2)and the integrating capacitors(C3 C10)should not be changed from the recommended values unless the characteristics of the noise or program material differ substantially from that of FM or tape sources Failure to use the correct values may result in degraded performance and therefore the application may not be approved for DNR trademark usage Please contact National Semiconductor for more information and technical assistance3Typical Performance CharacteristicsTL H 5176–2FIGURE 2 Supply current vs supply voltage TL H 5176–3FIGURE 3 Channel separation vs frequency TL H 5176–4FIGURE 4 Power supply rejection ratio vs frequencyTL H 5176–5FIGURE 5 Output level change vs supply voltageTL H 5176–6FIGURE 6 Output level vs frequency TL H 5176–7FIGURE 7 THD vs frequencyTL H 5176–8FIGURE 8 Output vs frequency and control path signal TL H 5176–9FIGURE 9 Frequency response for various input levelsTL H 5176–10FIGURE 10 Gain of control path vs frequencyTL H 5176–11FIGURE 11 Change in main signal path maximum bandwidth vs temperature4Circuit OperationThe LM832has two signal paths a main signal path and a bandwidth control path The main path is an audio low pass filter comprised of a g m block with a variable current and a unity gain buffer As seen in Figure1 DC feedback con-strains the low frequency gain to A v e b1 Above the cutoff frequency of the filter the output decreases at b6dB oct due to the action of the0 022m F capacitorThe purpose of the control path is to generate a bandwidth control signal which replicates the ear’s sensitivity to noise in the presence of a tone A single control path is used for both channels to keep the stereo image from wandering This is done by adding the right and left channels together in the summing amplifier of Figure1 The R1 R2resistor divider adjusts the incoming noise level to slightly open the bandwidth of the low pass filter Control path gain is about 60dB and is set by the gain amplifier and peak detector gain This large gain is needed to ensure the low pass filter bandwidth can be opened by very low noise floors The ca-pacitors between the summing amplifier output and the peak detector input determine the frequency weighting as shown in the typical performance curves The1m F capaci-tor at pin10 in conjunction with internal resistors sets the attack and decay times The voltage is converted into a proportional current which is fed into the g m blocks The bandwidth sensitivity to g m current is70Hz m A In FM stereo applications a19kHz pilot filter is inserted between pin8and pin9as shown in Figure16Normal methods of evaluating the frequency response of the LM832can be misleading if the input signal is also applied to the control path Since the control path includes a frequency weighting network a constant amplitude but vary-ing frequency input signal will change the audio signal path bandwidth in a non-linear fashion Measurements of the au-dio signal path frequency response will therefore be in error since the bandwidth will be changing during the measure-ment See Figure9for an example of the misleading results that can be obtained from this measurement approach Al-though the frequency response is always flat below a single high-frequency pole the lower curves do not resemble sin-gle pole responses at allA more accurate evaluation of the frequency response can be seen in Figure8 In this case the main signal path is frequency swept while the control path has a constant fre-quency applied It can be seen that different control path frequencies each give a distinctive gain roll-off PSYCHOACOUSTIC BASICSThe dynamic noise reduction system is a low pass filter that has a variable bandwidth of1kHz to30kHz dependent on music spectrum The DNR system operates on three princi-ples of psychoacoustics1 Music and speech can mask noise In the absence of source material background noise can be very audible However when music or speech is present the human ear is less able to distinguish the noise the source material is said to mask the noise The degree of masking is depen-dent on the amplitude and spectral content(frequencies)of the source material but in general multiple tones around1 kHz are capable of providing excellent masking of noise over a very wide frequency range2 The ear cannot detect distortion for less than1ms On a transient basis if distortion occurs in less than1ms the earacts as an integrator and is unable to detect it Because of this signals of sufficient energy to mask noise open the bandwidth to90%of the maximum value in less than1ms Reducing the bandwidth to within10%of its minimum value is done in about60ms long enough to allow the ambience of the music to pass through but not so long as to allow the noise floor to become audible3 Reducing the audio bandwidth reduces the audibility ofnoise Audibility of noise is dependent on noise spectrum or how the noise energy is distributed with frequency Depend-ing on the tape and the recorder equalization tape noise spectrum may be slightly rolled off with frequency on a per octave basis The ear sensitivity on the other hand greatly increases between2kHz and10kHz Noise in this region is extremely audible The DNR system low pass filters this noise Low frequency music will not appreciably open the DNR bandwidth thus2kHz to20kHz noise is not heard Application HintsThe DNR system should always be placed before tone and volume controls as shown in Figure1 This is because any adjustment of these controls would alter the noise floor seen by the DNR control path The sensitivity resistors R1 and R2may need to be switched with the input selector depending on the noise floors of different sources i e tape FM phono To determine the value of R1and R2in a tape system for instance apply tape noise(no program material) and adjust the ratio of R1and R2to slightly open the band-width of the main signal path This can easily be done by viewing the capacitor voltage of pin10with an oscilloscope or by using the circuit of Figure12 This circuit gives an LED display of the voltage on the peak detector capacitor Adjust the values of R1and R2(their sum is always1k X)to light the LEDs of pin1and pin18 The LED bar graph does not indicate signal level but rather instantaneous bandwidth of the two filters it should not be used as a signal-level indica-tor For greater flexibility in setting the bandwidth sensitivity R1and R2could be replaced by a1k X potentiometerTo change the minimum and maximum value of bandwidth the integrating capacitors C3and C10 can be scaled up or down Since the bandwidth is inversely proportional to the capacitance changing this0 022m F capacitor to0 015m F will change the typical bandwidth from1kHz–30kHz to1 5 kHz–44kHz With C3and C10set at0 022m F the maxi-mum bandwidth is typically30kHz A double pole double throw switch can be used to completely bypass DNRThe capacitor on pin10in conjunction with internal resistors sets the attack and decay times The attack time can be altered by changing the size of C9 Decay times can be decreased by paralleling a resistor with C9 and increased by increasing the value of C9When measuring the amount of noise reduction of DNR in a cassette tape system the frequency response of the cas-sette should be flat to10kHz The CCIR weighting network has substantial gain to8kHz and any additional roll-off in the cassette player will reduce the benefits of DNR noise reduction A typical signal-to-noise measurement circuit is shown in Figure13 The DNR system should be switched from maximum bandwidth to nominal bandwidth with tape noise as a signal source The reduction in measured noise is the signal-to-noise ratio improvement5Application Hints (Continued)TL H 5176–12FIGURE 12 Bar Graph Display of Peak Detector VoltageTL H 5176–13FIGURE 13 Technique for Measuring S N Improvement of the DNR SystemCASCADE CONNECTIONAdditional noise reduction can be obtained by cascading the DNR filters With two filters cascaded the rolloff is 12dB per octave For proper operating bandwidth the capacitors on pin 3and 12are changed to 15nF The resulting noise reduction is about 17dBFigure 15shows the monaural cascade connection Note that pin 14is grounded so only the pin 2input is fed to the summing amp and therefore the control pathFigure 14shows the stereo cascade connection Note that pin 14is open circuit as in normal stereo operationTL H 5176–14R1a R2e 1k X (refer to application hints)FIGURE 14 Stereo Cascade Connection6Application Hints(Continued)TL H 5176–15R1a R2e1k X(refer to application hints)FIGURE15 Monaural Cascade ConnectionFM STEREOWhen using the DNR system with FM stereo as the audio source it is important to eliminate the ultrasonic frequencies that accompany the audio If the radio has a multiplex filter to remove the ultrasonics there will be no problemThis filtering can be done at the output of the demodulator before the DNR system or in the DNR system control path Standard audio multiplex filters are available for use at the output of the demodulator from several filter companies Figure16shows the additional components L1 C15and C16that are added to the control path for FM stereo appli-cations The coil must be tuned to19kHz the FM pilot frequencyTL H 5176–16FIGURE16 FM Stereo Application FOR FURTHER READINGTape Noise Levels1 ‘‘A Wide Range Dynamic Noise Reduction System’’Blackmer ‘dB’Magazine August-September1972 Volume 6 82 ‘‘Dolby B-Type Noise Reduction System’’ Berkowitz and Gundry Sert Journal May-June1974 Volume83 ‘‘Cassette vs Elcaset vs Open Reel’’ Toole Audioscene Canada April19784 ‘‘CCIR ARM A Practical Noise Measurement Method’’ Dolby Robinson Gundry JAES 1978Noise Masking1 ‘‘Masking and Discrimination’’ Bos and De Boer JAESVolume39 4 19662 ‘‘The Masking of Pure Tones and Speech by WhiteNoise’’ Hawkins and Stevens JAES Volume22 1 19503 ‘‘Sound System Engineering’’ Davis Howard W Samsand Co4 ‘‘High Quality Sound Reproduction’’ Moir Chapman Hall19605 ‘‘Speech and Hearing in Communication’’ Fletcher VanNostrand 1953R1a R2e1K X(refer to application hints)7LM832Simple Circuit Schematic71–6715HLT89L M 832D y n a m i c N o i s e R e d u c t i o n S y s t e m D N RPhysical Dimensions inches (millimeters)Order LM832MNS Package Number M14AOrder LM832NNS Package Number N14ALIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injury to the userNational Semiconductor National Semiconductor National Semiconductor National Semiconductor CorporationEuropeHong Kong LtdJapan Ltd1111West Bardin RoadFax (a 49)0-180-530858613th Floor Straight Block Tel 81-043-299-2309元器件交易网This datasheet has been download from:Datasheets for electronics components.。
98822中文资料
Symbol Test Conditions Maximum RatingsV DSS T J = 25°C to 150°C800V V DGR T J = 25°C to 150°C; R GS = 1 M Ω800V V GS Continuous ±20V V GSM Transient ±30V I D25T C = 25°C750mA I DM T C = 25°C, pulse width limited by T JM3A I AR 1.0A E AR T C = 25°C 5mJ E AS T C = 25°C100mJ dv/dt I S ≤ I DM , di/dt ≤ 100 A/µs, V DD ≤ V DSS ,3V/ns T J ≤ 150°C, R G = 47 ΩP D T C = 25°C40W T J -55 ... +150°C T JM 150°C T stg -55 ... +150°CM d Mounting torque 1.13/10Nm/lb.in.WeightTO-220 4 g TO-252 0.8g TO-263 3gMaximum lead temperature for soldering 300°C1.6 mm (0.062 in.) from case for 10 s High Voltage MOSFETG = Gate, D = Drain,S = Source,TAB = DrainD (TAB)SymbolTest ConditionsCharacteristic Values(T J = 25°C, unless otherwise specified)min.typ.max.V DSS V GS = 0 V, I D = 250 µA 800V V GS(th)V DS = V GS , I D = 25 µA 2.54.5V I GSS V GS = ±20 V DC , V DS = 0±100nA I DSS V DS = V DSS T J = 25°C 25µA V GS = 0 VT J = 125°C500µA R DS(on)V GS = 10 V, I D = 500 mA9.511ΩPulse test, t ≤ 300 µs, duty cycle d ≤ 2 %Features!International standard packages !High voltage, Low R DS (on) HDMOS TMprocess!Rugged polysilicon gate cell structure!Fast switching timesApplications!Switch-mode and resonant-mode power supplies !Flyback inverters!DC choppers!High frequency matchingAdvantages !Space savings !High power densityDS98822C(11/03)TO-220AB (IXTP)© 2003 IXYS All rights reservedGSN-Channel Enhancement Mode Avalanche Energy Rated IXTA 1N80IXTP 1N80IXTY 1N80V DSS =800V I D25=750m A R DS(on)=11ΩPreliminary DataGSIXYS reserves the right to change limits, test conditions, and dimensions.IXYS MOSFETs and IGBTs are covered by one or more of the following U.S. patents:4,835,5924,881,1065,017,5085,049,9615,187,1175,486,7156,306,728B14,850,0724,931,8445,034,7965,063,3075,237,4815,381,025SymbolTest ConditionsCharacteristic Values(T J = 25°C, unless otherwise specified)min.typ.max.g fs V DS = 20 V; I D = 500 mA, pulse test0.70.8S C iss 220pF C oss V GS = 0 V, V DS = 25 V, f = 1 MHz23pF C rss 4pF t d(on)11ns t r V GS = 10 V, V DS = 0.5 • V DSS , I D = 1A 19ns t d(off)R G= 47Ω, (External)40ns t f 28ns Q G(on)8.5nC Q GS V GS = 10 V, V DS = 0.5 • V DSS , I D = 1A2.5nC Q GD 4.5nC R thJC 3.1K/W R thCK(IXTP)0.50K/WSource-Drain Diode Characteristic Values(T J = 25°C, unless otherwise specified)Symbol Test Conditions min.typ.max.I S V GS = 0 V750mA I SM Repetitive; pulse width limited by T JM 3A V SD I F = I S , V GS = 0 V,1.82V Pulse test, t ≤ 300 µs, duty cycle d ≤ 2 %t rrI F = I S , -di/dt = 100 A/µs, V R = 100 V710nsPins: 1 - Gate2 - Drain3 - Source4 - Drain Bottom SideTO-220 AD DimensionsTO-263 AA Outline1.Gate2.Drain3.Source4.DrainBottom Sidelimeter Inches Min.Max.Min.Max.A 4.06 4.83.160.190A1 2.03 2.79.080.110b 0.510.99.020.039b2 1.14 1.40.045.055c 0.460.74.018.029c2 1.14 1.40.045.055D 8.649.65.340.380D17.118.13.280.320E 9.6510.29.380.405E1 6.868.13.270.320e 2.54BSC .100BSC L 14.6115.88.575.625L1 2.29 2.79.090.110L2 1.02 1.40.040.055L3 1.27 1.78.050.070L400.380.015R0.460.74.018.029Dim. MillimeterInches Min.Max.Min.Max.A 2.19 2.380.0860.094A10.89 1.140.0350.045A200.1300.005b 0.640.890.0250.035b10.76 1.140.0300.045b2 5.21 5.460.2050.215c 0.460.580.0180.023c10.460.580.0180.023D 5.97 6.220.2350.245D1 4.32 5.210.1700.205E 6.35 6.730.2500.265E1 4.32 5.210.1700.205e 2.28 BSC 0.090 BSC e1 4.57 BSC 0.180 BSC H 9.4010.420.3700.410L 0.51 1.020.0200.040L10.64 1.020.0250.040L20.89 1.270.0350.050L32.54 2.920.1000.115TO-252 AA Outline。
S-8232中文资料
(9) TSSOP package (8-pin) 6.4 mm×3.1 mm
Applications
Lithium-ion rechargeable battery packs
Seiko Instruments Inc.
1
元器件交易网
Battery Protection IC (for a 2-serial-cell pack) S-8232 Series
Over discharge detection voltage is 0 to 1.2V)
Over current detection voltage 1
0.07 V ± 20 mV to 0.30 V ± 20 mV
5 mV-step
(2) High input-voltage device (absolute maximum rating: 18 V)
release voltage1,2 (VCD1,2)
detection voltage1,2 (VDD1,2)
release voltage1,2 (VDU1,2)
detection voltage1 (VIOV1)
detection delay time (tCU)
C3=0.22µF
charging function
Over discharge detection voltage1,2
(VDD1,2)
1.70 to 2.60 V 1.70 to 2.80 V 1.70 to 3.00 V
Table 2 Over charge detection voltage1,2
1.0 sec
Available
S-8232AFFT 4.25V±25mV
UG重用库GB标准件名称注释
Hex Head:六角头螺钉 GB/T 838-88 六角头不脱出螺钉
Knurled Head:滚花头螺钉 GB/T 835-88 滚花平头螺钉
Pan Head: 平头螺钉 GB/T 67-2000 开槽盘头螺钉 GB/T 818-2000 十字槽盘头螺钉 (H/Z)
普通垫圈平垫圈gbt952002平垫圈c级gbt9612002大垫圈a级gbt9622002大垫圈c级gbt9712002平垫圈a级gbt9722002平垫圈倒角型a级33bearing轴承angularball径向止推滚珠轴承角接触球轴承ball球轴承滚球轴承深沟球轴承cylindrical圆柱滚子轴承needle冲压外圈滚针轴承rolling滚动轴承外球面球轴承thrustball推力球轴承thrustcombined组合式推力轴承thrustcylindrical推力圆柱滚子轴承34profile型材bar条形棒形型材channelsection槽钢ibeam工字钢pipetube管形空心型材35
GB/T 5282-85 开槽盘头自攻螺钉 (C/F)
Pan Head: 平头螺钉 GB/T 828-88 开槽盘头定位螺钉
GB/T 837-88 开槽盘头不脱出螺钉
GB/T 845-85 十字槽盘头自攻螺钉 (C/F/H/Z)
Round Head: 圆头螺钉 GB/T 99-86 开槽圆头木螺钉 Set Screw: 固定[定位]螺丝 GB/T 77-2000 内六角平端紧定螺钉 GB/T 78-2000 内六角锥端紧定螺钉
机械设计手册中常用的标准件：
BOLT(螺栓，螺钉)： CUP Head 半圆头螺栓 GB-12-1988 半圆头方颈螺栓 (GB/T 12-1988)
出口商品技术指南——微波炉说明书
出口商品技术指南微波炉中华人民共和国商务部2021年11月前言2020年新冠肺炎疫情来袭，在疫情的影响之下，全球经济由疲软转向衰退的风险明显上升，供给侧和需求侧同时面临萎缩，贸易陷于停滞状态，加上地缘政治冲突升级、全球贸易摩擦不确定性风险犹存等因素，中国家用电器行业出口受到了一定冲击。
然而，“少聚会、少聚餐”的倡议让全球人们与吃有关的生活习惯发生了巨大的变化。
对于与人们生活紧密相关的厨房电器——微波炉而言，新冠肺炎疫情给之带来一波新的出口行情，自2020年起出口额逆势上扬，大幅增长。
据海关总署统计数据显示，2020年中国微波炉出口量为6741.28万台，较2019年增加了760.84万台。
2020年中国微波炉出口金额为323722.50万美元，较2019年增加了33574.74 万美元。
近年来国际经济贸易形势不断发生着复杂而深刻的变化。
虽然受到国际金融危机以及全球经济增速放缓等因素影响，我国家电产品的出口额总体上还是处于上升趋势。
中国是全球微波炉需求量的出口大国，在新的国际市场环境及经济贸易形势下，为了便于出口家电企业更充分地了解国际上各种技术性贸易措施产生背景和表现形式，以及有关家电产品标准的变化情况，在商务部发布的《出口商品技术指南——微波炉》（2014年版）的基础上，中国家用电器研究院再次受商务部委托，根据2014年以后出口家电市场面临的各种新的技术性贸易措施以及主要出口国家和地区产品技术标准的演变情况，进行了修订。
本次修订涉及的内容包括：1）对近十年出口微波炉市场的情况和数据进行了系统汇总统计，同时对各大洲以及重点国家的出口情况进行了分析说明；2）更新了我国微波炉安全标准与最新版IEC标准的技术差异比对和解读；3）更新了我国微波炉性能测试方法标准与最新版IEC标准的技术差异比对和解读；4）更新了我国安全标准与日本安全标准的技术差异的比对和解读，并对2014年实施的全新修订的日本电气用品安全法进行了分析说明；5）增加了我国安全标准与美国标准的技术差异的比对和解读；6）更新了欧盟RoHS指令对于家用电器产品中有害物质的豁免清单；7）增加了对一带一路沿线国家和地区技术壁垒近期对策的思考；8）增加了最新版IEC标准的译文：IEC 60335-2-25:2020家用和类似用途电器的安全微波炉，包括组合型微波炉的特殊要求；9）更新了我国微波炉性能测试方法标准的内容：GB/T 18800-2017 家用微波炉性能试验方法。
电磁保护设备TeSys GV系列产品参数表说明书
C i r c u i t b r e a k e r sCircuit breakersTeSys GV, GBC ontrol and P rotection C omponentsChapterB60.75g g 1.1g g 1.5375 2.533.5 LR2 K0308GV2LE071.1g g –––––– 2.533.5 LR2 K0308GV2LE071.5g g 1.5g g 3375451 LR2 K0310GV2LE08––– 2.2g g –––451 LR2 K0312GV2LE082.2g g 3501004375 6.378 LR2 K0312GV2LE103g g 410100 5.537510138 LR2 K0314GV2LE144g g 5.510100–––10138 LR2 K0316GV2LE14––––––7.537510138 LRD 14GV2LE14––––––937514170 LRD 16GV2LE165.515507.56751137514170 LR2 K0321GV2LE167.5155096751537518223 LRD 21GV2LE20915401147518.537525327 LRD 22GV2LE2211154015475–––25327 LRD 22GV2LE2215105018.54752237532416LRD 32GV2LE32(1) As % of Icu.g ) > 100 kA.GV2 LE10D F 526144.t i fC i r c u i t b r e a k e r s0.09––––––0.45LRD 03GV2L030.12g g –––0.37g g 0.638LRD 04GV2L040.18g g ––––––0.638LRD 04GV2L04––––––0.55g g 113LRD 05GV2L050.25g g ––––––113LRD 05GV2L05––––––0.75g g 113LRD 06GV2L050.37g g 0.37g g –––113LRD 05GV2L050.55g g 0.55g g 1.1g g 1.622.5LRD 06GV2L06–––0.75g g ––– 1.622.5LRD 06GV2L060.75g g 1.1g g 1.54100 2.533.5LRD 07GV2L07Example: GV3 L32 becomes GV3 L326.(1) As % of Icu. Associated current limiter or fuses, where required. See characteristics page B6/33.g > 100 kA.GV2 L10D F 526145.t i fGV3 L65D F 526146.t i fTeSys GVThermal-magnetic motor circuit breakers GV2 ME0.06gg––––––0.16…0.252.4GV2ME020.09g g––––––0.25…0.405GV2ME030.12 0.18g g g g – –– –– – 0.37 –g–g –0.40…0.638GV2ME040.25gg––– 0.55gg0.63…113GV2ME050.37 0.55 –g g –g g –0.37 0.55 0.75g g g g g g – 0.75 1.1– g g – g g 1…1622.5GV2ME060.75g g1.1gg1.5375 1.6...2.533.5GV2ME071.1 1.5g g g g 1.5 2.2g g g g 2.2 3 3 375 75 2.5 (4)51GV2ME082.2gg350100 43754...6.378GV2ME103 4g g g g 4 5.510 10100 100 5.5 7.5 3 375 756 (10)138GV2ME145.5 –15 –50 –7.5 – 6 –75 – 9 11 3 375 759…14170GV2ME167.5155096751537513…18223GV2ME209154011475 18.537517…23327GV2ME2111154015475 –––20…25327GV2ME22 (3)15105018.54752237524 (32)416GV2ME32Motor circuit breakers from 0.06 to 15 kW / 400 V, with lugsTo order thermal magnetic circuit breakers with connection by lugs, add the digit 6 to the end of reference selected above.Example: GV2 ME08 becomes GV2 ME086.Thermal magnetic circuit breakers GV2 ME with built-in auxiliary contact block With instantaneous auxiliary contact block (composition, see page B6/11):b GV AE1, add suffix AE1TQ to the motor circuit breaker reference selected above. Example: GV2 ME01AE1TQ .b GV AE11, add suffix AE11TQ to the motor circuit breaker reference selected above. Example: GV2 ME01AE11TQ .b GV AN11, add suffix AN11TQ to the motor circuit breaker reference selected above. Example: GV2 ME01AN11TQ .These circuit breakers with built-in contact block are sold in lots of 20 units in a single pack.(1) As % of Icu.(2) The thermal trip setting must be within the range marked on the graduated knob.(3) Maximum rating which can be mounted in enclosures GV2 MC or MP , please consult your Regional Sales Office. g > 100 kA.GV2 ME10D F 526134.t i fC i r c u i t b r e a k e r sTeSys GVTeSys protection componentsThermal-magnetic motor circuit breakers GV2 MEReferences0.06g g ––– 0.16…0.25 2.4GV2ME0230.09g g ––– 0.25…0.405GV2ME0330.120.18g g g g –––0.40…0.638GV2ME0430.250.37g g g g 0.37g g 0.63…113GV2ME0530.370.55g g g g 0.370.550.75g g g g g g 1…1.622.5GV2ME0630.75g g1.1g g 1.6…2.533.5GV2ME0731.11.5g g g g 1.52.2g g g g 2.5…451GV2ME0832.2g g 350100 4…6.378GV2ME10334g g g g 45.510101001006…10138GV2ME1435.515507.5675 9…14170GV2ME1637.515509675 13…18223GV2ME203911151540401147517…23327GV2ME2131115401547520 (25)327GV2ME223Contact blocksDescription Mounting Maximum number Type of contacts Sold in lots of Unitreference Instantaneous auxiliary contactsFront 1N/O + N/C 10GVAE113N/O + N/O 10GVAE203LH side2N/O + N/C 1GVAN113N/O + N/O1GVAN203AccessoryDescriptionApplicationSold in lots of Unitreference Cable end reducerFor connection of conductors from 1 to 1.5 mm 220LA9D99(1) For connection of conductors from 1 to 1.5 mm 2, the use of an LA9 D99 cable end reducer is recommended.(2) Maximum rating which can be mounted in enclosures GV2 MC or MP , please consult your Regional Sales Office (3) The thermal trip setting must be within the range marked on the graduated knob.g > 100 kA.GV2 ME pp 3D F 526135.t i fLA9 D99D F 533898.e p sTeSys GVReferencesTeSys protection componentsThermal-magnetic motor circuit breakersGV2 P, GV3 P and GV3 ME80GV2 P10D F 526137.t i fGV3 P65D F 526139.t i fGV3 P651D F 526140.t i fC i r c u i t b r e a k e r sTeSys GVReferences93610011181001581007.59707010010091150501001001115101010010012…20GV7RS20 2.0109113636100100111518181001001518.58810010015…25GV7RE25 2.0109117070100100111550501001001518.5101010010015…25GV7RS25 2.01018.53610018.522181810010022810025…40GV7RE40 2.01018.57010018.550100221010025…40GV7RS40 2.0102236100301810030810030…50GV7RE50 2.01522701003050100301010030 (50)GV7RS502.01537361004555181810010055810048...80GV7RE80 2.040377010045555050100100551010048...80GV7RS80 2.0404536100–1810075810060...100GV7RE100 2.0404570100–50100751010060...100GV7RS100 2.0405575353510010075903030100100901108810010090 (150)GV7RE1502.020557570701001007590505010010090110101010010090…150GV7RS150 2.02090110353510010011013216030303010010010016020088100100132…220GV7RE220 2.3509011070701001001101321605050501001001001602001010100100132…220GV7RS220 2.350(1) As % of lcu.TeSys protection componentsThermal-magnetic motor circuit breakers GV7 RGV7 RE40D F 526138.t i fGV7 RS220D F 526141.t i f0.12–0.120.180.18–0.370.40…0.6313GV2RT040.090.120.250.370.250.370.370.550.63…122GV2RT050.180.250.370.550.370.550.370.550.750.751.11…1.633GV2RT060.370.750.751.1 1.11.51.6…2.551GV2RT070.550.75 1.11.5 1.51.52.2 2.23 2.5…478GV2RT081.12.22.23344…6.3138GV2RT101.52.234445.5 5.57.56…10200GV2RT142.23 5.55.57.57.59119…14280GV2RT1647.57.5991513…18400GV2RT205.5911111118.517…23400GV2RT21(1) The thermal trip setting must be within the range marked on the graduated knob.GV2 RTD F 526142.t i fC i r c u i t b r e a k e r sblack handle, blue legend plate(1) The thermal trip setting must be within the range marked on the graduated knob.(2) Other accessories such as mounting, cabling and marking accessories are identical to those used for GV2 ME motor circuit breakers, see page B6/13.GV2 RTD F 526142.t i fD F 526340.e p sC i r c u i t b r e a k e r sTeSys GVDescription Mounting Maximum number Type of contacts Sold inlots of Unitreference Instantaneous auxiliary contactsFront (1)1N/O or N/C (2)10GVAE1N/O + N/C 10GVAE11N/O + N/O10GVAE20Side (LH)2N/O + N/C1GVAN11N/O + N/O1GVAN20Fault signalling contact + instantaneous auxiliary contact Side (3) (LH)1N/O (fault)+ N/O1GVAD1010+ N/C1GVAD1001N/C (fault)+ N/O1GVAD0110+ N/C1GVAD0101Short-circuit signalling contactSide (LH)1C/O common point1GVAM11(1 block on RH sideof circuit breaker GV2 ME)50 Hz GVAX11560 Hz GVAX116127 V60 Hz GVAX115220…240 V 50 Hz GVAX22560 Hz GVAX226380…400 V50 Hz GVAX38560 Hz GVAX386415…440 V 50 Hz GVAX415440 V60 Hz GVAX385Add-on contact blocksDescriptionMountingMaximum number Reference Visible isolation block (5)Front (1)1GV2AK00 (6)LimitersAt top(GV2 ME and GV2 P)1GV1L3Independent1LA9LB920(1) Mounting of a GV AE contact block or a GV2 AK00 visible isolation block on GV2 P and GV2 L .(2) Choice of N/C or N/O contact operation, depending on which way round the reversible block is mounted.(3) The GV AD is always mounted next to the circuit breaker.(4) To order an undervoltage trip: replace the dot (p ) in the reference with a U , example: GV AU025. To order a shunt trip: replace the dot (p ) in the reference with an S , example: GV AS025.(5) Visible isolation of the 3 poles upstream of circuit breaker GV2 P and GV2 L .Visible isolation block GV2 AK00 cannot be used with motor circuit breakers GV2 P32 and GV2 L32 (Ith max = 25 A).(6) Ie Max = 32 A.ReferencesTeSys protection componentsThermal-magnetic and magnetic motor circuit breakers GV2 with screw clamp connectionsAdd-on blocks and accessoriesCharacteristics:pages B6/89 and B6/94Dimensions, schemes:pages B6/70 to B6/82LA9LB920D B 126629.e p sC i r c u i t b r e a k e r sTeSys GVTerminal blockfor supply to one or more GV2 G busbar setsConnection from the top1GV1G09Can be fitted with current limiter GV1 L3 (GV2 ME and GV2 P)1GV2G05Cover for terminal block For mounting in modular panels10LA9E07Flexible 3-pole connection for connecting a GV2 to a contactor LC1-D09…D25 Centre distance between mounting rails: 100…120 mm10GV1G02Set of connections upstream/downstream For connecting GV2 ME to a printed circuit board 10GV2GA01“Large Spacing” adapter UL 508 type EFor GV2 P pp H7 (except 32 A)1GV2GH7Clip-in marker holders (supplied with each circuit breaker)For GV2 P , GV2 L, GV2 LE and GV2 RT (8 x 22 mm)100LA9D92ReferencesTeSys protection componentsThermal-magnetic and magnetic motor circuit breakers GV2 with screw clamp connectionsAccessoriesDimensions, schemes:pages B6/70 to B6/82D B 417942.e p sTeSys GVD B 126631.e p sD B 126630.e p sD B 126632.e p s7P B 106297_45.e p sExtended Rotary HandleAllows a circuit breaker or a starter-controller installed in back of an enclosure to be operated from the front of the enclosure.A rotary handle can be black or red/yellow, IP54 or IP65. It includes a function for locking the circuit breaker or the starter in the O (Off) or I (On) position(depending of the type of rotary handle) by means of up to 3 padlocks with a shank diameter of 4 to 8 mm. The extended shaft must be adjusted to use in different size enclosures. The IP54 rotary handle is fixed with a nut (Ø22) to make easierthe assembling. The new Laser Square tool brings the accuracy to align the circuit breaker and the rotary handle.device(padlocks not included)ReferencesTeSys protection componentsThermal-magnetic and magnetic motor circuit breakers GV2 with screw clamp connectionsC i r c u i t b r e a k e r sTeSys GVDescriptionMounting Maximum number Type of contacts Sold inlots of Unitreference Instantaneous auxiliary contactsFront1N/O or N/C (1)10GVAE1N/O + N/C 10GVAE11 (2)N/O + N/O10GVAE20 (2)Side (LH)2N/O + N/C1GVAN11 (2)N/O + N/O1GVAN20 (2)Fault signalling contact + instantaneous auxiliary contactFront 1N/O (fault)+ N/O1GVAED101 (2)N/O (fault)+ N/C1GVAED011 (2)Side (3) (LH)1N/O (fault)+ N/O1GVAD1010+ N/C1GVAD1001N/C (fault)+ N/O1GVAD0110+ N/C1GVAD0101Short-circuit signalling contact Side (LH)1C/O common point 1GVAM11(4)MountingVoltage ReferenceSide(1 block on RH side of circuit breaker)24 V 50 Hz GVA p 02560 Hz GVA p 02648 V 50 Hz GVA p 05560 Hz GVA p 05610050 Hz GVA p 107100…110 V 60 Hz GVA p 107110…115 V 50 Hz GVA p 11560 Hz GVA p 116120…127 V 50 Hz GVA p 125127 V 60 Hz GVA p 115200 V50 Hz GVA p 207200…220 V 60 Hz GVA p 207220…240 V 50 Hz GVA p 22560 Hz GVA p 226380…400 V 50 Hz GVA p 38560 Hz GVA p 386415…440 V 50 Hz GVA p 415415 V 60 Hz GVA p 416440 V 60 Hz GVA p 385480 V 60 Hz GVA p 415500 V 50 Hz GVA p 505600 V60 HzGVA p 505AccessoriesDescription Reference Sets of 3-pole 115 A busbars Pitch: 64 mm2 tap-off GV3 P pp and GV3 L pp GV3G2643 tap-off GV3 P pp and GV3 L pp GV3G364Cover “Large Spacing” UL 508 type E (Only one cover required on supply side)GV3 P ppGV3G66(1) Choice of N/C or N/O contact operation, depending on which way round the reversible block is mounted.(2) Contact blocks available in version with spring terminal connections. Add a figure 3 at the end of the references selected above. Example: GV AED101 becomes GV AED1013.(3) The GV AD pp is always mounted next to the circuit breaker.(4) To order an undervoltage trip: replace the dot (p ) in the reference with a U , example: GV AU025. To order a shunt trip: replace the dot (p ) in the reference with an S , example: GV AS025.Add-on blocks and accessoriesGV3 G66D F 537424.e p sTeSys GVD B 126637.e p sD B 126636.e p sD B 126632.e p s7P B 106297_45.e p sExtended Rotary HandleAllows a circuit breaker or a starter-controller installed in back of an enclosure to be operated from the front of the enclosure.A rotary handle can be black or red/yellow, IP54 or IP65. It includes a function for locking the circuit breaker or the starter in the O (Off) or I (On) position(depending of the type of rotary handle) by means of up to 3 padlocks with a shank diameter of 4 to 8 mm. The extended shaft must be adjusted to use in different size enclosures. The IP54 rotary handle is fixed with a nut (Ø22) to make easierthe assembling. The new Laser Square tool brings the accurency to align the circuit breaker and the rotary handle.For English 10-GVAPSEN For German 10-GVAPSDE For Spanish10-GVAPSES For Chinese 10-GVAPSCN For Portuguese 10-GVAPSPT For Russian 10-GVAPSRU For Italian10-GVAPSITD F 526342.e p sB6/21C i r c u i t b r e a k e r sTeSys GVfor locking the Start button (on open-mounted product)using up to 3 padlocks(padlocks to be ordered separately)External operator for mounting on enclosure door.Red Ø40 knob on yellow plate, padlockable in position O (with up to 3 padlocks). Door locked when knob in position I, and when knob padlocked in position O.GK3AP03(1) 1 voltage trip OR 1 fault signalling contact to be fitted inside the motor circuit breaker.Other versions24 to 690 V, 50 or 60 Hz voltage trips for circuit breakers GV3 ME80.Please consult your Regional Sales Office.ReferencesTeSys protection componentsMotor circuit breakers GV3 ME80 and GK3 EF80Add-on blocks and accessoriesCharacteristics:pages B6/89 and B6/92Dimensions:page B6/47B6/22D F 526344.e p sB6/23C i r c u i t b r e a k e r sTeSys GVThese allow remote indication of the circuit breaker contact states. They can be used for signalling, electrical locking, relaying, etc. They are available in two versions: standard and low level. They include a terminal block and the auxiliary circuits leave the circuit breaker through a hole provided for this purpose.They perform the following functions, depending on where they are located in the circuit breaker:Low levelGV7AB11Fault discrimination devicesThese make it possible to:b either differentiate a thermal fault from a magnetic fault,b or open the contactor only in the event of a thermal fault.VoltageReference a 24...48 and c 24…72 V GV7AD111 (1)z 110…240 VGV7AD112 (1)Electric tripsThese allow the circuit breaker to be tripped via an electrical control signal.b Undervoltage trip GV7 AUv Trips the circuit breaker when the control voltage drops below the tripping threshold, which is between 0.35 and 0.7 times the rated voltage.v Circuit breaker closing is only possible if the voltage exceeds 0.85 times the rated voltage. Circuit breaker tripping by a GV7 AU trip meets the requirements of IEC 60947-2.b Shunt trip GV7 ASTrips the circuit breaker when the control voltage rises above 0.7 times the rated voltage.b Operation (GV7 AU or GV7 AS)v When the circuit breaker has been tripped by a GV7 AU or AS, it must be reset either locally or by remote control. (For remote control, please consult your Regional Sales Office).v Tripping has priority over manual closing: if a tripping instruction is present, manual action does not result in closing, even temporarily, of the contacts.v Durability: 50 % of the mechanical durability of the circuit breaker.TypeVoltageReference Undervoltage trip48 V, 50/60 HzGV7AU055 (1)110…130 V, 50/60 Hz GV7AU107 (1)200…240 V, 50/60 Hz GV7AU207 (1)380…440 V, 50/60 Hz GV7AU387 (1)525 V, 50 HzGV7AU525 (1)Shunt trip48 V, 50/60 HzGV7AS055 (1)110…130 V, 50/60 Hz GV7AS107 (1)200…240 V, 50/60 Hz GV7AS207 (1)380…440 V, 50/60 Hz GV7AS387 (1)525 V, 50 HzGV7AS525 (1)(1) For mounting of a GV7 AD or a GV7 AU or AS.ReferencesTeSys protection componentsThermal-magnetic motor circuit breakers GV7 R with screw clamp connectionsAdd-on blocks and accessoriesCharacteristics:pages B6/51, B6/52 and B6/56Dimensions:pages B6/79 to B6/81Schemes:page B6/83B6/24B6/25C i r c u i t b r e a k e r sTeSys GVDescription ApplicationFor use on contactors Sold in lots of Unitreference Clip-on connectors for GV7 RUp to 150 A, 1.5…95 mm 2–3GV7AC021Up to 220 A, 1.5…185 mm 2–3GV7AC022Spreader 3-pole (1)To increase the pitch to 45 mm–1GV7AC03Terminal shields IP 405 (1)Supplied with sealing accessory–1GV7AC01Phase barriersSafety accessories used when fitting of shields is impossible –2GV7AC04Insulating screens Ensure insulation between the connections and the backplate –2GV7AC05Kits for combination with contactor (2)Allowing link between thecircuit breaker and the contactor. The cover provides protection against direct finger contactLC1 F115…F1851GV7AC06LC1 F225 and F2651GV7AC07LC1 D115 and D1501GV7AC08Replaces the circuit breaker front cover; secured by screws. It includes a device for locking the circuit breaker in the O (Off) position by means of up to 3 padlocks with a shank diameter of 5 to 8 mm (padlocks not included). A conversion accessory allows the direct rotary handle to be mounted on the enclosure door. In this case, the door cannot be opened if the circuit breaker is in the “ON” position. Circuit breaker closing is inhibited if the enclosure door is open.Description TypeDegree of protection Reference Direct rotary handleBlack handle, black legend plate IP 40GV7AP03Red handle, yellow legend plateIP 40GV7AP04Adapter plate (3)Four mounting direct rotary handle on enclosure doorIP 43GV7AP05Allows a circuit breaker installed in the back of an enclosure to be operated from the front of the enclosure. It comprises:b a unit which screws onto the front cover of the circuit breaker,b an assembly (handle and front plate) to be fitted on the enclosure door,b an extension shaft which must be adjusted (distance between the mounting surface and the door: 185 mm minimum, 600 mm maximum). It includes a device for locking the circuit breaker in the O (Off) position by means of up to 3 padlocks with a shank diameter of 5 to 8 mm (padlocks not included). This prevents the enclosure door from being opened.DescriptionTypeDegree of protection Reference Extended rotary handleBlack handle, black legend plate IP 55GV7AP01Red handle, yellow legend plateIP 55GV7AP02Allows circuit breakers not fitted with a rotary handle to be locked in the O (Off) position by means of up to 3 padlocks with a shank diameter of 5 to 8 mm (padlocks not included).Description ApplicationReference Locking deviceFor circuit breaker not fitted with a rotary handleGV7V01(1) Terminal shields cannot be used together with spreaders.(2) The kit comprises links, a protective shield and a depth adjustable metal bracket for the breaker.(3) This conversion accessory makes it impossible to open the door if the device is closed and prevents the device from being closed if the door is open.ReferencesTeSys protection componentsThermal-magnetic motor circuit breakers GV7 R with screw clamp connectionsAccessoriesGV7 AC07D F 537429.e p sGV7 AC08D F 537428.e p sDimensions:pages B6/79 to B6/81B6/260.5 6.63GB2DB051143GB2DB062263GB2DB073403GB2DB084503GB2DB095663GB2DB106833GB2DB1281083GB2DB14101383GB2DB16121653GB2DB20162203GB2DB21202703GB2DB22(1) Conforming to IEC 60947-1.GB2 CBppD F 526243.t i fGB2 CD ppD F 526244.t i fGB2 DBppD F 526245.t i fPresentation, selection :page B6/84Characteristics :pages B6/85 to B6/87Dimensions :page B6/88Schemes :page B6/88B6/27C i r c u i t b r e a k e r s(1) Conforming to IEC 60947-1.Accessories for circuit breakers GB2-CB, DB and CSDescriptionSold in lots of Unitreference Busbar set for supply to 10 GB2 DB or20 GB2 CB or GB2 CS with 2 connectors1GB2G210Supply connector 10GB2G01GB2 CS ppD F 526246.t i fPresentation, selection :page B6/84Characteristics :pages B6/85 to B6/87Dimensions :page B6/88Schemes :page B6/88B6/28B6/29B6/30TeSys GVCharacteristicsTeSys protection componentsMagnetic motor circuit breakers GV2 LE and GV2 LReferences:pages B6/2 and B6/3Dimensions:pages B6/43 to B6/47Schemes:page B6/48add-on contact blocks. Side by side mounting is possible up to 40 °C.(2) When mounting on a vertical rail, fit a stop to prevent any slippage.(1) As % of Icu.Average operating times at 20 °C related to multiples of the setting currentD F 534092.e p s1 3 poles from cold state2 2 poles from cold state3 3 poles from hot stateDynamic stressI peak = f (prospective Isc) at 1.05 Ue = 435 VD F 534093.e p s1 Maximum peak current2 32 A3 25 A4 18 A5 14 A6 10 A7 6.3 A8 4 A9 2.5 A 10 1.6 A11 Limit of rated ultimate breaking capacity on short-circuit of GV2 LE (14, 18, 23 and 25 A ratings).Dynamic stressI peak = f (prospective Isc) at 1.05 Ue = 435 VD F 534094.e p s1 Maximum peak current2 32 A3 25 A4 18 A5 14 A6 10 A7 6.3 A8 4 A9 2.5 A 10 1.6 A11 Limit of rated ultimate breaking capacity on short-circuit of GV2 LE (14, 18, 23 and 25 A ratings).Thermal limit in kA 2s in the magnetic operating zone Sum of I 2dt = f (prospective Isc) at 1.05 Ue = 435 V22Prospective Isc (kA)D F 534095.e p s1 32 A 2 25 A3 18 A4 14 A5 10 A6 6.3 A7 4 A8 2.5 A9 1.6 AThermal limit in kA 2s in the magnetic operating zone Sum of I 2dt = f (prospective Isc) at 1.05 Ue = 435 V22D F 534096.e p s1 25 A and 32 A 2 18 A3 14 A 4 10 A5 6.3 A6 4 A7 2.5 A8 1.6 AThermal limit in kA 2s in the magnetic operating zone Sum of I 2dt = f (prospective Isc) at 1.05 Ue = 435 V22D F 534097.e p s1 32 A (GV2 LE32)2 25 A and 32 A (GV2 L32)3 18 A4 14 A5 10 A6 6.3 A7 4 A8 2.5 A9 1.6 A10 Limit of rated ultimate breaking capacity on short-circuit of GV2 LE (14, 18, 23 and 25 A ratings).Average operating time at 20 °C without prior current flowx the setting current (Ir)D F 534098.e p s1 3 poles from cold state2 2 poles from cold state3 3 poles from hot stateA Thermal overload relay protection zoneB GV3 L protection zoneDynamic stressI peak = f (prospective Isc) at 1.05 Ue = 435 VProspective Isc (kA)D B 418280.e p s1 Maximum peak current2 GV3 L653 GV3 L504 GV3 L405 GV3 L326 GV3 L25Thermal limit in A 2sSum of I 2dt = f (prospective Isc) at 1.05 Ue = 435 V2Prospective Isc (kA)D B 418279.e p s1 GV3 L652 GV3 L503 GV3 L404 GV3 L325 GV3 L25TeSys GVDimensions, mountingD F 537440.e p sD F 537441.e p sD F 537444.e p sTeSys protection componentsMagnetic motor circuit breakers GV2 L and GV2 LETeSys GVDimensions, mounting TeSys protection componentsMagnetic motor circuit breakers GV2 L and GV2 LED B 127415.e p sD B 127414.e p sa b Mini Maxi Mini Maxi GV2 APN pp140250GV2 APN pp + GV APH02151250GV2 APN pp + GV APK11250434--GV2 APN pp + GV APH02 + GV APK11--250445TeSys GVDimensions,mounting Sets of busbars GV2 G445, GV2 G454, GV2 G472, with terminal block GV2 G05D F 537451.e p sGV2 G445224269314359GV2 G454260314368422GV2 G472332404476548D F 537452.e p sD F 537454.e p sGV2 G345 (3 x 45 mm)134GV2 G354 (3 x 54 mm)152TeSys protection componentsMagnetic motor circuit breakers GV2 L and GV2 LED F 537480.e psD F 537435.e p sD F 510637.e p sD F 510638.e p sD B 127416.e p sD B 127417.e p sa b Mini Maxi Mini Maxi GV3 APN pp189300--GV3 APN pp + GV APK12300481GV3 APN pp + GV APH03--200300GV3 APN pp + GV APH03 + GV APK12--300492TeSys GVSchemesTeSys protection componentsMagnetic motor circuit breakers GV2 L, GV2 LE, GV3 LD F 537474.e p sD F 537475.e p sD F 537476.e p sGV2 ME, GV2 P , GV3 ME, GV3 P and GV7 R motor circuit breakers are 3-pole thermal-magnetic circuit breakers specifically designed for the control and protection of motors , conforming to standards IEC 60947-2 and IEC 60947-4-1.Connection GV2GV2 ME and GV2 P circuit breakers are designed for connection by screw clamp terminals.Circuit breaker GV2 ME can be supplied with lugs or spring terminal connections.Spring terminal connections ensure secure, permanent and durable clamping that is resistant to harsh environments, vibration and impact and are even more effective when conductors without cable ends are used. Each connection can take two independent conductors.GV3GV3 circuit breakers feature connection by BTR screws (hexagon socket head), tightened using a n° 4 Allen key.This type of connection uses the Ever Link ® system with creep compensation (1) (Schneider Electric patent).This technique makes it possible to achieve accurate and durable tightening torque, in order to avoid cable creep.GV3 circuit breakers are also available with connection by lugs. This type of connection meets the requirements of certain Asian markets and is suitable for applications subject to strong vibration, such as railway transport.GV7GV7 circuit breakers: with connection by screw clamp terminals (for bars and lugs) and by clip-on connectors.OperationControl is manual and local when the motor circuit breaker is used on its own.Control is automatic and remote when it is associated with a contactor.GV2 ME and GV3 ME80Pushbutton control.Energisation is controlled manually by operating the Start button “I” 1.De-energisation is controlled manually by operating the Stop button “O” 2, or automatically by the thermal-magnetic protection elements or by a voltage trip attachment.GV2 P , GV3 P and GV7 Rb Control by rotary knob: for GV2 P and GV3 P b Control by rocker lever: for GV7 R.Energisation is controlled manually by moving the knob or rocker lever to position “I” 1.De-energisation is controlled manually by moving the knob or rocker lever to position “O” 2.De-energisation due to a fault automatically places the knob or rocker lever in the “Trip” position 3.Re-energisation is possible only after having returned the knob or rocker lever to position “O”.(1) Creep: normal crushing phenomenon of copper conductors, that is accentuated over time.GV2 MEwith screw clamp terminals124D F 526134.t i fGV2 MEwith spring terminals connections124D F 526135.t i fGV3 P1324D F 526136.t ifGV2 P1342D F 526137.t i fGV7 R132D F 526138.t i f。
GS8322Z36GE-225V资料
GS8322Z18/36/72(B/E/C)-xxxV36Mb Pipelined and Flow ThroughSynchronous NBT SRAM250 MHz –133 MHz 1.8 V or 2.5 V V DD 1.8 V or 2.5 V I/O119, 165 & 209 BGA Commercial Temp Industrial Temp Features• NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs• 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply• User-configurable Pipeline and Flow Through mode • ZQ mode pin for user-selectable high/low output drive • IEEE 1149.1 JTAG-compatible Boundary Scan • LBO pin for Linear or Interleave Burst mode• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices • Byte write operation (9-bit Bytes)• 3 chip enable signals for easy depth expansion • ZZ Pin for automatic power-down• JEDEC-standard 119-, 165- or 209-Bump BGA package • RoHS-compliant packages availableFunctional DescriptionThe GS8322Z18/36/72-xxxV is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.The GS8322Z18/36/72-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.The GS8322Z18/36/72-xxxV is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 119-bump, 165-bump or 209-bump BGA package.Parameter Synopsis-250-225-200-166-150-133Unit Pipeline 3-1-1-1KQ tCycle 4.0 4.4 5.0 6.0 6.77.5ns Curr (x18)Curr (x36)Curr (x72)275330415255300385240280340215245305205230285180205255mA mA mA Flow Through 2-1-1-1t KQ tCycle 6.57.07.58.08.58.5ns Curr (x18)Curr (x36)Curr (x72)200225300190215280180205255170195245160185230150170225mA mA mAGS8322Z18/36/72(B/E/C)-xxxVGS8322Z72C-xxxV Pad Out—209-Bump BGA—Top View (Package C)1234567891011A DQ G DQ G A E2A ADV A E3A DQB DQ B AB DQ G DQ G BC BG NC W A BB BF DQ B DQ B BC DQ G DQ G BH BD NC E1NC BE BA DQ B DQ B CD DQ G DQ G V SS NC NC G NC NC V SS DQ B DQ B DE DQP G DQP C V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPF DQP B EF DQ C DQ C V SS V SS V SS ZQ V SS V SS V SS DQ F DQ F FG DQ C DQ C V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQ F DQ F GH DQ C DQ C V SS V SS V SS MCL V SS V SS V SS DQ F DQ F H J DQ C DQ C V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQ F DQ F J K NC NC CK NC V SS CKE V SS NC NC NC NC K L DQ H DQ H V DDQ V DDQ V DD FT V DD V DDQ V DDQ DQ A DQ A L M DQ H DQ H V SS V SS V SS MCL V SS V SS V SS DQ A DQ A M N DQ H DQ H V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQ A DQ A N P DQ H DQ H V SS V SS V SS ZZ V SS V SS V SS DQ A DQ A P R DQP D DQP H V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQP A DQP E R T DQ D DQ D V SS NC NC LBO NC NC V SS DQ E DQ E T U DQ D DQ D NC A NC A A A NC DQ E DQ E U V DQ D DQ D A A A A1A A A DQ E DQ E V W DQ D DQ D TMS TDI A A0A TDO TCK DQ E DQ E W11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump PitchGS8322Z18/36/72(B/E/C)-xxxVGS8322Z72C-xxxV 209-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn IAddress InputsDQ A DQ B DQ C DQ D DQ E DQ F DQ G DQ H I/O Data Input and Output pinsB A , B B I Byte Write Enable for DQ A , DQ B I/Os; active low BC ,BD I Byte Write Enable for DQ C , DQ D I/Os; active low BE , BF , BG ,B HI Byte Write Enable for DQ E , DQ F , DQ G , DQ H I/Os; active lowNC —No ConnectCK I Clock Input Signal; active high E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowMCH I Must Connect High MCH IMust Connect High MCL Must Connect Low W I Write Enable; active low ZQ I FLXDrive Output Impedance Control Low = Low Impedance [High Drive], High = High Impedance [Low Drive]CKEIClock Enable; active lowGS8322Z18/36/72(B/E/C)-xxxVTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322Z72C-xxxV 209-Bump BGA Pin DescriptionSymbolTypeDescriptionGS8322Z18/36/72(B/E/C)-xxxVGS8322Z36B-xxxV Pad Out—119-Bump BGA—Top View 1234567A V DDQ A A A A A V DDQ A B NC E2A ADV A E3NC B C NC A A V DD A A NC C D DQC DQPC V SS ZQ V SS DQPB DQB D E DQC DQC V SS E1V SS DQB DQB E F V DDQ DQC V SS G V SS DQB V DDQ F G DQC DQC BC A BB DQB DQB G H DQC DQC V SS W V SS DQB DQB H J V DDQ V DD NC V DD NC V DD V DDQ J K DQD DQD V SS CK V SS DQA DQA K L DQD DQD BD NC BA DQA DQA L M V DDQ DQD V SS CKE V SS DQA V DDQ M N DQD DQD V SS A1V SS DQA DQA N P DQD DQPD V SS A0V SS DQPA DQA P R NC A LBO V DD FT A NC R T NC NC A A A A ZZ T UV DDQTMSTDITCKTDONCV DDQU7 x 17 Bump BGA—14 x 22 mm 2 Body—1.27 mm Bump Pitch(Package B)GS8322Z18/36/72(B/E/C)-xxxVGS8322Z18B-xxxV Pad Out—119-Bump BGA—Top View 1234567A V DDQ A A A A A V DDQ A B NC E2A ADV A E3NC B C NC A A V DD A A NC C D DQB NC V SS ZQ V SS DQPA NC D E NC DQB V SS E1V SS NC DQA E F V DDQ NC V SS G V SS DQA V DDQ F G NC DQB BB A NC NC DQA G H DQB NC V SS W V SS DQA NC H J V DDQ V DD NC V DD NC V DD V DDQ J K NC DQB V SS CK V SS NC DQA K L DQB NC NC NC BA DQA NC L M V DDQ DQB V SS CKE V SS NC V DDQ M N DQB NC V SS A1V SS DQA NC N P NC DQPB V SS A0V SS NC DQA P R NC A LBO V DD FT A NC R T NC A A A A A ZZ T UV DDQTMSTDITCKTDONCV DDQU7 x 17 Bump BGA—14 x 22 mm 2 Body—1.27 mm Bump Pitch(Package B)GS8322Z18/36/72(B/E/C)-xxxVGS8322Z18/36B-xxxV 119-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active high CKE I Clock Enable; active low W I Write Enable; active low E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable ZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance ControlLow = Low Impedance [High Drive], High = High Impedance [Low Drive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyBPR1999.05.18GS8322Z18/36/72(B/E/C)-xxxV165 Bump BGA—x18 Common I/O—Top View 1234567891011A NC A E1BB NC E3CKE ADV A A A A B NC A E2NC BA CK W G A A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA C D NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA D E NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA E F NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA F G NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA G H FT MCH NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC J K DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC K L DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC L M DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC M N DQPB NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P RLBOAAATMSA0TCKAAAAR11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch(Package E)GS8322Z18/36/72(B/E/C)-xxxV165 Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3CKE ADV A A NC A B NC A E2BD BA CK W G A A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCH NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD NC V DDQ V SS NC NC NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A NC P RLBOAAATMSA0TCKAAAAR11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch(Package E)GS8322Z18/36/72(B/E/C)-xxxVGS8322Z18/36E-xxxV 165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs A 18I Address Input DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active high CKE I Clock Enable; active low W I Write Enable; active low E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high FT I Flow Through / Pipeline Mode ControlG I Output Enable; active lowADV I Burst address counter advance enable; active highZQ I FLXDrive Output Impedance ControlLow = Low Impedance [High Drive], High = High Impedance [Low Drive])ZZ I Sleep mode control; active high LBO I Linear Burst Order mode; active lowTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCH —Must Connect High V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322Z18/36/72(B/E/C)-xxxVFunctional DetailsClockingDeassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.Pipeline Mode Read and Write OperationsAll inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E 1, E 2, and E 3). Deassertion of any one of the Enable inputs will deactivate the device. Function W B A B B B C B D Read H X X X X Write Byte “a”L L H H H Write Byte “b”L H L H H Write Byte “c”L H H L H Write Byte “d”L H H H L Write all Bytes L L L L L Write Abort/NOPLHHHHRead operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E 1, E 2, and E 3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B A , B B , B C, and B D ) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.Flow Through Mode Read and Write OperationsOperation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.Synchronous Truth TableOperationType Address CK CKE ADV W Bx E 1E 2E 3G ZZDQNotesRead Cycle, Begin Burst R External L-H L L H X L H L L L Q Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3Write Cycle, Continue Burst B Next L-H L H X L X X X X L D1,3,10Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle D None L-H L L L H L H L X L High-Z 1Deselect Cycle, Continue DNone L-H L H X X X X X X L High-Z 1Sleep ModeNone X X X X X X X X X H High-Z Clock Edge Ignore, StallCurrentL-HHXXXXXXXL-4Notes:1.Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-lect cycle is executed first.2.Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the Wpin is sampled low but no Byte Write pins are active so no write operation is performed.3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off duringwrite cycles.4.If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the buswill remain in High Z.5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Writesignals are Low6.All inputs, except G and ZZ must meet setup and hold times of rising clock edge.7.Wait states can be inserted by setting CKE high.8.This device contains circuitry that ensures all outputs are in High Z during power-up.9. A 2-bit burst counter is incorporated.10.The address counter is incriminated for all Burst continue cycles.GS8322Z18/36/72(B/E/C)-xxxVGS8322Z18/36/72(B/E/C)-xxxVDeselectNew ReadNew WriteBurst ReadBurst WriteWRBRBWDDBBWRD BWRDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input commandcodes as indicated in the Synchronous Truth Table.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipelined and Flow through Read/Write Control State DiagramWRPipelined and Flow Through Read Write Control State DiagramGS8322Z18/36/72(B/E/C)-xxxVPipeline Mode Data I/O State Diagram IntermediateIntermediateIntermediateIntermediateIntermediateIntermediateHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)TransitionƒInput Command CodeKeyTransitionIntermediate State (N+1)Notes1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateIntermediate ƒn n+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipeline Mode Data I/O State DiagramNext StateStateGS8322Z18/36/72(B/E/C)-xxxVFlow Through Mode Data I/O State Diagram High Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for: Pipeline and Flow Through Read Write Control State DiagramGS8322Z18/36/72(B/E/C)-xxxVBurst CyclesAlthough NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.Burst OrderThe burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have beenaccessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.FLXDrive™The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)Note:There are pull-up devices on the ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS8322Z18/36/72(B/E/C)-xxxVBurst Counter SequencesBPR 1999.05.18Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZStKLtKHtKCCKZZDesigning for CompatibilityThe GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal. Not all vendors offer this option, however most mark the pin V DD or V DDQ on pipelined parts and V SS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets. Other vendors mark the pin as a No Connect (NC). GSI RAMs have an internal pull-up device on the FT pin so a floating FT pin will result in pipelined operation. If the part being replaced is a pipelined mode part, the GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device, the pin will need to be pulled low for correct operation.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage on V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125oCT BIASTemperature Under Bias–55 to 125o CGS8322Z18/36/72(B/E/C)-xxxVNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version)ParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.7 1.82.0V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 1.8 V V DDQ I/O Supply Voltage V DDQ1 1.7 1.8V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8322Z18/36/72(B/E/C)-xxxVV DDQ2 & V DDQ1 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low VoltageV IL–0.3—0.3*V DDV1Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceFigure 1Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 1Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS8322Z18/36/72(B/E/C)-xxxVDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, ZQ, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output Characteristics (1.8 V/2.5 V Version)ParameterSymbolTest ConditionsMinMax1.8 V Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V —2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V1.7 V —1.8 V Output Low Voltage V OL1I OL = 4 mA —0.4 V2.5 V Output Low VoltageV OL2I OL = 8 mA—0.4 VGS8322Z18/36/72(B/E/C)-xxxVO p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 72)P i p e l i n eI D DI D D Q380354003535035370353203034030280253002526025280252352025520m AF l o w T h r o u g hI D DI D D Q275252852525525265252352024520225202352021020220202101522015m A(x 36)P i p e l i n eI D DI D D Q300303203027525295252552527525225202452021020230201901521015m AF l o w T h r o u g hI D DI D D Q210152201520015210151901520015180151901517015180151601017010m A(x 18)P i p e l i n eI D DI D D Q260152801524015260152251524515200152201519015210151701019010m AF l o w T h r o u g hI D DI D D Q190102001018010190101701018010160101701015010160101401015010m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 608060806080608060806080m AF l o w T h r o u g hI S B608060806080608060806080m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D100115951109010585100851008095m AF l o w T h r o u g hI D D85100851008095809575907085m AN o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .。
S-8324中文资料
元器件交易网ContentsFeatures (1)Applications (1)Block Diagram (1)Selection Guide (2)Pin Assignment (3)Absolute Maximum Ratings (3)Electrical Characteristics (4)Test Circuits (9)Operation (9)External Parts Selection for DC-DC Converter (12)Standard Circuits (16)Precautions (18)Application Circuits (19)Dimensions (24)Markings (24)Taping (25)Temperature Characteristics (28)Characteristics for the Power Voltage (30)Ripple characteristics (31)Transient Responses (32)Operation Start Voltage and Operation HoldingVoltage Characteristics for Output Current (34)Input Voltage Characteristics for Input Current (34)Reference Data (35)Frequently Asked Questions (48)Seiko Instruments Inc.1S-8324/8328 SeriesSMALL PACKAGE PWM/PFM CONTROL STEP-UP SWITCHING REGULATORThe S-8324/8328 is a series of CMOS PWM/PFM-control step-up switching regulators which mainly consist of a reference voltage source,an oscillation circuit, a power MOS FET (S-8324 Series) and an error amplifier. The new method PWM/PFM control circuit automatically switches the control method according to the current load, offering products of a wide range, high efficiency. A step-up switching regulator is constructed by externally connecting only a coil, a capacitor and a diode to the S-8324 Series. This feature, along with its small package and low current consumption, makes the S-8324 Series ideal for the power supply of portable equipment. For applications requiring a high output current, products used with an external transistor (S-8328 Series)are also available.FeaturesApplicationsLow voltage operation : 0.9 V (I OUT = 1mA) Power supplies for portable equipment such as Low current consumption :pagers, handy calculators, and remote controllers During operation : 17.2µA (typ.)Constant voltage power supplies for cameras,(V OUT = 3 V, 50 kHz)video equipment, and communications equipment During shutdown : 0.5µA (max.)Power supply for microcomputersLow Input current : 10.4µA ( typ.)(V OUT = 3 V, 50 kHz, no load)Duty ratio :During PWM control : 15 to 83 % typ.During PFM control : 15 % typ.External parts: coil, diode, and capacitor only(a transistor is needed for the S-8328 Series.)Output voltage: accuracy of ±2.4% Software start function : 6 msec (typ.) Shutdown functionExternal transistor type is available (S-8328 Series) SOT-23-5 small plastic package SOT-23-3 small plastic packageSOT-89-3 miniature power molded plastic package Step-down and invert type are also available.Block Diagram(1)S-8324 Series(2)S-8328 SeriesFigure 1 Block Diagram(ON / OFF)EXT(ON / OFF)V SSV OUTCONTPWM/PFM control circuit-+VREFV SSV OUTPWM/PFM control circuit-+VREFSoft start circuitSoft start circuitSMALL PACKAGE PWM/PFM CONTROL STEP-UP SWITCHING REGULATORS-8324/8328 Series2Seiko Instruments Inc.Selection Guide1. Product Name`S - 832 X X XX XX - XXX - T2Tape SpecificationProduct name (abbreviation)Package name (abbreviation)MA ; SOT-23-3 (without shutdown function )MC ; SOT-23-5 (with shutdown function, V DD /V OUT separate product )UA ; SOT-89-3 (without shutdown function )Output voltage (symbol) ×10Product categoryA ; Normal product, fosc=50 kHz (S-8324 only)B ; Normal product, fosc=100 kHz (S-8328 only)C ; For pagers, fosc=30 kHz (S-8324 only)D ; V DD /V OUT separate product, fosc=50 kHz (S-8324 only)E ; V DD /V OUT separate product, fosc=100 kHz (S-8328 only)Power transistor4 ; Built-in PWM/PFM control switch.8 ; PWM/PFM control switch with an external transistor.2. Product ListOutput voltage(v)S-8324AXXMCSeries S-8324AXXMASeries S-8324AXXUA Series S-8324CXXMA Series S-8324DXXMCSeries 2.0————S-8324D20MC-E2A-T22.5S-8324A25MC-EOF-T2S-8324A25MA-EOF-T2S-8324A25UA-EOF-T2S-8324C25MA-EQF-T2—2.7S-8324A27MC-EOH-T2S-8324A27MA-EOH-T2S-8324A27UA-EOH-T2S-8324C27MA-EQH-T2—2.8S-8324A28MC-EOI-T2————3.0S-8324A30MC-EOK-T2S-8324A30MA-EOK-T2S-8324A30UA-EOK-T2S-8324C30MA-EQK-T2S-8424D30MC-E2K-T23.3S-8324A33MC-EON-T2S-8324A33MA-EON-T2S-8324A33UA-EON-T2——5.0S-8324A50MC-EPE-T2S-8324A50MA-EPE-T2S-8324A50UA-EPE-T2—S-8324D50MC-E4E-T2Output voltage(v)S-8328BXXMCSeries S-8328BXXMASeries S-8328BXXUA Series S-8328EXXMCSeries 2.0———S-8328E20MC-EYA-T22.5S-8328B25MC-EWF-T2S-8328B25MA-EWF-T2S-8328B25UA-EWF-T2—2.7S-8328B28MC-EWH-T2S-8328B28MA-EWH-T2S-8328B28UA-EWH-T2—3.0S-8328B30MC-EWK-T2S-8328B30MA-EWK-T2S-8328B30UA-EWK-T2—3.3S-8328B33MC-EWN-T2S-8328B33MA-EWN-T2S-8328B33UA-EWN-T2—3.6S-8328B36MC-EWQ-T2———3.8S-8328B38MC-EWS-T2———5.0S-8328B50MC-EXE-T2S-8328B50MA-EXE-T2S-8328B50UA-EXE-T2S-8328E50MC-E9E-T25.2S-8328B52MC-EXG-T2———Consult our sales person for products with an output voltage other than specified above.3. Function ListProduct Name Built In power transistor with external power transistor Switching frequency (KHz)Shutdown function V DD /V OUTseparate type Package Application ReferencepageS-8324AXXMC Yes —50Yes —SOT-23-5With a shutdown function —S-8324AXXMA Yes —50——SOT-23-3without shutdown function —S-8324AXXUA Yes —50——SOT-89-3without shutdown function —S-8324DXXMC Yes —50—Yes SOT-23-5For variable output voltage by step-up DC/DC converter and step-down inverted output DC/DC converter with an external resistorPage.15S-8324CXXMA Yes —30——SOT-23-3For pagers —S-8328BXXMC —Yes 100Yes —SOT-23-5For large load current with shutdown functionPage.14 to 15S-8328BXXMA —Yes 100——SOT-23-3For large load current without shutdown functionPage.14 to 15S-8328BXXUA —Yes 100——SOT-89-3For large load current without shutdown functionPage.14 to 15S-8328EXXMC —Yes 100—Yes SOT-23-5For variable output voltage bystep-up DC/DC converter with anexternal resistorPage.15SMALL PACKAGE PWM/PFM CONTROL STEP-UP SWITCHING REGULATORS-8324/8328 SeriesSeiko Instruments Inc.Pin AssignmentFigure 2 Absolute Maximum RatingsNote:A protect circuit for static electricity is built into this IC chip.However, prevent a charge of static electricity which exceeds the capacity of the protect circuit.Pin No.Pin nameFunctions1ON / OFF Shutdown pin“H”:normal operation(stepping up operation)“L”:stop stepping up (whole circuit stop)2V OUT Output voltage pin and powersupply pin3—N.C. (Non Connection)4V SS GND pinCONT External inductor connectionpin (for S-8324 Series)EXT External transistor connectionpin (for S-8328 Series)Pin No. Pin name Functions1V OUT Output voltage pin 2V DDPower supply pin3—N.C. (Non Connection)4V SS GND pinCONT External inductor connection pin (for S-8324 Series)EXTExternal transistor connection pin (for S-8328 Series)Pin No.Pin name Functions 1V SS GND pin 2V OUT Output voltage pin and powersupply pinCONT External inductor connectionpin (for S-8324 Series)EXT External transistor connectionpin (for S-8328 Series)Parameter Symbol Ratings Unit VOUT pin voltage V OUT 11V ON/OFF pin voltage ON/OFF V ss - 0.3 to 11V CONT pin voltage V CONT 11V CONT pin current I CONT 300mA EXT pin voltage V EXT V ss - 0.3 to V OUT +0.3V EXT pin current I EXT±50mA Power dissipation PD SOT-89-3500mWSOT-23-5, SOT-23-3150Operating temperature T OPR -40 to +85 C Storage temperatureT STG-40 to +125C 231SOT-23-3Top view54321SOT-23-5Top view321SOT-89-3Top view5S-8324AXXMC, S-8328BXXMC SOT-23-55S-8324DXXMC, S-8328EXXMC SOT-23-5 S-8324AXXMA, S-8324AXXUA, S-8324CXXMA S-8328BXXMA, S-8328BXXUA SOT-23-3, SOT-89-33( Unless otherwise specified: Ta=25 C)SMALL PACKAGE PWM/PFM CONTROL STEP-UP SWITCHING REGULATORS-8324/8328 Series4Seiko Instruments Inc.Electrical Characteristics1-1.S-8324AXXMC(Unless otherwise specified: Ta=25°C)Parameter Symbol ConditionsMin.Typ.Max.Unit Test circuitS-8324A50MC4.8805.000 5.120S-8324A33MC 3.221 3.300 3.379Output voltage V OUTS-8324A30MC 2.928 3.000 3.072S-8324A28MC 2.733 2.800 2.867S-8324A27MC 2.635 2.700 2.765V 1S-8324A25MC2.440 2.500 2.560Input voltageV IN ——9Operation start voltage V ST1I OUT =1mA——0.9Oscillation start voltage V ST2No external parts, voltage applied to V OUT CONTpulled up to 5 V by 10k Ω——0.82Operation holding voltageV HLDI OUT =1mA, Measured by decreasing V IN voltage gradually0.7——V1S-8324A50MC —10.521.1S-8324A33MC—10.420.8Input current at no load I INNo load S-8324A30MC—10.420.7—S-8324A28MC —10.521.0S-8324A27MC —10.521.1S-8324A25MC —10.521.0S-8324A50MC —30.250.3S-8324A33MC—19.131.8Current consumption 1I SS1V OUT =output voltage ×0.95S-8324A30MC—17.228.7S-8324A28MC —16.126.8S-8324A27MC —15.525.9µAS-8324A25MC —14.323.92S-8324A50MC — 3.5 6.9S-8324A33MC— 3.3 6.5Current consumption 2I SS2V OUT =output voltage+0.5S-8324A30MC— 3.2 6.4S-8324A28MC — 3.2 6.4S-8324A27MC — 3.2 6.4S-8324A25MC— 3.2 6.3Current consumption during shutdownI SSSshutdown pin=0V——0.5S-8324A50MC 114182—S-8324A33MC 78125—Switching current I SW VCONT=0.4V S-8324A30MC 78125—mAS-8324A28MC 6198—S-8324A27MC 6198——S-8324A25MC6198—Switchin transistor leak currentI SWQ V OUT = VCONT=10V—— 1.0µA Line regulation ∆V OUT1V IN =output voltage ×0.4 to ×0.6—3060mVLoad regulation ∆V OUT2I OUT =10µA to I OUT (below) ×1.25—3060S-8324A50MC —±0.25—Output voltage S-8324A33MC —±0.17—1temperature ∆V OUT /∆Ta Ta=-40°C to +85°CS-8324A30MC —±0.15—mV/°CcoefficientS-8324A28MC —±0.14—S-8324A27MC —±0.14—S-8324A25MC—±0.13—Oscillation frequency fosc V OUT =output voltage ×0.95Measured waveform at CONT pin 42.55057.5kHz1Max duty ratioMaxDuty V OUT =output voltage ×0.95Measured waveform at CONT pin 758390%PWM/PFM control switch duty ratio PFMDuty V IN = output voltage - 0.1V No load515241Shutdown pin VSH V OUT =output voltage ×0.95Measured the oscillation at CONT pin 0.75——Input voltage (ON/OFF type)VSL1V OUT =output voltage ×0.95WhenV OUT ≥1.5V——0.3V2VSL2Judged the stop of oscillation at CONT pin When V OUT <1.5V——0.2Soft start time T SS3.0 6.012.0ms—S-8324A50MC—87—S-8324A33MC —83—Efficiency EFFI S-8324A30MC —83—%1S-8324A28MC —79—S-8324A27MC —79—S-8324A25MC—79—External parts used:-Coil:CD54 (100µH) of Sumida Electric Co., Ltd.-Diode:MA720 (schottky type) of Matsushita Electronic Components Co., Ltd.-Capacitor:F93 (16V, 22µF, tantalum type) of Nichicon Corporation)Applied V IN =output voltage ×0.6, I OUT =output voltage/250ΩThe shutdown pin is connected to V OUT pin.Note 1:The output voltage specified above is the typical value.SMALL PACKAGE PWM/PFM CONTROL STEP-UP SWITCHING REGULATORS-8324/8328 SeriesSeiko Instruments Inc.51-2.S-8324AXXMA, S-8324AXXUA, S-8324DXXMC(Unless otherwise specified: Ta=25°C)Parameter Symbol ConditionsMin.Typ.Max.Unit Test circuitS-8324X50XX4.8805.000 5.120S-8324X33XX 3.221 3.300 3.379Output voltage V OUTS-8324X30XX 2.928 3.000 3.072S-8324X27XX 2.635 2.700 2.765V 1S-8324X25XX 2.440 2.500 2.560S-8324X20XX1.9522.000 2.048Input voltageV IN ——9Operation start voltage V ST1I OUT =1mA——0.9Oscillation start voltage V ST2No external parts, voltage applied to V OUT CONTpulled up to 5 V by 10k Ω——0.82Operation holding voltageV HLDI OUT =1mA, Measured by decreasing V IN voltage gradually0.7——V1S-8324X50XX —10.521.1S-8324X33XX—10.420.8Input current at no load I IN No load S-8324X30XX—10.420.7—S-8324X27XX —10.521.1S-8324X25XX —10.521.0S-8324X20XX —10.821.5S-8324X50XX —30.250.3S-8324X33XX—19.131.8Current consumption 1I SS1V OUT =output voltage ×0.95S-8324X30XX—17.228.7S-8324X27XX —15.525.9µAS-8324X25XX —14.323.9S-8324X20XX —11.619.42S-8324X50XX — 3.5 6.9S-8324X33XX— 3.3 6.5Current consumption 2I SS2V OUT =output voltage+0.5S-8324X30XX— 3.2 6.4S-8324X27XX — 3.2 6.4S-8324X25XX — 3.2 6.3S-8324X20XX — 3.1 6.2S-8324X50XX 114182—S-8324X33XX78125—Switching current I SW VCONT=0.4V S-8324X30XX78125—mAS-8324X27XX 6198—S-8324X25XX 6198——S-8324X20XX4571—Switchin transistor leak currentI SWQ V OUT = VCONT=10V—— 1.0µA Line regulation ∆V OUT1V IN = output voltage ×0.4 to ×0.6—3060mVLoad regulation ∆V OUT2I OUT =10µA to I OUT (below) ×1.25—3060S-8324X50XX —±0.25—Output voltage S-8324X33XX —±0.17—temperature ∆V OUT /∆Ta Ta=-40°C to +85°C S-8324X30XX —±0.15—mV/°C 1coefficientS-8324X27XX —±0.14—S-8324X25XX —±0.13—S-8324X20XX—±0.10—Oscillation frequency fosc V OUT =output voltage ×0.95Measured waveform at CONT pin 42.55057.5kHz2Max duty ratioMaxDuty V OUT =output voltage ×0.95Measured waveform at CONT pin 758390%PWM/PFM control switch duty ratioPFMDuty V IN = output voltage - 0.1V No load515241Soft start timeT SS3.0 6.012.0ms—S-8324X50XX —87—S-8324X33XX —83—Efficiency EFFI S-8324X30XX —83—%1S-8324X27XX —79—S-8324X25XX —79—S-8324X20XX—75—External parts used:-Coil:CD54 (100µH) of Sumida Electric Co., Ltd.-Diode:MA720 (schottky type) of Matsushita Electronic Components Co., Ltd.-Capacitor:F93 (16V, 22µF, tantalum type) of Nichicon Corporation)Applied V IN =output voltage ×0.6, I OUT =output voltage/250ΩThe V DD pin is connected to V OUT pin for V DD /V OUT separate product.Note 1:The output voltage specified above is the typical value.Note 2:V DD /V OUT Separate products:Boot operation is performed from V DD =0.8V.However, 2.0 V or more voltage for V DD is recommended to stabilize the output voltage and oscilation frequency.SMALL PACKAGE PWM/PFM CONTROL STEP-UP SWITCHING REGULATORS-8324/8328 Series6Seiko Instruments Inc.1-3.S-8324CXXMA(Unless otherwise specified: Ta=25°C)ParameterSymbolConditionsMin.Typ.Max.Unit Test circuitS-8324C30MA2.9283.000 3.072Output voltage V OUT S-8324C27MA 2.635 2.700 2.765V1S-8324C25MA2.440 2.500 2.560Input voltageV IN ——9Operation start voltage V ST1I OUT =1mA——0.9Oscillation start voltage V ST2No external parts, voltage applied to V OUT CONTpulled up to 5 V by 10k Ω——0.82Operation holding voltageV HLD I OUT =1mA, Measured by decreasing V IN voltage gradually0.7——V1S-8324C30MA—9.619.1Input current at no load I INNo load S-8324C27MA—9.519.1—S-8324C25MA —9.719.3S-8324C30MA—11.619.3Current consumption 1I SS1V OUT =output voltage ×0.95S-8324C27MA—10.517.5µAS-8324C25MA —9.816.32S-8324C30MA— 3.0 5.9Current consumption 2I SS2V OUT =output voltage+0.5S-8324C27MA— 2.9 5.8S-8324C25MA — 2.9 5.8S-8324C30MA78125—mASwitching current I SW VCONT=0.4V S-8324C27MA6198——S-8324C25MA6198—Switchin transistor leak currentI SWQ V OUT = VCONT=10V—— 1.0µA Line regulation ∆V OUT1V IN =output voltage ×0.4 to ×0.6—3060mV Load regulation ∆V OUT2I OUT =10µA to I OUT (below) ×1.25—3060Output voltage S-8324C30MA —±0.15—mV/°Ctemperature ∆V OUT /∆Ta Ta=-40°C to +85°CS-8324C27MA —±0.14—1coefficientS-8324C25MA—±0.13—Oscillation frequency fosc V OUT =output voltage ×0.95Measured waveform at CONT pin 253035kHz2Max duty ratioMaxDuty V OUT =output voltage ×0.95Measured waveform at CONT pin 758390%PWM/PFM control switch duty ratioPFMDuty V IN = output voltage - 0.1V No load515241Soft start time T SS 3.0 6.012.0ms —S-8324C30MA —81—%EfficiencyEFFIS-8324C27MA —77—1S-8324C25MA—77—External parts used:-Coil:CD54 (100µH) of Sumida Electric Co., Ltd.-Diode:MA720 (schottky type) of Matsushita Electronic Components Co., Ltd.-Capacitor:F93 (16V, 22µF, tantalum type) of Nichicon Corporation)Applied V IN =output voltage ×0.6, I OUT =output voltage/250ΩNote 1:The output voltage specified above is the typical value.SMALL PACKAGE PWM/PFM CONTROL STEP-UP SWITCHING REGULATORS-8324/8328 SeriesSeiko Instruments Inc.72-1.S-8328BXXMC(Unless otherwise specified: Ta=25°C)Parameter Symbol ConditionsMin.Typ.Max.Unit Test circuitS-8328B52MC5.075 5.200 5.325S-8328B50MC 4.880 5.000 5.120S-8328B38MC 3.709 3.800 3.891Output voltage V OUTS-8328B36MC 3.514 3.600 3.686S-8328B33MC 3.221 3.300 3.379S-8328B30MC 2.928 3.000 3.072V 3S-8328B27MC 2.635 2.700 2.765S-8328B25MC2.440 2.500 2.560Input voltageV IN ——9Operation start voltage V ST1I OUT =1mA——0.9Oscillation start voltage V ST2No external parts, voltage applied to V OUT ——0.84Operation holding voltage V HLDI OUT =1mA, Measured by decreasing V IN voltage gradually0.7——V3S-8328B52MC —39.365.5S-8328B50MC —37.662.6S-8328B38MC—27.646.0Current consumption 1I SS1V OUT =output voltage ×0.95S-8328B36MC—26.043.3S-8328B33MC —23.739.5S-8328B30MC —21.435.7S-8328B27MC —19.232.0S-8328B25MC —17.829.7µA 4S-8328B52MC — 4.28.3S-8328B50MC — 4.28.3S-8328B38MC— 4.08.0Current consumption 2I SS2V OUT =output voltage+0.5S-8328B36MC— 4.07.9S-8328B33MC — 4.07.9S-8328B30MC — 3.97.8S-8328B27MC — 3.97.7S-8328B25MC— 3.97.7shutdown current I SSSshutdown pin=0V——0.5S-8328B52MC -5.3-8.0—S-8328B50MC -5.3-8.0—S-8328B38MC-3.5-5.3—I EXTHVCONT=-0.4V S-8328B36MC-3.5-5.3—S-8328B33MC -3.5-5.3—S-8328B30MC -3.5-5.3—S-8328B27MC -2.7-4.0—EXT pin output current S-8328B25MC -2.7-4.0—mA —S-8328B52MC 10.716.0—S-8328B50MC 10.716.0—S-8328B38MC7.010.5—I EXTLVCONT=0.4V S-8328B36MC7.010.5—S-8328B33MC 7.010.5—S-8328B30MC 7.010.5—S-8328B27MC 5.38.0—S-8328B25MC5.38.0—Line regulation ∆V OUT1V IN =output voltage ×0.4 to ×0.6—3060mVLoad regulation ∆V OUT2I OUT =10µA to I OUT (below) ×1.25—3060S-8328B52MC —±0.26—S-8328B50MC —±0.25—Output voltage S-8328B38MC—±0.19—temperature ∆V OUT /∆Ta Ta=-40°C to +85°C S-8328B36MC—±0.18—mV/°C 3coefficientS-8328B33MC —±0.17—S-8328B30MC —±0.15—S-8328B27MC —±0.14—S-8328B25MC—±0.13—Oscillation frequency fosc V OUT =output voltage ×0.95Measured waveform at EXT pin 85100115kHz 4Max. duty ratioMaxDuty V OUT =output voltage ×0.95Measured waveform at EXT pin 758390%PWM/PFM control switch duty ratio PFMDuty V IN = output voltage - 0.1V No load515243Shutdown pin VSH V OUT =output voltage ×0.95Measured the oscillation at CONT pin 0.75——V4Input voltage (ON/OFF type)VSL1V OUT =output voltage ×0.95WhenV OUT ≥1.5V——0.3VSL2Judged the stop of oscillation at CONT pin When V OUT <1.5V——0.2Soft start timeT SS3.0 6.012.0ms—S-8328B52MC—88—S-8328B50MC —88—S-8328B38MC —84—Efficiency EFFI S-8328B36MC —84—%3S-8328B33MC —84—S-8328B30MC —84—S-8328B27MC —80—S-8328B25MC—80—External parts used:-Coil:CD54 (47µH) of Sumida Electric Co., Ltd.-Diode:MA720 (schottky type) of Matsushita Electronic Components Co., Ltd.-Capacitor:F93 (16V, 47µF, tantalum type) of Nichicon Corporation)-Transistor:2SD1628G of Sanyo Electronics -Base resistor (Rb): 1.0K Ω-Base capacitor (Cb):2200pF (ceramic)Applied V IN =output voltage ×0.6, I OUT =output voltage/50ΩThe shutdown pin is connected to V OUT pin.Note 1:The output voltage specified above is the typical value.SMALL PACKAGE PWM/PFM CONTROL STEP-UP SWITCHING REGULATORS-8324/8328 Series8Seiko Instruments Inc.2-2.S-8328BXXMA, S-8328BXXUA, S-8328EXXMC(Unless otherwise specified: Ta=25°C)Parameter Symbol ConditionsMin.Typ.Max.Unit Test circuitS-8328X50XX4.8805.000 5.120S-8328X33XX 3.221 3.300 3.379Output voltage V OUTS-8328X30XX 2.928 3.000 3.072S-8328X27XX 2.635 2.700 2.765V 3S-8328X25XX 2.440 2.500 2.560S-8328X20XX1.9522.000 2.048Input voltageV IN ——9Operation start voltage V ST1I OUT =1mA——0.9Oscillation start voltage V ST2No external parts, voltage applied to V OUT ——0.84Operation holding voltage V HLDI OUT =1mA, Measured by decreasing V IN voltage gradually0.7——V3S-8328X50XX —37.662.6S-8328X33XX—23.739.5Current consumption 1I SS1V OUT =output voltage ×0.95S-8328X30XX—21.435.7S-8328X27XX —19.232.0S-8328X25XX —17.829.7S-8328X20XX —14.524.1µA 4S-8328X50XX — 4.28.3S-8328X33XX— 4.07.9Current consumption 2I SS2V OUT =output voltage+0.5S-8328X30XX— 3.97.8S-8328X27XX — 3.97.7S-8328X25XX — 3.97.7S-8328X20XX — 3.87.6S-8328X50XX -5.3-8.0—S-8328X33XX -3.5-5.3—I EXTHVCONT=-0.4VS-8328X30XX -3.5-5.3—S-8328X27XX -2.7-4.0—S-8328X25XX -2.7-4.0—EXT pin output current S-8328X20XX -1.9-2.9—mA —S-8328X50XX 10.716.0—S-8328X33XX 7.010.5—I EXTLVCONT=0.4VS-8328X30XX 7.010.5—S-8328X27XX 5.38.0—S-8328X25XX 5.38.0—S-8328X20XX3.8 5.7—Line regulation ∆V OUT1V IN =output voltage ×0.4 to ×0.6—3060mVLoad regulation ∆V OUT2I OUT =10µA to I OUT (below) ×1.25—3060S-8328X50XX —±0.25—Output voltage S-8328X33XX —±0.17—temperature ∆V OUT /∆Ta Ta=-40°C to +85°CS-8328X30XX —±0.15—mV/°C 3coefficientS-8328X27XX —±0.14—S-8328X25XX —±0.13—S-8328X20XX—±0.10—Oscillation frequency fosc V OUT =output voltage ×0.95Measured waveform at EXT pin 85100115kHzMax. duty ratioMaxDuty V OUT =output voltage ×0.95Measured waveform at EXT pin 758390%4PWM/PFM control switch duty ratioPFMDuty V IN = output voltage - 0.1V No load515243Soft start timeT SS3.0 6.012.0ms—S-8328X50XX —88—S-8328X33XX —84—Efficiency EFFI S-8328X30XX —84—%3S-8328X27XX —80—S-8328X25XX —80—S-8328X20XX—76—External parts used:-Coil:CD54 (47µH) of Sumida Electric Co., Ltd.-Diode:MA720 (schottky type) of Matsushita Electronic Components Co., Ltd.-Capacitor:F93 (16V, 47µF, tantalum type) of Nichicon Corporation)-Transistor:2SD1628G of Sanyo Electronics -Base resistor (Rb): 1.0K Ω-Base capacitor (Cb):2200pF (ceramic)Applied V IN =output voltage ×0.6, I OUT =output voltage/50ΩThe V DD pin is connected to V OUT pin for V DD /V OUT separate product.Note 1:The output voltage specified above is the typical value.Note 2:V DD /V OUT Separate products:Boot operation is performed from V DD =0.8V.However, 2.0 V or more voltage for V DD is recommended to stabilize the output voltage and oscilation frequency.SMALL PACKAGE PWM/PFM CONTROL STEP-UP SWITCHING REGULATORS-8324/8328 SeriesSeiko Instruments Inc.9Test CircuitsOperation1.Step-Up DC/DC ConverterThe S-8324/8328 series is a DC/DC converter using a pulse frequency modulation method (PFM) or a pulse width modulation method (PWM) which are switched automatically according to the load current with a low current consumption.Especially in the region of 100µA output load current, a high-efficiency DC/DC converter is obtained.In conventional fixed-duty type PFM DC/DC converters, pulses are skipped at low output load current, causing fluctuation in ripple frequency of the output voltage, with the result of increase in ripple voltage.The S-8324/8328 series operates with the PWM control which changes the pulse width duty from 15% to 83% in the region of large output load current.The ripple voltage generated from switching can be removed easily through the filter because the switching frequency is constant.The S-8324/8328 series operates with the PFM control which skips the pulse of the duty 15% pulth width and output that pulse to the switching transistor according to the load current.From the above operation, the self current consumption is reduced from the blocking oscilation of the oscilation circuit, and a fall of efficiency can be protected in small load.The switching point between PWM and PFM control differs according to the external elements (coil, diode and other), input voltage and output voltage.See reference data about this.1.Figure 3V SSV OUT CONTV-+-+(ON/OFF)2.3.4.V SSV OUT V-+-+(ON/OFF)Rb EXTV SS(ON/OFF)V OUTCONT 10k-+AV SS(ON/OFF)V OUT-+AEXT CbOscilloscopeOscilloscopeS-8324/8328 Series10Seiko Instruments Inc.Shutdown pin:Stops or starts step-up operation.(Only for SOT-23-5 package products of A and B Series.)Turning the shutdown pin low stops operation of all the internal circuits and reduces current consumption significantly. Do NOT use the shutdown pin in floating state because it has a structure shown in Figure 4 and is not pulled up or pulled down internally. Do NOT apply voltage of between 0.3 V and 0.75 V to the shutdown pin because applying such voltage increases the current consumption. If the shutdown pin is not used, connect it to V OUT pin.The shutdown pin doesn’t have hysteresis.The following are basic equations [(1) through (7)] of the step-up switching regulator (see Figure 5.)Voltage at CONT pin the moment M1 is turned ON (current I L flowing through L is zero):The change in I L over time:Integration of the above equation (I L ):I L flows while M1 is turned ON (t ON ). The time of t ON is determined by the oscillation frequency of the OSC.The peak current (I PK ) after ton:Shutdown pinCR oscillationcircuit Output voltage “H”Operation Fixed “L”Stop~V IN *Figure 4ON/OFFV OUTV SS*Voltage obtained by extracting the voltage drop due to DC resistance of the inductor and the diode forward voltage from V IN.= = (2)dI L dt V LL V IN - V S LI L =t (3)V IN - V SL+-+-OSC C OUTCONTM1V INFigure 5LDi ON/OFFV OUTV A =V S (1)(V S : Non-saturated voltage of M1)I PK =t ON (4)V IN - V SLS-8324/8328 SeriesSeiko Instruments Inc.11The energy stored in L is represented with 1/2 L (I PK )2.When M1 is turned OFF (t OFF ), the energy stored in L is transmitted through a diode to the output capacitor. Then reverse voltage (V L ) is generated.V L = (V OUT +V D ) - V IN (5)(V D : Diode forward voltage)The voltage at CONT pin rises only by the voltage corresponding to V OUT +V D .The change in the current flowing through the diode into V OUT during t OFF :Integration of the above equation is as follows:I L =I PK -t (7)During t ON , the energy is stored in L and is not transmitted to V OUT . When receiving output current (I OUT ) from V OUT , the energy of the capacitor (C OUT ) is consumed. As a result, the pin voltage of C OUT is reduced, and goes to the lowest level after M1 is turned ON (t ON ). When M1 is turned OFF, the energy stored in L is transmitted through the diode to C OUT , and thevoltage of C OUT rises drastically. V OUT is a time function that indicates the maximum value (ripple voltage: V P-P ) when the current flowing through the diode into V OUT and load current (I OUT ) match.Next, the ripple voltage is found out as follows:I OUT vs t 1 (time) from when M1 is turned OFF ( after t ON ) to when V OUT reaches the maximum level:After (t OFF ), I L =0 (when the energy of the inductor is completely transmitted). Based on equation (7),= (10)When substituting equation (10) for equation (9),t 1=t OFF -t OFF ..........................................................................(11)Electric charge ∆Q1 which is charged in C OUT during t1:∆Q 1= ∫ I l dt = I PK ∫ dt -∫tdt=I PK t 1 -t 12 (12)When substituting equation (12) for equation (9):∆Q 1=I PK - (I PK - I OUT ) t 1 =t 1 (13)A rise in voltage (V P-P ) due to ∆Q1:V P-P ==t1 (14)When taking into consideration I OUT to be consumed during t1 and ESR (Electric Series Resistance) of C OUT , namely R ESR :V P-P ==t1 +R ESR - (15)== (6)dI LdtV L LV OUT +V D - V INLV OUT +V D - V INLI OUT =I PK -t 1 (8)∴t 1 = (I PK - I OUT ) (9)V OUT +V D - V INLV OUT +V D - V INLV OUT +V D - V INLI PKt OFF I PK I OUTV OUT +V D - V IN L 21t 10V OUT +V D - V INLt 10t 1212I PK +I OUTC OUT∆Q 1C OUT12I PK +I OUTC OUT∆Q 1C OUT12I PK +I OUTC OUTI OUT - t 12I PK +I OUT。
AD8232 中文产品数据手册
ADI中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI不对翻译中存在的差异或由此产生的错误负责。如需确认任何词语的准确性，请参考ADI提供 的最新英文版数据手册。
10866-001
AD8232 目录
特性................................................................................................... 1 应用................................................................................................... 1 功能框图 .......................................................................................... 1 概述................................................................................................... 1 修订历史 .......................................................................................... 2 技术规格 .......................................................................................... 3 绝对最大额定值............................................................................. 6 ESD警告...................................................................................... 6 引脚配置和功能描述 .................................................................... 7 典型工作特性 ................................................................................. 8 仪表放大器性能曲线............................................................... 8 运算放大器性能曲线............................................................. 11 右腿驱动(RLD)放大器性能曲线......................................... 14 基准电压缓冲器性能曲线 .................................................... 15 系统性能曲线 .......................................................................... 16 工作原理 ........................................................................................ 17 架构概览................................................................................... 17 仪表放大器 .............................................................................. 17 运算放大器 .............................................................................. 17 右腿驱动放大器...................................................................... 17 基准电压缓冲器...................................................................... 18 快速恢复电路 .......................................................................... 18 导联脱落检测 .......................................................................... 19 待机操作................................................................................... 19 输入保护................................................................................... 20 射频干扰(RFI) ......................................................................... 20 电源调整与旁路...................................................................... 20 折合到输入端的失调............................................................. 20 布局建议................................................................................... 20 应用信息 ........................................................................................ 21 消除电极失调 .......................................................................... 21 高通滤波................................................................................... 21 低通滤波和增益...................................................................... 23 驱动电极................................................................................... 23 应用电路 ........................................................................................ 24 心脏附近心率测量 ................................................................. 24 应用练习：在双手处测量心率 ........................................... 24 心脏监护仪配置...................................................................... 25 带运动伪像消除功能的便携式心脏监护仪 ..................... 25 封装和订购信息........................................................................... 27 外形尺寸................................................................................... 27 订购指南................................................................................... 27
GS3662
400KHz 42V 2A Switching Current Boost / Buck-Boost / Inverting DC/DC ConverterFeaturesWide 5V to 32V Input Voltage RangePositive or Negative Output VoltageProgramming with a Single Feedback Pin Current Mode Control Provides ExcellentTransient Response1.25V reference adjustable version Fixed 400KHz Switching Frequency Maximum 2A Switching CurrentSW PIN Built in Over Voltage Protection Excellent line and load regulation EN PIN TTL shutdown capability Internal Optimize Power MOSFET High efficiency up to 90%Built in Frequency Compensation Built in Soft-Start FunctionBuilt in Thermal Shutdown Function Built in Current Limit Function Available in SOIC-8 packageApplications Automotive and Industrial Boost / Buck-Boost / Inverting Converters Portable Electronic Equipment General DescriptionThe GS3662 regulator is a wide input range, current mode, DC/DC converter which is capable of generating either positive or negative output voltages. It can be configured as either a boost, flyback, SEPIC or inverting converter. The GS3662 built in N-channel power MOSFET and fixed frequency oscillator, current-mode architecture results in stable operation over a wide range of supply and output voltages.The GS3662 regulator is special design for portable electronic equipment.Figure1. Package Type of GS3662400KHz 42V 2A Switching Current Boost / Buck-Boost / Inverting DC/DC Converter400KHz 42V 2A Switching Current Boost / Buck-Boost / Inverting DC/DC ConverterGS3662Figure4. GS3662 Typical Application Circuit (Boost Converter)400KHz 42V 2A Switching Current Boost / Buck-Boost / Inverting DC/DC Converter400KHz 42V 2A Switching Current Boost / Buck-Boost / Inverting DC/DC Converter400KHz 42V 2A Switching Current Boost / Buck-Boost / Inverting DC/DC ConverterGS3662Figure5. GS3662 Typical System Application (Boost Converter)400KHz 42V 2A Switching Current Boost / Buck-Boost / Inverting DC/DC ConverterGS3662Figure6. GS3662 Typical System Application (SEPIC Buck-Boost Converter)Typical System Application for Boost High Voltage Converter– FLYBACK Boost Topology (Input 10V~30VGS3662Figure7. GS3662 Typical System Application (Flyback Boost Converter)400KHz 42V 2A Switching Current Boost / Buck-Boost / Inverting DC/DC Converter400KHz 42V 2A Switching Current Boost / Buck-Boost / Inverting DC/DC Converter Package InformationSOP8 Package Mechanical Dimensions。
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PreliminaryGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)2M x 18, 1M x 36, 512K x 7236Mb S/DCD Sync Burst SRAMs250 MHz –133 MHz1.8 V V DD 1.8 V I/O119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 1.8 V +10%/–10% core power supply • 1.8 V +10%/–10% core power supply • 1.8 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications• JEDEC-standard 119-, 165-, and 209-bump BGA package • Pb-Free packages availableFunctional DescriptionApplicationsThe GS8322V18/36/72 is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count ineither linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM inPipeline mode, activating the rising-edge-triggered Data Output Register.SCD and DCD Pipelined ReadsThe GS8322V18/36/72 is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Parameter Synopsis-250-225-200-166-150-133UnitPipeline 3-1-1-1KQ t KQ (x72)tCycle 3.04.0 3.04.4 3.05.0 3.56.0 3.86.7 4.07.5ns ns Curr (x18)Curr (x36)Curr (x72)285350440265320410245295370220260320210240300185215265mA mA mA Flow Through 2-1-1-1t KQ tCycle 6.56.57.07.07.57.58.08.08.58.58.58.5ns ns Curr (x18)Curr (x36)Curr (x72)205235315195225295185210265175200255165190240155175230mA mA mAGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)209-Bump BGA—x72 Common I/O—Top View (Package C)1234567891011A DQ G DQ G A E2ADSP ADSC ADV E3A DQB DQ B AB DQ G DQ G BC BG NC BW A BB BF DQ B DQ B BC DQ G DQ G BH BD NC E1NC BE BA DQ B DQ B CD DQ G DQ G V SS NC NC G GW NC V SS DQ B DQ B DE DQP G DQP C V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPF DQP B EF DQ C DQ C V SS V SS V SS ZQ V SS V SS V SS DQ F DQ F FG DQ C DQ C V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQ F DQ F GH DQ C DQ C V SS V SS V SS MCL V SS V SS V SS DQ F DQ F H J DQ C DQ C V DDQ V DDQ V DD MCL V DD V DDQ V DDQ DQ F DQ F J K NC NC CK NC V SS MCL V SS NC NC NC NC K L DQ H DQ H V DDQ V DDQ V DD FT V DD V DDQ V DDQ DQ A DQ A L M DQ H DQ H V SS V SS V SS MCL V SS V SS V SS DQ A DQ A M N DQ H DQ H V DDQ V DDQ V DD SCD V DD V DDQ V DDQ DQ A DQ A N P DQ H DQ H V SS V SS V SS ZZ V SS V SS V SS DQ A DQ A P R DQP D DQP H V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQP A DQP E R T DQ D DQ D V SS NC NC LBO NC NC V SS DQ E DQ E T U DQ D DQ D NC A A A A A A DQ E DQ E U V DQ D DQ D A A A A1A A A DQ E DQ E V W DQ D DQ D TMS TDI A A0A TDO TCK DQ E DQ E W11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V72 209-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset Inputs.An IAddress InputsDQ A DQ B DQ C DQ D DQ E DQ F DQ G DQ H I/O Data Input and Output pinsB A , B B I Byte Write Enable for DQ A , DQ B I/Os; active low BC ,BD I Byte Write Enable for DQ C , DQ D I/Os; active low BE , BF , BG ,B HI Byte Write Enable for DQ E , DQ F , DQ G , DQ H I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowSCD I Single Cycle Deselect/Dual Cycle Deselect Mode ControlMCH IMust Connect High MCL Must Connect Low BW I Byte Enable; active lowZQ I FLXDrive Output Impedance Control(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCKIScan Test ClockGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V72 209-Bump BGA Pin Description (Continued)SymbolTypeDescriptionGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)165-Bump BGA—x18 Commom I/O—Top View (Package E)1234567891011A NC A E1BB NC E3BW ADSC ADV A A AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQPB SCD V DDQ V SS NC A NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)165-Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3BW ADSC ADV A NC A B NC A E2BD BA CK GW G ADSP A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD SCD V DDQ V SS NC A NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A A P RLBOAAATMSA0TCKAAAAR11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch(Package E)GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V18/36 165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active low (x36 Version)NC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSPI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect LowSCD —Single Cycle Deselect/Dual Cyle Deselect Mode ControlV DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)119-Bump BGA—x36 Common I/O—Top View1234567A V DDQ A A ADSP A A V DDQ A B NC A A ADSC A A NC B C NC A A V DD A A NC C D DQ DQP V SS ZQ V SS DQP B DQ B D E DQ DQ V SS E1V SS DQ B DQ B E F V DDQ DQ V SS G V SS DQ B V DDQ F G DQ DQ BC ADV BB DQ B DQ B G H DQ DQ V SS GW V SS DQ B DQ B H J V DDQ V DD NC V DD NC V DD V DDQ J K DQ D DQ D V SS CK V SS DQ A DQ A K L DQ D DQ D BD SCD BA DQ A DQ A L M V DDQ DQ D V SS BW V SS DQ A V DDQ M N DQ D DQ D V SS A1V SS DQ A DQ A N P DQ D DQP D V SS A0V SS DQP A DQ A P R NC A LBO V DD FT A NC R T NC NC A A A A ZZ T UV DDQTMSTDITCKTDONCV DDQU7 x 17 Bump BGA—14 x 22 mm 2 Body—1.27 mm Bump PitchC C C C C C2C C CGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)119-Bump BGA—x18 Common I/O—Top View1234567A V DDQ A A ADSP A A V DDQ AB NC A A ADSC A A NC BC NC A A V DD A A NC CD DQ B NC V SS ZQ V SS DQP A NC DE NC DQ B V SS E1V SS NC DQ A EF V DDQ NC V SSG V SS DQ A V DDQ FG NC DQ B BB ADV NC NC DQ A GH DQ B NC V SS GW V SS DQ A NC HJ V DDQ V DD NC V DD NC V DD V DDQ JK NC DQ B V SS CK V SS NC DQ A KL DQ B NC NC SCD BA DQ A NC LM V DDQ DQ B V SS BW V SS NC V DDQ MN DQ B NC V SS A1V SS DQ A NC NP NC DQP B V SS A0V SS NC DQ A PR NC A LBO V DD FT A NC RT NC A A A A A ZZ TU V DDQ TMS TDI TCK TDO NC V DDQ U7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V18/36 119-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])SCD I Single Cycle Deselect/Dual Cyle Deselect Mode ControlTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock V DD I Core power supply V SS I I/O and Core Ground V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)A1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx93636Note: Only x36 version shown for simplicity.SCD3636B AB BB CB DGS8322V18/36 Block DiagramMode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Note:There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.The burst counter wraps to initial state on the 5th clock.The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110I nterleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4Write all bytesLXXXXX1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Synchronous Truth TableOperationAddress UsedState Diagram Key 5E 1ADSPADSCADVW 3DQ 4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CWH X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend BurstCurrentHXHHTDNotes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)First WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Simplified State Diagram with GAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 3.6V V DDQ Voltage in V DDQ Pins –0.5 to 3.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 3.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 3.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD 1.6 1.82.0V 1.8 V V DDQ I/O Supply VoltageV DDQ1.61.82.0VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)DQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 100 uA FT, SCD, and ZQ Input Current I IN2V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL–100 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V—Output Low VoltageV OL1I OL = 4 mA, V DD = 1.6 V—0.4 VGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 72)P i p e l i n eI D DI D D Q380604006035060370603205034050280403004026040280402353025530m AF l o w T h r o u g hI D DI D D Q275402854025540265402353024530225302353021030220302102022020m A(x 36)P i p e l i n eI D DI D D Q300503205027545295452554027540225352453521030230301902521025m AF l o w T h r o u g hI D DI D D Q210252202520025210251902020020180201902017020180201601517015m A(x 18)P i p e l i n eI D DI D D Q260252802524025260252252024520200202202019020210201701519015m AF l o w T h r o u g hI D DI D D Q190152001518015190151701518015160151701515015160151401515015m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 608060806080608060806080m AF l o w T h r o u g hI S B608060806080608060806080m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D100115951109010585100851008095m AF l o w T h r o u g hI D D85100851008095809575907085m AN o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .AC Electrical CharacteristicsParameterSymbol-250-225-200-166-150-133UnitMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxPipelineClock Cycle Time tKC 4.0— 4.4— 5.0— 6.0— 6.7—7.5—ns Clock to Output Valid (x18/x36)tKQ — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns Clock to Output Valid (x72)tKQ — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.2— 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.3—0.4—0.5—0.5—0.5—ns Flow ThroughClock Cycle Time tKC 6.5—7.0—7.5—8.0—8.5—8.5—ns Clock to Output ValidtKQ — 6.5—7.0—7.5—8.0—8.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5— 1.5— 1.5— 1.5— 1.7—2—ns Clock to Output in High-Z (x18/x36)tHZ 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns Clock to Output in High-Z (x72)tHZ 1 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid (x18/x36)tOE — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns G to Output Valid(x72)tOE — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z (x18/x36)tOHZ 1— 2.5— 2.7— 3.0— 3.0— 3.0— 3.0ns G to output in High-Z (x72)tOHZ 1— 3.0— 3.0— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—nsGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Pipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL tKH Single Write Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Flow Through Mode Timing (SCD)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQd。