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ADN8810 12位高输出电流源数据手册（版本C）说明书

12-Bit High Output Current Source Data Sheet ADN8810Rev. C Document FeedbackInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2017 Analog Devices, Inc. All rights reserved. Technical Support FEATURESHigh precision 12-bit current sourceLow noiseLong term stabilityCurrent output from 0 mA to 300 mA Output fault indicationLow driftProgrammable maximum current24-lead, 4 mm × 4 mm LFCSP3-wire serial interface APPLICATIONSTunable laser current source Programmable high output current source Automatic test equipmentFUNCTIONAL BLOCK DIAGRAM3195-0 RESET4.096VSERIALINTERF ACEADDRESSSBF AULTINDICA TIONFigure 1.GENERAL DESCRIPTIONThe ADN8810 is a 12-bit current source with an adjustable full-scale output current of up to 300 mA. The full-scale output current is set with two external sense resistors. The output compliance voltage is 2.5 V, even at output currents up to 300 mA.The device is particularly suited for tunable laser control and can drive tunable laser front mirror, back mirror, phase, gain, and amplification sections. A host CPU or microcontroller controls the operation of the ADN8810 over a 3-wire serial peripheral interface (SPI). The 3-bit address allows up to eight devices to be independently controlled while attached to the same SPI bus.The ADN8810 is guaranteed with ±4 LSB integral nonlinearity (INL) and ±0.75 LSB differential nonlinearity (DNL). Noise and digital feedthrough are kept low to ensure low jitteroperation for laser diode applications. Full-scale and scaledoutput currents are given in Equation 1 and Equation 2,respectively.SNREFFS RVI⨯≈10(1)⎪⎪⎪⎪⎭⎫⎝⎛+Ω⨯⨯⨯=1.01514096kRRVCodeI SNSNREFOUT(2)ADN8810Data SheetRev. C | Page 2 of 14TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Terminology ...................................................................................... 9 Functional Description (10)Setting Full-Scale Output Current ........................................... 10 Power Supplies ............................................................................ 10 Serial Data Interface ................................................................... 10 Standby and Reset Modes ......................................................... 11 Power Dissipation....................................................................... 11 Using Multiple ADN8810 Devices for Additional Output Current ......................................................................................... 11 Adding Dither to the Output Current ..................................... 12 Driving Common-Anode Laser Diodes ................................. 12 PCB Layout Recommendations ............................................... 13 Suggested Pad Layout for CP-24 Package ............................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .. (14)REVISION HISTORY11/2017—Rev. B. to Rev. CChanged R S to R SN .......................................................... Throughout Change to Figure 1 ........................................................................... 1 Changes to Maximum Full-Scale Output Current Parameter and Power Supply Rejection Ratio Parameter, Table 1 ................ 3 Moved Timing Characteristics Section, Table 2, and Figure 2 ..... 4 Added Lead Temperature Range (Soldering 10 sec) Parameter, Table 3 ................................................................................................ 5 Changes to Figure 3 and Table 4 ..................................................... 6 Changes to Setting Full-Scale Output Current Section ............. 10 Changes to Adding Dither to the Output Current Section,Figure 20, and Figure 21 ................................................................ 12 Changes to PCB Layout Recommendations Section andFigure 25 .......................................................................................... 13 Updated to Outline Dimensions .................................................. 14 3/2016—Rev. A to Rev. BChanges to Figure 3 and Table 4 ...................................................... 7 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide . (15)4/2009—Rev. 0 to Rev. A Changes to Table 3 ............................................................................. 6 Changes to Figure 25 ...................................................................... 14 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide . (15)1/2004—Revision 0: Initial VersionData Sheet ADN8810 SPECIFICATIONSAVDD = DVDD = 5 V, PVDD = 3.3 V, AVSS = DVSS = DGND = 0 V, T A = 25°C, covering output current (I OUT) from 2% full-scale current (I FS) to 100% I FS, unless otherwise noted.Rev. C | Page 3 of 14ADN8810Data SheetRev. C | Page 4 of 141 With respect to AVSS. 2R SN = 20 Ω. 3See Table 2 for timing specifications.TIMING CHARACTERISTICS1, 21 Guaranteed by design. Not production tested.2Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of (V IL + V IH )/2.SCLKC SSDIRESET*ADDRESS BIT A3 MUST BE LOGIC LOW03195-0-002Figure 2. Timing DiagramData SheetADN8810Rev. C | Page 5 of 14ABSOLUTE MAXIMUM RATINGSTable 3.Parameter Rating Supply Voltage 6 VInput VoltageGND to V S + 0.3 V Output Short-Circuit Duration to GND IndefiniteStorage Temperature Range −65°C to +150°C Operating Temperature Range−40°C to +85°C Junction Temperature Range, CP Package −65°C to +150°C Lead Temperature Range (Soldering 10 sec)300°CStresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.ESD CAUTIONADN8810Data SheetRev. C | Page 6 of 14PIN CONFIGURATION AND FUNCTION DESCRIPTIONS03195-0-003FAULT ADDR0ADDR1FB RSN ADDR2NICVREF AVDD AVSS NIC DVSS117P V D D I O U T I O U T P V D D 1E N C O M P S B NOTES1. NIC = NOT INTERNALLY CONNECTED.2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO DGND.Figure 3. Pin ConfigurationData SheetADN8810Rev. C | Page 7 of 14TYPICAL PERFORMANCE CHARACTERISTICSCODE1.2–0.84,500500I N L E R R O R (L S B )1,0001,5002,0002,5003,0003,5004,0001.00.2–0.2–0.4–0.60.80.600.403195-0-005Figure 4. Typical INL PlotCODE0.4–0.304,500500D N LE R R O R (L S B )1,0001,5002,0002,5003,0003,5004,0000.1–0.1–0.20.300.203195-0-006Figure 5. Typical DNL PlotTEMPERATURE (°C)0.200.15–0.20–4085–15∆I N L (L S B )1035600–0.05–0.10–0.150.100.0503195-0-007Figure 6. ∆INL vs. TemperatureTEMPERATURE (°C)0.200.15–0.20–4085–15∆D N L (L S B )1035600–0.05–0.10–0.150.100.0503195-0-008Figure 7. ∆DNL vs. TemperatureTEMPERATURE (°C)0.2580.2570.250–4085–15F U L L -S C A L E O U T P U T (A )1035600.2540.2530.2520.2510.2560.255R SN = 1.6Ω03195-0-009Figure 8. Full-Scale Output vs. TemperatureTEMPERATURE (°C)20.76520.75520.720–4085–15F U L L -S C A L E O U T P U T (m A )10356020.74020.73520.73020.72520.75020.745R SN = 20Ω20.76003195-0-010Figure 9. Full-Scale Output vs. TemperatureADN8810Data SheetRev. C | Page 8 of 14TEMPERATURE (°C)0.500.35I P V D D (m A )0.200.150.100.050.300.250.400.4503195-0-011Figure 10. PVDD Supply Current (I PVDD ) vs. Temperature120I D V D D (µA )864210TEMPERATURE (°C)03195-0-012Figure 11. DVDD Supply Current (I DVDD ) vs. Temperature1.51.0I A V D D (m A )1.41.31.21.1TEMPERATURE (°C)03195-0-013Figure 12. AVDD Supply Current (I AVDD ) vs. TemperatureFREQUENCY (Hz)100k1O U T P U T I M P E D A N C E (Ω)1k1001010k03195-0-014Figure 13. Output Impedance vs. FrequencyTIME (1µs/DIV)CSI OUTV O L T A GE (2.7V /D I V )03195-0-015Figure 14. Full-Scale Settling TimeTIME (200ns/DIV)CSI OUT03195-0-016Figure 15. 1 LSB Settling TimeData SheetADN8810Rev. C | Page 9 of 14TERMINOLOGYRelative AccuracyRelative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in least significant bits (LSBs), from an ideal line passing through the endpoints of the DAC transfer function. Figure 4 shows a typical INL vs. code plot. The ADN8810 INL is measured from 2% to 100% of the full-scale (FS) output.Differential NonlinearityDifferential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. The ADN8810 is guaranteed monotonic by design. Figure 5 shows a typical DNL vs. code plot . Offset ErrorOffset error, or zero-code error, is an interpolation of the output voltage at code 0x000 as predicted by the line formed from the output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS). Ideally, the offset error is 0 V . Offset error occurs from a combination of the offset voltage of the amplifier and offset errors in the DAC. It is expressed in LSBs.Offset DriftThis is a measure of the change in offset error with a change in temperature. It is expressed in (ppm of full-scale range)/°C. Gain ErrorGain error is a measure of the span error of the DAC. It is the deviation in slope of the output transfer characteristic from ideal. The transfer characteristic is the line formed from the output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS). It is expressed as a percent of the full-scale range.Compliance VoltageThe maximum output voltage from the ADN8810 is a function of output current and supply voltage. Compliance voltage defines the maximum output voltage at a given current and supply voltage to guarantee the device operates within its INL, DNL, and gain error specifications.Output Current Change vs. Output Voltage ChangeThis is a measure of the ADN8810 output impedance and is similar to a load regulation spec in voltage references. For a given code, the output current changes slightly as output voltage increases. It is measured as an absolute value in (ppm of full-scale range)/V .O U T P U T V O L T A G E03195-0-004Figure 16. Output Transfer FunctionADN8810Data SheetRev. C | Page 10 of 14FUNCTIONAL DESCRIPTIONThe ADN8810 is a single 12-bit current output digital-to-analog converter (DAC) with a 3-wire SPI interface. Up to eight devices can be independently programmed from the same SPI bus. The full-scale output current is set with two external resistors. The maximum output current can reach 300 mA. Figure 17 shows the functional block diagram of the ADN8810.03195-0-017Figure 17. Functional Blocks, Pins, and Internal ConnectionsSETTING FULL-SCALE OUTPUT CURRENTTwo external resistors set the full-scale output current from the ADN8810. These resistors are equal in value and are labeled R SN in Figure 1. Use 1% or better tolerance resistors to achieve the most accurate output current and the highest output impedance.Equation 3 shows the approximate full-scale output current. The exact output current is determined by the data register code as shown in Equation 4. The variable code is an integer from 0 to 4095, representing the full 12-bit range of the ADN8810.SNFS R I ×≈10096.4(3)+Ω××=1.0151000,1k R R Code I SN SN OUT(4)The ADN8810 is designed to operate with a 4.096 V referencevoltage connected to VREF. The output current is directly proportional to this reference voltage. To achieve the bestperformance, use a low noise precision (the ADR292, ADR392, or REF198 is recommended).POWER SUPPLIESThere are three principal supply current paths through the ADN8810: •AVDD provides power to the analog front end of the ADN8810 including the DAC. Use this supply line topower the external voltage reference. For best performance, AVDD must be low noise.•DVDD provides power for the digital circuitry. Thisincludes the serial interface logic, the SB and RESET logic inputs, and the FAULT output. Tie DVDD to the same supply line used for other digital circuitry. It is not necessary for DVDD to be low noise.•PVDD is the power pin for the output amplifier. It canoperate from as low as 3.0 V to minimize power dissipation in the ADN8810. For best performance, PVDD must be low noise.Current is returned through the following three pins: •AVSS is the return path for both AVDD and PVDD. This pin is connected to the substrate of the die as well as the slug on the bottom of the lead frame chip scale package (LFCSP). For single-supply operation, connect this pin to a low noise ground plane.•DVSS returns current from the digital circuitry powered by DVDD. Connect DVSS to the same ground line or plane used for other digital devices in the application.•DGND is the ground reference for the digital circuitry. In a single-supply application, connect DGND to DVSS.For single-supply operation, set AVDD to 5 V , set PVDD from 3.0 V to 5 V , and connect AVSS, AGND, and DGND to ground.SERIAL DATA INTERFACEThe ADN8810 uses a serial peripheral interface (SPI) with three input signals: SDI, CLK, and CS . Figure 2 shows the timing diagram for these signals.Data applied to the SDI pin is clocked into the input shift register on the rising edge of CLK. After all 16 bits of the data-word have been clocked into the input shift register, a logic high on CS loads the shift register byte into the ADN8810. If more than 16 bits of data are clocked into the shift register before CS goes high, bits are pushed out of the register in first-in first-out (FIFO) fashion.The four MSB of the data byte are checked against the address of the device. If they match, the next 12 bits of the data byte are loaded into the DAC to set the output current. The first bit (MSB) of the data byte must be a logic zero, and the following three bits must correspond to the logic levels on pins ADDR2, ADDR1, and ADDR0, respectively, for the DAC to be updated. Up to eight ADN8810 devices with unique addresses can be driven from the same serial data bus.Table 5 shows how the 16-bit DATA input word is divided into an address byte and a data byte. The first four bits in the input word correspond to the address. Note that the first bit loaded (A3) must always be zero. The remaining bits set the 12-bit data byte for the DAC output. Three example inputs are demonstrated.•Example 1: This SDI input sets the device with an address of 111 to its minimum output current, 0 A. Connecting the ADN8810 pins ADDR2, ADDR1, and ADDR0 to VDD sets this address.• Example 2: This input sets the device with an address of 000 to a current equal to half of the full-scale output. •Example 3: The ADN8810 with an address of 100 is set to full-scale output.STANDBY AND RESET MODESApplying a logic low to the SB pin deactivates the ADN8810 and puts the output into a high impedance state. The device continues to draw 1.3 mA of typical supply current in standby. When logic high is reasserted on the SB pin, the output current returns to its previous value within 6 µs.Applying logic low to RESET sets the ADN8810 data register to all zeros, bringing the output current to 0 A. When RESET is deasserted, the data register can be reloaded. Data cannot be loaded into the device while it is in standby or reset mode.POWER DISSIPATIONThe power dissipation of the ADN8810 is equal to the output current multiplied by the voltage drop from PVDD to the output.()SN OUT OUT OUT DISS R I V PVDD I P ×−−×=²(5)The power dissipated by the ADN8810 causes a temperature increase in the device. For this reason, PVDD must be as low as possible to minimize power dissipation.While in operation, the ADN8810 die temperature, also known as junction temperature, must remain below 150°C to prevent damage. The junction temperature is approximatelyDISS JA A J P T T ×θ+=(6)where:T A is the ambient temperature in °C,θJA is the thermal resistance of the package (32°C/W). •Example 4: A 300 mA full-scale output current is required to drive a laser diode within an 85°C environment. The laser diode has a 2 V drop and PVDD is 3.3 V .Using Equation 5, the power dissipation in the ADN8810 is found to be 267 mW . At T A = 85°C, this makes the junction temperature 93.5°C, which is well below the 150°C limit. Note that even with PVDD set to 5 V , the junction temperature increases to only 110°C.USING MULTIPLE ADN8810 DEVICES FOR ADDITIONAL OUTPUT CURRENTConnect multiple ADN8810 devices in parallel to increase the available output current. Each device can deliver up to 300 mA of current. To program all parallel devices simultaneously, set all device addresses to the same address byte and drive all CS , SDI, and CLK from the same serial data interface bus. The circuit in Figure 18 uses two ADN8810 devices and delivers 600 mA to the pump laser.SERIAL INTERFACE (FROM µC OR DSP)I 600mA03195-0-018Figure 18. Using Multiple Devices for Additional Output CurrentTable 5. Serial Data Input ExamplesAddress Byte Data Byte SDI Input A3 A2 A1 A0D11 D10 D9 D8 D7 D6 D5 D4D3 D2 D1 D0 Example 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Example 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Example 31 01111 11 11 1 1 1 1ADDING DITHER TO THE OUTPUT CURRENTSome tunable laser applications require the laser diode bias current to be modulated or dithered. This is accomplished by dithering the V REF voltage input to the ADN8810. Figure 19 demonstrates one method.DITHERR203195-0-019Figure 19. Adding Dither to the Reference VoltageSet the gain of the dither by adjusting the ratio of R2 to R1. Increase C to lower the cutoff frequency of the high-pass filter created by C and R1. The cutoff frequency of Figure 19 is approximately 98 Hz.The AD8605 is recommended as a low offset, rail-to-rail input amplifier for this circuit.DRIVING COMMON-ANODE LASER DIODESThe ADN8810 can power common-anode laser diodes. These are laser diodes whose anodes are fixed to the laser module case. The module case is typically tied to either VDD or ground. For common anode to ground applications, a −5 V supply must be provided.In Figure 20, R SN sets up the diode current by the following equation:40965.16111.1096.4Code k R I SN ×Ω+×=(7)where Code is an integer value from 0 to 4095.Using the values in Figure 20, the diode current is 300.7 mA at a code value of 2045 (0x7FF), or half full-scale. This effectively provides 11-bit current control from 0 mA to 300 mA of diode current.The maximum output current of this configuration is limited by the compliance voltage at the IOUT pin of the ADN8810. The voltage at IOUT cannot exceed 1 V below PVDD, in this case, 4 V. The IOUT voltage is equal to the voltage drop across R S N plus the gate-to-source voltage of the external FET. For this reason, select a FET with a low threshold voltage.In addition, the voltage across the R SN resistor cannot exceed the voltage at the cathode of the laser diode. Given a forward laser diode voltage drop of 2 V in Figure 20, the voltage at the RSN pin (I × R SN ) cannot exceed 3 V . This sets an upper limit to the value of code in Equation 5.Although the configuration for anode-to-ground diodes is similar, the supply voltages must be shifted down to 0 V and −5 V , as shown in Figure 21. The AVDD, DVDD, and PVDD pins are connected to ground with AVSS connected to −5 V .The 4.096 V reference must also be referred to the −5 V supply voltage. The diode current is still determined by Equation 7. All logic levels must be shifted down to 0 V and −5 V levels as well. This includes RESET , CS , SCLK, SDI, SB , and all ADDR pins. Figure 22 shows a simple method to level shift a standard TTL or CMOS (0 V to 5 V) signal down using external FETs.NOTE: LEAVE FB WITH NO CONNECTION03195-0-020Figure 20. Driving Common-Anode-to-VDD Laser DiodesNOTE: LEAVE FB WITH NO CONNECTION03195-0-021Figure 21. Driving Common-Anode-to-Ground Laser Diodes with a NegativeSupplyRESETCS SCLK SDI03195-0-022Figure 22. Level Shifting TTL/CMOS LogicPCB LAYOUT RECOMMENDATIONSAlthough they can be driven from the same power supply voltage, keep DVDD and AVDD current paths separate on the printed circuit board (PCB) to maintain the highest accuracy; likewise for AVSS and DGND. Tie common potentials together at a single point located near the power regulator. This technique is known as star grounding and is shown in Figure 23. This method reduces digital crosstalk into the laser diode or load.LOGIC GROUNDRETURN03195-0-023Figure 23. Star Supply and Ground TechniqueTo improve thermal dissipation, solder the slug on the bottom of the LFCSP package be soldered to the PCB with multiple vias into a low noise ground plane. Connecting these vias to a copper area on the bottom side of the board further improves thermal dissipation.Use identical trace width and lengths for the two output sense resistors. These lengths are shown as X and Y in Figure 24. Differences in trace lengths cause differences in parasitic seriesresistance. Because the sense resistors can be as low as 1.37 Ω, small parasitic differences can lower both the output current accuracy and the output impedance. See the AN-619 Application Note for a sample layout for these traces.03195-0-024Figure 24. Use Identical Trace Lengths for Sense ResistorsSUGGESTED PAD LAYOUT FOR CP-24 PACKAGEFigure 25 shows the dimensions for the PCB pad layout for the ADN8810. The package is a 4 mm × 4 mm, 24-lead LFCSP . The metallic slug underneath the package must be soldered to a copper pad connected to AVSS, the lowest supply voltage to the ADN8810. For single-supply applications, this is ground. Use multiple vias to this pad to improve the thermal dissipation of the package.0.0270.011(0.28)0.020(0.50)CONTROLLING DIMENSIONS ARE IN MILLIMETERS03195-0-025Figure 25. Suggested PCB Layout for the CP-24-10 Pad LandingOUTLINE DIMENSIONS0.300.250.200.800.750.700.25 MIN2.202.10 SQ 2.000.50BSC0.500.400.30COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.BOTTOM VIEWTOP VIEWSIDE VIEW4.104.00 SQ 3.900.05 MAX 0.02 NOM0.203 REFCOPLANARITY0.08PIN 1INDICATORFOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.02-21-2017-AEXPOSED PAD00SEATING PLANEDETAIL A (JEDEC 95)Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP]4 mm × 4 mm Body and 0.75 mm Package Height(CP-24-10)Dimensions shown in millimetersORDERING GUIDEModel 1Temperature Range Package DescriptionPackage Option ADN8810ACPZ–40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-10 ADN8810ACPZ-REEL7–40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-101Z = RoHS Compliant Part.©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03195-0-11/17(C)。

LM8168A

LM8168 LED数码管驱动芯片LM8168是一种专门用于各种LED显示驱动及扫描按键控制芯片。

主要应用于各种LED显示屏、数码管显示屏的驱动，具有外围元件少、连线简单、使用简易灵活的特点。

一、特性：●采用三线串行通讯输入；●移位锁存后直接输出驱动；●10位段输出15mA；●8位公共端输出150 mA；●可级联使用扩展驱动多位数码，如用4片驱动32位数码管；●漏极开路输出，所以可复用。

●可代换1628，1638，1629，74HC164●超强抗干扰设计，无需增加抗干扰元件及抗干扰处理，甚至可去掉电源滤波电容。

二、管脚定义：LM8168A（20PIN SOP）LM8168B（24PIN SOP）三、管脚名称及其功能说明：四、LM8168逻辑原理说明：内部电路（D0~-D17~为寄存器CLK上升时改变，D0－－D17为寄存器EN ＝1时等于D0～－D17～，EN＝0不变。

）当CLK上升时DATA－》D0~ , D0~－》D1~,。

D16~->D17~EN=0时，D0、D1。

D17不变。

EN=1时，D0＝D0～，D1＝D1～。

D17=D17~D0通过输出电路直接输出Q0 。

时序图：五、电气参数：1、直流电参数：VDD=5V，CLK=500KHz (0-70℃)2、极限参数（Ta = 25℃, Vss = 0 V）六、典型应用电路1、LM8168A用于驱动4位数码管显示和24个LED指示灯以及16个按键，本应用将LM8168A与4位数码管做成一个模块，更方便构成显示和按键单元及易于软件排版。

七、封装规格。

Lenovo ThinkSystem PM1643 Capacity Entry SAS 12Gb

ThinkSystem PM1643 Capacity/Entry SAS 12Gb SSDs Product Guide (withdrawn product)The ThinkSystem PM1643 Capacity SAS 12Gb solid-state drives (SSDs) are next-generation high-capacity SSDs suitable for a wide range of applications. The PM1643 Capacity SAS SSDs are designed for dense storage and with a 12 Gb SAS interface, these drives feature all the capacity and performance that is needed to replace large numbers of 15K rpm and 10K rpm spinning disks, and consolidate storage into tightly packed server configurations.The PM1643 SSDs are the follow-on to the PM1633a SSDs and offer significantly improved performance, both for random and sequential workloads.Figure 1. ThinkSystem PM1643 Capacity SAS 12Gb SSDsDid you know?Capacity SSDs are a category of cost-effective high-capacity SSDs where it makes sense to store all of your data on the SSDs, and not use the SSDs only for caching or indexes. Unlike SATA drives, the 12 Gb/s SAS interface on these drives supports full duplex data transfer for higher performance, as well as dual port connectivity and enterprise-level error recovery for better availability.Click here to check for updatesTechnical specificationsThe following tables present technical specifications for the PM1643 Capacity and PM1643 Entry SSDs.Table 3. Technical specificationsFeature 960 GB drive 3.84 TB drive 7.68 TB drive 15.36 TB drive*30.72 TB drive*Interface 12 Gbps SAS 12 Gbps SAS 12 Gbps SAS 12 Gbps SAS 12 Gbps SAS Capacity960 GB 3.84 TB 7.68 TB 15.36 TB 30.72 TB Endurance(drive writes per day for 5 years) 1 DWPD1 DWPD1 DWPD1 DWPD1 DWPDEndurance(total bytes written)1,752 TB 7,008 TB 14,016 TB 28,032 TB 56,064 TB Data reliability (UBER)< 1 in 10 bits read < 1 in 10 bits read < 1 in 10 bits read < 1 in 10 bits read < 1 in 10 bits read MTBF2,000,000 hours 2,000,000 hours 2,000,000 hours 2,000,000 hours 2,000,000 hoursIOPS reads (4 KB blocks)230,000230,000230,000230,000230,000IOPS writes (4 KB blocks)30,00040,00040,00040,00025,000Sequential read rate (128 KB blocks)1,000 MBps 1,000 MBps 1,000 MBps 1,000 MBps 1,000 MBps Sequential write rate (128 KB blocks)1,000 MBps 1,000 MBps 1,000 MBps 950 MBps 750 MBps Shock, non-operating 1,500 G (Max)at 0.5 ms 1,500 G (Max)at 0.5 ms 1,500 G (Max)at 0.5 ms 1,500 G (Max)at 0.5 ms 1,500 G (Max)at 0.5 ms Vibration, non-operating20 G (10-2000 Hz)20 G (10-2000 Hz)20 G (10-2000 Hz)20 G (10-2000 Hz)20 G (10-2000 Hz)Typical power (R / W)9 W / 9 W9 W / 9 W9 W / 9 W9 W / 9 W9 W / 9 W* The 15TB and 30TB drives are available via Special Bid.Server support - ThinkSystemThe following tables list the ThinkSystem servers that are compatible.1717171717RMS RMS RMS RMS RMSPartNumber Description Edge1S IntelV2AMD V3Intel V32.5-inch hot-swap drives4XB7A17168ThinkSystem 2.5" PM1643 960GBEntry SAS 12Gb Hot Swap SSDN N N N N N N N N N N N N N N N N N N4XB7A13645ThinkSystem 2.5" PM1643 3.84TBCapacity SAS 12Gb Hot SwapSSDN N N N N N N N N N N N N N N N N N N4XB7A13646ThinkSystem 2.5" PM1643 7.68TBCapacity SAS 12Gb Hot SwapSSDN N N N N N N N N N N N N N N N N N N 3.5-inch hot-swap drives4XB7A13649ThinkSystem 3.5" PM1643 3.84TBCapacity SAS 12Gb Hot SwapSSD N N N N N N N N N N N N N N N N N N N SE35(7Z46/7D1X)SE35V2(7DA9)SE36V2(7DAM)SE45(7D8T)SE455V3(7DBY)ST5V2(7D8K/7D8J)ST25V2(7D8G/7D8F)SR25V2(7D7R/7D7Q)SR635V3(7D9H/7D9G)SR655V3(7D9F/7D9E)SR645V3(7D9D/7D9C)SR665V3(7D9B/7D9A)SR675V3(7D9Q/7D9R)ST65V3(7D7B/7D7A)SR63V3(7D72/7D73)SR65V3(7D75/7D76)SR85V3(7D97/7D96)SR86V3(7D94/7D93)SR95V3(7DC5/7DC4)PartNumber Description Dense V32S Intel V2AMD V1Dense V24SV28S2.5-inch hot-swap drives4XB7A17168ThinkSystem 2.5" PM1643960GB Entry SAS 12Gb HotSwap SSDN N N N N N N N N N N N N N N N N N N N4XB7A13645ThinkSystem 2.5" PM16433.84TB Capacity SAS 12GbHot Swap SSDN N N N N N N N N N N N N N N N N N N Y4XB7A13646ThinkSystem 2.5" PM16437.68TB Capacity SAS 12GbHot Swap SSDN N N N N N N N N N N N N N N N N N N Y 3.5-inch hot-swap drives4XB7A13649ThinkSystem 3.5" PM16433.84TB Capacity SAS 12GbHot Swap SSD N N N N N N N N N N N N N N N N N N N N SD665V3(7D9P)SD665-NV3(7DAZ)SD65V3(7D7M)SD65-IV3(7D7L)ST65V2(7Z75/7Z74)SR63V2(7Z7/7Z71)SR65V2(7Z72/7Z73)SR67V2(7Z22/7Z23)SR635(7Y98/7Y99)SR655(7Y/7Z1)SR655ClientOSSR645(7D2Y/7D2X)SR665(7D2W/7D2V)SD63V2(7D1K)SD65V2(7D1M)SD65-NV2(7D1N)SN55V2(7Z69)SR85V2(7D31/7D32)SR86V2(7Z59/7Z6)SR95(7X11/7X12)Part NumberDescription4S V11S Intel V12S Intel V1Dense V12.5-inch hot-swap drives4XB7A17168ThinkSystem 2.5" PM1643 960GBEntry SAS 12Gb Hot Swap SSD N N N N N N N N N N N N Y Y N Y N N N 4XB7A13645ThinkSystem 2.5" PM1643 3.84TBCapacity SAS 12Gb Hot Swap SSD Y Y Y N N N N Y Y Y Y Y Y Y N Y N Y Y4XB7A13646ThinkSystem 2.5" PM1643 7.68TBCapacity SAS 12Gb Hot Swap SSD Y Y Y N N N N Y Y Y Y Y Y Y N Y N Y Y3.5-inch hot-swap drives4XB7A13649ThinkSystem 3.5" PM1643 3.84TBCapacity SAS 12Gb Hot Swap SSDN N N N N N N Y Y Y Y Y Y Y N N N N N Server support - System xThe following tables list the System x servers that are compatible with the PM1643 Capacity SSDs.Support for System x and dense servers with Xeon E5/E7 v4 and E3 v5 processors Table 7. Support for System x and dense servers with Xeon E5/E7 v4 and E3 v5 processorsPart numberDescription4XB7A13665PM1643 3.84TB Enterprise Capacity 12Gb SAS G3HS 2.5" SSD N N N Y YNN S R 850 (7X 18 / 7X 19)S R 850P (7D 2F / 2D 2G )S R 860 (7X 69 / 7X 70)S T 50 (7Y 48 / 7Y 50)S T 250 (7Y 45 / 7Y 46)S R 150 (7Y 54)S R 250 (7Y 52 / 7Y 51)S T 550 (7X 09 / 7X 10)S R 530 (7X 07 / 7X 08)S R 550 (7X 03 / 7X 04)S R 570 (7Y 02 / 7Y 03)S R 590 (7X 98 / 7X 99)S R 630 (7X 01 / 7X 02)S R 650 (7X 05 / 7X 06)S R 670 (7Y 36 / 7Y 37)S D 530 (7X 21)S D 650 (7X 58)S N 550 (7X 16)S N 850 (7X 15)x 3250 M 6 (3943)x 3250 M 6 (3633)x 3550 M 5 (8869)x 3650 M 5 (8871)x 3850 X 6/x 3950 X 6 (6241, E 7 v 4)n x 360 M 5 (5465, E 5 v 4)s d 350 (5493)TrademarksLenovo and the Lenovo logo are trademarks or registered trademarks of Lenovo in the United States, other countries, or both. A current list of Lenovo trademarks is available on the Web athttps:///us/en/legal/copytrade/.The following terms are trademarks of Lenovo in the United States, other countries, or both:Lenovo®Flex SystemSystem x®ThinkSystem®The following terms are trademarks of other companies:Intel® and Xeon® are trademarks of Intel Corporation or its subsidiaries.Other company, product, or service names may be trademarks or service marks of others.。

M12L64322A-5BG中文资料

66 A9 65 A8 64 A7 63 A6 62 A5 61 A4 60 A3 59 DQM3 58 VSS
57 NC 56 DQ31 55 VDDQ 54 DQ30 53 DQ29 52 VSSQ 51 DQ28 50 DQ27 49 VDDQ 48 DQ26 47 DQ25 46 VSSQ 45 DQ24 44 VSS
M12L64322A
512K x 32 Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
86 Pin TSOP (TypeII) (400mil x 875mil)
Product No. MAX FREQ. PACKAGE COMMENTS
M12L64322A-5TG 200MHz TSOPII
Revision 1.9(Nov. 04 2005) - Modify tCC / tRCD spec
Revision 2.0(Dec. 08 2005) - Add –5T speed grade
Revision 2.1(Mar. 08 2006) - Modify Inch Dimension Max. A2 from 0.011 to 0.041
E VDDQ DQ31 NC
NC DQ16 VSSQ
F VSS DQM3 A3
A2 DQM2 VDD
G A4 A5 A6
A10 A0 A1
H A7 A8 NC
NC BA1 NC
J CLK CKE A9
BA0 CS RAS
K DQM1 NC NC
CAS WE DQM0
L VDDQ DQ8 VSS
VDD DQ7 VSSQ
Pb-free

Lem Products #606 垂直馅肠填充机的零件清单说明书

PARTS LIST5lb. #606 STAINLESS STEELVERTICAL SAUSAGE STUFFERSPART # DESCRIPTION QTY. PCS.Gasket 1 1A Piston1B Piston for Black Rod 12 Cylinder 1Ring 13 RetainingScrew 15 Wing6 Handle 17A Threaded Rod- Black 18 Set of 3 Stuffing Tubes 1ReleaseValve 1 9A Air9B Acorn Nut Set 110A Frame 111 Base 112 Horizontal Gear Bushing 114 BaseNut 2Washer 215 BaseWasher 116 Nylon17 BrassWasher 118 Clamps 2 19A Horizontal Gear – Black 119B Vertical Gear - Black 1#606 VERTICAL SAUSAGE STUFFERThoroughly hand clean all parts before first use in warm soapy water, to remove the lubricant applied during manufacturing. Rinse and dry thoroughly.ASSEMBLY AND PROPER USE1. Attach the handle (#6) to the gear using the Wing Screw (#5).2. Free the cylinder (#2) for removal by turning/cranking the handle counter-clockwise until the piston isfree of the cylinder. Slide the cylinder out of the frame.3. Place meat in the cylinder. Pack the meat tightly in the cylinder to minimize air pockets.4. Place the cylinder back onto the frame.5. Removing the retaining ring (#3), insert a stuffing tube into the retaining ring. Screw the retaining ringtightly to the unit.6. Slide casings onto stuffing tube.7. Turn the handle clockwise so the piston (#1) moves down into the cylinder and the meat is extrudedthrough the tube and into the casing.8. After extruding all the meat from the cylinder, turn the handle counter-clockwise so the piston backs outof the cylinder.9. Remove the cylinder for cleaning. Wash unit with warm soapy water and thoroughly dry.10. Clean the piston.11. Reassemble and spray with food grade Silicone Spray. (Available at LEM Products.)SALTSalt gives flavor, helps to hold water in the meat, and acts as a binding agent. As a binding agent, salt can cause unnecessary work if instructions are not followed.When salt is mixed with the meat along with other spices and ingredients, it causes the meat to stiffen, or “set-up” very much like cement. This process only requires 20-30 minutes to take affect. It then becomes very difficult to push the meat mixture through the stuffer. With a geared sausage stuffer, a stiffened meat mixture causes unnecessary wear on the gears. We strongly recommend that the meat mixture be packed into the sausage stuffer right after it is mixed. Then, quickly stuff the casings while the meat is pliable. Applying Food Grade Grease to the gears will make the gears work more smoothly and turning the handle much easier.LEM Products recommends that you use 1oz. of water for each pound of meat used. If you are using soy protein concentrate, you can use 2 oz. of water per pound of meat.SOY PROTEINLEM Products recommends the use of our Soy Protein when making sausage. It is available in a 1lb. package, which is enough to mix with 50 lbs. of meat. Use 2 teaspoons of Soy Protein per pound of meat to help retain moisture and prevent shrinking during smoking or cooking. It is very high in protein making it an excellent binder giving the finished sausage a smooth, moist consistency. Soy Protein has no taste, contains no cholesterol and is fat free because it is derived from a vegetable source.Clean the stuffer using a mild detergent and warm water. Rinse and hand dry all parts. With normal use and maintenance, this stuffer will give you years of enjoyment. After washing the unit, spray it with a food grade Silicone Spray. This will prevent oxidation and will keep your stuffer like new. This silicone coating can be washed off easily with hot soapy water before the next use. Silicone Spray is available from LEM Products.。

M13S128168A资料

Revision HistoryRevision 0.1 (15 Jan. 2002)- OriginalRevision 0.2 (19 Nov. 2002)-changed ordering information & DC/AC characteristicsRevision 0.1 Revision 0.2M13S128168A - 5T M13S128168A - 6TM13S128168A - 6T M13S128168A - 7.5AB Revision 0.3 (8 Aug. 2003)-Change IDD6 from 3mA to 5mA.Revision 0.4 (27 Aug. 2003)-Change ordering information & DC / AC characteristics.Revision 1.0 (21 Oct. 2003)-Modify tWTR from 2tck to 1tck.Revision 1.1 (10 Nov. 2003)-Correct some refresh interval that is not revised.-Correct some CAS Lantency that is not revised.Revision 1.2 (12 Jan. 2004)-Correct IDD1; IDD4R and IDD4W test condition.-Correct tRCD; tRP unit-Add tCCD spec.-Add tDAL spec.Revision 1.3 (12 Mar. 2004)-Add Cas Latency=2; 2.5Revision 1.4 (23 Jun. 2005)-Add Pb-free to ordering information-Modify IDD0 and IDD1 spec-Modify some AC timing unit from tCK to ns.Revision 1.5 (29 May. 2006)-Delete CL2 ; CL2.5-Modify tREFI-Delete Non-pb-free form ordering informationRevision 1.6 (3 Jan. 2007)-Add CL2.5Revision 1.7 (12 Apr. 2007)-Add BGA packageRevision 1.8 (01 Jun. 2007)-Delete CL 2.5DDR SDRAM 2M x 16 Bit x 4 BanksDouble Data Rate SDRAMFeaturesz JEDEC Standardz Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLLz Differential clock inputs (CLK and CLK )z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 3z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe (DQS)z DQS is edge-aligned with data for reads; center-aligned with data for WRITE z Data mask (DM) for write masking only z V DD = 2.375V ~ 2.75V, V DDQ = 2.375V ~ 2.75V z Auto & Self refreshz 15.6us refresh interval (64ms refresh period, 4K cycle) z SSTL-2 I/O interface z66pin TSOPII packageOrdering information :PRODUCT NO. MAX FREQ VDDPACKAGECOMMENTS M13S128168A -5TG 200MHz Pb-free M13S128168A -6TG 166MHz 2.5V TSOPIIPb-free M13S128168A -5BG 200MHz Pb-free M13S128168A -6BG166MHz2.5V BGAPb-freeFunctional Block DiagramPin ArrangementDQS12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 PIN TSOP(II)(400mil x 875mil) (0.65 mm PIN PITCH)V DD DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 N CV DDQ LDQS N CV DD N C LDM WE CAS RAS CSN C BA0 BA1A10/A P A0A1A2A3V DDV SSDQ15V SSQDQ14DQ13V DDQDQ12DQ11V SSQDQ10DQ9V DDQDQ8N CV SSQUDQSN CV REFV SSUDMCLKCLKCKEN CN CA11A9A8A7A6A5A4V SS 666564636261605958575655545352515049484746454443424140393837363534x16 x1660 Ball BGAPin Description(M13S128168A)Absolute Maximum RatingUnitValueParameter SymbolVoltage on any pin relative to V SS V IN, V OUT-0.5 ~ 3.6 VVoltage on V DD supply relative to V SS V DD, V DDQ-1.0 ~ 3.6 VVoltage on V DDQ supply relative to V SS V DDQ-0.5 ~ 3.6 VStorage temperature T STG-55 ~ +150 C°Power dissipation P D TBD WShort circuit current I OS 50 mANote : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommend operation condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.DC Operation Condition & SpecificationsDC Operation ConditionRecommended operating conditions (Voltage reference to V SS = 0V, T A = 0 to 70C°)Notes 1. V REF is expected to be equal to 0.5* V DDQ of the transmitting device, and to track variations in the DC level of the same.Peak-to-peak noise on V REF may not exceed 2% of the DC value.2. V TT is not applied directly to the device. V TT is system supply for signal termination resistors, is expected to be set equalto V REF, and must track variations in the DC level of V REF .3. V ID is the magnitude of the difference between the input level on CLK and the input level on CLK.DC SpecificationsNote 1. Enable on-chip refresh and address counters.AC Operation Conditions & Timing SpecificationID2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of thesame.Input / Output Capacitance(V DD = 2.375V~2.75V, V DDQ =2.375V~2.75V, T A = 25C°, f = 1MHz)AC Operating Test ConditionsParameter Value Unit Input reference voltage for clock (V REF ) 0.5*V DDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate1.0V/nsInput levels (V IH /V IL ) V REF +0.31/V REF -0.31 V Input timing measurement reference level V REF V Output timing reference level V TT VAC Timing Parameter & Specifications(V DD = 2.375V~2.75V, V DDQ =2.375V~2.75V, T A =0C ° to 70C °)(Note)AC Timing Parameter & Specifications-continued-5 -6 Parameter Symbolmin max min max Half Clock Period t HP t CL min or t CH min- t CL min or t CH min - nsDQ-DQS output holdtimet QH t HP-0.45 - t HP-0.5 - nsACTIVE to PRECHARGE command t RAS40 120Kns 42 120KnsnsRow Cycle Time t RC60 - 60 -nsAUTO REFRESH Row Cycle Time t RFC70 - 72 -nsACTIVE to READ,WRITE delay t RCD18 - 18 -nsPRECHARGE command period t RP18 - 18 -nsACTIVE to READ withAUTOPRECHARGE command t RAP 18 120K 18 120KnsACTIVE bank A to ACTIVE bank B command t RRD10 - 12 -nsWrite recovery time t WR 2 - 2 -t CKWrite data in to READ command delay t WTR 1 - 1 -t CKCol. Address to Col. Address delay t CCD 1 - 1 -t CKAverage periodic refresh interval t REFI - 15.6 - 15.6usWrite preamble t WPRE0.25 - 0.25 -t CK Write postamble t WPST0.4 0.6 0.4 0.6t CK DQS read preamble t RPRE0.9 1.1 0.9 1.1t CK DQS read postamble t RPST0.4 0.6 0.4 0.6t CKClock to DQS write preamble setup time t WPRES0 - 0 -nsLoad Mode Register /Extended Mode register cycle time t MRD 2 - 1 -t CKExit self refresh to READ command t XSRD200 - 200 -t CKExit self refresh to non-READ command t XSNR75 - 75 -nsAutoprecharge write recovery+Precharge time t DAL(t WR/t CK)+(t RP/t CK)(t WR/t CK)+(t RP/t CK)t CKCommand Truth Table1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS)2. EMRS/MRS can be issued only at all banks precharge state.A new command can be issued 1 clock cycles after EMRS or MRS.3. Auto refresh functions are same as the CBR refresh of DRAM.The automatical precharge without row precharge command is meant by “Auto”..Auto/self refresh can be issued only at all banks precharge state.4. BA0~BA1 : Bank select addresses.If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.6. During burst write with auto precharge, new read/write command can not be issued.Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after end of burst.7. Burst stop command is valid at every burst length.8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).Basic FunctionalityPower-Up and Initialization SequenceThe following sequence is required for POWER UP and Initialization.1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)-Apply VDD before or at the same time as VDDQ.-Apply VDDQ before or at the same time as V TT & V REF).2. Start clock and maintain stable condition for a minimun of 200us.3. The minimun of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high.4. Issue precharge commands for all banks of the device.*1 5. I ssue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the rest address pins, A1~A11 and BA1)*1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.(To issue DLL reset command, provide “High” to A8 and “Low” to BA0)*2 7. Issue precharge commands for all banks of the device.8. Issue 2 or more auto-refresh commands.9. Issue a mode register set command with low to A8 to initialize device operation.*1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.*2 Sequence of 6 & 7 is regardless of the order.Mode Register DefinitionMode Register Set (MRS)The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A11 in the same cycle as CS, RAS, CAS, WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.Bus BA1 BA0 A11 A10A9 A8 A7A6A5A4A3A2A1 A0 AddressBurst Address Ordering for Burst LengthBurst Length StartingAddress (A2, A1,A0)Sequential Mode Interleave Mode xx0 0, 1 0, 1 2xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 4x11 3, 0, 1, 23, 2, 1, 0000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 81117, 0, 1, 2, 3, 4, 5, 67, 6, 5, 4, 3, 2, 1, 0DLL Enable / DisableThe DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.Output Drive StrengthThe normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S128168A also support a weak drive strength option, intended for lighter load and/or point-to-point environments.Mode Register SetExtended Mode Register Set (EMRS)The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0~A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.*QFC is not used; don’t care.PrechargeThe precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, t WR(min.) must be satisfied until the precharge command can be issued. After t RP from the precharge, an active command to the same bank can be initiated.Burst Selection for Precharge by Bank address bitsA10/AP BA1 BA0 PrechargeOnlyABank0 0 0BOnlyBank0 0 1COnlyBank0 1 0OnlyDBank0 1 1AllBanks1 X XNOP & Device DeselectThe device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS, CAS and WE. For both Deselect and NOP the device should finish the current operation when this command is issued.Row ActiveThe Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (t RCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD min).Read BankThis command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS, CAS, and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.Write BankThis command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS, CAS, and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command.Essential Functionality for DDR SDRAMBurst Read OperationBurst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after t RCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst (Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM until the burst length is completed.Burst Write OperationThe Burst Write command is issued by having CS, CAS and WE low while holding RAS high at the rising edge of the clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins t DS (Data-in setup time) prior to data strobe edge enabled after t DQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored.Read Interrupted by a ReadA Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.Read Interrupted by a PrechargeA Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank.1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on therising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after t RP (RAS precharge time).2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edgewhich is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after t RP.3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after t RP where t RPbegins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.4. For all cases above, t RP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between aPrecharge command and a new Bank Activate command to the same bank equals t RP / t CK (where t CK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles.In all cases, a Precharge operation cannot be initiated unless t RAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where t RAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.Write Interrupted by a WriteA Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.The following functionality establishes how a Write command may interrupt a Read burst.1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burstand tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].2. It is illegal for a Write command to interrupt a Read with autoprecharge command.Write Interrupted by a Read & DMA burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (t WTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command.The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the memory.1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case wherethe Write to Read delay is 1 clock cycle is disallowed.2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediatelyprecede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memorycontroller) in time to allow the buses to turn around before the SDRAM drives them during a read operation.4. If input Write data is masked by the Read command, the DQS inputs is ignored by the SDRAM.5. It is illegal for a Read command interrupt a Write with autoprecharge command.Write Interrupted by a Precharge & DMA burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time (t WR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM.Precharge timing for Write operations in DRAMs requires enough time to allow “Write recovery” which is the time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, t WR, is used to indicate the required of time between the last valid write operation and a Precharge command to the same bank.The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronizes with the address path by switching clock domains from the data strobe clock domain to the input clock domain.This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain.t WR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge that strobes in the precharge command.1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for writerecovery is defined by t WR.2. When a precharge command interrupts a Write burst operation, the data mask pin, DQ, is used to mask input data during thetime between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM.The minimum time for write recovery is defined by t WR.3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after t WR + t RP wheret WR + t RP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above.4. In all cases, a Precharge operation cannot be initiated unless t RAS(min) [minimum Bank Activate to Precharge time] has beensatisfied. This includes Write with autoprecharge commands where t RAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst.Burst StopThe burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock (CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation.The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required.1. The BST command may only be issued on the rising edge of the input clock, CLK.2. BST is only a valid command during Read burst.3. BST during a Write burst is undefined and shall not be used.4. BST applies to all burst lengths.5. BST is an undefined command during Read with autoprecharge and shall not be used.6. When terminating a burst Read command, the BST command must be issued L BST ( “BST Latency”) clock cycles before theclock edge at which the output buffers are tristated, where L BST equals the CAS latency for read operations.7. When the burst terminates, the DQ and DQS pins are tristated.The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).DM maskingThe DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe.Read With Auto PrechargeIf a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when t RAS(min) is satisfied. If not, the start point of precharge operation will be delayed until t RAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time (t RP) has been satisfiedAt burst read / write with auto precharge, CAS interrupt of the same bank is illegal.。

GA-C621-WD12(-IPMI) Quick Installation Guide 快速安

Disclaimer
Information in this manual is protected by copyright laws and is the property of GIGABYTE. Changes to the specifications and features in this manual may be made by GIGABYTE without prior notice. No part of this manual may be reproduced, copied, translated, transmitted, or published in any form or by any means without GIGABYTE's prior written permission. For product-related information, check on our website at: https://
19) F_PANEL
1 2 Pin Definition
Pin Definition
1 Power LED+ 2 5V Standby
3-
4 ID LED+
5 Power LED- 6 ID LED-
7 HDD LED+
8 System Status LED+
23 24 9 HDD LED1
10 System Status LED-
Box Contents
55 GA-C621-WD12 or GA-C621-WD12-IPMI motherboard
55 Motherboard driver disk
55 I/O Shield

Atmel ATmegaS128 微控制器商品说明书

The new Atmel ® AVR ® ATmegaS128 microcontroller (MCU) brings the industry-leading AVR core to the aerospace industry. The ATmegaS128 MCU is designed for enhanced radiation performance and increased reliability in space applications. It takes advantage of mature Atmel AVR tools designed and used in the mass market worldwide for many years. The ATmegaS128 microcontroller targets many of the most common space applications, which typically require a small footprint, low power and analog control of motors and sensors.Key FeaturesHigh-performance, Low-power 8-bit Atmel AVR MCU• Advanced RISC architecture / Up to 8MIPS• On-chip 2-cycle multiplier• 3V-3.6V / 0 - 8MHz operating voltages & speed grades High-endurance Non-volatile Memory • 128 Kbytes of Flash program memory• 4 Kbytes EEPROM – 4 Kbytes internal SRAM1Advance Risc Architecture 8 Mips3.0 3-55 • Up to 64 Kbytes optionalexternal memory space • SPI interface for in-system programmingPeripheral Features • Two 8-bit and two 16-bit timers/counters • 6 PWM channels • 8-channel, 10-bit ADC• TWI/USARTs/SPI serial interface • Programmable watchdog timer • On-chip analog comparator Special Microcontroller Features• Power-on reset and programmable brown-out detection• Internal calibrated RC oscillator • External and internal interrupt sources• Six Sleep modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended StandbyKey Highlights for Space Environment• Full wafer lot traceability • 64-lead ceramic package (CQFP) • Space screening • Space qualification• Total ionizing Dose: up to 30 Krad (Si)• Single event latch-up LET > 62.5MeV.cm²/mg• Single event upset LET > 3 MeV.cm²/mg•SEU 10-3 to 10-1 error/ device/dayATmegaS128 Starter kitTo ease your design process and reduce time-to-market, Atmel delivers a complete starter kit STK600 and development system for the ATmegaS128 AVR microcontroller. With its advanced features for proto-typing and testing new designs, the kit gives designers a head start for developing code on AVR devices. Customers can start with the industrial version using the ATmega128 MCU or the Space Version ATme-gaS128 device as both share the same pinout.Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T : (+1)(408) 441. 0311 F : (+1)(408) 436. 4200 | © 2015 Atmel Corporation. / Rev.: Atmel-45160A-ATmegaS128-Aerospace-Rad-Tolerant-Flyer_E_US_102015Atmel,® Atmel logo and combinations thereof, Enabling Unlimited Possibilities,® and others are registered trademarks or trademarks of Atmel Corporation in U. S. and other countries. Other terms and product names may be trademarks of others.Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RE-LATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.Atmel StudioAtmel Studio is the integrated development platform (IDP) for developing and debugging Atmel AVR and Atmel | SMART ARM ® processor-based MCU applications. The Atmel Studio IDP gives you a seamless and easy-to-use environment to write, build and debug your applications written in C/C++ or assembly code. Atmel Studio supports all 8- and 32-bit AVR MCUs. It also connects seamlessly to Atmel debuggers and development kits.Atmel Software FrameworkThe Atmel Software Framework (ASF) is an MCU software library providing a 1,600 project examples of embedded software for Atmel Flash-based MCUs, including AVR and Atmel | SMART devices. This library contains basic C code examples for all ATmegaS128 peripherals.Application NotesIn addition to the Atmel Software framework, Atmel provides a broad range of application notes to implement different peripherals of the ATmegaS128 device. Most of those ap-plication notes are provided with source code in C language.。

NSi812x高可靠双通道数字隔离器数据手册说明书

C O NF ID EN T IA LNSi8120/NSi8121/NSi8122: High ReliabilityDual-Channel Digital IsolatorsDatasheet (EN) 1.8Product OverviewThe NSi812x devices are high reliability dual-channel digital isolator. The NSi812x device is safety certified by UL1577 support several insulation withstand voltages (3.75kV rms , 5kV rms ), while providing high electromagnetic immunity and low emissions at low power consumption. The data rate of the NSi812x is up to 150Mbps, and the common-mode transient immunity (CMTI) is up to 150kV/us. The NSi812x device provides digital channel direction configuration and the default output level configuration when the input power is lost. Wide supply voltage of the NSi812x device support to connect with most digital interface directly, easy to do the level shift. High system level EMC performance enhance reliability and stability of use. AEC-Q100 (Grade 1) option is provided for all devices.Key Features• Up to 5000V rms Insulation voltage• Date rate: DC to 150Mbps• Power supply voltage: 2.5V to 5.5V • All devices are AEC-Q100 qualified • High CMTI: 150kV/us • Chip level ESD: HBM: ±6kV• High system level EMC performance:Enhanced system level ESD, EFT, Surge immunity• Default output high level or low level option • Isolation barrier life: >60 years• Low power consumption: 1.5mA/ch (1 Mbps) • Low propagation delay: <15ns • Operation temperature: -40℃~125℃ • RoHS-compliant packages:SOIC-8 narrow body SOIC-16 wide bodySafety Regulatory Approvals• UL recognition: up to 5000V rms for 1 minute per UL1577• CQC certification per GB4943.1-2011• CSA component notice 5A • DIN VDE V 0884-11:2017-01Applications• Industrial automation system • Isolated SPI, RS232, RS485• General-purpose multichannel isolation • Motor controlFunctional Block DiagramsC O NF ID EN T IA LIndex1.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................................................. 3 2.0 SPECIFICATIONS ........................................................................................................................................................... 3 2.1. E LECTRICAL CHARACTERISTICS .................................................................................................................................................. 3 2.2. TYPICAL PERFORMANCE CHARACTERISTICS ........................................................................................................................... 7 2.3. P ARAMETER M EASUREMENT I NFORMATION . (8)3.0 HIGH VOLTAGE FEATURE DESCRIPTION (9)3.1. INSULATION AND SAFETY RELATED SPECIFICATIONS (9)3.2. DIN VDE V 0884-11（VDE V 0884-11）:2017-01 INSULATION CHARATERISTICS ....................................................................... 9 3.3. R EGULATORY INFORMATION ................................................................................................................................................... 11 4.0 FUNCTION DESCRIPTION ..........................................................................................................................................11 5.0 APPLICATION NOTE ................................................................................................................................................... 12 5.1. PCB L AYOUT ...................................................................................................................................................................... 12 5.2. H IGH SPEED PERFORMANCE ................................................................................................................................................... 12 5.3. T YPICAL S UPPLY C URRENT E QUATIONS ..................................................................................................................................... 13 6.0 PACKAGE INFORMATION ......................................................................................................................................... 13 7.0 TAPE AND REEL INFORMATION ............................................................................................................................. 17 8.0 ORDER INFORMATION .............................................................................................................................................. 20 9.0 REVISION HISTORY . (21)C O NF ID EN T IA L1.0 ABSOLUTE MAXIMUM RATINGSPower Supply Voltage VDD1, VDD2 -0.5 6.5 V Maximum Input Voltage VINA, VINB -0.4 VDD+0.41 V Maximum Output Voltage V OUTA , V OUTB -0.4 VDD+0.41 VMaximum Input/Output Pulse VoltageVINA, VINB, V OUTA , V OUTB-0.8VDD+0.8VPulse width should be less than 100ns, and the duty cycle should be less than 10%Common-Mode Transients CMTI ±150 kV/us Output currentIo -15 15mAMaximum Surge Isolation VoltageV IOSM5.3kVOperating Temperature Topr -40125 ℃Storage Temperature Tstg -40150℃Electrostatic dischargeHBM±6000VCDM±2000V1 The maximum voltage must not exceed 6.5V.2.0 SPECIFICATIONS2.1. ELECTRICAL CHARACTERISTICS(VDD1=2.5V~5.5V, VDD2=2.5V~5.5V, Ta=-40℃ to 125℃. Unless otherwise noted, Typical values are at VDD1 = 5V, VDD2 = 5V, Ta =25℃)Power on ResetVDD POR2.2 V POR threshold as during power-upVDD HYS 0.1 V POR threshold Hysteresis Input ThresholdV IT1.6 V Input Threshold at rising edge V IT_HYS 0.4 V Input Threshold Hysteresis High Level Input Voltage V IH 2 V Low Level Input Voltage V IL 0.8 V High Level Output Voltage V OH VDD-0.3 V I OH ≤ 4mA Low Level Output VoltageV OL0.3VI OL ≤ 4mAC O NF ID EN T IA LOutput Impedance R out 50 ohm Input Pull high or low CurrentI pull 8 15 uA Start Up Time after POR trbs 40 usec Common Mode Transient ImmunityCMTI±100±150kV/us(VDD1=5V± 10%, VDD2=5V± 10%, Ta=-40℃ to 125℃. Unless otherwise noted, Typical values are at VDD1 = 5V, VDD2 = 5V, Ta = 25℃)Supply currentNSi8120 I DD1(Q0) 0.58 0.87 mAAll Input 0V for NSi8120x0 Or All Input at supply for NSi8120x1 I DD2(Q0) 1.18 1.77 mA I DD1(Q1) 2.92 4.38 mA All Input at supply for NSi8120x0 Or All Input 0V for NSi8120x1I DD2(Q1) 1.241.86mAI DD1(1M) 1.71 2.56 mA All Input with 1Mbps, C L =15pFI DD2(1M)1.382.07mAI DD1(10M) 1.78 2.67 mA All Input with 10Mbps, C L =15pF I DD2(10M)3.24.8mA I DD1(100M)2.103.15 mA All Input with 100Mbps, C L =15pFI DD2(100M)21.031.5mANSi8121/ NSi8122 I DD1(Q0) 1.031.55 mA All Input 0V for NSi812xx0 Or All Input at supply for NSi812xx1 I DD2(Q0) 1.00 1.5 mA I DD1(Q1)2.203.3 mA All Input at supply for NSi812xx0Or All Input 0V for NSi812xx1 I DD2(Q1)2.133.2 mA I DD1(1M) 1.72 2.58 mA All Input with 1Mbps, C L =15pFI DD2(1M) 1.68 2.52 mA I DD1(10M) 2.62 3.93 mA All Input with 10Mbps, C L =15pFI DD2(10M) 2.71 4.06 mA I DD1(100M) 11.01 16.5 mA All Input with 100Mbps, C L = 15pF I DD2(100M)12.8 19.2 mA Data RateDR 0 150 MbpsC O NF ID EN T IA LPropagation Delayt PLH 5 8.20 15 ns See Figure 2.7 , C L = 15pF t PHL 5 10.56 15 ns See Figure 2.7, C L = 15pF Pulse Width Distortion |t PHL – t PLH | PWD5.0nsSee Figure 2.7 , C L = 15pFRising Time t r 5.0 ns See Figure 2.7 , C L = 15pF Falling Timet f 5.0 ns See Figure 2.7 , C L = 15pFPeak Eye Diagram Jitter t JIT (PK) 350 ps Channel-to-Channel Delay Skewt SK (c2c) 2.5 nsPart-to-Part Delay Skewt SK (p2p)5.0ns(VDD1=3.3V± 10%, VDD2=3.3V± 10%, Ta=-40℃ to 125℃. Unless otherwise noted, Typical values are at VDD1 = 3.3V, VDD2 = 3.3V, Ta =25℃)Supply currentNSi8120 I DD1(Q0) 0.550.83mA All Input 0V for NSi8120x0 Or All Input at supply for NSi8120x1 I DD2(Q0) 1.12 1.68 mA I DD1(Q1) 2.87 4.3 mA All Input at supply for NSi8120x0 Or All Input 0V for NSi8120x1 I DD2(Q1)1.18 1.77mA I DD1(1M)1.72.55mA All Input with 1Mbps, C L = 15pFI DD2(1M)1.271.91 mA I DD1(10M) 1.732.6 mA All Input with 10Mbps, C L = 15pF I DD2(10M)2.413.6 mA I DD1(100M) 2.05 3.08 mA All Input with 100Mbps, C L = 15pF I DD2(100M)14.0521.08mANSi8121/ NSi8122 I DD1(Q0) 0.98 1.47 mA All Input 0V for NSi812xx0 Or All Input at supply for NSi812xx1 I DD2(Q0) 0.95 1.43 mA I DD1(Q1) 2.14 3.21 mA All Input at supply for NSi812xx0 Or All Input 0V for NSi812xx1 I DD2(Q1) 2.08 3.12 mA I DD1(1M) 1.63 2.45 mA All Input with 1Mbps, C L = 15pFI DD2(1M) 1.59 2.39 mA I (10M)2.223.33mAAll Input with 10Mbps,C O NF I D EN T IA LI DD2(10M) 2.25 3.38 mA C L = 15pFI DD1(100M) 7.57 11.36 mA All Input with 100Mbps, C L = 15pF I DD2(100M)8.5 12.75 mA Data RateDR 0 150 Mbps Minimum Pulse Width PW 5.0 nsPropagation Delayt PLH 5 9.20 15 ns See Figure 2.7 , C L = 15pF t PHL5 10.40 15 ns See Figure 2.7, C L = 15pF Pulse Width Distortion |t PHL – t PLH | PWD5.0nsSee Figure 2.7 , C L = 15pFRising Time t r 5.0 ns See Figure 2.7 , C L = 15pF Falling Timet f5.0 nsSee Figure 2.7 , C L = 15pFPeak Eye Diagram Jitter t JIT (PK) 350psChannel-to-Channel Delay Skewt SK (c2c)2.5nsPart-to-Part Delay Skew t SK (p2p)5.0ns(VDD1=2.5V± 10%, VDD2=2.5V± 10%, Ta=-40℃ to 125℃. Unless otherwise noted, Typical values are at VDD1 = 2.5V, VDD2 = 2.5V, Ta =25℃)Supply currentNSi8120I DD1(Q0) 0.53 0.8 mA All Input 0V for NSi8120x0 Or All Input at supply for NSi8120x1 I DD2(Q0) 1.11.65 mA I DD1(Q1)2.85 4.28 mA All Input at supply for NSi8120x0 Or All Input 0V for NSi8120x1 I DD2(Q1)1.15 1.73 mA I DD1(1M) 1.632.45 mA All Input with 1Mbps, C L = 15pFI DD2(1M) 1.21 1.82 mA I DD1(10M) 1.68 2.52 mA All Input with 10Mbps, C L = 15pFI DD2(10M) 2.05 3.08 mA I DD1(100M) 1.95 2.93 mA All Input with 100Mbps, C L = 15pFI DD2(100M)10.415.6mANSi8121/ NSi8122I DD1(Q0) 0.96 1.44 mA All Input 0V for NSi812xx0 Or All Input at supply for NSi812xx1I (Q0)0.931.395mAF ID EN T IA LI DD1(Q1) 2.11 3.165 mA All Input at supply for NSi812xx0Or All Input 0V for NSi812xx1 I DD2(Q1) 2.05 3.075 mA I DD1(1M) 1.58 2.37 mA All Input with 1Mbps, C L = 15pFI DD2(1M) 1.54 2.31 mA I DD1(10M) 2.02 3.03 mA All Input with 10Mbps, C L = 15pFI DD2(10M) 2.04 3.06 mA I DD1(100M) 6.03 9.045 mA All Input with 100Mbps, C L = 15pF I DD2(100M)6 9 mAData RateDR 0 150 Mbps Minimum Pulse Width PW 5.0 nsPropagation Delayt PLH 5 10 15 nsSee Figure 2.7 , C L = 15pF t PHL5 10 15nsSee Figure 2.7, C L = 15pFPulse Width Distortion |t PHL – t PLH | PWD5.0nsSee Figure 2.7 , C L = 15pFRising Time t r5.0ns See Figure 2.7 , C L = 15pF Falling Timet f5.0 ns See Figure 2.7 , C L = 15pFPeak Eye Diagram Jitter t JIT (PK)350ps Channel-to-Channel Delay Skewt SK (c2c)2.5ns Part-to-Part Delay Skew t SK (p2p)5.0ns2.2. TYPICAL PERFORMANCE CHARACTERISTICSFigure 2.1 NSi8120 VDD1 Supply Current vs Data Rate Figure 2.2 NSi8120 VDD2 Supply Current vs Data RateC OE2.3. PARAMETER MEASUREMENT INFORMATIONC LFigure 2.7 Switching Characteristics Test Circuit and WaveformFigure 2.8 Common-Mode Transient Immunity Test CircuitC O NF ID EN T IA L3.0 HIGH VOLTAGE FEATURE DESCRIPTION3.1. INSULATION AND SAFETY RELATED SPECIFICATIONSMinimum External Air Gap (Clearance)L(I01) 4.0 8.0 mm Shortest terminal-to-terminal distance through air Minimum External Tracking (Creepage)L(I02)4.08.0mmShortest terminal-to-terminal distance across the package surfaceMinimum internal gap DTI 20 um Distance through insulationTrackingResistance(Comparative Tracking Index) CTI>400VDIN EN 60112 (VDE 0303-11); IEC 60112Material GroupⅡ3.2. DIN VDE V 0884-11（VDE V 0884-11）:2017-01 INSULATION CHARATERISTICSSOIC-8 SOIC-16 Installation Classification per DIN VDE 0110For Rated Mains Voltage ≤ 150V rms Ⅰto Ⅳ Ⅰto Ⅳ For Rated Mains Voltage ≤ 300V rms Ⅰto Ⅲ Ⅰto Ⅳ For Rated Mains Voltage ≤ 400V rms Ⅰto Ⅲ Ⅰto Ⅳ Climatic Classification10/105/2110/105/21 Pollution Degree per DIN VDE 0110, Table 122Maximum repetitive isolation voltageVIORM 565 849 Vpeak Input to Output Test Voltage, Method B1V IORM × 1.5 = V pd (m) , 100%production test, t ini = t m = 1 sec, partial discharge < 5 pCV pd (m)8471273VpeakInput to Output Test Voltage, Method AAfter Environmental Tests Subgroup 1V IORM × 1.2= V pd (m) , t ini = 60 sec, t m = 10 sec, partial V pd (m)6781018VpeakC O N T IA LAfter Input and /or Safety Test Subgroup 2 and Subgroup 3 V IORM × 1.2= V pd (m) , t ini = 60 sec, t m = 10 sec, partialdischarge < 5 pC V pd (m)6781018VpeakMaximum transient isolation voltage t = 60 sec VIOTM 5300 7000 Vpeak Maximum Surge Isolation VoltageTest method per IEC60065,1.2/50uswaveform, VTEST=VIOSM×1.3VIOSM53845384VpeakIsolation resistance VIO =500V RIO >109 >109 Ω Isolation capacitance f = 1MHzCIO 0.6 0.6pFInput capacitanceCI22pF Total Power Dissipation at 25℃Ps1499 mW Safety input, output, or supply currentθJA = 140 °C/W, V I = 5.5 V, T J = 150 °C, T A = 25 °C Is160mAθJA = 84 °C/W, V I = 5.5 V, T J = 150 °C, T A = 25 °C237 mA Case TemperatureTs150150℃Figure 3.2 NSi8120W/NSi8121W/NSi8122W Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE V 0884-11C O NF ID EN T IA L3.3. REGULATORY INFORMATIONThe NSi8120N/NSi8121N/NSi8122N are approved by the organizations listed in table.UL 1577 Component Recognition Program 1Approved under CSA ComponentAcceptance Notice 5ADIN VDE V 0884-11:2017-012Certified by CQC11-471543-2012 GB4943.1-2011Single Protection, 3750V rms Isolation voltageSingle Protection, 3750V rms IsolationvoltageBasic Insulation 565Vpeak, V IOSM =5384VpeakBasic insulation at 400V rms (565Vpeak)File (E500602)File (E500602)File (5024579-4880-0001)File (pending)1 In accordance with UL 1577, each NSi8120N/NSi8121N/NSi8122N is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 sec.2 In accordance with DIN VDE V 0884-11, each NSi8120N/NSi8121N/NSi8122N is proof tested by applying an insulation test voltage ≥ 847 V peak for 1 sec(partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN VDE V 0884-11 approval.The NSi8120W/NSi8121W/NSi8122W are approved by the organizations listed in table.UL 1577 Component Recognition Program 1Approved under CSAComponent Acceptance Notice5ADIN VDE V 0884-11(VDE V 0884-11):2017-012 Certified by CQC11-471543-2012 GB4943.1-2011Single Protection, 5000V rms Isolation voltageSingle Protection, 5000V rmsIsolation voltageBasic Insulation 849Vpeak, V IOSM =5384Vpeak Basic insulation at 800V rms (1131Vpeak) Reinforced insulation at 400V rms (565Vpeak)File (E500602)File (E500602)File (5024579-4880-0001)File (pending)1 In accordance with UL 1577, each NSi8120W/NSi8121W/NSi8122W is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec.2 In accordance with DIN VDE V 0884-11, each NSi8120W/NSi8121W/NSi8122W is proof tested by applying an insulation test voltage ≥ 1273 V peak for 1 sec(partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN VDE V 0884-11 approval.4.0 FUNCTION DESCRIPTIONThe NSi812x is a Dual-channel digital isolator based on a capacitive isolation barrier technique. The digital signal is modulated with RF carrier generated by the internal oscillator at the Transmitter side. Then it is transferred through the capacitive isolation barrier and demodulated at the Receiver side.The NSi812x devices are high reliability dual-channel digital isolator with AEC-Q100 qualified. The NSi812x device is safety certified by UL1577 support several insulation withstand voltages (3.75kV rms , 5kV rms ), while providing high electromagnetic immunity and low emissions at low power consumption. The data rate of the NSi812x is up to 150Mbps, and the common-mode transient immunity (CMTI) is up to 150kV/us. The NSi812x device provides digital channel direction configuration and the default output level configuration when the input power is lost. Wide supply voltage of the NSi812x device support to connect with most digital interface directly, easy to do the level shift. High system level EMC performance enhance reliability and stability of use.The NSi812x has a default output status when VDDIN is unready and VDDOUT is ready as shown in Table 4.1, which helps for diagnosis when power is missing at the transmitter side. The output B follows the same status with the input A within 1us after powering up.C O NF ID EN T IA LCopyright © 2019, NOVOSENSEPage 12 Table 4.1 Output status vs. power statusH Ready Ready H Normal operation.L Ready Ready L XUnreadyReadyL HThe output follows the same status with the input within 60us after input side VDD1 is powered on.X Ready Unready XThe output follows the same status with the input within 60us after output side VDD2 is powered on.5.0 APPLICATION NOTE5.1. PCB LAYOUTThe NSi812x requires a 0.1 µF bypass capacitor between VDD1 and GND1, VDD2 and GND2. The capacitor should beplaced as close as possible to the package. Figure 5.1 to Figure 5.4 show the recommended PCB layout, make sure the space under the chip should keep free from planes, traces, pads and via. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series with the inputs and outputs if the system is excessively noisy. The series resistors also improve the system reliability such as latch-up immunity.The typical output impedance of an isolator driver channel is approximately 50 Ω, ±40%. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.Figure5.1 Recommended PCB Layout — Top Layer Figure5.2 Recommended PCB Layout — Bottom LayerFigure5.3 Recommended PCB Layout — Top Layer Figure5.4 Recommended PCB Layout — Bottom Layer5.2. HIGH SPEED PERFORMANCEFigure 5.5 shows the eye diagram of NSi812x at 200Mbps data rate output. The result shows a typical measurement on the NSi812x with 350ps p-p jitter.C O NF ID EN T IA LFigure5.5 NSi812x Eye Diagram5.3. TYPICAL SUPPLY CURRENT EQUATIONSThe typical supply current of NSi812x can be calculated using below equations. I DD1 and I DD2 are typical supply currents measured in mA, f is data rate measured in Mbps, C L is the capacitive load measured in pFNSi8120:I DD1 = 0.19 *a1+1.45*b1+0.82*c1. I DD2 = 1.36+ VDD1*f* C L *c1*10-9When a1 is the channel number of low input at side 1, b1 is the channel number of high input at side 1, c1 is the channel number of switch signal input at side 1.NSi8121/ NSi8122:I DD1 = 0.87 +1.26*b1+0.63*c1+ VDD1*f* C L *c2*10-9I DD2 = 0.87 +1.26*b2+0.63*c2+ VDD1*f* C L *c1*10-9When b1 is the channel number of high input at side 1, c1 is the channel number of switch signal input at side 1, b2 is the channel number of high input at side 2, c2 is the channel number of switch signal input at side 2.6.0 PACKAGE INFORMATIONVDD GND 22VDD INA GND 2VDD 2Figure 6.1 NSi8120N Package Figure 6.2 NSi8121N PackageC O NF ID EN T IA LVDD INBGND 22Figure 6.3 NSi8122N PackageFigure 6.4 SOIC8 Package Shape and Dimension in millimeters (inches)Table6.1 NSi8120N/ NSi8121N/ NSi8122N Pin Configuration and DescriptionNSi8121N PIN NO.NSi8122N PIN NO.SYMBOL FUNCTION1 1 1 VDD1 Power Supply for Isolator Side 12 7 2 INA Logic Input A3 3 6 INB Logic Input B4 4 4 GND1 Ground 1, the ground reference for Isolator Side 15 5 5 GND2 Ground 2, the ground reference for Isolator Side 26 6 3 OUTB Logic Output B7 2 7 OUTA Logic Output A888VDD2Power Supply for Isolator Side 2C O NFVDD GND GND 2VDD 2GND 2GND NC NCNC VDD GND GND 2VDD 22GND NC NC NCFigure 6.5 NSi8120W Package Figure 6.6 NSi8121W PackageVDD INB GND GND 2VDD 2GND 2GND NC NC NCFigure 6.7 NSi8122W PackageFigure 6.8 WB SOIC16 Package Shape and Dimension in millimeters and (inches)C O NF ID EN T IA LTable 6.2 NSi8120W/ NSi8121W/ NSi8122W Pin Configuration and Description1 1 1 GND1 Ground 1, the ground reference for Isolator Side 12 2 2 NC No Connection.3 3 3 VDD1 Power Supply for Isolator Side 14 13 4 INA Logic Input A5 5 12 INB Logic Input B6 6 6 NC No Connection.7 7 7 GND1 Ground 1, the ground reference for Isolator Side 18 8 8 NC No Connection. 9 9 9 GND2 Ground 2, the ground reference for Isolator Side 210 10 10 NC No Connection. 11 11 11 NC No Connection. 12 12 5OUTB Logic Output A 13 4 13OUTALogic Output B 14 14 14 VDD2 Power Supply for Isolator Side 215 15 15 NC No Connection.161616GND2Ground 2, the ground reference for Isolator Side 27.0TAPE AND REEL INFORMATIONLAITNEDIFNOCC O NF ID EN T IA LFigure 7.1 Tape and Reel Information of SOIC8LAITNEDIFNOCFigure 7.2 Tape and Reel Information of WB SOIC16NF ID EN T IA L8.0 ORDER INFORMATIONNSi8120N0 3.75 2 0 150 Low -40 to 125℃ NO SOIC8 NSi8120N1 3.75 2 0 150 High -40 to 125℃ NO SOIC8 NSi8121N0 3.75 1 1 150 Low -40 to 125℃ NO SOIC8 NSi8121N1 3.75 1 1 150 High -40 to 125℃ NO SOIC8 NSi8122N0 3.75 1 1 150 Low -40 to 125℃ NO SOIC8 NSi8122N1 3.75 1 1 150 High -40 to 125℃ NO SOIC8 NSi8120W0 5 2 0 150 Low -40 to 125℃ NO WB SOIC16 NSi8120W1 5 2 0 150 High -40 to 125℃ NO WB SOIC16 NSi8121W0 5 1 1 150 Low -40 to 125℃ NO WB SOIC16 NSi8121W1 5 1 1 150 High -40 to 125℃ NO WB SOIC16 NSi8122W0 5 1 1 150 Low -40 to 125℃ NO WB SOIC16 NSi8122W1 5 1 1 150 High -40 to 125℃ NO WB SOIC16 NSi8120N0Q 3.75 2 0 150 Low -40 to 125℃ YES SOIC8 NSi8120N1Q 3.75 2 0 150 High -40 to 125℃ YES SOIC8 NSi8121N0Q 3.75 1 1 150 Low -40 to 125℃ YES SOIC8 NSi8121N1Q 3.75 1 1 150 High -40 to 125℃ YES SOIC8 NSi8122N0Q 3.75 1 1 150 Low -40 to 125℃ YES SOIC8 NSi8122N1Q 3.75 1 1 150 High -40 to 125℃ YES SOIC8 NSi8120W0Q 5 2 0 150 Low -40 to 125℃ YES WB SOIC16 NSi8120W1Q 5 2 0 150 High -40 to 125℃ YES WB SOIC16 NSi8121W0Q 5 1 1 150 Low -40 to 125℃ YES WB SOIC16 NSi8121W1Q 5 1 1 150 High -40 to 125℃ YES WB SOIC16 NSi8122W0Q 5 1 1 150 Low -40 to 125℃ YES WB SOIC16 NSi8122W1Q 5 1 1 150 High -40 to 125℃YES WB SOIC16 NOTE: All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. All devices are AEC-Q100 qualified.Part Number Rule:NSi(81)(2)(1)(N)(1)(Q)C O NF ID EN T IA LNSi8120/NSi8121/NSi81229.0 REVISION HISTORY1.0 Original2017/11/15 1.1 Change to Ordering information2018/3/26 1.2 Add maximum operation current specification. 2018/6/20 1.3 Change block diagram 2018/7/28 1.4 Correct Table 6.2 Pin No.2018/8/20 1.5 Add specification “Input Pull high or low Current” 2018/9/10 1.6 Add “Maximum Input/Output Pulse Voltage” 2018/10/91.7 Change to Ordering information 2018/12/20 1.8 Change Certification Information2019/06/17。

MJ1214;MJ1213;MJ1211;MJ1222;MJ1225;中文规格书,Datasheet资料

.012" ± .006" (0.30 ±0.15 mm) 160 grams ±50 grams (.35 lbs.) -20°C to +70°C -30°C to +80°C for 96 hours 30G (peak value) for 11 millisec. per Method 213B, MIL-STD-202F (3 times each on 6 sides). 10-55-10 Hz. for 1 minute in X, Y and Z planes per Method 201A, MIL-STD-202F (2 hours in each direction).
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE.
MJTP SERIES - 12 MM SQUARE TACT SWITCHES
MJTP1212
MJTP1212A
MJTP1212B
MJTP1212C
FEATURES
SPST momentary action. Excellent tactile feed-back (Snap dome). Long operating life for high reliability. Molded-in terminals minimize wicking of flux or solder. Flush, round, keyed or square actuator. Thru-hole mounting.
US # MJ122 EU # U5550 Round cap
M
Note - add digit from table to cap part numbers above for color. Example - MJ1212 indicates square black cap.

M12L16161A_datasheet

Revision HistoryRevision 0.1 (Oct. 23 1998)-OriginalRevision 0.2 (Dec. 4 1998)-Add 200MHZRevision 1.0 (Dec. 10 1999)-Delete Preliminary-Rename the filenameRevision 1.1 (Jan. 26 2000)-Add –5.5 Spec.Revision 1.2 (Apr. 25 2000)-Correct error typing of C1 dimensionRevision 1.3 (Nov. 27 2000)-P5 Number of valid output data CAS Latency 3Æ 2ea -P17. P19. P21 Read Command shift right 1CLK-P15. P19. P20 Precharge Command shift left 1CLK Revision 1.4 (Feb. 22 2001)-P6 modify tOH –6(2ns) & -7(2ns)Revision 1.5 (Jun. 4 2001)-P3. P4 modify DC currentRevision 1.6(Sep. 7 2001)-P5 modify AC parametersRevision 1.7 (Mar. 20 2002)-P28 C1(Nom)=0.15mmÆ0.127mm-P28 delete symbol=ZDRevision 1.8 (Dec. 16 2003)-Modify stand off=0.051~0.203mmRevision 1.9 (Mar. 05 2004)-Correct typing error of timing (tRC; tRP;tRCD)-Add tRRD timing chartRevision 2.0 (May. 10 2005)Add “Pb-free” to ordering informationRevision 2.1 (Jul. 07 2005)-Modify I CC1, I CC2N, I CC3N, I CC4, I CC5 spec-Delete –5.5, -6, -8, -10 AC specRevision 2.2 (Oct. 06 2005)-Add 60V FBGARevision 2.3 (Nov. 15 2005)-Modify VFBGA 60Ball Total high specRevision 2.4 (May. 03 2007)-Delete BGA ball name of packing dimensionsSDRAM 512K x 16Bit x 2BanksSynchronousDRAMFEATURESz JEDEC standard 3.3V power supplyz LVTTL compatible with multiplexed addressz Dual banks operationz MRS cycle with address key programs-CAS Latency (2 & 3 )-Burst Length (1, 2, 4, 8 & full page)-Burst Type (Sequential & Interleave)z All inputs are sampled at the positive going edge of the system clockz Burst Read Single-bit Write operationz DQM for maskingz Auto & self refreshz32ms refresh period (2K cycle)GENERAL DESCRIPTIONThe M12L16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by16 bits, fabricated with high performance CMOS technology.Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.ORDERING INFORMATIONPart NO. MAX Freq. PACKAGE COMMENTSM12L16161A-5TG200MHz TSOP(II) Pb-free M12L16161A-7TG143MHz TSOP(II) Pb-free M12L16161A-7BG143MHz VFBGA Pb-freePIN CONFIGURATION (TOP VIEW)V DD DQ0 DQ1V SSQ DQ2 DQ3V DDQ DQ4 DQ5V SSQ DQ6 DQ7V DDQ LDQMCAS RAS CSBAA10/AP A0A1A2A3V DD V SSDQ15DQ14V SSQDQ13DQ12V DDQDQ11DQ10V SSQDQ9DQ8V DDQN.C/RFUUDQMCLKCKEN.CA9A8A7A6A5A4V SS50PIN TSOP(II)(400mil x 825mil)(0.8 mm PIN PITCH)FUNCTIONAL BLOCK DIAGRAMPIN FUNCTION DESCRIPTIONDQ0 ~ 15 Data Input / Output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved noise immunity.N.C/RFU No Connection/Reserved for Future UseThis pin is recommended to be left No Connection on the device.ABSOLUTE MAXIMUM RATINGSParameter Symbol Value UnitVoltage on any pin relative to V SS V IN,V OUT-1.0 ~ 4.6 VVoltage on V DD supply relative to V SS V DD,V DDQ-1.0 ~ 4.6 VStorage temperature T STG-55 ~ + 150 C°Power dissipation P D 0.7 W Short circuit current I OS 50 MA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, T A=0 to 70C°)Parameter Symbol Min Typ Max Unit NoteSupply voltage V DD,V DDQ 3.0 3.3 3.6 VInput logic high voltage V IH 2.0 3.0V DD+0.3 V 1Input logic low voltage V IL -0.3 0 0.8 V 2 Output logic high voltage V OH 2.4 - - VI OH =-2mAOutput logic low voltage V OL - - 0.4VI OL = 2mAInput leakage current I IL -5 - 5 uA 3 Output leakage current I OL -5 - 5 uA 4 Note : 1.V IH (max) = 4.6V AC for pulse width ≤ 10ns acceptable.2.V IL (min) = -1.5V AC for pulse width ≤ 10ns acceptable.3.Any input 0V≤V IN≤V DD+ 0.3V, all other pins are not under test = 0V.4.Dout is disabled, 0V ≤V OUT≤ VDD.CAPACITANCE (V DD = 3.3V, T A = 25C°, f = 1MHz)DC CHARACTERISTICS°V IH(min)/V IL(max)=2.0V/0.8V) (Recommended operating condition unless otherwise noted, T A = 0 to 70CNote: 1.Measured with outputs open. Addresses are changed only one time during t CC(min).2.Refresh period is 32ms. Addresses are changed only one time during t CC(min).AC OPERATING TEST CONDITIONS (V DD =3.3V ±0.3V,T A = 0 to 70C °)ParameterValue Unit Input levels (Vih/Vil)2.4 / 0.4 V Input timing measurement reference level 1.4 V Input rise and fall timetr / tf = 1 / 1ns Output timing measurement reference level 1.4 V Output load conditionSee Fig.2OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time andthen rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks. (Fig.2) AC Output Load Circuit1.4V(Fig.1) DC Output Load circuitΩAC CHARACTERISTICS (AC operating conditions unless otherwise noted)-5 -7 ParameterSymbol Min Max Min Max UnitNoteCAS Latency =3 5 7 CLK cycle time CAS Latency =2 t CC 710008.61000ns 1CAS Latency =3 - 4.5 - 6CLK to validoutput delayCAS Latency =2t SAC - 5 - 6ns 1Output data hold time t OH 2 2 ns 2 CLK high pulse width t CH 2 2.5 ns 3 CLK low pulse width t CL 2 2.5 ns 3 Input setup time t SS 2 2 ns 3 Input hold time t SH 1 1 ns 3 CLK to output in Low-Z t SLZ 1 1 ns 2 CAS Latency =3 - 5.5 - 6CLK to output in Hi-ZCAS latency =2t SHZ- 5.5 - 6ns*All AC parameters are measured from half to half.Note: 1.Parameters depend on programmed CAS latency.2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.3.Assumed input rise and fall time (tr & tf)=1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter.FREQUENCY vs. AC PARAMENTER RELATIONSHIP TABLEM12L16161A-5T(G)(Unit: number of clock)t RC t RAS t RP t RRD t RCD t CCD t CDL t RDL FrequencyCASLatency 55ns 40ns 15ns 10ns 15ns 5ns 5ns 10ns200MHz(5.0ns) 3 11 8 3 2 3 1 1 2 166MHz(6.0ns) 3 10 7 3 2 3 1 1 2 143MHz(7.0ns) 2 8 6 3 2 3 1 1 2 125MHz(8.0ns) 2 7 5 2 2 2 1 1 2 111MHz(9.0ns) 2 7 5 2 2 2 1 1 2M12L16161A-7T(G)(Unit: number of clock)t RC t RAS t RP t RRD t RCD t CCD t CDL t RDL FrequencyCASLatency 63ns 42ns 20ns 14ns 20ns 7ns 7ns 14ns143MHz(7.0ns) 3 9 6 3 2 3 1 1 2 125MHz(8.0ns) 3 8 6 3 2 3 1 1 2 111MHz(9.0ns) 2 7 5 3 2 3 1 1 2 100MHz(10.0ns) 2 7 5 2 2 2 1 1 2 83MHz(12.0ns) 2 6 4 2 2 2 1 1 2Note : 1. t RDL ≥16.7ns is recommended for M12L16161A.Mode Register11 10 9 8 7 6 5 4 3 2 1 00 0 0 0 1 JEDEC Standard Test Set (refresh counter test) 11 10 9 8 7 6 5 4 3 2 1 0x x 1 0 0 LTMODE WT BL Burst Read and Single Write (for WriteCache)Through11 10 9 8 7 6 5 4 3 2 1 01 0 Use in future11 10 9 8 7 6 5 4 3 2 1 0x x x 1 1 v v v v v v v Vender SpecificMode Register WriteBurst Length and Sequence (Burst of Two)Starting Address(column address A0 binary)Sequential AddressingSequence (decimal)Interleave AddressingSequence (decimal)0 0,10,11 1,01,0 (Burst of Four)Starting Address(column address A1-A0, binary)Sequential AddressingSequence (decimal)Interleave AddressingSequence (decimal)00 0,1,2,30,1,2,301 1,2,3,01,0,3,210 2,3,0,12,3,0,111 3,0,1,23,2,1,0 (Burst of Eight)Starting Address(column address A2-A0, binary)Sequential AddressingSequence (decimal)Interleave AddressingSequence (decimal)000 0,1,2,3,4,5,6,70,1,2,3,4,5,6,7001 1,2,3,4,5,6,7,01,0,3,2,5,4,7,6010 2,3,4,5,6,7,0,12,3,0,1,6,7,4,5011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4100 4,5,6,7,0,1,2,34,5,6,7,0,1,2,3101 5,6,7,0,1,2,3,45,4,7,6,1,0,3,2110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice.POWER UP SEQUENCE1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs.2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.3.Issue precharge commands for all banks of the devices.4.Issue 2 or more auto-refresh commands.5.Issue mode register set command to initialize the mode register.Cf.)Sequence of 4 & 5 is regardless of the order.SIMPLIFIED TRUTH TABLE(V=Valid, X=Don’t Care, H=Logic High , L =Logic Low)Note:1. OP Code: Operation CodeA0~ A10/AP, BA: Program keys.(@MRS)2. MRS can be issued only at both banks precharge state.A new command can be issued after 2 clock cycle of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge command is meant by “Auto”.Auto / self refresh can be issued only at both banks idle state.4. BA: Bank select address.If “Low”: at read, write, row active and precharge, bank A is selected.If “High”: at read, write, row active and precharge, bank B is selected.If A10/AP is “High” at row precharge, BA ignored and both banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued.Another bank read /write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), butmakesHi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1C L O C KC K EC SR A SC A SA D D RW ED QD Q MA10/A P B A*Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.2. Bank active & read/write are controlled by BA.BA Active & Read/Write0 BankAB1 Bank3.Enable and disable auto precharge function are controlled by A10/AP in read/write command.A10/AP BA Operation0 Disable auto precharge, leave bank A active at end of burst.1 Disable auto precharge, leave bank B active at end of burst.10 Enable auto precharge, precharge bank A at end of burst.1 Enable auto precharge, precharge bank B at end of burst.4.A10/AP and BA control bank precharge when precharge command is asserted.A10/AP BA prechargeA0 0 Bank0 1 BankBBanks1 X BothPower Up SequenceC L O C KC K EA D D RD QD Q MA10/A PR o w A c t i v e: D o n 't c a r eBACSRASCASWERead & Write Cycle at Same Bank @Burst Length = 4*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ ) after the clock.3.Access time from Row active command. tcc*(t RCD +CAS latency-1)+t SAC4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst) Burst can’t end in Full Page Mode.Read (A-Bank)(A-Bank)(A-Bank)(A-Bank)W rite (A-Bank)(A-Bank): Don't careQCPage Read & Write Cycle at Same Bank @ Burst Length=4*Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid buscontention.2.Row precharge will interrupt writing. Last data input, t RDL before Row precharge, will be written.3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.CLOCK CKECSRASBAADDR A10/APCL=2CL=3WEDQMRow Active (A-Bank)(A-Bank)(A-Bank)(A-Bank)(A-Bank)(A-Bank)DQPage Read Cycle at Different Bank @ Burst Length=4*Note: 1.CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege.2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.CLOCKCKECSBAADDRA10/AP CL=2CL=3WEDQM(B-Bank)DQPage Write Cycle at Different Bank @Burst Length = 4*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.CLOCKCKE CSRASCASBAADDR A10/AP WEDQMDQ(A-Bank)(B-Bank)Read & Write Cycle at Different Bank @ Burst Length = 4*Note: 1.t CDL should be met to complete write.Read & Write Cycle with auto Precharge @ Burst Length =4*Note: 1.t CDL Should be controlled to meet minimum t RAS before internal precharge start(In the case of Burst Length=1 & 2 and BRSW mode)C L O C KC K EC A SA D D RD QD Q MA10/A P B AC L =2C L =3( B - Bank ): D o n ' t C a r eC SR A SClock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4*Note:1.DQM is needed to prevent bus contention.C L O C KC K EAD D R D Q D Q MA10/A PR e a d D Q MW r i t eS u s p e n s i o n:D o n 't C a r eBAC SR A SC A SW ERead Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page*Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue.2.About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycle”.3.Burst stop is valid at every burst length.C L O C KC K EA D DR D QD Q MA10/A P BAC L =2C L =3CSRASCASWrite Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page*Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue.2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of t RDL .DQM at write interrupted by precharge command is needed to prevent invalid write. Input data after Row precharge cycle will be masked internally. 3.Burst stop is valid at every burst length.C L O C KC K EA D D R D Q D Q MA10/A PC SR A SBABurst Read Single bit Write Cycle @Burst Length=2*Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.2.When BRSW write command with auto precharge is executed, keep it in mind that t RAS should not be violated. Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge command will be issued after two clock cycles.C L O C KC K EA D DR C L =2D Q MA 10/A P BAD QC L =3C SR A SActive/Precharge Power Down Mode @CAS Latency=2, Burst Length=4*Note :1.Both banks should be in idle state prior to entering precharge power down mode.2.CKE should be set high at least 1CLK+tss prior to Row active command.3.Can not violate minimum refresh specification. (32ms)C LA A10Self Refresh Entry & Exit Cycle*Note: TO ENTER SELF REFRESH MODE1. CS ,RAS & CAS with CKE should be low at the same clock cycle.2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.3. The device remains in self refresh mode as long as CKE stays “Low”.cf.) Once the device enters self refresh mode, minimum t RAS is required before exit from self refresh.TO EXIT SELF REFRESH MODE4. System clock restart and be stable before returning CKE high.5. CS Starts from high.6. Minimum t RC is required after CKE going high to complete self refresh exit.7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.C L O C KC K EA D D RD QD Q MA10/A P: D o n 't c a r eBAR A SC SMode Register Set CycleAuto Refresh Cycle*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.MODE REGISTER SET CYCLE*Note: 1.CS ,RAS ,CAS &WE activation at the same clock cycle with address key will set internal mode register.2.Minimum 2 clock cycles should be met before new RAS activation.3.Please refer to Mode Register Set table.C L O C KC K EA D D RC SR A SC A SD QD Q MPACKAGE DIMENSIONS50-LEAD TSOP(II) SDRAM(400mil)PACKING DIMENSIONS60-BALL SDRAM ( 6.4x10.1 mm )Symbol Dimension in mm Dimension in inchMin Norm Max Min Norm MaxA 1.00 0.039A10.20 0.25 0.30 0.0080.0100.012A20.61 0.66 0.71 0.0240.0260.028Φb0.30 0.35 0.40 0.0120.0140.016D 6.30 6.40 6.50 0.2480.2520.256E 10.00 10.1010.200.3940.3980.402D1 3.90 0.154E19.10 0.358e 0.65 0.026Controlling dimension : Millimeter.Important NoticeAll rights reserved.No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT.The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice.The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others.Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs.ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.。

奇岩读卡器ICMA8121FMA8125CMA8127MA8168MA6116M110E

奇岩(MOAI) 产品线介绍联系人BillTEL: 135****9940。

读卡器IC ：型号接口属性封装支持存储卡类型备注MA8121HMA8121FUSB2.0DiceTF、SD、、mini SD、RS-MMC、MINI SDHC、MMCmobile、MMC、MMC Plus、micro SD单卡免晶振读卡器ICMA8125C USB2.0DiceTF、SD、mini SD、RS-MMC、MINI SDHC、MMCmobile、MMC、MMC Plus、MS Pro Duo、MS Micro(M2)、MS Pro、micro SD、MS Duo双卡免晶振读卡器ICMA8168USB2.0LQFP48(7X7)TF、SD、CF、mini SD、RS-MMC、MINI SDHC、MMCmobile、MMC、MMC Plus、MS Pro Duo、MS Micro(M2)、MS Pro、micro SD、MS Duo多卡读卡器IC MA8168A USB2.0LQFP48(7X7)TF、SD、CF、mini SD、RS-MMC、MINI SDHC、MMCmobile、MMC、MMC Plus、MS Pro Duo、MS Micro(M2)、MS Pro、micro SD、MS Duo多卡免晶振读卡器ICMA8121CThe MA8121C is an USB 2.0 Card Reader controller by a highly integrated single chipsolution designed to deliver high-speed data transmission between USB2.0 and SD, SDHC,miniSD, Micro SD(T-Flash), MMC, RC-MMC, MMC Micro, MMC Mobile flash interfacesspecification. The MA8121C is offered with COB (Chip On Board) Bounding and 28SSOPpackage. MA8121C complies with USB specification Rev. 2.0 and USB Mass Storage Classspecification Rev. 1.0 to support Windows ME/2000/XP/Vista/Win7, Mac OS 10.x above, andLinux Kernel 2.4 above. MA8121C needs fewest external component and bounding cost,thus manufacturers can effectively reduce the BOM and labor cost on PCBA. MA8121C isthe SD card reader with the best C/P value.MA8128MA8128 is a highly integrated USB SIM Card reader controller. The MA8128supports SIM card interface and extra SD card reader slot. MA8128 supports SIMwith proprietary user command and manufacturers can easily create a high-security SIM Card reader by deploying MA8128 and SIM Editor AP. The SD readersupports SD, SDHC, miniSD, Micro SD(T-Flash), MMC, RC-MMC, MMC Micro, MMC Mobile flash interfaces specification. MA8128 is offered with 28SSOP package andsupport Windows ME/2000/XP/Vista/Win7 OS system.MA8168The MA8168 is a single LUN USB2.0 to Flash Card Reader designed to deliveroutstanding performance for data transmission between USB and compatible flash cards such as CF, SD(SDHC), MMC, xD and Memory Stick Micro. Besides, MA8168 supports several operating systems, including MS Windows, LINUX and Mac OS.MA8168 integrate high speed MCU and DMA for highest data transfer. Besides 48pin LQFP package, MA8168 also customize pad design to fit dice base shipping format for cost effective solution. For moreMA8127The MA8127 is an USB 2.0 Card Reader controller by a highly integrated singlechip solution designed to deliver high-speed data transmission between USB and versatile flash card interfaces with up-to-date specification. The MA8127 is packaged with 48-pin LQFP for up to 3 LUNs (SD/MMC/Memory Stick Micro, SD/MMC/Memory Stick Micro, Micro SD/MMC micro /T-Flash) flash card reader.The MA8127 complies with USB specification Rev. 2.0 and USB Mass Storage Class specification Rev. 1.0 to support Windows ME/2000/XP/Vista, Mac OS 10.xabove, and Linux Kernel 2.4 above. MA8127 integrates a high speed 1T 8051 microprocessor and a high efficiency DMA hardware engine for the best data transfer performance between USB and flash card interfaces.MA8125EN MA8125 is a high performance USB 2.0 card reader controller that integratesan USB 2.0 PHY, an SIE (Serial Interface Engine), 8051, and memory cardcontroller logic into a single chip. It supports access to Memory Stick Micro,Micro SD/MMC Micro, Secure Digital™ (SD), Multi Media Card™ (MMC) throughUSB interface.MA8125 is developed with highest performance and fewest external componentsrequirement. The COB and SSOP-28 packaged provide the best cost/performanceratio for manufacturers. For more product information,外接硬盘盒IC型号接口属性封装支持硬盘类型备注MA6116USB2.0SSOP-282.5寸3.5寸硬盘，20G-1.5TB 容量硬盘USB toSATAM110E USB2.0LQFP-482.5寸3.5寸硬盘，20G-120G 容量硬盘USB TOIDEMOAI MA6116A is a bridge chip for USB to SATA interface, translating the host SCSIcommand to ATA/ATAPI command of SATA device, targeting the external HDDapplication. MA6116A complies with the USB Storage Class specifications ver.1.0 Bulkmode protocol and compatible with Windows 98/2000/XP/Vista/Win7, Mac OS 9, LinuxRedhat. With the in-house DMA and Transceiver capability, MA6116A provides themarket most outstanding read/write performance and BOM cost. MOAI providesproprietary password partition and OTB AP.2.1 MA6116 General DescriptionMOAI MA6116 is a bridge chip for USB to SATA interface, translating the host SCSI command to ATA/ATAPI command of SATA device, targeting the external HDD and DVD drives application.MA6116complies with the USB Storage Class specifications ver.1.0 Bulk mode protocol and compatible with Windows 98/2000/XP/Vista, Mac OS 9, Linux Redhat. With the in-house DMA and Transceiver capability, MA6116 provides the market most outstanding read/write performance and BOM cost.2.2 MA6116 Feature2.2.1 USB Featurez Supports USB2.0 specification with USB-IF LOGOz Supports USB2.0 specifications for 480Mbps and 12Mbps transfer ratez Supports Mass Storage Device Class Bulk only transferz Integrated USB 2.0 UTMI transceiver and Serial Interface Engine (SIE)z USB2.0 Self power and Bus power compliancez Endpoint:. Endpoint 0: 64 bytes control transfer.. Endpoint 1: 512 bytes bulk transfer for IN transaction.. Endpoint 2: 512 bytes bulk transfer for OUT transaction.2.2.2 Serial ATA Featurez Supports Gen1 (1.5Gbps) of SATA specification Rev 2.5z Supports ATA/ATAPI command for DMA, UDMA and PIO mode data transferz Supports ATA/ATAPI LBA 48bit addressing modez Support SATAII Asynchronous Recovery Feature. (Hot Plug)z Support SATA tri-state mode for pass through applicationz Supports SATA 1.5G/3G speed negotiation2.2.3 Overall Featurez Embedded 5V to 3.3V; 3.3V to 1.8V regulatorz Supports Windows 98/ME/XP/Vista, Linux Redhat, Mac 10 OS systemz Supports Microsoft WHQL certificationz Maximum data transfer rate at 36MB/secz One 12Mhz crystalz One LED pin for data access indicationz 28 SSOP packageMA6116 应用：1 外接硬盘盒，2外接CD光驱/CD-ROM全新支持DOS直接引导启动2000,xp,Vista系统直接光盘安装SATA串口笔记本USB2.0光驱外置光驱转接卡（转接板）。

PA12M,PA12M883, 规格书,Datasheet 资料

SG PARAMETER SYMBOL TEMP. POWER TEST CONDITIONS MIN MAX UNITS 1 Quiescent current I Q 25°C ±40V V IN = 0, A V = 100, R CL = .1Ω50 mA 1 Input offset voltage V OS 25°C ±40V V IN = 0, A V = 100 ±6 mV 1 Input offset voltage V OS 25°C ±10V V IN = 0, A V = 100 ±12 mV 1 Input offset voltage V OS 25°C ±45V V IN = 0, A V = 100 ±7 mV 1 Input bias current, +IN +I B 25°C ±40V V IN = 0 ±30 nA 1 Inout bias current,–IN –I B 25°C ±40V V IN = 0 ±30 nA 1 Input offset current I OS 25°C ±40V V IN = 0±30 nA 3 Quiescent current I Q –55°C ±40V V IN = 0, A V = 100, R CL = .1Ω 100 mA 3 Input offset voltage V OS –55°C ±40V V IN = 0, A V = 100 ±11.2 mV 3 Input offset voltage V OS –55°C ±10V V IN = 0, A V = 100 ±17.2 mV 3 Input offset voltage V OS –55°C ±45V V IN = 0, A V = 100 ±12.2 mV 3 Input bias current, +IN +I B –55°C ±40V V IN = 0 ±115 nA 3 Input bias current,–IN –I B –55°C ±40V V IN = 0 ±115 nA 3 Input offset current I OS –55°C ±40V V IN = 0±115 nA 2 Quiescent current I Q 125°C ±40V V IN = 0, A V = 100, R CL = .1Ω 50 mA 2 Input offset voltage V OS 125°C ±40V V IN = 0, A V = 100 ±12.5 mV 2 Input offset voltage V OS 125°C ±10V V IN = 0, A V = 100 ±18.5 mV 2 Input offset voltage V OS 125°C ±45V V IN = 0, A V = 100 ±13.5 mV 2 Input bias current, +IN +I B 125°C ±40V V IN = 0 ±70 nA 2 Input bias current, –IN –I B 125°C ±40V V IN = 0 ±70 nA 2 Input offset current I OS 125°C ±40V V IN = 0±70 nA 4 Output voltage, I O = 10A V O 25°C ±16V R L = 1Ω 10 V 4 Output voltage, I O = 80mA V O 25°C ±45V R L = 500Ω 40 V 4 Output voltage, I O = 5A V O 25°C ±35V R L = 6Ω30 V 4 Current limits I CL 25°C ±14V R L = 6Ω, R CL = 1Ω.6 .89 A 4 Stability/noise E N 25°C ±40V R L = 500Ω, C L = 1.5nF , / 1 1 mV 4 Slew rateSR 25°C ±40V R L = 500Ω2.5 10 V/µs 4 Open loop gainA OL 25°C ±40V R L = 500Ω, F = 10Hz96 dB 4 Common mode rejection CMR 25°C ±15V R L = 500Ω, F = DC, V CM = ±9V 74 dB 6 Output voltage, I O = 8A V O –55°C ±14V R L = 1Ω 8 V 6 Output voltage, I O = 80mA V O –55°C ±45V R L = 500Ω40 V 6 Stability/noise E N –55°C ±40V R L = 500Ω, C L = 1.5nF , / 1 1 mV 6 Slew rateSR –55°C ±40V R L = 500Ω2.5 10 V/µs 6 Open loop gainA OL –55°C ±40V R L = 500Ω, F = 10Hz96 dB 6 Common mode rejection CMR –55°C ±15V R L = 500Ω, F = DC, V CM = ±9V 74 dB 5 Output voltage, I O = 8A V O 125°C ±14V R L = 1Ω 8 V 5 Output voltage, I O = 80mA V O 125°C ±45V R L = 500Ω40 V 5 Stability/noise E N 125°C ±40V R L = 500Ω, C L = 1.5nF , / 1 1 mV 5 Slew rateSR 125°C ±40V R L = 500Ω2.5 10 V/µs 5 Open loop gainA OL 125°C ±40V R L = 500Ω, F = 10Hz96 dB 5Common mode rejectionCMR125°C±15VR L = 500Ω, F = DC, V CM = ±9V74dB/ 1 Minimum gain recommendation is either G = +4 (non-inverting) or G = –3 (inverting)./ 2 Input signals are calculated to result in internal powerdissipation of approximately 2.1W at case temperature = 125°C./ 3 These components are used to stabilize device due topoor hgh frequency characteristics of burn in board./22 PA12MUCONTACTING CIRRUS LOGIC SUPPORTFor all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact apex.support@.International customers can also request support by contacting their local Cirrus Logic Sales Representative.To find the one nearest to you, go to IMPORTANT NOTICECirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PROD-UCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUS-TOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex Precision Power, Apex and the Apex Precision Power logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.。

海尔生锂无金质紧密管系列用户指南说明书

—Features & Benefits:• Meets UL 514B and CSA C22.2, No. 18.3 for liquid-tight fittings• Full compliance to IEC 61386-1, -23 requirements, CE Certified• Trade sizes from 3/8” to 4” (12mm to 103mm)• Straight and 90° conduit bodies• NPT Threads• Coordinated performance with T&B Liquidtight Systems Flexible Metallic Conduits• Ingress protection ratings aligned with industrial enclosures• Safe Edge®, zinc plated steel ground cones provides superior bonding• Double Bevel Sealing Ring eases assembly and insures liquid-tight performance• Revolver® grounding version with GR part number suffix—Applications:• Typical applications include raceway for industrial and commercial applications such as suspended electrical systems, corrosive environments and portable equipment, where light weight requirements must be met• Ideal for use with LTAE and LTLE aluminum LT Flexible Metallic Conduits• Used where liquid-tight flexible metallic raceway is installed in outdoor or indoor locations, and exposed to continuous or intermittent moisture• Used to positively bond flexible liquid-tight flexible metallic conduit to boxes or enclosures • Liquid-tight applications against water, oils, cutting fluids, mild acids• For use in electrical circuits up to 1,000 V• Suitable for use in Class 1 Division 2, Class 2 Division 1 & 2 Hazardous Locations perNEC® Section 500—Construction / Material / Finish:• Trade sizes 3/8” to 4” Copper-Free Aluminum• Zinc plated steel ground cones• Thermoplastic Nylon sealing rings• Halogen Free seal rings• Aluminum Cast Locknuts with teeth for vibration resistance—Environment ratings:Working Temperature:• UL: Gen: -20 to +105°C (-4 to +221°F)• CSA: Gen: -20 to +105°C (-4 to +221°F)• IEC/CE: Gen: -25 to +105°C (-13 to +221°F)—Chemical Resistance Guide:• See Publication TDS000081 (Fittings: Aluminum & PA66 Polyamide)• See Publication TDS000117 (Liquid-tight Flexible Metal Conduits)—Conforms to:• UL 514B, Fittings for Cable and Conduit–File: E23018• CSA C22.2, No. 18.3, Outlet and Conduit Boxes, Fittings and Accessories–File: LR-4484• IEC/EN 61386-1, -23, Conduit Systems for Cable Management–EU DoC: EC-012-7187• RoHS (Restriction of Hazardous Substance directive)• NEMA FB-1 (Fittings and Conduit Bodies)• JIC EGP1 (Electrical standard for GP machine tools)• JIC EMP1 (Electrical Standard for Mass Production Engineering)• Federal Specification A-A 50552 (Fittings for flexible conduit)• Federal Specification H-28 (Threads)—Ingress Protection:• Provides “Ingress Integrity” between enclosures, fittings, conduits & seals when using Series 5200AL liquid-tight fittings and T&B Liquidtight Systems LFMC• Covers all trade sizes from 3/8” to 4” (12mm to 103mm)• Ingress ratings require use of Series 5260 Seal GasketsUL, CSA & NEMA system ingress ratings:• 5200AL UL Listed type ratings tested to UL 50E requirements with UL Listed LFMC• UL File No.: E23018–Indoor: Type 4, 12, 13–Outdoor: Type 3, 3R, 4• CSA C22.2, No. 94.2: Type 3, 3R, 4, 12, 13• NEMA 250: Type 3, 3R, 4, 12, 13IEC system ingress ratings:• IP Ingress Protection per IEC/EN EC 60529 requirements• IEC Ingress Ratings: IP66, IP67—Standards requirements:Designed to UL 514B and CSA C22.2, No. 18.3 test requirements including:• Assembly, Pull, Resistance, Oil spray, Polymer durability, Flammability coating thickness, Current withstandMeets all IEC/EN 61386-1, -23 standard requirements including:• Impact resistance - Code 3 Medium; 6 Joules• Tensile strength - Code 3 Medium; 500 N/2 min.• Lower and upper temperatures• IP protection against solid and liquidsAluminum Liquid-tight fittings areideal for use in corrosive environ-ments and where light weightconduit systems are required.Certifications / Standards:1—TECHNICAL DATA SHEETLiquid-tight fittings - Series 5200AL Aluminum For liquid-tight flexible metallic conduit• Dimensions for reference only.• Product must be installed in accordance with applicable national and local electrical codes.—We reserve the right to make technical changes or modify the contents of this document without prior notice. With re-gard to purchase orders, the agreed par-ticulars shall prevail. ABB Inc. does not ac-cept any responsibility whatsoever for potential errors or possible lack of infor-mation in this document.We reserve all rights in this document and in the subject matter and illustrations con-tained therein. Any reproduction, disclo-sure to third parties or utilization of its contents – in whole or in parts – is forbidden without prior written consent of ABB Inc. Copyright© 2018 ABB Inc.All rights reservedLet’s write the future.Together. S e r i e s 5200A L | T e c h n i c a l d a t a s h e e t | T D S 000118 A—ABB Inc.Electrification products Memphis, Tennessee USA2。

M12L128168A(2L)

SDRAM 2M x 16 Bit x 4 BanksSynchronous DRAMFEATURESy JEDEC standard 3.3V power supplyy LVTTL compatible with multiplexed addressy Four banks operationy MRS cycle with address key programs- CAS Latency ( 2 & 3 )- Burst Length ( 1, 2, 4, 8 & full page )- Burst Type ( Sequential & Interleave )y All inputs are sampled at the positive going edge of the system clocky Burst Read single write operationy DQM for maskingy Auto & self refreshy64ms refresh period (4K cycle)ORDERING INFORMATIONProduct ID Max Freq. Package Comments M12L128168A-5TG2L200MHz 54 Pin TSOP II Pb-free M12L128168A-5BG2L200MHz 54 Ball FBGAPb-freeM12L128168A-6TG2L166MHz 54 Pin TSOP IIPb-freeM12L128168A-6BG2L166MHz 54 Ball FBGA Pb-freeM12L128168A-7TG2L143MHz 54 Pin TSOP II Pb-freeM12L128168A-7BG2L143MHz 54 Ball FBGA Pb-freeGENERAL DESCRIPTIONThe M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.PIN CONFIGURATION (TOP VIEW) BALL CONFIGURATION (TOP VIEW)(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch )(BGA 54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2010BLOCK DIAGRAMPIN DESCRIPTIONDQElite Semiconductor Memory Technology Inc. Publication Date : Jul. 2010ABSOLUTE MAXIMUM RATINGSParameter Symbol Value UnitVoltage on any pin relative to V SS V IN , V OUT -1.0 ~ 4.6 V Voltage on V DD supply relative to V SS V DD , V DDQ -1.0 ~ 4.6 V Storage temperature TSTG -55 ~ +150C ° Power dissipation PD1WShort circuit currentI OS 50 mANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.DC OPERATING CONDITIONRecommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70C °)Parameter Symbol Min Typ Max Unit NoteSupply voltage V DD , V DDQ 3.0 3.33.6VInput logic high voltage V IH 2.0 3.0 V DD +0.3 V 1Input logic low voltage V IL -0.3 0 0.8 V 2Output logic high voltage V OH 2.4 --V I OH= -2mAOutput logic low voltage V OL - - 0.4 V I OL = 2mA Input leakage current I IL -5 - 5 μA 3 Output leakage currentI OL -5 - 5 μA4Note: 1. V IH (max) = 4.6V AC for pulse width ≤ 10ns acceptable.2. V IL (min) = -1.5V AC for pulse width ≤ 10ns acceptable.3. Any input 0V ≤ V IN ≤ V DD , all other pins are not under test = 0V.4. Dout is disabled, 0V ≤ V OUT ≤ V DD .CAPACITANCE (V DD = 3.3V, T A = 25C °, f = 1MHz)DC CHARACTERISTICS°Recommended operating condition unless otherwise noted，T A = 0 to 70CNote: 1. Measured with outputs open.2. Input signals are changed one time during 2 CLKS.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2010AC OPERATING TEST CONDITIONS (V DD = 3.3V ±0.3V ， T A = 0 to 70C °)Parameter Value UnitInput levels (Vih/Vil)2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall-timetr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load conditionSee Fig. 2(Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load CircuitOPERATING AC PARAMETER(AC operating conditions unless otherwise noted)Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and thenrounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.5. A new command may be given t RFC after self refresh exit.6. A maximum of eight consecutive AUTO REFRESH commands (with t RFC (min)) can be posted to any given SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6μs.)Outp utΩElite Semiconductor Memory Technology Inc. Publication Date : Jul. 2010AC CHARACTERISTICS (AC operating condition unless otherwise noted)-5 -6 -7Parameter SymbolMIN MAX MIN MAX MIN MAX Unit NoteCAS latency = 3 5 6 7CLK cycle time CAS latency = 2t CC10 100010 100010 1000ns 1 CAS latency = 3 -4.5-5.4-5.4CLK to validoutput delay CAS latency = 2t SAC- 6 - 6 - 6 ns 1,2CAS latency =32 - 2 - 2 - Output data hold time CAS latency = 2t OH2 - 2 - 2 -ns 2CLK high pulse width t CH 2 - 2.5 - 2.5 - ns 3 CLK low pulse width t CL 2 - 2.5 - 2.5 - ns 3 Input setup time t SS 1.5 - 1.5 - 1.5 - ns 3 Input hold time t SH 0.85- 1 - 1 - ns 3CLK to output in Low-Z t SLZ 1 - 1 - 1 - ns 2 CAS latency = 3 -4.5-5.4-5.4CLK to output in Hi-ZCAS latency = 2 t SHZ- 6 - 6 - 6ns-Note: 1. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.3. Assumed input rise and fall time (tr & tf) =1ns. If tr & tf is longer than 1ns. transient time compensation should be considered. i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.SIMPLIFIED TRUTH TABLE(V =Valid, X =Don’t Care. H =Logic High, L =Logic Low) Note: 1.OP Code: Operating CodeA0~A11 & BA0~BA1: Program keys. (@ MRS)2.MRS can be issued only at all banks precharge state.A new command can be issued after 2 CLK cycles of MRS.3.Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge of command is meant by “Auto”.Auto/self refresh can be issued only at all banks idle state.4.BA0~BA1: Bank select addresses.If BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.If BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selectedIf A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.5.During burst read or write with auto precharge, new read/write command can not be issued.Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after the end of burst.6.Burst stop command is valid at every burst length.7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), butmakes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010MODE REGISTER FIELD TABLE TO PROGRAM MODESRegister Programmed with MRSAddress BA0~BA1 A11~A10/AP A9 A8A7A6A5A4A3 A2 A1 A0Function RFU RFU W.B.L.TM CAS Latency BT Burst LengthTest Mode CAS Latency Burst Type Burst LengthA8 A7 Type A6 A5 A4Latency A3Type A2A1 A0 BT = 0BT = 1Set0 0 0 Reserved0 Sequential0 0 0 1 1 Register0 0 Mode0 1 Reserved 0 0 1 Reserved 1 Interleave0 0 1 2 21 0 Reserved 0 1 02 0 1 0 4 41 3 0 1 1 8 8111 Reserved 0Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved A9 Length 1 0 1 Reserved 1 0 1 Reserved ReservedReserved Reserved0 Burst 111Reserved 1Reserved 1 1 1 FullPage Reserved1Bit 11 Single1Full Page Length: 512Note: 1. RFU (Reserved for future use) should stay “0” during MRS cycle.2. If A9 is high during MRS cycle, “Burst Read single write” function will be enabled.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010BURST SEQUENCE (BURST LENGTH = 4)Initial AddressSequential Interleave A1 A00 0 0 1 2 3 0 1 2 30 1 1 2 3 0 1 0 3 21 023 0 1 2 3 0 11 1 3 0 123 2 1 0BURST SEQUENCE (BURST LENGTH = 8)Initial AddressSequential Interleave A2 A1 A00 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 70 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 60 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 50 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 41 0 0 4 5 6 7 0 1234567 0 1 2 31 0 1 5 6 7 0 12345 4 76 1 0 3 21 1 0 6 7 0 1234567 4 5 2 3 0 11 1 1 7 0 1234567 6 5 4 3 2 1 0Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010DEVICE OPERATIONSCLOCK (CLK)The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V IL and V IH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and I CC specifications.CLOCK ENABLE(CKE)The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least “1CLK + t SS” before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.BANK ADDRESSES (BA0~BA1)This SDRAM is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. The BA0~BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The banks addressed BA0~BA1 are latched at bank active, read, write, mode register set and precharge operations.ADDRESS INPUTS (A0~A11)The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (A0~A11). The 12 row addresses are latched along with RAS and BA0~BA1 during bank active command. The 9 bit column addresses are latched along with CAS, WE and BA0~BA1 during read or with command.NOP and DEVICE DESELECTWhen RAS, CAS and WE are high , The SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored. POWER-UP1.Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at the inputs.2.Maintain stable power, stable clock and NOP input condition for minimum of 200us.3.Issue precharge commands for all banks of the devices.4.Issue 2 or more auto-refresh commands.5.Issue a mode register set command to initialize the mode register.cf.) Sequence of 4 & 5 is regardless of the order.The device is now ready for normal operation.MODE REGISTER SET (MRS)The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE(The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11 and BA0~BA1in the same cycle as CS, RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields into depending on functionality. The burst length field uses A0~A2, burst type uses A3, CAS latency (read latency from column address) use A4~A6, vendor specific options or test mode use A7~A8, A10/AP~A11 and BA0~BA1. The write burst length is programmed using A9. A7~A8, A10/AP~A11 and BA0~BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.BANK ACTIVATEThe bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of t RCD(min) from the time of bank activation. t RCD is the internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t RCD(min) with cycle time of the clock and thenElite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010DEVICE OPERATIONS (Continued)rounding of the result to the next higher integer. The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies to recover before another bank can be sensed reliably. t RRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to t RCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t RAS(min). Every SDRAM bank activate command must satisfy t RAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by t RAS(max) and t RAS(max) can be calculated similar to t RCD specification.BURST READThe burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CSand RAS with WE being high on the positive edge of the clock. The bank must be active for at least t RCD(min)before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length.BURST WRITEThe burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be complete by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and precharge the bank t RDL after the last data input to be written into the active row. See DQM OPERATION also. DQM OPERATIONThe DQM is used mask input and output operations. It works similar to OE during operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. Please refer to DQM timing diagram also. PRECHARGEThe precharge is performed on an active bank by asserting low on clock cycles required between bank activate and clock cycles required between bank activate and CS, RAS, WE and A10/AP with valid BA0~BA1 of the bank to be procharged. The precharge command can be asserted anytime after t RAS(min) is satisfy from the bank active command in the desired bank. t RP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing t RP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t RAS(max). Therefore, each bank has to be precharge with t RAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state.AUTO PRECHARGEThe precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy t RAS(min) and “t RP” for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst write by asserting high on A10/AP, the bank is precharge command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state.FOUR BANKS PRECHARGEFour banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with high on A10/AP after all banks have satisfied t RAS(min)requirement, performs precharge on all banks. At the end of t RP after performing precharge all, all banks are in idle state.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010DEVICE OPERATIONS (Continued)AUTO REFRESHThe storage cells of SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS, RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by t RFC(min). The minimum number of clock cycles required can be calculated by driving t RFC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP’s until the auto refresh operation is completed. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us. SELF REFRESHThe self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption.The self refresh mode is entered from all banks idle state by asserting low on CS, RAS, CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the refresh.The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of t RFC before the SDRAM reaches idle state to begin normal operation. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010Mode register set command(CS,RAS,CAS,WE =Low)The M12L128168A has a mode register that defines how the device operates. Inthis command, A0~A11 and BA0~BA1 are the data input pins. After power on, themode register set command must be executed to initialize the device.The mode register can be set only when all banks are in idle state.During 2CLK following this command, the M12L128168A cannot accept anyother commands.(CS,RAS =Low,CAS,WE= High)The M12L128168A has four banks, each with 4,096 rows.This command activates the bank selected by BA1 and BA0 (BS) and a rowaddress selected by A0 through A11.This command corresponds to a conventional DRAM’s RAS falling.Precharge command(CS,RAS,WE =Low,CAS= High )This command begins precharge operation of the bank selected by BA1 and BA0(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.When A10 is Low, only the bank selected by BA1 and BA0 is precharged.After this command, the M12L128168A can’t accept the activate command to theprecharging bank during t RP (precharge to activate command period).This command corresponds to a conventional DRAM’s RAS rising.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2010Write command(CS ,CAS ,WE = Low, RAS = High)If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst can be input with this command with subsequent data on following clocks.Read command(CS ,CAS = Low, RAS ,WE = High)Read data is available after CAS latency requirements have been met. This command sets the burst start address given by the column address.CBR (auto) refresh command(CS ,RAS ,CAS = Low, WE , CKE = High)This command is a request to begin the CBR refresh operation. The refresh address is generated internally.Before executing CBR refresh, all banks must be precharged.After this cycle, all banks will be in the idle (precharged) state and ready for arow activate command.During t RFCperiod (from refresh command to refresh or activate command), the M12L128168A cannot accept any other command.Self refresh entry command(CS,RAS,CAS, CKE = Low ,WE =High)After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the M12L128168A exits the self refresh mode.During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control.Before executing self refresh, all banks must be precharged.Burst stop command(CS,WE =Low,RAS,CAS =High)This command terminates the current burst operation.Burst stop is valid at every burst length.No operation(CS= Low ,RAS,CAS,WE=High)This command is not a execution command. No operations begin or terminate bythis command.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010BASIC FEATURE AND FUNCTION DESCRIPTIONS1. CLOCK Suspend*Note: 1. CKE to CLK disable/enable = 1CLK.2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.3. DQM masks both data-in and data-out.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 20103. CAS Interrupt (I)*Note: 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.By ”CAS interrupt ”, to stop burst read/write by CAS access ; read and write.2. t CCD:CAS to CAS delay. (=1CLK)3. t CDL: Last data in to new column address delay. (=1CLK)Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 20104. CAS Interrupt (II): Read Interrupted by Write & DQMElite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010*Note: 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.2. To inhibit invalid write, DQM should be issued.3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interruptbut only another bank precharge of four banks operation.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 20106. Precharge*Note: 1. t RDL: Last data in to row precharge delay.2. Number of valid output data after row precharge: 1, 2 for CAS Latency = 2, 3 respectively.3. The row active command of the precharge bank can be issued after t RP from this point.The new read/write command of other activated bank can be issued from this point.At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 20108. Burst Stop & Interrupted by Precharge9. MRS*Note: 1. t BDL: 1 CLK; Last data in to burst stop delay.Read or write burst stop command is valid at every burst length.2. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely.3. Write burst is terminated. t BDL determinates the last data write.4. DQM asserted to prevent corruption of locations D2 and D3.5. Precharge can be issued here or earlier (satisfying t RAS min delay) with DQM.6. PRE: All banks precharge, if necessary.MRS can be issued only at all banks precharge state.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 201010. Clock Suspend Exit & Power Down Exit*Note: 1. Active power down : one or more banks active state.2. Precharge power down: all banks precharge state.3. The auto refresh is the same as CBR refresh of conventional DRAM.No precharge commands are required after auto refresh command.During t RFC from auto refresh command, any other command can not be accepted.4. Before executing auto/self refresh command, all banks must be idle state.5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.6. During self refresh entry, refresh interval and refresh operation are performed internally.After self refresh entry, self refresh mode is kept while CKE is low.During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.For the time interval of t RFC from self refresh exit command, any other command can not be accepted.4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010。

Instructions_Leica_DM2700_M CN

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使用说明
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1.2 版于 2013 年 1 月 21 日发布，由： Leica Microsystems CMS GmbH Ernst Leitz-StraBe 17-37 D-35578 Wetzlar (Germany)
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载物台 .............................................. 21
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符号、视图及其含义 ........................ 7
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一般安全说明 .................................. 10

maxim MAX811 MAX812 datasheet说明书

General DescriptionThe MAX811/MAX812 are low-power microprocessor (μP) supervisory circuits used to monitor power supplies in μP and digital systems. They provide excellent circuit reliability and low cost by eliminating external compo-nents and adjustments when used with 5Vpowered or 3V-powered circuits. The MAX811/MAX812 also provide a debounced manual reset input.These devices perform a single function: They assert a reset signal whenever the V CC supply voltage falls below a preset threshold, keeping it asserted for at least 140ms after V CC has risen above the reset threshold. The only difference between the two devices is that the MAX811 has an active-low RESET output (which is guaranteed to be in the correct state for V CC down to 1V), while the MAX812 has an active-high RESET output. The reset comparator is designed to ignore fast transients on V CC. Reset thresholds are available for operation with a variety of supply voltages.Low supply current makes the MAX811/MAX812 ideal for use in portable equipment. The devices come in a 4-pin SOT143 package.Applications●Computers●Controllers●Intelligent Instruments●Critical μP and μC Power Monitoring●Portable/Battery-Powered Equipment Benefits and Features●Integrated Voltage Monitor Increases SystemRobustness with Added Manual Reset• Precision Monitoring of 3V, 3.3V, and 5VPower-Supply Voltages• 140ms Min Power-On-Reset Pulse Width• RESET Output (MAX811), RESET Output(MAX812)• Guaranteed Over Temperature• Guaranteed RESET Valid to V CC = 1V (MAX811)• Power-Supply Transient Immunity●Saves Board Space• No External Components• 4-Pin SOT143 Package●Low Power Consumption Simplifies Power-SupplyRequirements• 6μA Supply Current*This part offers a choice of five different reset threshold voltages. Select the letter corresponding to the desired nominal reset threshold voltage, and insert it into the blank to complete the part number.Devices are available in both leaded and lead(Pb)-free packaging. Specify lead-free by replacing “-T” with “+T” when ordering.RESET THRESHOLDSUFFIX VOLTAGE (V)L 4.63M 4.38T 3.08S 2.93R2.63PART*TEMP RANGE PIN-PACKAGEMAX811_EUS-T-40°C to +85°C 4 SOT143MAX812_EUS-T-40°C to +85°C 4 SOT1431243V CCMR(RESET) RESETGNDMAX811MAX812SOT143TOP VIEW( ) ARE FOR MAX812NOTE: SEE PACKAGE INFORMATION FOR MARKING INFORMATION. MAX811/MAX8124-Pin μP Voltage Monitorswith Manual Reset InputPin ConfigurationOrdering InformationClick here for production status of specific part numbers.19-0411; Rev 6; 5/18Terminal Voltage (with respect to GND)V CC.....................................................................-0.3V to 6.0V All Other Inputs .....................................-0.3V to (V CC + 0.3V) Input Current, V CC, MR......................................................20mA Output Current, RESET or RESET ....................................20mA Continuous Power Dissipation (T A = +70°C)SOT143 (derate 4mW/°C above +70°C) .....................320mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range ............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C(V CC = 5V for L/M versions, V CC = 3.3V for T/S versions, V CC = 3V for R version, T A = -40°C to +85°C, unless otherwise noted. Typical values are at T A = +25°C.) (Note 1)PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSOperating Voltage Range V CC T A = 0°C to +70°C 1.0 5.5V T A = -40°C to +85°C 1.2Supply Current I CC MAX81_L/M, V CC = 5.5V, I OUT = 0615µA MAX81_R/S/T, V CC = 3.6V, I OUT = 0 2.710Reset Threshold V TH MAX81_LT A = +25°C 4.54 4.63 4.72V T A = -40°C to +85°C 4.50 4.75MAX81_MT A = +25°C 4.30 4.38 4.46T A = -40°C to +85°C 4.25 4.50MAX81_TT A = +25°C 3.03 3.08 3.14T A = -40°C to +85°C 3.00 3.15MAX81_ST A = +25°C 2.88 2.93 2.98T A = -40°C to +85°C 2.85 3.00MAX81_RT A = +25°C 2.58 2.63 2.68T A = -40°C to +85°C 2.55 2.70Reset Threshold Tempco30ppm/°CV CC to Reset Delay (Note 2)V OD = 125mV, MAX81_L/M40µs V OD = 125mV, MAX81_R/S/T20Reset Active Timeout Period t RP V CC = V TH(MAX)140560ms MR Minimum Pulse Width t MR10µs MR Glitch Immunity (Note 3)100ns MR to Reset PropagationDelay (Note 2)t MD0.5µsMR Input Threshold V IHV CC > V TH(MAX), MAX81_L/M2.3V V IL0.8V IHV CC > V TH(MAX), MAX81_R/S/T0.7 x V CCV IL0.25 x V CCMR Pull-Up Resistance102030kΩRESET Output Voltage (MAX812)V OH I SOURCE = 150µA, 1.8V < V CC < V TH(MIN)0.8 x V CCVV OLMAX812R/S/T only, I SINK = 1.2mA,V CC = V TH(MAX)0.3MAX812L/M only, I SINK = 3.2mA,V CC = V TH(MAX)0.4with Manual Reset InputAbsolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Electrical Characteristics(V CC = 5V for L/M versions, V CC = 3.3V for T/S versions, V CC = 3V for R version, T A = -40°C to +85°C, unless otherwise noted.Typical values are at T A = +25°C.) (Note 1)Note 1: Production testing done at T A = +25°C, over temperature limits guaranteed by design using six sigma design limits.Note 2: RESET output for MAX811, RESET output for MAX812.Note 3: “Glitches” of 100ns or less typically will not generate a reset pulse.PARAMETERSYMBOLCONDITIONSMINTYPMAX UNITSRESET Output Voltage (MAX811)V OLMAX811R/S/T only, I SINK = 1.2mA, V CC = V TH(MIN)0.3V MAX811L/M only, I SINK = 3.2mA, V CC = V TH(MIN)0.4I SINK = 50µA, V CC > 1.0V0.3V OHMAX811R/S/T only, I SOURCE = 500µA, V CC > V TH(MAX)0.8 x V CC MAX811L/M only, I SOURCE = 800µA, V CC > V TH(MAX)V CC - 1.5with Manual Reset InputElectrical Characteristics (continued)(T A = +25°C, unless otherwise noted.)SUPPLY CURRENT vs. TEMPERATURE(MAX81_L/M)8TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )426-408510-156035190POWER-UP RESET TIMEOUTvs. TEMPERATURE230TEMPERATURE (°C)P O W E R -U P R E S E T T I M E O U T (m s )210200220-408535-1510600POWER-DOWN RESET DELAY vs. TEMPERATURE(MAX81_R/S/T)80100TEMPERATURE (°C)P O W E R -D O W N R E S E T D E L A Y (µs )402060-408510-156035RESET THRESHOLD DEVIATIONvs. TEMPERATURE0.99951.00001.0005M A X 811/12-T O C 6TEMPERATURE (°C)N O R M A L I Z E D T H R E S H O L D (V )0.99850.99800.9990-408535-1510600-4085SUPPLY CURRENT vs. TEMPERATURE(MAX81_R/S/T)2.02.53.0M A X 811/12-T O C 1TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )101.00.5-15601.535POWER-DOWN RESET DELAY vs. TEMPERATURE(MAX81_L/M)200TEMPERATURE (°C)P O W E R -D O W N R E S E T D E L A Y (µs )10050150-408510-156035with Manual Reset InputTypical Operating CharacteristicsDetailed DescriptionReset OutputA microprocessor’s (μP’s) reset input starts the μP in a known state. These μP supervisory circuits assert reset to prevent code execution errors during power-up, power-down, or brownout conditions.RESET is guaranteed to be a logic low for V CC> 1V. Once V CC exceeds the reset threshold, an internal timer keeps RESET low for the reset timeout period; after this interval, RESET goes high.If a brownout condition occurs (V CC dips below the reset threshold), RESET goes low. Any time V CC goes below the reset threshold, the internal timer resets to zero, and RESET goes low. The internal timer starts after V CC returns above the reset threshold, and RESET remains low for the reset timeout period.The manual reset input (MR) can also initiate a reset. See the Manual Reset Input section.The MAX812 has an active-high RESET output that is the inverse of the MAX811’s RESET output.Manual Reset InputMany μP-based products require manual reset capabil-ity, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic low on MR asserts reset. Reset remains asserted while MR is low, and for the Reset Active Timeout Period (t RP) after MR returns high. This input has an internal 20kΩ pull-up resistor, so it can be left open if it is not used. MR can be driven with TTL or CMOS-logic levels, or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual-reset function; external debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environment, connecting a 0.1μF capacitor from MR to ground provides additional noise immunity.Reset Threshold AccuracyThe MAX811/MAX812 are ideal for systems using a 5V ±5% or 3V ±5% power supply with ICs specified for 5V ±10% or 3V ±10%, respectively. They are designed to meet worst-case specifications over temperature. The reset is guaranteed to assert after the power supply falls out of regulation, but before power drops below the minimum specified operating voltage range for the system ICs. The thresholds are pre-trimmed and exhibit tight dis-tribution, reducing the range over which an undesirable reset may occur.PINNAME FUNCTION MAX811MAX81211GND Ground2—RESET Active-Low Reset Output. RESET remains low while V CC is below the reset threshold or while MR is held low. RESET remains low for the Reset Active Timeout Period (t RP) after the reset conditions are terminated.—2RESET Active-High Reset Output. RESET remains high while V CC is below the reset threshold or while MR is held low. RESET remains high for Reset Active Timeout Period (t RP) after the reset conditions are terminated.33MR Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR is low and for 180ms after MR returns high. This active-low input has an internal 20kΩpull-up resistor. It can be driven from a TTL or CMOS-logic line, or shorted to ground with a switch. Leave open if unused.44V CC+5V, +3.3V, or +3V Supply Voltage with Manual Reset InputPin DescriptionApplications InformationNegative-Going V CC TransientsIn addition to issuing a reset to the μP during power-up, power-down, and brownout conditions, the MAX811/ MAX812 are relatively immune to short duration negative-going V CC transients (glitches).Figure 1 shows typical transient durations vs. reset com-parator overdrive, for which the MAX811/MAX812 do not generate a reset pulse. This graph was generated using a negative-going pulse applied to V CC, starting above the actual reset threshold and ending below it by the magnitude indicated (reset comparator overdrive). The graph indicates the typical maximum pulse width a negative-going V CC transient may have without causing a reset pulse to be issued. As the magnitude of the tran-sient increases (goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a V CC transient that goes 125mV below the reset thresh-old and lasts 40μs or less (MAX81_L/M) or 20μs or less (MAX81_T/S/R) will not cause a reset pulse to be issued.A 0.1μF capacitor mounted as close as possible to V CC provides additional transient immunity.Ensuring a Valid RESET OutputDown to V CC = 0VWhen V CC falls below 1V, the MAX811 RESET output no longer sinks current—it becomes an open circuit. Therefore, high-impedance CMOS-logic inputs connected to the RESET output can drift to undetermined voltages. This presents no problem in most applications, since most μP and other circuitry is inoperative with V CC below 1V. However, in applications where the RESET output must be valid down to 0V, adding a pulldown resistor to the RESET pin will cause any stray leakage currents to flow to ground, holding RESET low (Figure 2). R1’s value is not critical; 100kΩ is large enough not to load RESET and small enough to pull RESET to ground.A 100kΩ pull-up resistor to V CC is also recommended for the MAX812 if RESET is required to remain valid for V CC < 1V.Figure 1. Maximum Transient Duration without Causing a Reset Pulse vs. Comparator Overdrive Figure 2. RESET Valid to V CC = Ground Circuitwith Manual Reset InputInterfacing to μPs with Bidirectional Reset PinsμPs with bidirectional reset pins (such as the Motorola 68HC11 series) can contend with the MAX811/MAX812 reset outputs. If, for example, the MAX811 RESET output is asserted high and the μP wants to pull it low, indeter -minate logic levels may result. To correct such cases, connect a 4.7kΩ resistor between the MAX811 RESET (or MAX812 RESET) output and the μP reset I/O (Figure 3). Buffer the reset output to other system components.Figure 3. Interfacing to μPs with Bidirectional Reset I/Owith Manual Reset InputChip InformationTRANSISTOR COUNT: 341with Manual Reset Input Package InformationFor the latest package outline information and land patterns (footprints), go to /packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.PACKAGE TYPE PACKAGE CODE OUTLINE ND PATTERN NO.4 SOT143U4+121-005290-0183REVISION NUMBERREVISION DATE DESCRIPTIONPAGES CHANGED56/15Updated Benefits and Features and Package Information sections 1, 865/18Updated Absolute Maximum Ratings2Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.with Manual Reset InputRevision HistoryFor pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https:///en/storefront/storefront.html.。