TC74LVX125F_07中文资料

元器件交易网 TC74LVX125F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74LVX125F,TC74LVX125FN,TC74LVX125FT
Quad Bus Buffer
The TC74LVX125F/ FN/ FT is a high-speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. Designed for use in 3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. This device is suitable for low-voltage and battery operated systems.
ICC VIN = VCC or GND
3.6
⎯
⎯
4.0
⎯ 40.0 μA
3
2007-10-17
元器件交易网
TC74LVX125F/FN/FT
AC Characteristics (input: tr = tf = 3 ns)
Characteristics Propagation delay time
VCC VIN VOUT Topr dt/dv
2.0 to 3.6 0 to 5.5 0 to VCC −40 to 85 0 to 100
V V V °C ns/V
Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND.
0.8
⎯
0.8
IOH = −50 μA 2.0
1.9 2.0
⎯
1.9
⎯
VOH
VIN = VIH or VIL
IOH = −50 μA
3.0
2.9 3.0
⎯
2.9
⎯
IOH = −4 mA
3.0
2.58
⎯
⎯ 2.48 ⎯
V
IOL = 50 μA
2.0
⎯
0Hale Waihona Puke 0.1⎯0.1
VOL
VIN = VIH or VIL
Symbol Test Condition
Ta = 25°C
Ta = −40 to
85°C
Unit
VCC (V) CL (pF) Min Typ. Max Min Max
15
⎯
5.8 10.1 1.0 13.5
tpLH ⎯
2.7
50
⎯
8.3 13.6 1.0 17.0
ns
15
⎯
4.4 6.2 1.0
Output disable time
tpLZ tpHZ
RL = 1 kΩ
2.7
50
3.3 ± 0.3 50
⎯ 10.0 15.7 1.0 19.0
ns
⎯
8.3 11.2 1.0 13.0
Output to output skew
tosLH tosHL
2.7
50
⎯
⎯
1.5
⎯
1.5
(Note 1)
ns
Note: xxxFN (JEDEC SOP) is not available in Japan.
TC74LVX125F
TC74LVX125FN
TC74LVX125FT
Weight SOP14-P-300-1.27A SOL14-P-150-1.27 TSSOP14-P-0044-0.65A
: 0.18 g (typ.) : 0.12 g (typ.) : 0.06 g (typ.)
VCC VIN VOUT IIK IOK IOUT ICC PD Tstg
−0.5 to 7.0
V
−0.5 to 7.0
V
−0.5 to VCC + 0.5
V
−20
mA
±20
mA
±25
mA
±50
mA
180
mW
−65 to 150
°C
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 2: Parameter guaranteed by design.
Note 3:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption. Average operating current can be obtained by the equation:
1
2007-10-17
元器件交易网
Pin Assignment (top view)
1G 1 1A 2 1Y 3 2G 4 2A 5 2Y 6 GND 7
14 VCC 13 4G 12 4A 11 4Y 10 3G 9 3A 8 3Y
TC74LVX125F/FN/FT
IEC Logic Symbol
Electrical Characteristics
DC Characteristics
Characteristics
Input voltage
H-level L-level
H-level Output voltage
L-level
3-state output Off-state current Input leakage current Quiescent supply current
3.3 ± 0.3 50
⎯
⎯
1.5
⎯
1.5
Input capacitance
CIN
(Note 2) ⎯
4
10
⎯
10
pF
Output capacitance
COUT
⎯
⎯
6
⎯
⎯
⎯
pF
Power dissipation capacitance CPD
(Note 3) ⎯
14
⎯
⎯
⎯
pF
Note 1: Parameter guaranteed by design. (tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|)
Characteristics
Symbol
Rating
Unit
Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature
8.5
tpHL
3.3 ± 0.3
50
⎯
6.9 9.7 1.0 12.0
Output enable time
tpZL tpZH
RL = 1 kΩ
15 2.7
50
15 3.3 ± 0.3
50
⎯
5.3 9.3 1.0 12.5
⎯
7.8 12.8 1.0 16.0
ns
⎯
4.0 5.6 1.0
7.5
⎯
6.5 9.1 1.0 11.0
VIH = 2.0 V (min) (VCC = 3 V) • Power-down protection is provided on all inputs • Balanced propagation delays: tpLH ∼− tpHL • Low noise: VOLP = 0.5 V (max) • Pin and function compatible with 74HC125