M74HCT373B1R中文资料

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74HC373中文资料_数据手册_参数

All information provided in this document is subject to legal disclaimers.
Rev. 6 — 26 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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Fig 6. Pin configuration SO20, SSOP20 and TSSOP20
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4 of 25
NXP Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
6. Functional description
6.1 Function table
Table 3. Function table[1]
Pin 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20
Description 3-state output enable input (active LOW) 3-state latch output data input ground (0 V) latch enable input (active HIGH) supply voltage
3 of 25
NXP Semiconductors
74HC373; 74HCT373

SL74HCT373资料

ORDERING INFORMATION SL74HCT373N Plastic SL74HCT373D SOIC TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs Output Enable PIN 20=VCC PIN 10 = GND L L L H Latch Enable H H L X D H L X X Output Q H L No Change Z
VIH VIL VOH
Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage
VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 6.0 mA
元器件交易网
SL74HCT373
AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V ± 10%, CL=50pF,Input t r=t f=6.0 ns)
Guaranteed Limit Symbol tPLH, t PHL tPLH, t PHL tPLZ, t PHZ tPZL, t PZH tTLH, t THL CIN COUT Parameter Maximum Propagation Delay, Input D to Q (Figures 1 and 5) Maximum Propagation Delay , Latch Enable to Q (Figures 2 and 5) Maximum Propagation Delay ,Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay , Output Enable to Q (Figures 3 and 6) Maximum Output Transition Time, Any Output (Figures 1 and 5) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Latch) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 25 °C to -55°C 28 32 30 35 12 10 15 ≤85°C 35 40 38 44 15 10 15 ≤125°C 42 48 45 53 18 10 15 Unit ns ns ns ns ns pF pF

M74HC74B1中文资料

IEC LOGIC SYMBOL
4, 10 5, 9 6, 8 7 14
1PR, 2PR 1Q, 2Q 1Q, 2Q GND V CC
LOGIC DIAGRAM
2/11
元器件交易网
M54/M74HC74
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW
VIH
High Level Input Voltage Low Level Input Voltage
V IL
4/11
元器件交易网
M54/M74HC74
AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns)
o
Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 95 19 16 190 38 32 190 38 32 4.2 21 25 110 22 19 110 22 19 110 22 19 0 0 0 35 7 6 10 pF pF ns ns ns ns MHz 110 22 19 225 45 38 225 45 38 ns ns ns Unit

SN74LVC373AQPWRQ1,SN74LVC373AQDWRQ1,CLVC373AQDWRG4Q1,CLVC373AQPWRG4Q1, 规格书,Datasheet 资料

FEATURES1 2 3 4 5 6 7 8 9 1020 19 18 17 16 15 14 13 12 11OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND V CC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LEDW OR PW PACKAGE (TOP VIEW)DESCRIPTION/ORDERINGINFORMATIONSN74LVC373A-Q1OCTAL TRANSPARENT D-TYPE LATCHWITH3-STATE OUTPUTSSCAS710B–SEPTEMBER2003–REVISED FEBRUARY2008•Qualified for Automotive Applications•ESD Protection Exceeds2000V PerMIL-STD-883,Method3015;Exceeds200VUsing Machine Model(C=200pF,R=0)•Operates From2V to3.6V•Inputs Accept Voltages to5.5V•Max t pd of7.5ns at3.3V•Typical V OLP(Output Ground Bounce)<0.8Vat V CC=3.3V,T A=25°C•Typical V OHV(Output V OH Undershoot)>2Vat V CC=3.3V,T A=25°C•Supports Mixed-Mode Signal Operation on AllPorts(5-V Input/Output Voltage With3.3-V V CC)•I off Supports Partial-Power-Down ModeOperationThe SN74LVC373A octal transparent D-type latch is designed for2.7-V to3.6-V V CC operation.While the latch-enable(LE)input is high,the Q outputs follow the data(D)inputs.When LE is taken low,the Q outputs are latched at the logic levels set up at the D inputs.A buffered output-enable(OE)input can be used to place the eight outputs in either a normal logic state(high or low logic levels)or the high-impedance state.In the high-impedance state,the outputs neither load nor drive the bus lines significantly.The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.OE does not affect the internal operations of the latches.Old data can be retained or new data can be entered while the outputs are in the high-impedance state.This device is fully specified for partial-power-down applications using I off.The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.To ensure the high-impedance state during power up or power down,OE should be tied to V CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.Inputs can be driven from either3.3-V or5-V devices.This feature allows the use of this device as a translator in a mixed3.3-V/5-V system environment.ORDERING INFORMATION(1)T A PACKAGE(2)ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC–DW Reel of2000SN74LVC373AQDWRQ1L373AQ1–40°C to125°CTSSOP–PW Reel of2000SN74LVC373AQPWRQ1L373AQ1(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TIweb site at .(2)Package drawings,thermal data,and symbolization are available at /packaging.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2003–2008,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.OETo Seven Other ChannelsLE1D1QAbsolute Maximum Ratings (1)SN74LVC373A-Q1OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTSSCAS710B–SEPTEMBER 2003–REVISED FEBRUARY 2008FUNCTION TABLE (EACH LATCH)INPUTSOUTPUTQOE LE D L H H H L H L L L L X Q 0HXXZLOGIC DIAGRAM (POSITIVE LOGIC)over operating free-air temperature range (unless otherwise noted)MINMAX UNIT V CC Supply voltage range –0.5 6.5V V I Input voltage range (2)–0.5 6.5V V O Voltage range applied to any output in the high-impedance or power-off state (2)–0.5 6.5V V O Voltage range applied to any output in the high or low state (2)(3)–0.5V CC +0.5V I IK Input clamp current V I <0–50mA I OK Output clamp current V O <0–50mA I OContinuous output current±50mA Continuous current through V CC or GND±100mA DW package 58θJA Package thermal impedance (4)°C/W PW package83T stg Storage temperature range–65150°C(1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3)The value of V CC is provided in the recommended operating conditions table.(4)The package thermal impedance is calculated in accordance with JESD 51-7.2Submit Documentation FeedbackCopyright ©2003–2008,Texas Instruments IncorporatedProduct Folder Link(s):SN74LVC373A-Q1Recommended Operating Conditions(1) Electrical CharacteristicsTiming RequirementsSN74LVC373A-Q1 OCTAL TRANSPARENT D-TYPE LATCHWITH3-STATE OUTPUTS SCAS710B–SEPTEMBER2003–REVISED FEBRUARY2008MIN MAX UNIT Operating2 3.6V CC Supply voltage VData retention only 1.5V IH High-level input voltage V CC=2.7V to3.6V2VV IL Low-level input voltage V CC=2.7V to3.6V0.8VV I Input voltage0 5.5VHigh or low state0V CCV O Output voltage V3-state0 5.5V CC=2.7V–12I OH High-level output current mAV CC=3V–24V CC=2.7V12I OL Low-level output current mAV CC=3V24Δt/Δv Input transition rise or fall rate10ns/VT A Operating free-air temperature–40125°C (1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs,literature number SCBA004.over recommended operating free-air temperature range(unless otherwise noted)PARAMETER TEST CONDITIONS V CC MIN TYP(1)MAX UNITI OH=–100µA 2.7V to3.6V V CC–0.22.7V 2.2V OH I OH=–12mA V3V 2.4I OH=–24mA3V 2.2I OL=100µA 2.7V to3.6V0.2V OL I OL=12mA 2.7V0.4VI OL=24mA3V0.55I I V I=0to5.5V 3.6V±5µAI OZ V O=0to5.5V 3.6V±15µAV I=V CC or GND10I CC I O=0 3.6VµA3.6V≤V I≤5.5V(2)10ΔI CC One input at V CC–0.6V,Other inputs at V CC or GND 2.7V to3.6V500µAC i V I=V CC or GND 3.3V412pFC o V O=V CC or GND 3.3V 5.512pF(1)All typical values are at V CC=3.3V,T A=25°C.(2)This applies in the disabled state only.over recommended operating free-air temperature range(unless otherwise noted)(see Figure1)V CC=3.3VV CC=2.7V±0.3V UNITMIN MAX MIN MAXt w Pulse duration,LE high 3.3 3.3nst su Setup time,data before LE↓22nst h Hold time,data after LE↓22nsCopyright©2003–2008,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):SN74LVC373A-Q1Switching CharacteristicsOperating CharacteristicsSN74LVC373A-Q1OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTSSCAS710B–SEPTEMBER 2003–REVISED FEBRUARY 2008over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1)V CC =3.3V V CC =2.7V FROM TO ±0.3V PARAMETERUNIT(INPUT)(OUTPUT)MIN MAXMIN MAX D 8.517.5t pd Q ns LE 9.518.5t en OE Q 8.717.7ns t disOEQ80.57ns T A =25°CV CC =2.5VV CC =3.3VTEST PARAMETERUNIT CONDITIONS TYPTYP Outputs enabled (1)46C pd Power dissipation capacitance per latchf =10MHzpFOutputs disabled(1)3(1)This information was not available at the time of publication.4Submit Documentation FeedbackCopyright ©2003–2008,Texas Instruments IncorporatedProduct Folder Link(s):SN74LVC373A-Q1PARAMETER MEASUREMENT INFORMATIONFrom Output Under TestLOAD CIRCUITOpen Data InputTiming InputV I0 VV I0 V0 VInputVOLTAGE WAVEFORMS SETUP AND HOLD TIMESVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSVOLTAGE WAVEFORMS PULSE DURATIONV OHV OHV OLV OLV I0 V InputOutput Waveform 1S1 at V LOAD (see Note B)Output Waveform 2S1 at GND (see Note B)V OLV OH V LOAD /20 V≈0 VV IVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLINGOutputOutputt PLH /t PHL t PLZ /t PZL t PHZ /t PZHOpen V LOAD GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .H.All parameters and waveforms are not applicable to all devices.Output Control V I2.7 V3.3 V ± 0.3 V500 Ω500 ΩV CC R L 6 V 6 VV LOAD C L 50 pF 50 pF0.3 V 0.3 VV ∆2.7 V 2.7 VV I 1.5 V 1.5 VV M t r /t f ≤2.5 ns ≤2.5 nsINPUTS SN74LVC373A-Q1OCTAL TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTSSCAS710B–SEPTEMBER 2003–REVISED FEBRUARY 2008Figure 1.Load Circuit and Voltage WaveformsCopyright ©2003–2008,Texas Instruments Incorporated Submit Documentation Feedback 5Product Folder Link(s):SN74LVC373A-Q1Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins Package QtyEco Plan(2)Lead/Ball FinishMSL Peak Temp(3)Samples (Requires Login)CLVC373AQDWRG4Q1ACTIVE SOIC DW 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CLVC373AQPWRG4Q1ACTIVE TSSOP PW 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVC373AQDWRQ1ACTIVE SOIC DW 20TBD Call TI Call TI SN74LVC373AQPWRQ1ACTIVETSSOPPW20TBDCall TICall TI(1)The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3)MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF SN74LVC373A-Q1 :•Catalog: SN74LVC373A芯天下--/•Enhanced Product: SN74LVC373A-EP•Military: SN54LVC373ANOTE: Qualified Version Definitions:•Catalog - TI's standard catalog product•Enhanced Product - Supports Defense, Aerospace and Medical Applications•Military - QML certified for Military and Defense ApplicationsAddendum-Page 2芯天下--/IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by applicable law,testing of all parameters of each component is not necessarily performed.TI assumes no liability for applications assistance or the design of Buyers’products.Buyers are responsible for their products and applications using TI components.To minimize the risks associated with Buyers’products and applications,Buyers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any patent right,copyright,mask work right,or other intellectual property right relating to any combination,machine,or process in which TI components or services are rmation published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal,regulatory and safety-related requirements concerning its products,and any use of TI components in its applications,notwithstanding any applications-related information or support that may be provided by TI.Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures,monitor failures and their consequences,lessen the likelihood of failures that might cause harm and take appropriate remedial actions.Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.In some cases,TI components may be promoted specifically to facilitate safety-related applications.With such components,TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements.Nonetheless,such components are subject to these terms.No TI components are authorized for use in FDA Class III(or similar life-critical medical equipment)unless authorized officers of the parties have executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or“enhanced plastic”are designed and intended for use in military/aerospace applications or environments.Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk,and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI has specifically designated certain components which meet ISO/TS16949requirements,mainly for automotive ponents which have not been so designated are neither designed nor intended for automotive use;and TI will not be responsible for any failure of such components to meet such requirements.Products ApplicationsAudio /audio Automotive and Transportation /automotiveAmplifiers Communications and Telecom /communicationsData Converters Computers and Peripherals /computersDLP®Products Consumer Electronics /consumer-appsDSP Energy and Lighting /energyClocks and Timers /clocks Industrial /industrialInterface Medical /medicalLogic Security /securityPower Mgmt Space,Avionics and Defense /space-avionics-defense Microcontrollers Video and Imaging /videoRFID OMAP Mobile Processors /omap TI E2E Community Wireless Connectivity /wirelessconnectivityMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2012,Texas Instruments Incorporated芯天下--/。

74HC373及74HCT373规格书

74HC373; 74HCT373Octal D-type transparent latch; 3-stateRev. 4 — 3 September 2010Product data sheet1. General descriptionThe 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatiblewith Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-typeinputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)input and an output enable (OE) input are common to all latches.The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state trueoutputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition thelatches are transparent, i.e. a latch output will change state each time its correspondingD input changes.When LE is LOW the latches store the information that was present at the D inputs aset-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contentsof the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches.The 74HC373; 74HCT373 is functionally identical to:•74HC563; 74HCT563: but inverted outputs and different pin arrangement•74HC573; 74HCT573: but different pin arrangement2. Features and benefits3-state non-inverting outputs for bus oriented applicationsCommon 3-state output enable inputFunctionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573ESD protection:HBM JESD22-A114F exceeds 2000VMM JESD22-A115-A exceeds 200VSpecified from −40°C to+85°C and from −40°C to+125°C3. Ordering information4. Functional diagramTable 1.Ordering informationType number PackageTemperature rangeName DescriptionVersion 74HC373N −40°C to +125°CDIP20plastic dual in-line package; 20leads (300mil)SOT146-174HCT373N 74HC373D −40°C to +125°CSO20plastic small outline package; 20leads;body width 7.5mmSOT163-174HCT373D 74HC373DB −40°C to +125°CSSOP20plastic shrink small outline package; 20leads; body width 5.3mmSOT339-174HCT373DB 74HC373PW −40°C to +125°CTSSOP20plastic thin shrink small outline package; 20leads; body width 4.4mmSOT360-174HCT373PW 74HC373BQ −40°C to +125°CDHVQFN20plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20terminals; body 2.5×4.5×0.85mmSOT764-174HCT373BQ5. Pinning information5.1Pinning5.2Pin descriptionTable 2.Pin descriptionSymbol Pin DescriptionOE13-state output enable input (active LOW) Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q72, 5, 6, 9, 12, 15, 16, 193-state latch outputD0, D1, D2, D3, D4, D5, D6, D73, 4, 7, 8, 13, 14, 17, 18data inputGND10ground (0V)LE11latch enable input (active HIGH)V CC20supply voltage6. Functional description6.1Function table[1]H =HIGH voltage level;h =HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;L =LOW voltage level;I =LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;X =don’t care;Z = high-impedance OFF-state.7. Limiting values[1]For DIP20 package: P tot derates linearly with 12mW/K above 70°C.[2]For SO20: P tot derates linearly with 8mW/K above 70°C.[3]For SSOP20 and TSSOP20 packages: P tot derates linearly with 5.5mW/K above 60°C.[4]For DHVQFN20 package: P tot derates linearly with 4.5mW/K above 60°C.Table 3.Function table [1]Operating mode Control Input Internal latches Output OE LE Dn Qn Enable and read register (transparent mode)L H L L L H H H Latch and read register L L l L L h H H Latch register and disable outputsHXXXZTable 4.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).Symbol Parameter ConditionsMin Max Unit V CC supply voltage −0.5+7V I IK input clamping current V I < −0.5V or V I >V CC +0.5 V -±20mA I OK output clamping current V O <−0.5V or V O >V CC +0.5V -±20mA I O output current V O = −0.5V to (V CC +0.5V)-±35mA I CC supply current -+70mA I GND ground current -−70mA T stg storage temperature −65+150°C P tottotal power dissipationDIP20 package [1]-750mW SO20 package [2]-500mW SSOP20 package [3]500mW TSSOP20 package [3]500mW DHVQFN20 package[4]-500mW8. Recommended operating conditions9. Static characteristicsTable 5.Recommended operating conditions Voltages are referenced to GND (ground = 0V)Symbol Parameter Conditions74HC37374HCT373UnitMin Typ Max Min Typ Max V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5V V I input voltage 0-V CC 0-V CC V V O output voltage 0-V CC 0-V CC V T amb ambient temperature−40+25+125−40+25+125°C Δt/ΔVinput transition rise and fall rateV CC = 2.0 V --625---ns/V V CC = 4.5 V - 1.67139- 1.67139ns/V V CC = 6.0 V --83---ns/V Table 6.Static characteristics 74HC373At recommended operating conditions; voltages are referenced to GND (ground = 0 V).Symbol ParameterConditions Min Typ Max Unit T amb =25°CV IHHIGH-level input voltageV CC = 2.0 V 1.5 1.2-V V CC = 4.5 V 3.15 2.4-V V CC = 6.0 V4.2 3.2-V V ILLOW-level input voltageV CC = 2.0 V -0.80.5V V CC = 4.5 V - 2.1 1.35V V CC = 6.0 V- 2.8 1.8V V OHHIGH-level output voltageV I = V IH or V IL---I O =−20μA; V CC =2.0V 1.9 2.0-V I O =−20μA; V CC =4.5V 4.4 4.5-V I O =−20μA; V CC =6.0V 5.9 6.0-V I O = −6.0 mA; V CC = 4.5 V 3.98 4.32-V I O = −7.8 mA; V CC = 6.0 V5.48 5.81-V V OLLOW-level output voltageV I = V IH or V ILI O =20μA; V CC =2.0V -00.1V I O =20μA; V CC =4.5V -00.1V I O =20μA; V CC =6.0V -00.1V I O = 6.0 mA; V CC = 4.5 V -0.150.26V I O = 7.8 mA; V CC = 6.0 V-0.160.26V I I input leakage current V I =V CC or GND; V CC = 6.0 V --±0.1μA I OZ OFF-state output current V I =V IH or V IL ; V CC =6.0V; V O =V CC or GND --±0.5μA I CC supply current V CC = 6.0 V; I O = 0 A; V I =V CC or GND--8.0μA C Iinput capacitance-3.5-pFT amb =−40°C to +85°CV IHHIGH-level input voltageV CC = 2.0 V 1.5--V V CC = 4.5 V 3.15--V V CC = 6.0 V4.2--V V ILLOW-level input voltageV CC = 2.0 V --0.5V V CC = 4.5 V -- 1.35V V CC = 6.0 V-- 1.8VV OHHIGH-level output voltageV I = V IH or V ILI O =−20μA; V CC =2.0V 1.9--V I O =−20μA; V CC =4.5V 4.4--V I O =−20μA; V CC =6.0V 5.9--V I O = −6.0 mA; V CC = 4.5 V 3.84--V I O = −7.8 mA; V CC = 6.0 V5.34--VV OLLOW-level output voltageV I = V IH or V ILI O =20μA; V CC =2.0V --0.1V I O =20μA; V CC =4.5V --0.1V I O =20μA; V CC =6.0V --0.1V I O = 6.0 mA; V CC = 4.5 V --0.33V I O = 7.8 mA; V CC = 6.0 V--0.33V I I input leakage current V I =V CC or GND; V CC = 6.0 V --±1.0μA I OZ OFF-state output current V I =V IH or V IL ; V CC =6.0V; V O =V CC or GND --±5.0μA I CCsupply currentV CC = 6.0 V; I O =0 A; V I =V CC or GND -80μAT amb =−40°C to +125°C V IHHIGH-level input voltageV CC = 2.0 V 1.5--V V CC = 4.5 V 3.15--V V CC = 6.0 V4.2--V V ILLOW-level input voltageV CC = 2.0 V --0.5V V CC = 4.5 V -- 1.35V V CC = 6.0 V-- 1.8VV OHHIGH-level output voltageV I = V IH or V ILI O =−20μA; V CC =2.0V 1.9--V I O =−20μA; V CC =4.5V 4.4--V I O =−20μA; V CC =6.0V 5.9--V I O = −6.0 mA; V CC = 4.5 V 3.7--V I O = −7.8 mA; V CC = 6.0 V5.2--VTable 6.Static characteristics 74HC373 …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).Symbol ParameterConditions Min Typ Max UnitV OL LOW-level output voltage V I = V IH or V ILI O=20μA; V CC=2.0V--0.1VI O=20μA; V CC=4.5V--0.1VI O=20μA; V CC=6.0V--0.1VI O = 6.0 mA; V CC = 4.5 V--0.4VI O = 7.8 mA; V CC = 6.0 V--0.4V I I input leakage current V I=V CC or GND; V CC = 6.0 V--±1.0μA I OZ OFF-state output current V I=V IH or V IL; V CC=6.0V;V O=V CC or GND--±10.0μAI CC supply current V CC = 6.0 V; I O = 0 A;V I=V CC or GND --160μATable 6.Static characteristics 74HC373 …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).Symbol Parameter Conditions Min Typ Max Unit Table 7.Static characteristics 74HCT373At recommended operating conditions; voltages are referenced to GND (ground=0V).Symbol Parameter Conditions Min Typ Max Unit T amb=25°CV IH HIGH-level input voltage V CC=4.5V to 5.5V 2.0 1.6-VV IL LOW-level input voltage V CC=4.5V to 5.5V- 1.20.8VV OH HIGH-level output voltage V I=V IH or V ILI O=−20μA; V CC=4.5V 4.4 4.5-VI O=−6.0mA; V CC=4.5V 3.98 4.32-VV OL LOW-level output voltage V I=V IH or V ILI O=20μA; V CC=4.5V-0.00.1VI O=6.0mA;V CC=4.5V-0.160.26VI I input leakage current V I=V CC or GND; V CC=5.5V--±0.1μA I OZ OFF-state output current V I=V IH or V IL; V CC=5.5V;V O=V CC or GND per input pin;other inputs at V CC or GND; I O=0 A--±0.5μAI CC supply current V I=V CC or GND; I O=0A;V CC=5.5V--8.0μAΔI CC additional supply current V I=V CC−2.1V;other inputs at V CC or GND;V CC=4.5V to5.5V; I O=0ADn-30108μALE-150540μAOE-100360μA C I input capacitance- 3.5-pF T amb=−40°C to +85°CV IH HIGH-level input voltage V CC=4.5V to 5.5V 2.0--VV IL LOW-level input voltage V CC=4.5V to 5.5V--0.8VV OHHIGH-level output voltageV I =V IH or V ILI O =−20μA; V CC =4.5V4.4--V I O =−6.0μA; V CC =4.5V3.84--V V OLLOW-level output voltageV I =V IH or V ILI O =20μA; V CC =4.5V --0.1V I O =6.0mA;V CC =4.5V--0.33V I I input leakage current V I =V CC or GND; V CC =5.5V --±1.0μA I OZOFF-state output currentV I =V IH or V IL ; V CC =5.5V; V O =V CC or GND per input pin; other inputs at V CC or GND; I O =0 A --±5.0μAI CC supply currentV I =V CC or GND; I O =0A; V CC =5.5V--80μAΔI CCadditional supply currentV I =V CC −2.1V;other inputs at V CC or GND; V CC =4.5V to 5.5V; I O =0A Dn --135μA LE --675μA OE--450μAT amb =−40°C to +125°C V IH HIGH-level input voltage V CC =4.5V to 5.5V 2.0--V V IL LOW-level input voltage V CC =4.5V to 5.5V --0.8VV OHHIGH-level output voltageV I =V IH or V ILI O =−20μA; V CC =4.5V 4.4--V I O =−6.0mA; V CC =4.5V3.7--VV OLLOW-level output voltageV I =V IH or V ILI O =20μA; V CC =4.5V --0.1V I O =6.0mA;V CC =4.5V--0.4V I I input leakage current V I =V CC or GND; V CC =5.5V --±1.0μA I OZOFF-state output currentV I =V IH or V IL ; V CC =5.5V; V O =V CC or GND per input pin; other inputs at V CC or GND; I O =0 A --±10μAI CC supply currentV I =V CC or GND; I O =0A; V CC =5.5V--160μAΔI CCadditional supply currentV I =V CC −2.1V;other inputs at V CC or GND; V CC =4.5V to 5.5V; I O =0A Dn --147μA LE --735μA OE--490μATable 7.Static characteristics 74HCT373 …continuedAt recommended operating conditions; voltages are referenced to GND (ground =0V).Symbol ParameterConditions MinTypMaxUnit10. Dynamic characteristicsTable 8.Dynamic characteristics 74HC373Voltages are referenced to GND(ground =0V); C L = 50 pF unless otherwise specified; for test circuit see Figure12. Symbol Parameter Conditions Min Typ Max Unit T amb=25°Ct pd propagation delay Dn to Qn; see Figure8[1]V CC = 2.0 V-41150nsV CC = 4.5 V-1530nsV CC=5V; C L=15pF-12-nsV CC = 6.0 V-1226nsLE to Qn; see Figure9V CC = 2.0 V-50175nsV CC = 4.5 V-1835nsV CC=5V; C L=15pF-15-nsV CC = 6.0 V-1430ns t en enable time OE to Qn; see Figure10[2]V CC = 2.0 V-44150nsV CC = 4.5 V-1630nsV CC = 6.0 V-1326ns t dis disable time OE to Qn; see Figure10[3]V CC = 2.0 V-47150nsV CC = 4.5 V-1730nsV CC = 6.0 V-1426ns t t transition time Qn; see Figure8 and Figure9[4]V CC = 2.0 V-1460nsV CC = 4.5 V-512nsV CC = 6.0 V-410ns t W pulse width LE HIGH; see Figure9V CC = 2.0 V8017-nsV CC = 4.5 V166-nsV CC = 6.0 V145-ns t su set-up time Dn to LE; see Figure11V CC = 2.0 V5014-nsV CC = 4.5 V105-nsV CC = 6.0 V94-ns t h hold time Dn to LE; see Figure11V CC = 2.0 V+5−8-nsV CC = 4.5 V+5−3-nsV CC = 6.0 V+5−2-ns C PD power dissipation capacitance per latch; V I=GND to V CC[5]-45-pFTable 8.Dynamic characteristics 74HC373 …continuedVoltages are referenced to GND(ground =0V); C L = 50 pF unless otherwise specified; for test circuit see Figure12. Symbol Parameter Conditions Min Typ Max Unit T amb=−40°C to+85°Ct pd propagation delay Dn to Qn; see Figure8[1]V CC = 2.0 V--190nsV CC = 4.5 V--38nsV CC = 6.0 V--33nsLE to Qn; see Figure9V CC = 2.0 V--220nsV CC = 4.5 V--44nsV CC = 6.0 V--37ns t en enable time OE to Qn; see Figure10[2]V CC = 2.0 V--190nsV CC = 4.5 V--38nsV CC = 6.0 V--33ns t dis disable time OE to Qn; see Figure10[3]V CC = 2.0 V--190nsV CC = 4.5 V--38nsV CC = 6.0 V--33ns t t transition time Qn; see Figure8 and Figure9[4]V CC = 2.0 V--75nsV CC = 4.5 V--15nsV CC = 6.0 V--13ns t W pulse width LE HIGH; see Figure9V CC = 2.0 V100--nsV CC = 4.5 V20--nsV CC = 6.0 V17--ns t su set-up time Dn to LE; see Figure11V CC = 2.0 V65--nsV CC = 4.5 V13--nsV CC = 6.0 V11--ns t h hold time Dn to LE; see Figure11V CC = 2.0 V5--nsV CC = 4.5 V5--nsV CC = 6.0 V5--nsTable 8.Dynamic characteristics 74HC373 …continuedVoltages are referenced to GND(ground =0V); C L = 50 pF unless otherwise specified; for test circuit see Figure12. Symbol Parameter Conditions Min Typ Max Unit T amb=−40°C to+125°Ct pd propagation delay Dn to Qn; see Figure8[1]V CC = 2.0 V--225nsV CC = 4.5 V--45nsV CC = 6.0 V--38nsLE to Qn; see Figure9V CC = 2.0 V--265nsV CC = 4.5 V--53nsV CC = 6.0 V--45ns t en enable time OE to Qn; see Figure10[2]V CC = 2.0 V--225nsV CC = 4.5 V--45nsV CC = 6.0 V--38ns t dis disable time OE to Qn; see Figure10[3]V CC = 2.0 V--225nsV CC = 4.5 V--45nsV CC = 6.0 V--38ns t t transition time Qn; see Figure8 and Figure9[4]V CC = 2.0 V--90nsV CC = 4.5 V--18nsV CC = 6.0 V--15ns t W pulse width LE HIGH; see Figure9V CC = 2.0 V120--nsV CC = 4.5 V24--nsV CC = 6.0 V20--ns t su set-up time Dn to LE; see Figure11V CC = 2.0 V75--nsV CC = 4.5 V15--nsV CC = 6.0 V13--ns[1]t pd is the same as t PLH and t PHL .[2]t en is the same as t PZH and t PZL .[3]t dis is the same as t PLZ and t PHZ .[4]t t is the same as t THL and t TLH .[5]C PD is used to determine the dynamic power dissipation (P D in μW).P D =C PD ×V CC 2×f i ×N +∑(C L ×V CC 2×f o ) where:f i =input frequency in MHz;f o =output frequency in MHz;C L =output load capacitance in pF;V CC =supply voltage in V;N =number of inputs switching;∑(C L ×V CC 2×f o )=sum of outputs.t hhold timeDn to LE; see Figure 11V CC = 2.0 V 5--ns V CC = 4.5 V 5--ns V CC = 6.0 V5--nsTable 8.Dynamic characteristics 74HC373 …continuedVoltages are referenced to GND (ground =0V); C L = 50 pF unless otherwise specified; for test circuit see Figure 12.Symbol Parameter ConditionsMin Typ Max Unit Table 9.Dynamic characteristics 74HCT373Voltages are referenced to GND (ground =0V); C L = 50 pF unless otherwise specified; for test circuit see Figure 12.Symbol Parameter Conditions Min Typ Max UnitT amb =25°C t pdpropagation delayDn to Qn; see Figure 8[1]V CC = 4.5 V-1730ns V CC =5V; C L =15pF -14-ns LE to Qn; see Figure 9V CC = 4.5 V-1632ns V CC =5V; C L =15pF-13-ns t en enable time OE to Qn; see Figure 10[2]V CC = 4.5 V-1932ns t dis disable time OE to Qn; see Figure 10[3]V CC = 4.5 V-1830ns t t transition time Qn; see Figure 8 and Figure 9[4]V CC = 4.5 V -512ns t W pulse width LE HIGH; see Figure 9V CC = 4.5 V164-ns t su set-up time Dn to LE; see Figure 11V CC = 4.5 V126-ns t h hold timeDn to LE; see Figure 11V CC = 4.5 V4−1-ns C PDpower dissipation capacitanceper latch;V I =GND to (V CC −1.5V)[5]-41-pFTable 9.Dynamic characteristics 74HCT373 …continuedVoltages are referenced to GND(ground =0V); C L = 50 pF unless otherwise specified; for test circuit see Figure12. Symbol Parameter Conditions Min Typ Max Unit T amb=−40°C to+85°Ct pd propagation delay Dn to Qn; see Figure8[1]V CC = 4.5 V--38nsLE to Qn; see Figure9V CC = 4.5 V--40ns t en enable time OE to Qn; see Figure10[2]V CC = 4.5 V--40ns t dis disable time OE to Qn; see Figure10[3]V CC = 4.5 V--38ns t t transition time Qn; see Figure8 and Figure9[4]V CC = 4.5 V--15ns t W pulse width LE HIGH; see Figure9V CC = 4.5 V20--ns t su set-up time Dn to LE; see Figure11V CC = 4.5 V15--ns t h hold time Dn to LE; see Figure11V CC = 4.5 V4--ns T amb=−40°C to+125°Ct pd propagation delay Dn to Qn; see Figure8[1]V CC = 4.5 V--45nsLE to Qn; see Figure9V CC = 4.5 V--48ns t en enable time OE to Qn; see Figure10[2]V CC = 4.5 V--48ns t dis disable time OE to Qn; see Figure10[3]V CC = 4.5 V--45ns t t transition time Qn; see Figure8 and Figure9[4]V CC = 4.5 V--18ns t W pulse width LE HIGH; see Figure9V CC = 4.5 V24--ns t su set-up time Dn to LE Dn to LE; see Figure11V CC = 4.5 V18--nsTable 9.Dynamic characteristics 74HCT373 …continuedVoltages are referenced to GND(ground =0V); C L = 50 pF unless otherwise specified; for test circuit see Figure12. Symbol Parameter Conditions Min Typ Max Unit t h hold time Dn to LE Dn to LE; see Figure11V CC = 4.5 V4--ns[1]t pd is the same as t PLH and t PHL.[2]t en is the same as t PZH and t PZL.[3]t dis is the same as t PLZ and t PHZ.[4]t t is the same as t THL and t TLH.[5]C PD is used to determine the dynamic power dissipation (P D in μW).P D=C PD×V CC2×f i×N+∑(C L×V CC2×f o) where:f i=input frequency in MHz;f o=output frequency in MHz;C L=output load capacitance in pF;V CC=supply voltage in V;N=number of inputs switching;∑(C L×V CC2×f o)=sum of outputs.11. WaveformsTable 10.Measurement pointsType Input OutputV M V M74HC3730.5V CC0.5V CC 74HCT373 1.3V 1.3VTable 11.Test dataType Input Load S1 positionV I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC373V CC6ns15pF, 50 pF1kΩopen GND V CC74HCT3733V6ns15pF, 50 pF1kΩopen GND V CC12. Package outlineDIP20: plastic dual in-line package; 20 leads (300 mil)SOT146-1Fig 13.Package outline SOT146-1 (DIP20)SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1Fig 14.Package outline SOT163-1 (SO20)SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1Fig 15.Package outline SOT339-1 (SSOP20)TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1Fig 16.Package outline SOT360-1 (TSSOP20)Fig 17.Package outline SOT764-1 (DHVQFN20)SOT764-1DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;20 terminals; body 2.5 x 4.5 x 0.85 mm13. Abbreviations14. Revision historyTable 12.AbbreviationsAcronym DescriptionCMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine ModelTTLTransistor-Transistor LogicTable 13.Revision historyDocument ID Release date Data sheet status Change notice Supersedes 74HC_HCT373 v.420100903Product data sheet-74HC_HCT373 v.3Modifications:•The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.•Legal texts have been adapted to the new company name where appropriate.•Figure 5 changed: inversion sign added to the output buffers.74HC_HCT373 v.320060120Product data sheet -74HC_HCT373_CNV v.274HC_HCT373_CNV v.219970827Product specification--15. Legal information15.1 Data sheet status[1]Please consult the most recently issued document before initiating or completing a design.[2]The term ‘short data sheet’ is explained in section “Definitions”.[3]The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product statusinformation is available on the Internet at URL .15.2 DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. 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Export might require a prior authorization from national authorities.15.4 TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.16. Contact informationFor more information, please visit: For sales office addresses, please send an email to: salesaddresses@。

M74HCT533M1R中文资料

X: DON’T CARE Z: HIGH IMPEDANCE *: Q/Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL.
LOGIC DIAGRAMS
HCT373
HCT533
3/13
元器件交易网
HCT373 HCT533
ORDER CODES : M54HCTXXXF1R M74HCTXXXM1R M74HCTXXXB1R M74HCTXXXC1R
or low logic level) and while high level the outpts will be in a high impedance state. The application designer has a choise of combination of inverting and non inverting outputs. The three state output configuration and the wide choise of outline make bus organized system simple. These integrated circuits have input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. All inputs are equipped with protection circuits against discharge and transient excess voltage.

M74HC592TTR,M74HC592B1R, 规格书,Datasheet 资料

1/14August 2001sHIGH SPEED: f MAX = 53 MHz (TYP .) at V CC = 6V sLOW POWER DISSIPATION:I CC = 4µA(MAX.) at T A =25°C sHIGH NOISE IMMUNITY:V NIH = V NIL = 28 % V CC (MIN.)sSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 4mA (MIN)sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsWIDE OPERATING VOLTAGE RANGE:V CC (OPR) = 2V to 6VsPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 592DESCRIPTIONThe M74HC592 is an high speed CMOS 8-BIT REGISTER COUNTER fabricated with silicon gate C 2MOS technology.The M74HC592 is a parallel input, 8 bit storage register feeding an 8 bit binary counter. Both the register and the counter have individual positive edge triggered clock. In addition, the counter hasdirect load and clear functions. Expansion is easily accomplished by connecting RCO at the first stage to the count enable of the second stage.All inputs are equipped with protection circuits against static discharge and transient excess voltage.M74HC592PIN CONNECTION AND IEC LOGIC SYMBOLSORDER CODESPACKAGE TUBE T & RDIP M74HC592B1R SOP M74HC592M1RM74HC592RM13TR TSSOPM74HC592TTR8 BIT REGISTER BINARY COUNTERM74HC5922/14INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLEX: Don’t CarePIN No SYMBOL NAME AND FUNCTION 1 to 7, 15A to H Data Inputs9RCO Ripple Carry Output 10CCLR Counter Clear Input 11CCK Counter Clock Input 12CCKEN Counter Clock Enable Input13RCK Register Clock Input 14CLOAD Counter Load Input 8GND Ground (0V)16V CCPositive Supply VoltageM74HC592 LOGIC DIAGRAM3/14M74HC5924/14TIMING CHARTABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°CSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7V V I DC Input Voltage -0.5 to V CC + 0.5V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current ± 20mA I OK DC Output Diode Current ± 20mA I ODC Output Current± 25mA ICC or I GND DC V CC or Ground Current± 50mA P D Power Dissipation500(*)mW T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CM74HC5925/14RECOMMENDED OPERATING CONDITIONSDC SPECIFICATIONSSymbol ParameterValue Unit V CC Supply Voltage 2 to 6V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature -55 to 125°C t r , t fInput Rise and Fall TimeV CC = 2.0V 0 to 1000ns V CC = 4.5V 0 to 500ns V CC = 6.0V0 to 400nsSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IHHigh Level Input Voltage2.0 1.5 1.5 1.5V 4.53.15 3.15 3.156.04.24.24.2V ILLow Level Input Voltage2.00.50.50.5V4.5 1.35 1.35 1.356.0 1.81.81.8V OHHigh Level Output Voltage2.0I O =-20 µA 1.9 2.0 1.9 1.9V4.5I O =-20 µA 4.4 4.5 4.4 4.46.0I O =-20 µA5.96.0 5.9 5.94.5I O =-4.0 mA 4.18 4.31 4.13 4.106.0I O =-5.2 mA 5.685.8 5.635.60V OLLow Level Output Voltage2.0I O =20 µA 0.00.10.10.1V 4.5I O =20 µA 0.00.10.10.16.0I O =20 µA 0.00.10.10.14.5I O =4.0 mA 0.170.260.330.406.0I O =5.2 mA 0.180.260.330.40I I Input Leakage Current6.0V I = V CC or GND ± 0.1± 1± 1µA I CCQuiescent Supply Current6.0V I = V CC or GND44080µAM74HC5926/14AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6ns)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t TLH t THL Output TransitionTime 2.0307595110ns 4.581519226.07131619t PLH t PHL Propagation DelayTime(CCK - RCO) 2.063165205250ns4.5213341506.018283543t PLH t PHL Propagation DelayTime(CLOAD - RCO) 2.0110235295355ns4.5304759716.026405060t PHLPropagation Delay Time(CCLR - RCO)2.0701********ns4.5203240486.017273441t PLH t PHL Propagation DelayTime(RCK - RCO) 2.0120260325390ns4.5345265786.029445566f MAXMaximum Clock Frequency 2.0 5.411 4.4 3.6MHz4.5274522186.032532621t W(H) t W(L)Minimum Pulse Width2.0407595110ns4.581519226.07131619t W(L)Minimum Pulse Width (CCLR, CLOAD) 2.0407595110ns4.581519226.07131619t sMinimum Set-up Time (CCKEN - CCK)2.028*******ns4.571519226.06131619t sMinimum Set-up Time(RCK-CLOAD) (A...H - RCK) 2.040100125145ns4.5102025296.09172125t hMinimum Hold Time2.0000ns4.50006.0000t REMMinimum Removal Time2.028*******ns4.571519226.06131619M74HC5927/14CAPACITIVE CHARACTERISTICS1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CCTEST CIRCUITL R T = Z OUT of pulse generator (typically 50Ω)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance 5101010pF C PDPower Dissipation Capacitance (note 1)30pFM74HC5928/14WAVEFORM 1 : MINIMUM PULSE WIDTH, REMOVAL TIME(f=1MHz; 50% duty cycle)M74HC5929/14WAVEFORM 2 : PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle)WAVEFORM 3 : MINIMUM SETUP AND HOLD TIME(f=1MHz; 50% duty cycle)M74HC59210/14WAVEFORM 4 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)WAVEFORM 5 : MINIMUM PULSE WIDTH, SETUP AND HOLD TIME(f=1MHz; 50% duty cycle)Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2000 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom© 14/14。

74hc373中文资料

54/74373八D锁存器(3S,锁存允许输入有回环特性)简要说明:373为三态输出的八D透明锁存器,共有54/74S373和54/74LS373两种线路结构型式，其主要电器特性的典型值如下(不同厂家具体值有差别):型号t Pd P D54S373/74S373 7ns 525mW54LS373/74LS373 17ns 120mW373的输出端O0~O7可直接与总线相连。

当三态允许控制端OE为低电平时，O0~O7为正常逻辑状态，可用来驱动负载或总线。

当OE为高电平时，O0~O7呈高阻态，即不驱动总线，也不为总线的负载，但锁存器内部的逻辑操作不受影响。

当锁存允许端LE为高电平时，O随数据D而变。

当LE为低电平时，O被锁存在已建立的数据电平。

当LE端施密特触发器的输入滞后作用，使交流和直流噪声抗扰度被改善400mV。

引出端符号：D0～D7 数据输入端OE 三态允许控制端（低电平有效）LE 锁存允许端O0~O7 输出端外部管腿图：逻辑图：真值表：极限值:电源电压 (7V)输入电压54/74S373…………………………….………….5.5V54/74LS373…………………………………….7V输出高阻态时高电平电压 …………………………. 5.5V工作环境温度54XXX ………………………………….-55~125℃ 74XXX ………………………………….0~70℃存储温度 …………………………………………. -65~150℃推荐工作条件：54/74S373 54LS373/74LS373最小额定最大最小额定最大单位54 4.5 5 5.5 4.5 5 5.5电源电压Vcc74 4.75 5 5.25 4.75 5 5.25V 输入高电平电压V iH 2 2 V54 0.8 0.7输入低电平电压V iL74 0.8 0.8V54 -2 -1输出高电平电流I OH74 -6.5 -2.6mA54 20 12 输出低电平电流I OL74 20 24 mAｗｗｗ．ｅｌｅｃｆａｎｓ．ｃｏｍLE(H) 6 15脉冲宽度t w LE(L) 7.3 15 ns保持时间t H D 10↓ 10↓ ns 建立时间t set D 0↓0↓ns静态特性（TA 为工作环境温度范围） S373 LS373参数测试条件【1】最小最大最小最大单位V IK 输入嵌位电压 Vcc=最小，I ik =-18mA－1.5-1.5 VV OH 输出高电平电压Vcc ＝最小，V IL ＝最大，V IH =2V ，I OH ＝最大2.4 2.4 V54 0.5 0.4 V OL 输出低电平电压Vcc=最小，V IL ＝最大，V IH =2V,I OL =最大74 0.5 0.5 V V I =5.5V 1 I I 最大输入电压时输入电流Vcc ＝最大V I =7V 0.1 mA V IL =0.5V -0.25I IL 输入低电平电流 Vcc ＝最大,V IL =0.4V -0.4mA I IH 输入高电平电流 Vcc ＝最大,V IH ＝2.7V50 20 uA I OS 输出短路电流 Vcc ＝最大-40 -100 -30 -130 mA Icc 电源电流 Vcc ＝最大，OE 接4.5V160 40 mA V 0＝2.4V 50 I OZH 输出高阻态时高电平电流 Vcc ＝最大，V IH =2VV 0＝2.7V 20 mA V 0＝0.5V-50 I OZL 输出高阻态时低电平电流Vcc ＝最大，V IH =2VV 0＝0.4V-20 mA[1]: 测试条件中的“最小”和“最大”用推荐工作条件中的相应值。

M74HC133B1R,M74HC133RM13TR,M74HC133RM13TR,M74HC133RM13TR,M74HC133B1R, 规格书,Datasheet 资料

1/9July 2001sHIGH SPEED : t PD = 14 ns (TYP.) at V CC = 6V sLOW POWER DISSIPATION:I CC =1µA(MAX.) at T A =25°C sHIGH NOISE IMMUNITY:V NIH = V NIL = 28 % V CC (MIN.)sSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 4mA (MIN)sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsWIDE OPERATING VOLTAGE RANGE:V CC (OPR) = 2V to 6VsPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 133DESCRIPTIONThe M74HC133 is an high speed CMOS 13-INPUT NAND GATE fabricated with silicon gate C 2MOS technology.The internal circuit is composed of 7 stages including buffer output, which enables high noise immunity and stable output.All inputs are equipped with protection circuits against static discharge and transient excess voltage.M74HC13313 INPUT NAND GATEORDER CODESPACKAGE TUBE T & RDIP M74HC133B1R SOP M74HC133M1RM74HC133RM13TR TSSOPM74HC133TTRM74HC1332/9INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLEX : Don’t CareABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied(*) 500mW at 65 °C ; derate to 300mW by 10mW/°C from 65°C to 85°CPIN No SYMBOL NAME AND FUNCTION 1 to 7,10 to 15A to G, H to M Data Inputs9Y Data Output 8GND Ground (0V)16VccPositive Supply VoltageA B C D E F G H I J K L M Y L X X X X X X X X X X X X H X L X X X X X X X X X X X H X X L X X X X X X X X X X H X X X L X X X X X X X X X H X X X X L X X X X X X X X H X X X X X L X X X X X X X H X X X X X X L X X X X X X H X X X X X X X L X X X X X H X X X X X X X X L X X X X H X X X X X X X X X L X X X H X X X X X X X X X X L X X H X X X X X X X X X X X L X H X X X X X X X X X X X X L H HHHHHHHHHHHHHLSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7V V I DC Input Voltage -0.5 to V CC + 0.5V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current ± 20mA I OK DC Output Diode Current ± 20mA I ODC Output Current± 25mA I CC or I GND DC V CC or Ground Current± 50mA P D Power Dissipation500(*)mW T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CM74HC1333/9RECOMMENDED OPERATING CONDITIONSDC SPECIFICATIONSSymbol ParameterValue Unit V CC Supply Voltage 2 to 6V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature -55 to 125°C t r , t fInput Rise and Fall TimeV CC = 2.0V 0 to 1000ns V CC = 4.5V 0 to 500ns V CC = 6.0V0 to 400nsSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IHHigh Level Input Voltage2.0 1.5 1.5 1.5V 4.53.15 3.15 3.156.04.24.24.2V ILLow Level Input Voltage2.00.50.50.5V4.5 1.35 1.35 1.356.0 1.81.81.8V OHHigh Level Output Voltage2.0I O =-20 µA 1.9 2.0 1.9 1.9V4.5I O =-20 µA 4.4 4.5 4.4 4.46.0I O =-20 µA5.96.0 5.9 5.94.5I O =-4.0 mA 4.18 4.31 4.13 4.106.0I O =-5.2 mA 5.685.8 5.635.60V OLLow Level Output Voltage2.0I O =20 µA 0.00.10.10.1V 4.5I O =20 µA 0.00.10.10.16.0I O =20 µA 0.00.10.10.14.5I O =4.0 mA 0.170.260.330.406.0I O =5.2 mA 0.180.260.330.40I I Input Leakage Current6.0V I = V CC or GND ± 0.1± 1± 1µA I CCQuiescent Supply Current6.0V I = V CC or GND11020µAM74HC1334/9AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6ns)CAPACITIVE CHARACTERISTICS1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CCTEST CIRCUITL R T = Z OUT of pulse generator (typically 50Ω)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t TLH t THL Output TransitionTime 2.0307595110ns 4.581519226.07131619t PLH t PHL Propagation DelayTime2.0421********ns4.5162633396.014222833SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance 5.05101010pF C PDPower Dissipation Capacitance (note 1)5.029pFM74HC1335/9WAVEFORM : PROPAGATION DELAY TIME(f=1MHz; 50% duty cycle)M74HC133 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2001 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom© 9/9。

DM74AS373中文资料

© 2000 Fairchild Semiconductor Corporation DS006309April 1984Revised March 2000DM74AS373 Octal D-Type Transparent Latch with 3-STATE OutputsDM74AS373Octal D-Type Transparent Latch with 3-STATE OutputsGeneral DescriptionThese 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or rela-tively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for inter-face or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.The eight latches of the DM74AS373 are transparent D-type latches, meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up.A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high impedance state. In the high-imped-ance state the outputs neither load nor drive the bus lines significantly.The output control does not affect the internal operation of the latches. That is, the old data can be retained or new data can be entered even while the outputs are OFF.Featuress Switching specifications at 50 pFs Switching specifications guaranteed over full tempera-ture and V CC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin for pin compatible with LS and ALS TTL counterparts s Improved AC performance over LS and ALS TTL coun-terparts s 3-STATE buffer-type outputs drive bus lines directlyOrdering Code:Devices also available in T ape and Reel. Specify by appending the suffix letter “X” to the ordering code.Connection DiagramOrder Number Package NumberPackage DescriptionDM74AS373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74AS373NN20A20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 2D M 74A S 373Logic Diagram Function TableL = LOW State H = HIGH State X = Don’t CareZ = High Impedance State Q 0 = Previous Condition of QOutput Enable Output ControlG D Q L H H H L H L L L L X Q 0HXXZDM74AS373Absolute Maximum Ratings (Note 1)Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditions for actual device operation.Recommended Operating ConditionsNote 2: The (↓) arrow indicates the negative edge of the enable is used for reference.Electrical Characteristicsover recommended operating free air temperature range. All typical values are measured at V CC = 5V, T A = 25°C.Supply Voltage 7V Input Voltage7V Voltage Applied to Disabled Output 5.5VOperating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°CTypical θJA N Package 52.5°C/W M Package70.5°C/WSymbol ParameterMin Nom Max Units V CC Supply Voltage4.555.5V V IH HIGH Level Input Voltage 2V V IL LOW Level Input Voltage 0.8V I OH HIGH Level Output Current −15mA I OL LOW Level Output Current 48mA t W Width of Enable Pulse, HIGH 4.5ns t SU Data Setup Time (Note 2)2↓ns t H Data Hold Time (Note 2)3↓ns T AFree Air Operating Temperature70°CSymbol ParameterConditionsMinTypMax Units V IK Input Clamp Voltage V CC = 4.5V, I I = −18 mA −1.2V V OH HIGH Level Output V CC = 4.5V, I OH = Max2.43.2V VoltageI OH = −2 mA, V CC = 4.5V to 5.5V V CC − 2V OL LOW Level Output Voltage V CC = 4.5V, I OL = Max 0.350.5V I I Input Current at Max Input Voltage V CC = 5.5V, V IH = 7V 0.1mA I IH HIGH Level Input Current V CC = 5.5V, V IH = 2.7V 20µA I IL LOW Level Input Current V CC = 5.5V, V IL = 0.4V −0.5mA I O Output Drive CurrentV CC = 5.5V, V O = 2.25V −30−112mA I OZH OFF-State Output Current with V CC = 5.5V, V O = 2.7V50µAHIGH Level Voltage Applied I OZL OFF-State Output Current with V CC = 5.5V, V O = 0.4V−50µALOW Level Voltage Applied I CCSupply CurrentV CC = 5.5V Outputs HIGH 5590Outputs OpenOutputs LOW 5585mAOutputs Disabled65100 4D M 74A S 373Switching Characteristicsover recommended operating free air temperature range Symbol ParameterConditionsFrom To Min MaxUnits t PLH Propagation Delay Time V CC = 4.5V to 5.5V Data Any Q 3.56ns LOW-to-HIGH Level Output R L = 500Ωt PHL Propagation Delay Time C L = 50 pFData Any Q 3.56ns HIGH-to-LOW Level Output t PLH Propagation Delay Time Enable Any Q 6.511.5ns LOW-to-HIGH Level Output t PHL Propagation Delay Time Enable Any Q 57.5ns HIGH-to-LOW Level Output t PZH Output Enable Time Output Any Q 2 6.5 ns to HIGH Level Output Control t PZL Output Enable Time Output Any Q 4.59.5ns to LOW Level Output Control t PHZ Output Disable Time Output Any Q 3 6.5ns from HIGH Level Output Control t PLZOutput Disable Time Output Any Q37nsfrom LOW Level OutputControl DM74AS373Physical Dimensions inches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 WidePackage Number M20B6D M 74A S 373 O c t a l D -T y p e T r a n s p a r e n t L a t c h w i t h 3-S T A TE O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N20AFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。

CD74HCT373M,CD74HCT373E,CD74HCT373M96,CD74HCT373M96G4,CD74HCT373EE4,规格书,Datasheet 资料

TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CD74HCT373M96SOICDW202000330.024.410.813.0 2.712.024.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CD74HCT373M96SOIC DW202000346.0346.041.0PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package DrawingPins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)CD54HCT373F ACTIVE CDIP J 201TBD A42N /A for Pkg Type CD54HCT373F3A ACTIVE CDIP J 201TBD A42N /A for Pkg Type CD74HCT373E ACTIVE PDIP N 2020Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type CD74HCT373EE4ACTIVE PDIP N 2020Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type CD74HCT373M ACTIVE SOIC DW 2025Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74HCT373M96ACTIVE SOIC DW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74HCT373M96G4ACTIVE SOIC DW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD74HCT373MG4ACTIVESOICDW2025Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current 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74HCT373

1.一般说明：74HC373 ，74HCT373是一个高速Si -gate CMOS设备和引脚兼容与低功率肖特基TTL 。

它是符合JEDEC标准没有规定。

7A。

74HC373 74HCT373是一个八进制D型透明锁存设有独立的D型输入每个锁存和三态输出总线导向的应用。

锁存使能（LE ）输入和输出使能（OE）输入共同所有插销。

74HC373 74HCT373由8个D型透明锁存器三态真输出。

LE为高电平时，数据在DN输入进入闩锁。

在此条件下锁存器是透明的，即一个锁存输出状态会改变其对应的每次D输入的变化。

当LE是低锁存器存储的信息，是目前在D输入一个建立时间前HIGH - to-LOW过渡LE 。

当OEIS低的内容的8个锁存器提供输出。

当OEIS高，输出到高高阻关断状态。

的OEinput操作不影响锁存器的状态。

74HC373 ，74HCT373是功能上等同于：•74HC563 ;的74HCT563 ：但反向输出和不同的引脚排列•74HC573 ;的74HCT573 ：但不同的引脚排列2.特点和优点：三态非反相输出总线导向的应用常见的3态输出使能输入功能相同的74HC563;74HCT563和74HC573;74HCT573ESD保护：HBM JESD22-A114F超过2000 VMM JESD22-A115-A超过200 V40CTO+85C40CTO+125 C3.功能图图1 功能图图2 逻辑符号图3 逻辑图4.管脚信息引脚配置DIP20，SO20，SSOP20和TSSOP20表2中。

引脚说明符号引脚说明OE 1 3态输出使能输入（低电平有效）Q0，Q1，Q2，Q3，Q4，Q5，Q6，5，6,9，12，15，16，三态锁存输出5．功能描述5.1功能表表3中。

功能表[1] H=高电平;H =高电压等级的设置时间之前HIGH-LOW LE过渡;L =低电压水平;I =低电平一建立时间之前HIGH-LOW LE过渡;X =不关心;Z =高阻关断状态。

74系列功能大全(中文)

74系列功能大全（中文）74、74HC、74LS系列芯片资料，从网上下的，集合了一下系列电平典型传输延迟ns 最大驱动电流(-Ioh/Lol)mAAHC CMOS 8.5 -8/8AHCT COMS/TTL 8.5 -8/8HC COMS 25 -8/8HCT COMS/TTL 25 -8/8ACT COMS/TTL 10 -24/24F TTL 6.5 -15/64ALS TTL 10 -15/64LS TTL 18 -15/24注：同型号的74系列、74HC系列、74LS系列芯片，逻辑功能上是一样的。

74LSxx的使用说明如果找不到的话，可参阅74xx或74HCxx的使用说明。

有些资料里包含了几种芯片，如74HC161资料里包含了74HC160、74HC161、74HC162、74HC163四种芯片的资料。

找不到某种芯片的资料时，可试着查看一下临近型号的芯片资料。

7400 QUAD 2-INPUT NAND GATES 与非门7401 QUAD 2-INPUT NAND GATES OC 与非门7402 QUAD 2-INPUT NOR GATES 或非门7403 QUAD 2-INPUT NAND GATES 与非门7404 HEX INVERTING GATES 反向器7406 HEX INVERTING GATES HV 高输出反向器7408 QUAD 2-INPUT AND GATE 与门7409 QUAD 2-INPUT AND GATES OC 与门7410 TRIPLE 3-INPUT NAND GATES 与非门7411 TRIPLE 3-INPUT AND GATES 与门74121 ONE-SHOT WITH CLEAR 单稳态74132 SCHMITT TRIGGER NAND GATES 触发器与非门7414 SCHMITT TRIGGER INVERTERS 触发器反向器74153 4-LINE TO 1 LINE SELECTOR 四选一74155 2-LINE TO 4-LINE DECODER 译码器74180 PARITY GENERATOR/CHECKER 奇偶发生检验74191 4-BIT BINARY COUNTER UP/DOWN 计数器7420 DUAL 4-INPUT NAND GATES 双四输入与非门7426 QUAD 2-INPUT NAND GATES 与非门7427 TRIPLE 3-INPUT NOR GATES 三输入或非门7430 8-INPUT NAND GATES 八输入端与非门7432 QUAD 2-INPUT OR GATES 二输入或门7438 2-INPUT NAND GATE BUFFER 与非门缓冲器7445 BCD-DECIMAL DECODER/DRIVER BCD译码驱动器7474 D-TYPE FLIP-FLOP D型触发器7475 QUAD LATCHES 双锁存器7476 J-K FLIP-FLOP J-K触发器7485 4-BIT MAGNITUDE COMPARATOR 四位比较器7486 2-INPUT EXCLUSIVE OR GATES 双端异或门74HC00 QUAD 2-INPUT NAND GATES 双输入与非门74HC02 QUAD 2-INPUT NOR GATES 双输入或非门74HC03 2-INPUT OPEN-DRAIN NAND GATES 与非门74HC04 HEX INVERTERS 六路反向器74HC05 HEX INVERTERS OPEN DRAIN 六路反向器74HC08 2-INPUT AND GATES 双输入与门74HC107 J-K FLIP-FLOP WITH CLEAR J-K触发器74HC109A J-K FLIP-FLOP W/PRESET J-K触发器74HC11 TRIPLE 3-INPUT AND GATES 三输入与门74HC112 DUAL J-K FLIP-FLOP 双J-K触发器74HC113 DUAL J-K FLIP-FLOP PRESET 双JK触发器74HC123A RETRIGGERABLE MONOSTAB 可重触发单稳74HC125 TRI-STATE QUAD BUFFERS 四个三态门74HC126 TRI-STATE QUAD BUFFERS 六三态门74HC132 2-INPUT TRIGGER NAND 施密特触发与非门74HC133 13-INPUT NAND GATES 十三输入与非门74HC137 3-TO-8 DECODERS W/LATCHES 3-8线译码器74HC138 3-8 LINE DECODER 3线至8线译码器74HC139 2-4 LINE DECODER 2线至4线译码器74HC14 TRIGGERED HEX INVERTER 六触发反向器74HC147 10-4 LINE PRIORITY ENCODER 10-4编码器74HC148 8-3 LINE PRIORITY ENCODER 8-3编码器74HC149 8-8 LINE PRIORITY ENCODER 8-8编码器74HC151 8-CHANNEL DIGITAL MUX 8通道多路器74HC153 DUAL 4-INPUT MUX 双四输入多路器74HC154 4-16 LINE DECODER 4线至16线译码器74HC155 2-4 LINE DECODER 2线至4线译码器74HC157 QUAD 2-INPUT MUX 四个双端多路器74HC161 BINARY COUNTER 二进制计数器74HC163 DECADE COUNTERS 十进制计数器74HC164 SERIAL-PARALLEL SHIFT REG 串入并出74HC165 PARALLEL-SERIAL SHIFT REG 并入串出74HC166 SERIAL-PARALLEL SHIFT REG 串入并出74HC173 TRI-STATE D FLIP-FLOP 三态D触发器74HC174 HEX D FLIP-FLOP W/CLEAR 六D触发器74HC175 HEX D FLIP-FLOP W/CLEAR 六D触发器74HC181 ARITHMETIC LOGIC UNIT 算术逻辑单元74HC182 LOOK AHEAD CARRYGENERATR 进位发生器74HC190 BINARY UP/DN COUNTER 二进制加减计数器74HC191 DECADE UP/DN COUNTER 十进制加减计数器74HC192 DECADE UP/DN COUNTER 十进制加减计数器74HC193 BINARY UP/DN COUNTER 二进制加减计数器74HC194 4BIT BI-DIR SHIFT 4位双向移位寄存器74HC195 4BIT PARALLEL SHIFT 4位并行移位寄存器74HC20 QUAD 4-INPUT NAND GATE 四个四入与非门74HC221A NON-RETRIG MONOSTAB 不可重触发单稳74HC237 3-8 LINE DECODER 地址锁3线至8线译码器74HC242/243 TRI-STAT TRANSCEIVER 三态收发器74HC244 OCTAL 3-STATE BUFFER 八个三态缓冲门74HC245 OCTAL 3-STATE TRANSCEIVER 三态收发器74HC251 8-CH 3-STATE MUX 8路3态多路器74HC253 DUAL 4-CH 3-STATE MUX 4路3态多路器74HC257 QUAD 2-CH 3-STATE MUX 4路3态多路器74HC258 2-CH 3-STATE MUX 2路3态多路器74HC259 3-8 LINE DECODER 8位地址锁存译码器74HC266A 2-INPUT EXCLUSIVE NOR GATE 异或非74HC27 TRIPLE 3-INPUT NOR GATE三个3输入或非门74HC273 OCTAL D FLIP-FLOP CLEAR 8路D触发器74HC280 9BIT ODD/EVEN GENERATOR 奇偶发生器74HC283 4BIT BINARY ADDER CARRY 四位加法器74HC299 3-STATE UNIVERSAL SHIFT 三态移位寄存74HC30 8-INPUT NAND GATE 8输入端与非门74HC32 QUAD 2-INPUT OR GATE 四个双端或门74HC34 NON-INVERTER 非反向器74HC354 8-CH 3-STATE MUX 8路3态多路器74HC356 8-CH 3-STATE MUX 8路3态多路器74HC365 HEX 3-STATE BUFFER 六个三态缓冲门74HC366 3-STATE BUFFER INVERTER 缓冲反向器74HC367 3-STATE BUFFER INVERTER 缓冲反向器74HC368 3-STATE BUFFER INVERTER 缓冲反向器74HC373 3-STATE OCTAL D LATCHES 三态D型锁存器74HC374 3-STATE OCTAL D FLIPFLOP 三态D触发器74HC393 4-BIT BINARY COUNTER 4位二进制计数器74HC4016 QUAD ANALOG SWITCH 四路模拟量开关74HC4020 14-Stage Binary Counter 14输出计数器74HC4017 Decade Counter/Divider with 10 Decoded Outputs 十进制计数器带10个译码输出端74HC4040 12 Stage Binary Counter 12出计数器74HC4046 PHASE LOCK LOOP 相位监测输出器74HC4049 LEVEL DOWN CONVERTER 电平变低器74HC4050 LEVEL DOWN CONVERTER 电平变低器74HC4051 8-CH ANALOG MUX 8通道多路器74HC4052 4-CH ANALOG MUX 4通道多路器74HC4053 2-CH ANALOG MUX 2通道多路器74HC4060 14-STAGE BINARY COUNTER 14阶BIN计数74HC4066 QUAD ANALOG MUX 四通道多路器74HC4075 TRIPLE 3-INPUT OR GATE 3输入或门74HC42 BCD TO DECIMAL BCD转十进制译码器74HC423A RETRIGGERABLE MONOSTAB 可重触发单稳74HC4511 BCD-7 SEG DRIVER/DECODER 7段译码器74HC4514 4-16 LINE DECODER 4至16线译码器74HC4538A RETRIGGERAB MONOSTAB 可重触发单稳74HC4543 LCD BCD-7 SEG LCD用的BCD-7段译码驱动74HC51 AND OR GATE INVERTER 与或非门74HC521 8BIT MAGNITUDE COMPARATOR 判决定路74HC533 3-STATE D LATCH 三态D锁存器74HC534 3-STATE D FLIP-FLOP 三态D型触发器74HC540 3-STATE BUFFER 三态缓冲器74HC541 3-STATE BUFFER INVERTER三态缓冲反向器74HC58 DUAL AND OR GATE 与或门74HC589 3STATE 8BIT SHIFT 8位移位寄存三态输出74HC594 8BIT SHIFT REG 8位移位寄存器74HC595 8BIT SHIFT REG 8位移位寄存器出锁存74HC597 8BIT SHIFT REG 8位移位寄存器入锁存74HC620 3-STATE TRANSCEIVER 反向3态收发器74HC623 3-STATE TRANSCEIVER 八路三态收发器74HC640 3-STATE TRANSCEIVER 反向3态收发器74HC643 3-STATE TRANSCEIVER 八路三态收发器74HC646 NON-INVERT BUS TRANSCEIVER 总线收发器74HC648 INVERT BUS TRANCIVER 反向总线收发器74HC688 8BIT MAGNITUDE COMPARATOR 8位判决电路74HC7266 2-INPUT EXCLUSIVE NOR GATE 异或非门74HC73 DUAL J-K FLIP-FLOP W/CLEAR 双JK触发器74HC74A PRESET/CLEAR D FLIP-FLOP 双D触发器74HC75 4BIT BISTABLE LATCH 4位双稳锁存器74HC76 PRESET/CLEAR JK FLIP-FLOP 双JK触发器74HC85 4BIT MAGNITUDE COMPARATOR 4位判决电路74HC86 2INPUT EXCLUSIVE OR GATE 2输入异或门74HC942 BAUD MODEM 300BPS低速调制解调器74HC943 300 BAUD MODEM 300BPS低速调制解调器74LS00 QUAD 2-INPUT NAND GATES 与非门74LS02 QUAD 2-INPUT NOR GATES 或非门74LS03 QUAD 2-INPUT NAND GATES 与非门74LS04 HEX INVERTING GATES 反向器74LS05 HEX INVERTERS OPEN DRAIN 六路反向器74LS08 QUAD 2-INPUT AND GATE 与门74LS09 QUAD 2-INPUT AND GATES OC 与门74LS10 TRIPLE 3-INPUT NAND GATES 与非门74LS109 QUAD 2-INPUT AND GATES OC 与门74LS11 TRIPLE 3-INPUT AND GATES 与门74LS112 DUAL J-K FLIP-FLOP 双J-K触发器74LS113 DUAL J-K FLIP-FLOP PRESET 双JK触发器74LS114 NEGATIVE J-K FLIP-FLOP 负沿J-K触发器74LS122 Retriggerable Monostab 可重触发单稳74LS123 Retriggerable Monostable 可重触发单稳74LS125 TRI-STATE QUAD BUFFERS 四个三态门74LS13 QUAL 4-in NAND TRIGGER 4输入与非触发器74LS160 BCD DECADE 4BIT BIN COUNTERS 计数器74LS136 QUADRUPLE 2-INPUT XOR GATE 异或门74LS138 3-8 LINE DECODER 3线至8线译码器74LS139 2-4 LINE DECODER 2线至4线译码器74LS14 TRIGGERED HEX INVERTER 六触发反向器74HC147 10-4 LINE PRIORITY ENCODER 10-4编码器74HC148 8-3 LINE PRIORITY ENCODER 8-3编码器74HC149 8-8 LINE PRIORITY ENCODER 8-8编码器74LS151 8-CHANNEL DIGITAL MUX 8通道多路器74LS153 DUAL 4-INPUT MUX 双四输入多路器74LS155 2-4 LINE DECODER 2线至4线译码器74LS156 2-4 LINE DECODER/DEMUX 2-4译码器74LS157 QUAD 2-INPUT MUX 四个双端多路器74LS158 2-1 LINE MUX 2-1线多路器74LS160A BINARY COUNTER 二进制计数器74LS161A BINARY COUNTER 二进制计数器74LS162A BINARY COUNTER 二进制计数器74LS163A DECADE COUNTERS 十进制计数器74LS164 SERIAL-PARALLEL SHIFT REG 串入并出74LS168 BI-DIRECT BCD TO DECADE 双向计数器74LS169 4BIT UP/DN BIN COUNTER 四位加减计数器74LS173 TRI-STATE D FLIP-FLOP 三态D触发器74LS174 HEX D FLIP-FLOP W/CLEAR 六D触发器74LS175 HEX D FLIP-FLOP W/CLEAR 六D触发器74LS190 BINARY UP/DN COUNTER 二进制加减计数器74LS191 DECADE UP/DN COUNTER 十进制加减计数器74LS192 DECADE UP/DN COUNTER 十进制加减计数器74LS193 BINARY UP/DN COUNTER 二进制加减计数器74LS194A 4BIT BI-DIR SHIFT 4位双向移位寄存器74LS195A 4BIT PARALLEL SHIFT4位并行移位寄存器74LS20 QUAD 4-INPUT NAND GATE 四个四入与非门74LS21 4-INPUT AND GATE 四输入端与门74LS240 OCTAL 3-STATE BUFFER 八个三态缓冲门74LS244 OCTAL 3-STATE BUFFER 八个三态缓冲门74LS245 OCTAL 3-STATE TRANSCEIVER 三态收发器74LS253 DUAL 4-CH 3-STATE MUX 4路3态多路器74LS256 4BIT ADDRESS LATCH 四位可锁存锁存器74LS257 QUAD 2-CH 3-STATE MUX 4路3态多路器74LS258 2-CH 3-STATE MUX 2路3态多路器74LS27 TRIPLE 3-INPUT NOR GATES 三输入或非门74LS279 QUAD R-S LATCHES 四个RS非锁存器74LS28 QUAD 2-INPUT NOR BUFFER 四双端或非缓冲74LS283 4BIT BINARY ADDER CARRY 四位加法器74LS30 8-INPUT NAND GATES 八输入端与非门74LS32 QUAD 2-INPUT OR GATES 二输入或门74LS352 4-1 LINE SELECTOR/MUX 4-1线选择多路器74LS365 HEX 3-STATE BUFFER 六个三态缓冲门74LS367 3-STATE BUFFER INVERTER 缓冲反向器74LS368A 3-STATE BUFFER INVERTER 缓冲反向器74LS373 OCT LATCH W/3-STATE OUT三态输出锁存器74LS76 Dual JK Flip-Flop w/set 2个JK触发器74LS379 QUAD PARALLEL REG 四个并行寄存器74LS38 2-INPUT NAND GATE BUFFER 与非门缓冲器74LS390 DUAL DECADE COUNTER 2个10进制计数器74LS393 DUAL BINARY COUNTER 2个2进制计数器74LS42 BCD TO DECIMAL BCD转十进制译码器74LS48 BCD-7 SEG BCD-7段译码器74LS49 BCD-7 SEG BCD-7段译码器74LS51 AND OR GATE INVERTER 与或非门74LS540 OCT Buffer/Line Driver 8路缓冲驱动器74LS541 OCT Buffer/LineDriver 8路缓冲驱动器74LS74 D-TYPE FLIP-FLOP D型触发器74LS682 8BIT MAGNITUDE COMPARATOR 8路比较器74LS684 8BIT MAGNITUDE COMPARATOR 8路比较器74LS75 QUAD LATCHES 双锁存器74LS83A 4BIT BINARY ADDER CARRY 四位加法器74LS85 4BIT MAGNITUDE COMPARAT 4位判决电路74LS86 2INPUT EXCLUSIVE OR GATE 2输入异或门74LS90 DECADE/BINARY COUNTER 十/二进制计数器74LS95B 4BIT RIGHT/LEFT SHIFT 4位左右移位寄存74LS688 8BIT MAGNITUDE COMPARAT 8位判决电路74LS136 2-INPUT XOR GATE 2输入异或门74LS651 BUS TRANSCEIVERS 总线收发器74LS653 BUS TRANSCEIVERS 总线收发器74LS670 3-STATE 4-BY-4 REG 3态4-4寄存器74LS73A DUAL J-K FLIP-FLOP W/CLEAR 双JK触发器。

74LVT373MTCX,74LVT373MTC,74LVT373WMX,74LVT373WM,74LVT373SJ,74LVT373SJX,规格书,Datasheet 资料

74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE OutputsLow Voltage Octal Transparent Latch with 3-STATE OutputsFeatures■ Input and output interface capability to systems at 5V V CC■Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373) ■ Live insertion/extraction permitted■ Power Up/Down high impedance provides glitch-free bus loading■ Outputs source/sink –32 mA/+64 mA■ Functionally compatible with the 74 series 373 ■ESD performance:– Human-body model > 2000V – Machine model > 200V– Charged-device model > 1000VGeneral DescriptionThe LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications.The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfy-ing the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in a high impedance state.The LVTH373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.These octal latches are designed for low-voltage (3.3V)V CC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT373 and LVTH373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.Ordering InformationDevice also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.All packages are lead free per JEDEC: J-STD-020B standard.Order NumberPackage NumberPackage Description74LVT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74LVT373MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74LVTH373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVTH373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74LVTH373MTCMTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePin DescriptionFunctional DescriptionThe LVT373 and LVTH373 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the D n inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the infor-mation that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard out-puts are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.IEEE/IECTruth TableH = HIGH Voltage LevelL = LOW Voltage LevelZ = High ImpedanceX = ImmaterialO0= Previous O0 before HIGH-to-LOW transition of Latch EnablePin Names DescriptionD0–D7Data InputsLE Latch Enable InputOE Output Enable InputO0–O73-STATE Latch OutputsInputs OutputsLE OE D n O nX H X ZH L L LH L H HL L X O074LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs Please note that this diagram is provided only for the understanding of logic operations and should not be used toestimate propagation delays.74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE OutputsNote:1.I O Absolute Maximum Rating must be observed.Recommended Operating ConditionsThe Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.V CC Supply Voltage –0.5V to +4.6V V I DC Input Voltage –0.5V to +7.0V V ODC Output Voltage Output in 3-STATE–0.5V to +7.0V Output in HIGH or LOW State (1)–0.5V to +7.0VI IK DC Input Diode Current, V I < GND –50mA I OK DC Output Diode Current, V O < GND –50mA I ODC Output Current, V O > V CC Output at HIGH State 64mA Output at LOW State128mA I CC DC Supply Current per Supply Pin ±64mA I GND DC Ground Current per Ground Pin ±128mAT STGStorage Temperature–65°C to +150°CSymbolParameter MinMaxUnitsV CC Supply Voltage 2.7 3.6V V I Input Voltage5.5V I OH HIGH-Level Output Current –32mA I OL LOW-Level Output Current 64mA T A Free-Air Operating Temperature–4085°C ∆ t / ∆ VInput Edge Rate, V IN = 0.8V–2.0V , V CC =3.0V10ns/VNotes:2.All typical values are at V CC=3.3V, T A= 25°C.3.Applies to bushold versions only (74LVTH373).V O≥ V CC – 0.1VV IL Input LOW Voltage 2.7–3.60.8V V OH Output HIGH Voltage 2.7–3.6I OH= –100µA V CC–0.2 V2.7I OH= –8mA 2.43.0I OH= –32mA 2.0V OL Output LOW Voltage 2.7I OL= 100µA 0.2VI OL= 24mA0.53.0I OL= 16mA 0.4I OL= 32mA0.5I OL= 64mA 0.55I I(HOLD)(3)Bushold Input MinimumDrive 3.0V I= 0.8V75µAV I= 2.0V –75I I(OD)(3)Bushold Input Over-DriveCurrent to Change State 3.0(4)500µA(5)–500I I Input Current 3.6V I= 5.5V10µAControl Pins 3.6V I= 0V or V CC±1Data Pins 3.6V I= 0V–5V I= V CC 1I OFF Power Off Leakage Current 00V ≤ V I or V O≤ 5.5V±100µAI PU/PD Power up/down 3-STATEOutput Current 0–1.5V V O= 0.5V to 3.0V,V I= GND or V CC±100µAI OZL3-STATE Output LeakageCurrent3.6V O= 0.5V–5 µAI OZH3-STATE Output LeakageCurrent3.6V O= 3.0V5µAI OZH+3-STATE Output LeakageCurrent3.6V CC< V O≤ 5.5V 10µAI CCH Power Supply Current 3.6Outputs HIGH0.19mA I CCL Power Supply Current 3.6Outputs LOW5mA I CCZ Power Supply Current 3.6Outputs Disabled 0.19mA I CCZ+Power Supply Current 3.6V CC≤ V O≤ 5.5V,Outputs Disabled0.19mA∆I CC Increase in Power SupplyCurrent(6)3.6One Input at V CC – 0.6V,Other Inputs at V CC orGND0.2mA74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE OutputsCapacitance(10)Symbol Parameter Conditions Typical UnitsC IN Input Capacitance V CC= OPEN, V I= 0V or V CC3pFC OUT Output Capacitance V CC= 3.0V, V O= 0V or V CC5pFNote:10.Capacitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012.Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:/packaging/Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify orFigure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any mannersubsidiaries,and is not intended to be an exhaustive list of all such trademarks.ACEx®Build it Now™CorePLUS™CROSSVOLT™CTL™Current Transfer Logic™EcoSPARK®EZSWITCH™*™®Fairchild®Fairchild Semiconductor®FACT Quiet Series™FACT®FAST®FastvCore™FlashWriter®*FPS™FRFET®Global Power Resource SMGreen FPS™Green FPS™e-Series™GTO™i-Lo™IntelliMAX™ISOPLANAR™MegaBuck™MICROCOUPLER™MicroFET™MicroPak™MillerDrive™Motion-SPM™OPTOLOGIC®OPTOPLANAR®®PDP-SPM™Power220®POWEREDGE®Power-SPM™PowerTrench®Programmable Active Droop™QFET®QS™QT Optoelectronics™Quiet Series™RapidConfigure™SMART START™SPM®STEALTH™SuperFET™SuperSOT™-3SuperSOT™-6SuperSOT™-8SupreMOS™SyncFET™®The Power Franchise®TinyBoost™TinyBuck™TinyLogic®TINYOPTO™TinyPower™TinyPWM™TinyWire™µSerDes™UHC®Ultra FRFET™UniFET™VCX™*EZSWITCH™and FlashWriter®are trademarks of System General Corporation,used under license by Fairchild Semiconductor.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY,FUNCTION,OR DESIGN.FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS,NOR THE RIGHTS OF OTHERS.THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS,SPECIFICALLY THE WARRANTY THEREIN,WHICH COVERS THESE PRODUCTS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systemswhich,(a)are intended for surgical implant into the body or(b)support or sustain life,and(c)whose failure to performwhen properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury of the user.2.A critical component in any component of a life support,device,or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONSDefinition of TermsDatasheet Identification Product Status DefinitionAdvance Information Formative or In Design This datasheet contains the design specifications for product development.Specifications may change in any manner without notice.Preliminary First Production This datasheet contains preliminary data;supplementary data will bepublished at a later date.Fairchild Semiconductor reserves the right tomake changes at any time without notice to improve design. 74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs。

MM74HCT373SJ中文资料

established.

2
MM74HCT373 • MM74HCT374
元器件交易网
Logic Diagrams
MM74HCT373
MM74HCT374
3

元器件交易网
General Description
The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic & pin-out compatible. The 3-STATE outputs are capable of driving 15 LS-TTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground.
Symbol
Parameter
Conditions
VIH
Minimum HIGH Level
Input Voltage
VIL
Maximum LOW Level
Input Voltage
VOH
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage

74LCX373中文资料

1/10September 2001s 5V TOLERANT INPUTS AND OUTPUTS sHIGH SPEED :t PD = 8.0 ns (MAX.) at V CC = 3VsPOWER DOWN PROTECTION ON INPUTS AND OUTPUTSsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 24mA (MIN) at V CC = 3Vs PCI BUS LEVELS GUARANTEED AT 24 mA sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsOPERATING VOLTAGE RANGE:V CC (OPR) = 2.0V to 3.6V (1.5V Data Retention)sPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373sLATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)sESD PERFORMANCE:HBM > 2000V (MIL STD 883 method 3015); MM > 200VDESCRIPTIONThe 74LCX373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON-INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs.These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE).While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE)input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while (OE) is in high level, the outputs will be in a high impedance state.It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.74LCX373OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)WITH 5V TOLERANT INPUTS AND OUTPUTSORDER CODESPACKAGE TUBE T & R SOP 74LCX373M74LCX373MTR TSSOP74LCX373TTR74LCX3732/10INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLEX : Don’t CareZ : High Impedance* : Q Outputs are latched at the time when the LE input is taken LOW.LOGIC DIAGRAMPIN No SYMBOL NAME AND FUNCTION 1OE 3 State Output Enable Input (Active LOW)2, 5, 6, 9, 12, 15, 16,19D0 to D7 Data Inputs 3, 4, 7, 8, 13, 14, 17, 18Q0 to Q7 3-State Outputs 11LE Latch Enable Input 10GND Ground (0V)20V CCPositive Supply VoltageINPUTOUTPUTOE LE D Q H X X ZL L X NO CHANGE*L H L L LHHH74LCX3733/10ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied1) I O absolute maximum rating must be observed 2) V O < GNDRECOMMENDED OPERATING CONDITIONS1) Truth Table guaranteed: 1.5V to 3.6V 2) V IN from 0.8V to 2V at V CC = 3.0VSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7.0V V I DC Input Voltage-0.5 to +7.0V V O DC Output Voltage (OFF State)-0.5 to +7.0V V O DC Output Voltage (High or Low State) (note 1)-0.5 to V CC + 0.5V I IK DC Input Diode Current- 50mA I OK DC Output Diode Current (note 2)- 50mA I O DC Output Current± 50mA I CC DC Supply Current per Supply Pin ± 100mA I GND DC Ground Current per Supply Pin ± 100mA T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CSymbol ParameterValue Unit V CC Supply Voltage (note 1) 2.0 to 3.6V V I Input Voltage0 to 5.5V V O Output Voltage (OFF State)0 to 5.5V V O Output Voltage (High or Low State)0 to V CC V I OH , I OL High or Low Level Output Current (V CC = 3.0 to 3.6V)± 24mA I OH , I OL High or Low Level Output Current (V CC = 2.7V)± 12mA T op Operating Temperature-55 to 125°C dt/dvInput Rise and Fall Time (note 2)0 to 10ns/V74LCX3734/10DC SPECIFICATIONSDYNAMIC SWITCHING CHARACTERISTICS1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.SymbolParameterTest ConditionValueUnitV CC (V)-40 to 85 °C -55 to 125 °C Min.Max.Min.Max.V IH High Level Input Voltage2.7 to3.62.02.0V V IL Low Level Input Voltage0.80.8VV OHHigh Level Output Voltage2.7 to3.6I O =-100 µA V CC -0.2V CC -0.2V2.7I O =-12 mA 2.2 2.23.0I O =-18 mA 2.4 2.4I O =-24 mA 2.22.2V OLLow Level Output Voltage2.7 to3.6I O =100 µA 0.20.2V 2.7I O =12 mA 0.40.43.0I O =16 mA 0.40.4I O =24 mA 0.550.55I I Input Leakage Current2.7 to3.6V I = 0 to 5.5V ± 5± 5µA I off Power Off Leakage Current0V I or V O = 5.5V 1010µA I OZ High Impedance Output Leakage Current2.7 to3.6V I = V IH or V IL V O = 0 to V CC ± 5± 5µA I CC Quiescent Supply Current2.7 to3.6V I = V CC or GND 1010µA V I or V O = 3.6 to 5.5V ± 10± 10∆I CCI CC incr. per Input2.7 to3.6V IH = V CC - 0.6V500500µA SymbolParameterTest ConditionValue UnitV CC (V)T A = 25 °C Min.Typ.Max.V OLP Dynamic Low Level Quiet Output (note 1)3.3C L = 50pFV IL = 0V, V IH = 3.3V0.8V V OLV-0.874LCX3735/10AC ELECTRICAL CHARACTERISTICS1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-ing in the same direction, either HIGH or LOW (t OSLH = | t PLHm - t PLHn |, t OSHL = | t PHLm - t PHLn |)2) Parameter guaranteed by designCAPACITIVE CHARACTERISTICS1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /8 (per latch)SymbolParameterTest ConditionValueUnitV CC (V)C L (pF)R L (Ω)t s = t r (ns)-40 to 85 °C -55 to 125 °C Min.Max.Min.Max.t PLH t PHL Propagation Delay Time (Dn to Qn) 2.750500 2.5 1.59.0 1.59.0ns 3.0 to 3.6 1.58.0 1.58.0t PLH t PHL Propagation Delay Time (LE to Qn) 2.750500 2.5 1.59.5 1.59.5ns 3.0 to 3.6 1.58.5 1.58.5t PZL t PZH Output Enable Time to HIGH and LOW level2.7505002.51.59.5 1.59.5ns 3.0 to 3.6 1.58.5 1.58.5t PLZ t PHZOutput Disable Time from HIGH to LOW level2.7505002.51.58.5 1.58.5ns 3.0 to 3.6 1.57.51.57.5t S Set-Up Time, HIGH or LOW level (Dn to LE)2.7505002.52.5 2.5ns3.0 to 3.6 2.5 2.5t hHold Time, HIGH or LOW level (Dn to LE)2.750500 2.5 1.5 1.5ns3.0 to 3.6 1.5 1.5t W LE Pulse Width, HIGH2.750500 2.53.3 3.3ns 3.0 to 3.6 3.33.3t OSLH t OSHLOutput To Output Skew Time (note1, 2)3.0 to 3.6505002.51.0 1.0ns SymbolParameterTest ConditionValue UnitV CC (V)T A = 25 °C Min.Typ.Max.C IN Input Capacitance 3.3V IN = 0 to V CC 6pF C OUT Output Capacitance3.3V IN = 0 to V CC 12pF C PDPower Dissipation Capacitance (note 1)3.3f IN = 10MHz V IN = 0 or V CC50pF74LCX3736/10TEST CIRCUITC L = 50 pF or equivalent (includes jig and probe capacitance)R L = R1 = 500Ω or equivalentR T = Z OUT of pulse generator (typically 50Ω)WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)TESTSWITCH t PLH , t PHL Open t PZL , t PLZ 6V t PZH , t PHZGND74LCX3737/10WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)WAVEFORM 3 : PROPAGATION DELAY TIME(f=1MHz; 50% duty cycle)74LCX373Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2000 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom© 10/10。

SN74AC373DWR,SN74AC373DWR,SN74AC373DWR,SN74AC373NSR,SN74AC373NSR,, 规格书,Datasheet 资料

1POST OFFICE BOX 655303 •DALLAS, TEXAS 75265working registers.The eight latches are D-type transparent latches.When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.ORDERING INFORMATIONT APACKAGE †ORDERABLEPART NUMBER TOP-SIDE MARKING PDIP − N Tube SN74AC373N SN74AC373N SOIC DW Tube SN74AC373DW SOIC − DWTape and reel SN74AC373DWR AC373−40°°SOP − NS Tape and reel SN74AC373NSR AC37340C to 85CSSOP − DB Tape and reel SN74AC373DBR AC373TSSOP PW Tube SN74AC373PW TSSOP − PW Tape and reel SN74AC373PWR AC373CDIP − JTube SNJ54AC373J SNJ54AC373J −55°°CFP − W Tube SNJ54AC373W SNJ54AC373W 55C to 125CLCCC − FKTubeSNJ54AC373FKSNJ54AC373FK†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at /sc/package.Copyright © 2003, Texas Instruments IncorporatedPRODUCTION DATA information is curre nt as of publication date .Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.32120199101112134567818171615148D 7D 7Q 6Q 6D2D 2Q 3Q 3D 4D1D 1Q O E 5Q 5D8Q4Q G N D L E V C CSN54AC373...FK PACKAGE(TOP VIEW)On products compliant to MIL-PRF-38535, all parameters are tested unl ss oth rwis not d. On all oth r products, production processing does not necessarily include testing of all parameters.SN54AC373, SN74AC373OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTSSCAS540D − OCTOBER 1995 − REVISED OCTOBER 20032POST OFFICE BOX 655303 •DALLAS, TEXAS 75265description/ordering information (continued)To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.FUNCTION TABLE(each latch)INPUTS OUTPUTOE LE D QL H H H L H L L L L X Q0HXXZlogic diagram (positive logic)OE LE1D1QTo Seven Other Channelsabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, V CC −0.5 V to 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, V I (see Note 1) −0.5 V to V CC + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range, V O (see Note 1) −0.5 V to V CC + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, I IK (V I < 0 or V I > V CC) ±20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, I OK (V O < 0 or V O > V CC) ±20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous output current, I O (V O = 0 to V CC ) ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous current through V CC or GND ±200 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2):DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DW package 58°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 69°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 60°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, T stg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES: 1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51-7.SN54AC373, SN74AC373OCTAL D-TYPE TRANSPARENT LATCHESWITH 3-STATE OUTPUTSSCAS540D − OCTOBER 1995 − REVISED OCTOBER 20033POST OFFICE BOX 655303 •DALLAS, TEXAS 75265recommended operating conditions (see Note 3)SN54AC373SN74AC373MINMAXMIN MAXUNIT V CC Supply voltage2626VV CC = 3 V2.1 2.1High-level input voltage V CC = 4.5 V3.15 3.15V IHHigh level input voltageV CC = 5.5 V 3.853.85VV CC = 3 V0.90.9Low-level input voltage V CC = 4.5V 1.35 1.35V IL Low level input voltage V CC = 5.5 V1.65 1.65V V I Input voltage 0V CC 0V CC V V O Output voltage0V CC 0V CC V V CC = 3 V−12−12High-level output current V CC = 4.5 V −24−24I OHHigh level output currentV CC = 5.5 V −24−24mA V CC = 3 V1212Low-level output current V CC = 4.5 V 2424I OL Low level output current V CC = 5.5 V 2424mA Δt/Δv Input transition rise or fall rate 88ns/V T AOperating free-air temperature−55125−4085°C NOTE 3:All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs , literature number SCBA004.electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)TEST CONDITIONS T A = 25°C SN54AC373SN74AC373PARAMETERTEST CONDITIONSV CC MIN TYPMAXMIN MAXMIN MAXUNIT3 V2.9 2.9 2.9 = −50 μ 4.5 V 4.4 4.4 4.4I OH 50 A5.5 V 5.4 5.4 5.4V OHI OH = −12 mA 3 V 2.56 2.4 2.46V24mA 4.5 V 3.86 3.7 3.76I OH = −24 mA5.5 V 4.864.74.763 V0.10.10.1 = 50 μA4.5 V 0.10.10.1I OL 505.5 V 0.10.10.1V OLI OL = 12 mA 3 V 0.360.50.44V 24mA4.5 V 0.360.50.44I OL = 24 mA5.5 V 0.360.50.44I I V I = V CC or GND 5.5 V ±0.1±1±1μA I OZ V O = V CC or GND 5.5 V ±0.25±5±2.5μA I CC V I = V CC or GND,I O = 05.5 V 48040μA C iV I = V CC or GND5 V4.5pFSN54AC373, SN74AC373OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTSSCAS540D − OCTOBER 1995 − REVISED OCTOBER 20034POST OFFICE BOX 655303 •DALLAS, TEXAS 75265timing requirements over recommended operating free-air temperature range, V CC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)T A = 25°C SN54AC373SN74AC373MINMAXMIN MAXMIN MAXUNIT t w Pulse duration, LE high 5.5 6.56ns t su Setup time, data before LE ↓ 5.5 6.56ns t hHold time, data after LE ↓111nstiming requirements over recommended operating free-air temperature range, V CC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)T A = 25°C SN54AC373SN74AC373MINMAXMIN MAXMIN MAXUNIT t w Pulse duration, LE high 45 4.5ns t su Setup time, data before LE ↓45 4.5ns t hHold time, data after LE ↓111nsswitching characteristics over recommended operating free-air temperature range,V CC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)TO TO T A = 25°C SN54AC373SN74AC373PARAMETER(INPUT)(OUTPUT)MIN TYP MAX MIN MAX MIN MAX UNIT t PLH 1.51013.5116.5 1.515t PHL D Q 1.59.513.0116 1.514.5ns t PLH 1.51013.5116.5 1.515t PHL LE Q 1.59.512.5115 1.514ns t PZH 1.5911.5114113t PZL OE Q 1.58.511.5113.5113ns t PHZ 1.51012.5116114.5t PLZOEQ1.5811.5113112.5nsswitching characteristics over recommended operating free-air temperature range,V CC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)T A = 25°C SN54AC373SN74AC373PARAMETERTO (INPUT)TO (OUTPUT)MIN TYP MAX MIN MAX MIN MAX UNIT t PLH 1.579.5111.5 1.510.5t PHL D Q 1.579.5111.5 1.510.5ns t PLH 1.57.59.5112 1.510.5t PHL LE Q 1.579.5111 1.510.5ns t PZH 1.578.5110.519.5t PZL OE Q 1.5 6.58.511019.5ns t PHZ 1.5811113.5112.5t PLZOEQ1.56.58.5110.5110nsoperating characteristics, V CC = 5 V, T A = 25°CPARAMETERTEST CONDITIONS TYP UNIT C pdPower dissipation capacitanceC L = 50 pF,f = 1 MHz40pFSN54AC373, SN74AC373OCTAL D-TYPE TRANSPARENT LATCHESWITH 3-STATE OUTPUTSSCAS540D − OCTOBER 1995 − REVISED OCTOBER 20035POST OFFICE BOX 655303 •DALLAS, TEXAS 75265PARAMETER MEASUREMENT INFORMATIONV CCV CC0 V0 VVOLTAGE WAVEFORMSData InputInputOut-of-PhaseOutputIn-Phase OutputTiming InputVOLTAGE WAVEFORMSFrom Output Under TestC L LOAD CIRCUIT2 × V CCOutput Control (low-level enabling)Output Waveform 1S1 at 2 × V CC (see Note B)Output Waveform 2S1 at Open (see Note B)V OLV OH ≈V CC0 V≈0 VOpenVOLTAGE WAVEFORMSt PLH /t PHL t PLZ /t PZL t PHZ /t PZHOpen 2 × V CC OpenTEST S13 V0 VVOLTAGE WAVEFORMSInput V CCNOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics:PRR ≤ 1 MHz, Z O = 50 Ω, t r ≤ 2.5 ns, t f ≤ 2.5 ns.D.The outputs are measured one at a time with one input transition per measurement.Figure 1. Load Circuit and Voltage WaveformsAddendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins Package QtyEco Plan(2)Lead/Ball Finish MSL Peak Temp (3)Samples (Requires Login)5962-87555012A ACTIVE LCCC FK 201TBD Call TI Call TI 5962-8755501RA ACTIVE CDIP J 201TBD Call TI Call TI 5962-8755501SA ACTIVE CFP W 201TBD Call TI Call TI5962-8755501VRA ACTIVE CDIP J 2020TBD A42N / A for Pkg Type 5962-8755501VSA ACTIVE CFP W 2025TBD Call TI N / A for Pkg Type SN74AC373DBLE OBSOLETE SSOP DB 20TBDCall TICall TISN74AC373DBR ACTIVE SSOP DB 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373DBRE4ACTIVE SSOP DB 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373DBRG4ACTIVE SSOP DB 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373DW ACTIVE SOIC DW 2025Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373DWE4ACTIVE SOIC DW 2025Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373DWG4ACTIVE SOIC DW 2025Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373DWR ACTIVE SOIC DW 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373DWRE4ACTIVE SOIC DW 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373DWRG4ACTIVE SOIC DW 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373N ACTIVE PDIP N 2020Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type SN74AC373NE4ACTIVE PDIP N 2020Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type SN74AC373NSR ACTIVE SO NS 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373NSRE4ACTIVE SO NS 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373NSRG4ACTIVESONS202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM芯天下--/Addendum-Page 2Orderable Device Status(1)Package Type PackageDrawingPins Package QtyEco Plan(2)Lead/Ball FinishMSL Peak Temp(3)Samples (Requires Login)SN74AC373PW ACTIVE TSSOP PW 2070Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373PWE4ACTIVE TSSOP PW 2070Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373PWG4ACTIVE TSSOP PW 2070Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373PWLE OBSOLETE TSSOP PW 20TBD Call TICall TISN74AC373PWR ACTIVE TSSOP PW 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373PWRE4ACTIVE TSSOP PW 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74AC373PWRG4ACTIVE TSSOP PW 202000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SNJ54AC373FK ACTIVE LCCC FK 201TBD POST-PLATE N / A for Pkg TypeSNJ54AC373J ACTIVE CDIP J 201TBD A42N / A for Pkg Type SNJ54AC373WACTIVECFPW201TBDCall TIN / A for Pkg Type(1)The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3)MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.芯天下--/Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF SN54AC373, SN54AC373-SP, SN74AC373 :•Catalog: SN74AC373, SN54AC373•Enhanced Product: SN74AC373-EP, SN74AC373-EP•Military: SN54AC373•Space: SN54AC373-SPNOTE: Qualified Version Definitions:•Catalog - TI's standard catalog product•Enhanced Product - Supports Defense, Aerospace and Medical Applications•Military - QML certified for Military and Defense Applications•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based applicationAddendum-Page 3芯天下--/TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74AC373DBR SSOP DB 202000330.016.48.27.5 2.512.016.0Q1SN74AC373DWR SOIC DW 202000330.024.410.813.0 2.712.024.0Q1SN74AC373NSR SO NS 202000330.024.48.213.0 2.512.024.0Q1SN74AC373PWRTSSOPPW202000330.016.46.957.11.68.016.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) SN74AC373DBR SSOP DB202000367.0367.038.0 SN74AC373DWR SOIC DW202000367.0367.045.0 SN74AC373NSR SO NS202000367.0367.045.0SN74AC373PWR TSSOP PW202000367.0367.038.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by applicable law,testing of all parameters of each component is not necessarily performed.TI assumes no liability for applications assistance or the design of Buyers’products.Buyers are responsible for their products and applications using TI components.To minimize the risks associated with Buyers’products and applications,Buyers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any patent right,copyright,mask work right,or other intellectual property right relating to any combination,machine,or process in which TI components or services are rmation published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal,regulatory and safety-related requirements concerning its products,and any use of TI components in its applications,notwithstanding any applications-related information or support that may be provided by TI.Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures,monitor failures and their consequences,lessen the likelihood of failures that might cause harm and take appropriate remedial actions.Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.In some cases,TI components may be promoted specifically to facilitate safety-related applications.With such components,TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements.Nonetheless,such components are subject to these terms.No TI components are authorized for use in FDA Class III(or similar life-critical medical equipment)unless authorized officers of the parties have executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or“enhanced plastic”are designed and intended for use in military/aerospace applications or environments.Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk,and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI has specifically designated certain components which meet ISO/TS16949requirements,mainly for automotive ponents which have not been so designated are neither designed nor intended for automotive use;and TI will not be responsible for any failure of such components to meet such requirements.Products ApplicationsAudio /audio Automotive and Transportation /automotiveAmplifiers Communications and Telecom /communicationsData Converters Computers and Peripherals /computersDLP®Products Consumer Electronics /consumer-appsDSP Energy and Lighting /energyClocks and Timers /clocks Industrial /industrialInterface Medical /medicalLogic Security /securityPower Mgmt Space,Avionics and Defense /space-avionics-defense Microcontrollers Video and Imaging /videoRFID OMAP Mobile Processors /omap TI E2E Community Wireless Connectivity /wirelessconnectivityMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2012,Texas Instruments Incorporated。

M74HC07B1R中文资料

M74HC07B1R中文资料M54HC07M74HC07February 1993HEX BUFFER (OPEN DRAIN)B1R(Plastic Package)ORDER CODES :M54HC07F1R M74HC07M1R M74HC07B1R M74HC07C1R F1R(Ceramic Package)M1R(Micro Package)C1R (Chip Carrier)PIN CONNECTIONS (top view)NC =No Internal Connecti o nINPUT AND OUTPUT EQUIVALENT CIRCUIT.HIGH SPEEDt PD =5ns (TYP.)AT V CC =5V .LOW POWER DISSIPATION I CC =1 μA (MAX.)AT T A =25°C .HIGH NOISE IMMUNITYV NIH =V NIL =28%V CC (MIN.).OUTPUT DRIVE CAPABILITY 10LSTTL LOADS.WIDE OPERATING VOLTAGE RANGE V CC (OPR)=2V TO 6V .PIN AND FUNCTION COMPATIBLE WITH 54/74LS07The M54/74HC07is a high speed CMOS HEX OPEN DRAIN BUFFER fabricated in silicon gate C 2MOS technology.It has the same high speed per-formance of LSTTL combined with true CMOS low power consumption.The internal circuit is composed of 2stages includ-ing buffer output,which enables high noise im-munity and stable output.All inputs are equipped with circuits against static discharge andtransient excess voltage.DESCRIPTION1/9M54/M74HC07IEC LOGIC SYMBOLTRUTH TABLEA YL LH ZZ=High imped ancePIN DESCRIPTIONPIN No SYMBOL NAME AND FUNCTION1A to6A Data Inputs1,3,5,9,11,131Y to6Y Data Outputs2,4,6,8,10,127GND Ground(0V)14V CC Positive Supply VoltageLOGIC DIAGRAM(Per Gate)ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value Unit V CC Supply Voltage-0.5to+7V V I DC Input Voltage-0.5to V CC+0.5V V O DC Output Voltage-0.5to V CC+0.5VI IK DC Input Diode Current±20mAI OK DC Output Diode Current±20mAI O DC Output Sink Current Per Output Pin25mAI CC or I GND DC V CC or Ground Current±50mAP D Power Dissipation500(*)mW T stg Storage Temperature-65to+150o C T L Lead Temperature(10sec)300o C Absolute Maximum Ratings are those values beyond whichdamage to the device may occu r.Functiona l ope ration und er these cond ition isnotimplied. (*)500mW:?65o C derate to300mW by10mW/o C:65o C to85o C2/9RECOMMENDED OPERATING CONDITIONSSymbol Parameter Value Unit V CC Supply Voltage2to6V V I Input Voltage0to V CC V V O Output Voltage0to V CC V T op Operating Temperature:M54HC SeriesM74HC Series -55to+125-40to+85o Co Ct r,t f Input Rise and Fall Time V CC=2V0to1000nsV CC=4.5V0to500V CC=6V0to400DC SPECIFICATIONSSymbol ParameterTest Conditions ValueUnit V CC(V)T A=25o C54HC and74HC-40to85o C74HC-55to125o C54HCMin.Typ.Max.Min.Max.Min.Max.V IH High Level InputVoltage 2.0 1.5 1.5 1.5V 4.5 3.15 3.15 3.156.0 4.2 4.2 4.2V IL Low Level InputVoltage 2.00.50.50.5V 4.5 1.35 1.35 1.356.0 1.8 1.8 1.8V OL Low Level OutputVoltage 2.0V I=V IHorV ILI O=20μA0.00.10.10.1V 4.50.00.10.10.16.00.00.10.10.14.5I O=4.0mA0.170.260.330.406.0I O=5.2mA0.180.260.330.40I I Input LeakageCurrent 6.0V I=V CC or GND±0.1±1±1μAI OZ Output LeakageCurrent 6.0V I=V IH or V ILV O=V CC or GND±0.5±5±10μAI CC Quiescent SupplyCurrent 6.0V I=V CC or GND11020μA M54/M74HC073/9AC ELECTRICAL CHARACTERISTICS(C L=50pF,Input t r=t f=6ns)Symbol ParameterTest Conditions ValueUnit V CC(V)T A=25o C54HC and74HC-40to85o C74HC-55to125o C54HCMin.Typ.Max.Min.Max.Min.Max.t THL Output TransitionTime 2.0307595110ns 4.581519226.07131619t PLZ PropagationDelay Time 2.0R L=1K?1090115135ns 4.571823276.06152023t PZL PropagationDelay Time 2.0R L=1K?1790115135ns 4.571823276.05152023C IN Input Capacitance5101010pFC OUT OutputCapacitance 3pFC PD(*)Power DissipationCapacitance 4pF(*)C PD is defined as the value of the IC’s internal equivalent capac itanc e which is calculated from the operating current con sump tion without load. (Refer to Test Circuit).Average operting current can be obtained by the following equ ation.I CC(opr)=C PD?V CC?f IN+I CC/6(per Gate)M54/M74HC074/9M54/M74HC07 Plastic DIP14MECHANICAL DATAmm inchDIM.MIN.TYP.MAX.MIN.TYP.MAX.a10.510.020B 1.39 1.650.0550.065b0.50.020b10.250.010D200.787E8.50.335e 2.540.100e315.240.600F7.10.280I 5.10.201L 3.30.130Z 1.27 2.540.0500.100P001A5/9M54/M74HC07Ceramic DIP14/1MECHANICAL DATAmm inch DIM.MIN.TYP.MAX.MIN.TYP.MAX.A200.787 B7.00.276D 3.30.130E0.380.015e315.240.600F 2.29 2.790.0900.110G0.40.550.0160.022H 1.17 1.520.0460.060L0.220.310.0090.012 M 1.52 2.540.0600.100 N10.30.406 P7.88.050.3070.317 Q 5.080.200P053C 6/9M54/M74HC07SO14MECHANICAL DATAmm inchDIM.MIN.TYP.MAX.MIN.TYP.MAX.A 1.750.068a10.10.20.0030.007a2 1.650.064b0.350.460.0130.018b10.190.250.0070.010C0.50.019c145°(typ.)D8.558.750.3360.344E 5.8 6.20.2280.244e 1.270.050e37.620.300F 3.8 4.00.1490.157G 4.6 5.30.1810.208L0.5 1.270.0190.050M0.680.026S8°(max.)P013G7/9M54/M74HC07PLCC20MECHANICAL DATAmm inch DIM.MIN.TYP.MAX.MIN.TYP.MAX.A9.7810.030.3850.395 B8.899.040.3500.356D 4.2 4.570.1650.180d1 2.540.100d20.560.022E7.378.380.2900.330e 1.270.050e3 5.080.200F0.380.015G0.1010.004 M 1.270.050M1 1.140.045P027A 8/9M54/M74HC07 Information furnished is believed to be accurate and reliable.However,SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use.No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specificationsmentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics.1994SGS-THOMSON Microelectronics-All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia-Brazil-France-Germany-Hong Kong-Italy-Japan-Korea-Malaysia-Malta-Morocco-The Netherlands-Singapore-Spain-Sweden-Switzerland-Taiwan-Thailand-United Kingdom-U.S.A9/9。