03-Logic Gates

25
Noise Margin
Noise margin = voltage difference between output of one gate and input of next. Noise must exceed noise margin to make second gate produce wrong output In static gates, t= voltages are VDD and VSS, so noise margins are VDD-VIH and VIL-VSS

26
Delay

Assume ideal input (step), RC load
27
Delay Assumptions

Assume that only one transistor is on at a time. This gives two cases:
rise time, pull-up on fall time, pull-up off
23
Inverter Transfer Curve
24
Logic Thresholds
Choose threshold voltages at points where slope of transfer curve = -1 Inverter has a high gain between VIL and VIH points, low gain at outer regions of transfer curve Note that logic 0 and 1 regions are not equal sized—in this case, high pull-up resistance leads to smaller logic 1 range

3
Gate Design

Designing gates for logic functions is non-trivial:
May not have logic gates in the library for all logic expressions A logic expression may map into gates that consume a lot of area, delay, or power
ttot
= n(Cbig/Cg)1/n tmin. (tmin : the time to drive a minimum sized-load, Cg : the minimum-sized load capacitance)
EIE511 VLSI System Design Lecture 3
Logic Gates
1
Introduction
Layout of logic gates Physical characteristics of logic gates

Delay Wire sizing


Different types of logic gate designs

Transistor starts in saturation region, then moves to linear region
29
Ways of Measuring Gate Delay
Delay: time required for gate’s output to reach 50% of final value Transition time: time required for gate’s output to reach 10% (logic 0) or 90% (logic 1) of final value

7
Static Complementary Gate Structure

Pull-up and pull-down networks:
VDD
pullup network inputs pulldown network
VSS
out
8
Inverter

Structure:
+
a
out
9
Inverter Layout
VDD
logic 1
unknown
VSS
VH
VL
logic 0
21
Logic Level Matching

Levels at output of one gate must be sufficient to drive next gate
22
Transfer Characteristics

Transfer curve shows static input/output relationship—hold input voltage, measure output voltage

Assume resistor model for transistor Ignore saturation region and mischaracterizes linear region, but results are acceptable

28
Current Through Transistor
VDD + out b a out tub ties b a GND
13
NOR Gate

Truth Table:
A 0 0 B 0 1 O 1 0
1
1
0
1
0
0
14
NOR Gate

Structure:
+ b a out
15
NOR Gate Layout
VDD
b a
tub ties b out out a GND

32
t Model Inverter Delay

0.5 micron process:
Rn = 3.9 kW Cl = 0.68 fF


So
td
= 0.69 x 3.9 x .68E-15 = 1.8 ps tf = 2.2 x 3.9 x .68E-15 = 5.8 ps
33
Quality of RC Approximation
35
Cascaded Driver Circuit
36
Optimal Sizing

Use a chain of inverters, each stage has transistors larger than previous stage Minimize total delay through driver chain:
16
AOI/OAI Gates
AOI = and/or/invert; OAI = or/and/invert Implement larger functions Pull-up and pull-down networks are compact: smaller area, higher speed than NAND/NOR network equivalents AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert

30
Inverter Delay Circuit

Load is resistor + capacitor, driver is resistor
31
Inverter Delay with t Model
t model: gate delay based on RC time constant t. Vout(t) = VDD exp{-t/(Rn+RL)/ CL} tf = 2.2 R CL For pull-up time, use pull-up resistance

19
Class Exercise 3.1

Draw a stick diagram of the following circuits
c
b
a
o
20
Logic Levels

Solid logic 0/1 defined by VSS/VDD Inner bounds of logic values VL/VH are not directly determined by circuit properties, as in some other logic families

17
AOI Example
out = [ab+c]’:
invert
symbol
or
circuit
and
18
Pull-up/pull-down Network Design
Pull-up and pull-down networks are duals To design one gate, first design one network, then compute dual to get other network Example: design network which pulls down when output should be 0, then find dual to get pull-up network
5
Completeness
A set of functions f1, f2, ... is complete iff every Boolean function can be generated by a combination of the functions NAND is a complete set; NOR is a complete set; {AND, OR} is not complete Transmission gates are not complete If your set of logic gates is not complete, you can’t design arbitrary logic

6
Static Complementary Gates
Complementary: have complementary pull-up (p-type) and pull-down (n-type) networks Static: do not rely on stored charge Simple, effective, reliable
Switching logic DCVS logic Domino logic

2
Combinational Logic Expressions
Combinational logic: function value is a combination of function arguments A logic gate implements a particular logic function Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic

4
Boolean Algebra Terminology

Function:

f = a’b + ab’
a is a variable; a and a’ are literals ab’ is a term A function is irredundant if no literal can be removed without changing its truth value
34
Driving Large Loads

Sometimes, large loads must be driven:
off-chip long wires on-chip


Sizing up the driver transistors only pushes back the problem—driver now presents larger capacitance to earlier stage
VDD + tub ties out transistors a a out
(tubs not shown)
GND
10
NAND Gate

Truth Table:
A 0 0 B 0 1 O 1wk.baidu.com1
1
1
0
1
1
0
11
NAND Gate

Structure:
+
out b
a
12
NAND Gate Layout