ST7FMC2M9T6中文资料

ST7MC1
8K 384 (256)
16K 24K 32K 48K 768 (256) 1024 (256) 1024 (256) 1536 (256) Watchdog, 16-bit Timer A, LINSCI, 10-bit ADC, MTC, 8-bit PWM ART, ICD SPI, 16-bit Timer B 4.5 to 5.5V with fCPU≤8MHz -40°C to +85 °C SDIP56/TQFP64 TQFP64
ST7MC2
Device Summary
Features
Program memory - bytes RAM (stack) - bytes Peripherals Operating Supply vs. Frequency Temperature Range Package -40°C to +85°C / -40°C to +125°C SDIP32/TQFP32 TQFP44
ST7MC1/ST7MC2
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI
PRODUCT PREVIEW
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Memories – 8K to 60K dual voltage FLASH Program memory or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming. – 384 to 1.5K RAM – HDFlash endurance: 100 cycles, data retention: 20 years Clock, Reset And Supply Management – Enhanced reset system – Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability – Clock sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system. – Four power saving modes: Halt, Active-Halt, Wait and Slow Interrupt Management – Nested interrupt controller – 14 interrupt vectors plus TRAP and RESET – MCES top level interrupt pin – 16 external interrupt lines (on 3 vectors) Up to 60 I/O Ports – up to 60 multifunctional bidirectional I/O lines – up to 41 alternate function lines – up to 11 high sink outputs 5 Timers – Main Clock Controller with: Real time base, Beep and Clock-out capabilities – Configurable window watchdog timer – Two 16-bit timers with: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes – 8-bit PWM Auto-Reload timer with: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
60K 1536 (256)
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TQFP80
Rev. 2.1
April 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 6.3 6.4 6.5 6.6 6.7 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 43
1/294
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 4.3 4.4 4.5 4.6 4.7 4.8 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TQFP80 14 x 14
TQFP64 14 x 14
源自文库
TQFP44 10 x 10
TQFP32 7x7
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SDIP56
SDIP32
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2 Communication Interfaces – SPI synchronous serial interface – LINSCI asynchronous serial interface Brushless Motor Control Peripheral – 6 high sink PWM output channels for sinewave or trapezoidal inverter control – Motor safety including asynchronous emergency stop and write-once registers – 4 analog inputs for rotor position detection (sensorless/hall/tacho/encoder) – Permanent magnet motor coprocessor including multiplier, programmable filters, blanking windows and event counters – Operational amplifier and comparator for current/voltage mode regulation and limitation Analog peripheral – 10-bit ADC with 16 input pins In-circuit Debug Instruction Set – 8-bit Data Manipulation – 63 Basic Instructions – 17 main Addressing Modes – 8 x 8 Unsigned Multiply Instruction – True Bit Manipulation Development Tools – Full hardware/software development package
5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 5.3 5.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 32