SN74AUP1G00中文资料
合集下载
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
YEP OR YZP PACKAGE (BOTTOM VIEW)
D
A B GND
1 2 3
5 4
VCC Y
GND B A
3 4 2 1 5
Y VCC
description /ordering information
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2).
† AUP1G08 data at CL = 15 pF.
Figure 1. AUP−The Lowest-Power Family
Figure 2. Excellent Signal Integrity
This single 2-input positive-NAND gate performs the Boolean function Y = A • B or Y = A + B in positive logic. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
TA PACKAGE† NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP −40°C to 85°C NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) SOT (SOT-23) − DBV SOT (SC-70) − DCK SOT (SOT-533) − DRL Tape and reel Tape and reel Tape and reel Tape and reel Reel or 4000 ORDERABLE PART NUMBER SN74AUP1G00YEPR _ _ _HA_ SN74AUP1G00YZPR SN74AUP1G00DBVR SN74AUP1G00DCKR SN74AUPG00DRLR H00_ HA_ TOP-SIDE MARKING‡
SwitchingBiblioteka BaiduCharacteristics at 25 MHz† 3.5 3 2.5 2 1.5 1 0.5 0 −0.5 0 5 10 15 20 25 30 Time − ns 35 40 45 Input Output
LVC †
† Single, dual, and triple gates.
Copyright 2005, Texas Instruments Incorporated
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
元器件交易网www.cecb2b.com
SN74AUP1G00 LOWĆPOWER SINGLE 2ĆINPUT POSITIVEĆNAND GATE
SCES604A – SEPTEMBER 2004 – REVISED APRIL 2005
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS A L L H H B L H L H OUTPUT Y H H H L
SCES604A – SEPTEMBER 2004 – REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Output voltage range in the high or low state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W DRL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
logic diagram (positive logic)
A B 1 2 4 Y
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
元器件交易网www.cecb2b.com
SN74AUP1G00 LOWĆPOWER SINGLE 2ĆINPUT POSITIVEĆNAND GATE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments.
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION
元器件交易网www.cecb2b.com
SN74AUP1G00 LOWĆPOWER SINGLE 2ĆINPUT POSITIVEĆNAND GATE
SCES604A – SEPTEMBER 2004 – REVISED APRIL 2005
D Available in the Texas Instruments D D D D D D
NanoStar and NanoFree Packages Low Static-Power Consumption; ICC = 0.9-µA Max Low Dynamic-Power Consumption; Cpd = 4 pF Typical at 3.3 V Low Input Capacitance; Ci = 1.5 pF Typical Low Noise − Overshoot and Undershoot <10% of VCC Ioff Supports Partial-Power-Down Mode Operation Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Static-Power Consumption (µA) 100% 80% 60% 40% 20% 0%
AUP 3.3-V Logic†
Dynamic-Power Consumption (pF) 100% 80% Voltage − V 60% 40% 20% 0%
AUP 3.3-V Logic
Signal Operation tpd = 4.8 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) ESD Protection Exceeds ±5000-V With Human-Body Model
DBV, DCK, OR DRL PACKAGE (TOP VIEW)
D Wide Operating VCC Range of 0.8 V to 3.6 V D Optimized for 3.3-V Operation D 3.6-V I/O Tolerant to Support Mixed-Mode D D D D
D
A B GND
1 2 3
5 4
VCC Y
GND B A
3 4 2 1 5
Y VCC
description /ordering information
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2).
† AUP1G08 data at CL = 15 pF.
Figure 1. AUP−The Lowest-Power Family
Figure 2. Excellent Signal Integrity
This single 2-input positive-NAND gate performs the Boolean function Y = A • B or Y = A + B in positive logic. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
TA PACKAGE† NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP −40°C to 85°C NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) SOT (SOT-23) − DBV SOT (SC-70) − DCK SOT (SOT-533) − DRL Tape and reel Tape and reel Tape and reel Tape and reel Reel or 4000 ORDERABLE PART NUMBER SN74AUP1G00YEPR _ _ _HA_ SN74AUP1G00YZPR SN74AUP1G00DBVR SN74AUP1G00DCKR SN74AUPG00DRLR H00_ HA_ TOP-SIDE MARKING‡
SwitchingBiblioteka BaiduCharacteristics at 25 MHz† 3.5 3 2.5 2 1.5 1 0.5 0 −0.5 0 5 10 15 20 25 30 Time − ns 35 40 45 Input Output
LVC †
† Single, dual, and triple gates.
Copyright 2005, Texas Instruments Incorporated
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
元器件交易网www.cecb2b.com
SN74AUP1G00 LOWĆPOWER SINGLE 2ĆINPUT POSITIVEĆNAND GATE
SCES604A – SEPTEMBER 2004 – REVISED APRIL 2005
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS A L L H H B L H L H OUTPUT Y H H H L
SCES604A – SEPTEMBER 2004 – REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Output voltage range in the high or low state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W DRL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
logic diagram (positive logic)
A B 1 2 4 Y
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
元器件交易网www.cecb2b.com
SN74AUP1G00 LOWĆPOWER SINGLE 2ĆINPUT POSITIVEĆNAND GATE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments.
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION
元器件交易网www.cecb2b.com
SN74AUP1G00 LOWĆPOWER SINGLE 2ĆINPUT POSITIVEĆNAND GATE
SCES604A – SEPTEMBER 2004 – REVISED APRIL 2005
D Available in the Texas Instruments D D D D D D
NanoStar and NanoFree Packages Low Static-Power Consumption; ICC = 0.9-µA Max Low Dynamic-Power Consumption; Cpd = 4 pF Typical at 3.3 V Low Input Capacitance; Ci = 1.5 pF Typical Low Noise − Overshoot and Undershoot <10% of VCC Ioff Supports Partial-Power-Down Mode Operation Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Static-Power Consumption (µA) 100% 80% 60% 40% 20% 0%
AUP 3.3-V Logic†
Dynamic-Power Consumption (pF) 100% 80% Voltage − V 60% 40% 20% 0%
AUP 3.3-V Logic
Signal Operation tpd = 4.8 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) ESD Protection Exceeds ±5000-V With Human-Body Model
DBV, DCK, OR DRL PACKAGE (TOP VIEW)
D Wide Operating VCC Range of 0.8 V to 3.6 V D Optimized for 3.3-V Operation D 3.6-V I/O Tolerant to Support Mixed-Mode D D D D