chapter4(4)

A static-0 hazard(静态0险象) is the possibility of a 1 glitch when we expect the circuit to have a steady 0 output: Definition: A static-0 hazard is a pair of input combinations that: (a) differ in only one input variable and (b) both give a 0 output; such that it is possible for a momentary 1 output to occur during a transition in the differing input variable. Since a static-0 hazard is just the dual(对偶 of a static对偶) 对偶 1 hazard, an OR-AND circuit that is the dual of Figure 4-44(a) would have a static-0 hazard.
图4-45
4.5.1 Static Hazards(6)
静态0险象的基本电 静态 险象的基本电 路如图所示： 路如图所示： F=A•A’ 静态0险象只出现 静态 险象只出现 在“或-与”电路中。 与 电路中。
A F
4.5.2 Finding Static Hazards Using Maps
4.5.2 Finding Static Hazards Using Maps(利用卡诺图判 利用卡诺图判 别静态险象) 别静态险象 A Karnaugh map can be used to detect static hazards in a two-level sum-of-products or product-of-sums circuit. The existence or nonexistence of static hazards depends on the circuit design for a logic function. A properly designed two-level sum-of-products (AND-OR) circuit has no static-0 hazards. A static-0 hazard would exist in such a circuit only if both a variable and its complement were connected to the same AND gate, which would be silly. However, the circuit may have static-1 hazards. Their existence can be predicted from a Karnaugh map when the product terms corresponding to the AND gates in the circuit are circled.
4.5 Timing Hazards
4.5 Timing Hazards(险象 险象) 险象
The analysis methods that we developed in Section 4.2 ignore circuit delay and predict only the steadystate behavior(稳态特性) of combinational logic circuits. That is, they predict a circuit's output as a function of its inputs under the assumption that the inputs have been stable for a long time, relative to the delays in the circuit's electronics. However, we showed in Section 3.6 that the actual delay from an input change to the corresponding output change in a real logic circuit is nonzero and depends on many factors.
4.5 Timing Hazards(2)
Because of circuit delays, the transient behavior(瞬态 特性) of a logic circuit may differ from what is predicted by a steady-state analysis. In particular, a circuit’s output may produce a short pulse, often called a glitch (尖脉冲), at a time when steady-state analysis predicts that the output should not change. A hazard is said to exist when a circuit has the possibility of producing such a glitch. Whether or not the glitch actually occurs depends on the exact delays and other electrical characteristics of the circuit. Since such parameters are difficult to control in production circuits, a logic designer must be prepared to eliminate(消除 hazards 消除) 消除 (the possibility of a glitch) even though a glitch may occur only under a worst-case combination of logical and electrical conditions.
4.5.2 Finding Static Hazards (2)
险象的判别方法有卡诺图法和逻辑表达式法二种。 险象的判别方法有卡诺图法和逻辑表达式法二种。 1.卡诺图判别法 卡诺图判别法 F=XY’Z’+W’Z+WY F=XZ’+YZ WX
XY Z Z YZ X W
1 1 1 1
Y
1 1 1 1 Z 1 1 1 1 Y 1 1
4.5.1 Static Hazards(5)
An OR-AND circuit with four static-0 hazards is shown in Figure 4-45(a). One of the hazards occurs when W,X,Y = 000 and Z is changed, as shown in (b). You should be able to find the other three hazards and eliminate all of them after studying the next subsection.
4.5.1 Static Hazardnsider the logic circuit in Figure 4- 44(a). Suppose that X and Y are both I and that Z is changing from 1 to 0. Then (b) shows the timing diagram, assuming that the propagation delay(传输延迟 through each gate 传输延迟) 传输延迟 or inverter is one unit time. Even though "static" analysis predicts that the output is 1 for both input combinations X,Y,Z = 111 and X,Y,Z = 110, the timing diagram shows that F goes to 0 for one unit time during a 1-0 transition on Z, because of the delay in the inverter that generates Z'.
Figure 4-44
图4-44
4.5.1 Static Hazards(3)
静态1险象的基本电 静态 险象的基本电 A 路及时序如图所示： 路及时序如图所示： F=A+A’ A 静态1险象只出现 静态 险象只出现 在“与-或”电路中。 或 电路中。
F F
A' ∆t
4.5.1 Static Hazards(4)
可见： 的变化会使电路产生险象。 变化时 可见：当B=C=1时，A的变化会使电路产生险象。C变化时 时 的变化会使电路产生险象 不会产生险象。 不会产生险象。
险象的消除
例1：F=X٠Z'+YZ ： 当X=1且Y=1，而Z由1→0时，时会产生险象。 且 ， 由 时 时会产生险象。
XY X' X 00 01 11 10 Z 1 1 Z' 0 1 1 Z 1 Y' Y Y'
YZ XZ'
为了避免静态1险象，F中必 为了避免静态 险象， 中必 险象 须添加冗余项XY。 须添加冗余项 。 F=XZ'+YZ+XY 当X=1且Y=1时，XY为1，因 且 时 为 ， 此F=1，就不会有静态 险象 ，就不会有静态1险象 了。