东南大学soc课件10 芯片验证(3学时)

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for (i = 0; i < d; i= i+2) { if (y > 3) p = p * 3; else q = q + r; }
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Bottom line: to fix as many bugs in your design as possible
Design Creation
RTL
Design Implementation
Gate Gate
Physical Implementation
GDSII
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Where are the Bugs?
• Functional specification
– system or behavior-level descriptions
• 其中file_arm.f文件中列出了所有的.v文件
– – – – – – – – – – – – Arm.v Amba.v Dmac.v Ssi.v Emi.v Intc.v Top.v Ssi_model.v Sdram.v Sram.v Nand.v Test.v
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开始运行arm测试程序
SoC芯片验证
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目录
• Why Verification • Verification Alternatives
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What is Design Verification?
always @(posedge clk) begin if (rst==1'b1) cnt <= sv; else if (cnt==2'b00) cnt <= 2'b01; else if (cnt==2'b01) cnt <= 2'b10; else if (cnt==2'b10) cnt <= 2'b11; else cnt <= sv; end
• SoC芯片外接模型
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编写RTL testbench
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编写RTL testbench
• 在初始化部分添加
– 系统复位信号 – 系统时钟信号激励
• 把SoC芯片的各个管脚连接好
– 暂无用的输入管脚置0或置1，暂无用的输出管脚可悬 空 – 和功能验证相关的管脚必须对应连接好
• 每个片选上所接的存储器须按存储器的要求连接好各个信号线
– fromelf -vhx -8x1 “ssi.axf" -o asc
• 把asc加载到SoC的CSA片选所接的存储器中
– 在RTL的testbench中编写 – $readmemh ("asc",u_csa0.memory);
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开始编译RTL代码并仿真
• vcs -f file_arm.f -l sim.log
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Percentage of Total Flaws
Power Race 4% 5% Clocking 5% Yield 7% Noise 12%
Other 9% Logical/ Functional 45%
Slow Path 13%
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Importance of Verification
• More than half of all chips require one or more re-spins, and that functional errors were found in 74% of these re-spins. • With increasing chip complexity, this situation could worsen. • Who can afford that with >= 1M Dollar NRE cost?
ATPG Fault Simulation Scan / BIST
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Agenda
• Why Verification • Verification Alternatives
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Verification Alternatives
• Simulation • FPGA Prototyping • Formal Verification
• 在testbench中所加的复位和时钟信号的激 励下
– arm在复位后从0x0地址取指令运行 – 0x0地址一般为片选CSA所接的存储器
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观察仿真波形
• 普通、简单、基础而又易被忽视的信号！
– CLK – RESET_N
• 但是无论在仿真还是测试中都是最重要的 信号！！！
•CLK •RESET_N
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观察仿真波形（续）
• 看arm是否正常取指令运行
– 先取0x0地址中的跳转指令（e开头的指令）， 内容是否正确可参考asc文件中的第一行。 – 下一个取的地址就不是0x4，而是根据跳转指 令而跳转到其它地址去取指令
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观察仿真波形（续）
• 观察AMBA总线的信号是否正确 • 先看HTRANS信号
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RTL仿真
• 所使用的工具：VCS or Modelsim • 仿真步骤：
– – – – 搭建RTL验证环境 编写RTL的testbench 编写ARM的测试代码 把ARM测试代码的二进制文件加载到RTL验证环境中 的RAM中 – 开始运行arm测试程序 – 观察仿真波形，观察调试信息
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搭建RTL验证环境
Behavioral Design
RTL Design
Gate Level Design
Device Production
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Verification vs. Testing
Design Specification Design Creation Design Implementation Chip Manufacture
• 以DMAC模块的验证为例
SSI模型
SOC芯片
SRAM1 (CSA 16 *1)
SRAM2 (CSB 8*1) DMAC SDRAM (CSE 16*1)
SRAM (CSF 16*1)
NAND (8*1)
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搭建RTL验证环境（续）
• SoC芯片
– – – – – – – – – – ARM7TDMI AMBA DMAC模块 SSI控制模块 EMI INTC SSI外设模型 SRAM模型 SDRAM模型 NAND模型
• Design creation
– Inconsistent with spec – RTL coding error (typo, X, logical error) – Assumption on the environment
• Design/Physical implementation
– Synthesis tools – Manual optimization
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Bug Fixing Cost in Time
• Cost of fixing a bug/problem increases as design progresses.
– Need verification method at early design stage
Cost of Fixing a Problem
Testbench a = 1; #20 b = 1; $display (“status is = %d”,c); ... Some part of the design is tested repeatedly. DUV Other parts are not even tested.
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Software Simulation
Verification takes ~ 70% of resources in today’s IC design
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• 设计验证verification的目的是确认设计的功 能正确性和性能（速度和功耗等）满足设 计要求，贯穿于设计的整个过程
Design Flow
Functional Specification
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观察仿真波形（续）
• 看DMAC模块的接口信号波形 • 如果是存储器到外设的传输
– 看存储器的接口信号 – 看相应外设的接口信号
• SSI
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观察调试信息
• 如何把C代码中打印的调试信息打印到VCS仿真运行 的控制台中？
– 在SoC芯片的顶层文件中例化Tube模块，作为一个AHB slave设备，设占用的地址为0x1100c000。 – Tube模块接收往0x1100c000地址所写的字符并保存到log 文件中。 – 在arm测试代码中的retarget.c文件实现print函数，print函 数把要打印的调试信息发送到0x1100c000 地址 – 则arm代码调用print函数，即可把调试信息打印到VCS仿真 运行的控制台中。
• Cons
– Slow (~k cycles/sec) ; Speed gap between the speed of software simulation and real silicon widens. (Simulation speed = size of the circuit simulated / speed of the simulation engine) – The designer does not exactly know how much percentage of the design have been tested.
– 00：IDLE – 01：BUSY – 10：NONSEQ – 11：SEQ
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观察仿真波形（续）
• • • • • • • • • • • • HBUSREQ HGRANTx HSELx (Slave select signal) HLOCK HTRANS[1:0] HBURST[2:0] HADDR[31:0] HREADY (Slave response signal, transfer done.) HRESP[1:0] HWDATA[31:0] HRDATA[31:0] HWRITE