STK3228 Data Sheets_v0.93
MT6333_PMIC_Data_Sheet_V01_NoRestriction
Document Revision HistoryM E D I A T E K C O N F I D E L O R z h a o l i f e n g @ v a n z o t e c .c o m ONTable of ContentsDocument Revision History .................................................................................................. 2 Table of Contents.. (3)1Overview (5)1.1 Features .............................................................................................................. 5 1.2 Applications ......................................................................................................... 5 1.3 General Descriptions ............................................................................................. 5 1.4 Ordering Information ............................................................................................. 6 1.5 Top Marking Definition ........................................................................................... 6 1.6 Pin Assignments and Descriptions........................................................................... 6 2 Electrical Characteristics (8)2.1 Absolute Maximum Ratings over Operating Free-Air Temperature Range...................... 8 2.2 Thermal Characteristic........................................................................................... 8 2.3 Pin Voltage Range ................................................................................................ 8 2.4 Recommended Operating Range ............................................................................ 9 2.5 Electrical Characteristics ........................................................................................ 9 2.6 Regulator Output ................................................................................................ 10 2.7 Flash . (10)3 Functional Descriptions ............................................................................................. 11 3.1 General Descriptions ........................................................................................... 11 3.2 PMIC Functional Blocks ....................................................................................... 11 3.2.1 Power-On/Off Sequence ........................................................................ 12 Power on/off sequence. (12)3.2.2 Buck Converter..................................................................................... 12 3.2.3 Flash Driver ......................................................................................... 13 3.3 Register Table and Description ............................................................................. 14 4 Application Notes (47)4.1 Connection with Main Chip & Main PMIC................................................................ 47 5MT6333 Packaging (48)5.1 Package Dimensions ........................................................................................... 48 Appendix (49)Lists of FiguresFigure 1-1. MT6333 WLCSP - 30L pin assignment (6)Figure 3-1. MT6333 block diagram ......................................................................................... 11 Figure 3-2. Power-on/off control sequence is controlled by MT6322/23: through pin BUCK_EN .......12 Figure 4-1. MT6333 connection with main chip and main PMIC (47)M E D I A T E K C O N F I D E N T I A L O R z h a o l i f e n g @ v a n z o t e c .c o m U S E ONLists of TablesT able 1-1. MT6333 pin descriptions ......................................................................................... 7 T able 2-1. Absolute maximum ratings ....................................................................................... 8 T able 2-2. Operation condition ................................................................................................ 8 T able 2-2. Operation condition ................................................................................................ 9 T able 2-3. General electrical specifications................................................................................ 9 T able 2-4. Regulator specifications .........................................................................................10 T able 3-1. Buck converter brief specifications (13)M E D I A T E K C O N F I D E N T I A L O R z h a o l i f e n g @ v a n z o t e c .c o m U S E ON1 Overview1.1 Features⏹ Thermal regulation and thermal shut-down ⏹ Boost mode for Flashlight,T orch: 300mA(base on LED rating), Flash: 1.0A⏹ Three bucks for VCORE (1.15V/2A), VMEM (1.225V/1.5A) and VRF (1.825V/450mA)⏹ Buck_EN & Sleep_B balls communicate with main PMIC (MT6323/MT6322). ⏹ I2C interface⏹2.1259X 2.638 WLCSP , 30-balls, 0.4-pitch1.2 ApplicationsFor power management of smart phones and other portable systems.1.3 General DescriptionsMT6333 is a sub-power management system chip optimized for 2G/3G handsets and smart phones, especially based on the MediaT ek MT6323/MT6322 system solution.MT6333 highly integrates one boost converter for flashlight driver and 3 buck converters for system power optimization.The boost mode can be used to supply flashlight from VLED pin.MT6333 also integrates three buck converters for VCORE/VMEM/VRF which is used for higher current demand.Buck_En pin is provided for power-on sequence controlled by main PMIC, and Sleep_B pin is for sleep mode control.MT6333 is available in a WLCSP - 30L package. The operating temperature ranges from -20 to +80°C.M E D I A T E K C O N F I D E N T I A L O R z h a o l i f e n g @ v a n z o t e c .c o m U S E ON1.4 Ordering Information1.5 Top Marking DefinitionMT6333P/AYYWW: Date code$$$$$$$: Random code1.6 Pin Assignments and DescriptionsFigure 1-1. MT6333 WLCSP - 30L pin assignmentMTKMT6333P YYWW-A$$H $$$$$$BATSNS LX SDALXISET BOOT DRVCDT VLED SCL VMEM_FBVCORE_FBBUCK_EN CSCS VMEM_LX VBAT VBATINTVCORE_LXPGND_CHRAGNDPGND_BUCKSLEEP_B A B CD E F12345CHRINVRF_LXVRF_FB VBUSCHR_G ATEGND PGND_BUCKM E D I A T E K C O N F I D E N T I O R z h a o l i f e n g @ v a n z o t e c .c o m U S E ONTable 1-1. MT6333 pin descriptionsM O R z h a o l2 Electrical Characteristics2.1 Absolute Maximum Ratings over Operating Free-AirTemperature RangeStresses beyond those listed under T able 2-1. Absolute maximum ratings may cause permanent damage to the device. These numbers are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the device reliability.Table 2-1. Absolute maximum ratings2.2 Thermal CharacteristicNote: The device is mounted on a 4-metal-layer PCB and modeled per JEDEC51-9 condition.2.3 Pin Voltage RangeTable 2-2. Operation conditionA T E E N T I A L O n g @ z o m U S E ON2.4 Recommended Operating RangeTable 2-3. Operation condition2.5 Electrical CharacteristicsVBAT = 3.4 ~ 4.35V , minimum loads applied on all outputs, unless otherwise noted. T ypical values are at T A = 25°C.Table 2-4. General electrical specificationsE K CF I O R z h v a n e c .c2.6 Regulator OutputTable 2-5. Regulator specifications2.7 FlashTable 2-9. Flash specificationsM E O O R z h a o l i f o t e N3 Functional Descriptions3.1General DescriptionsMT6333 is an integrated PMIC that contains flashlight driver and BUCKs. Figure 3-1. is the block diagram of the whole picture of MT6333 PMIC.Figure 3-1. MT6333 block diagram3.2 PMIC Functional BlocksMT6333 features three BUCKs for baseband, memory and RF and the flashlight driver for flash LED. MT6333 includes the following analog functions for use on smart phone platforms.∙ BUCK: Provides regulated lower output voltage level from Li-Ion battery∙ Controller: Generates power-on/off sequence for BUCKs in such way to be applicable withMT6323/6322M E D I I A L O R z h a o l i f e S E ONFlash driver: Supports LED driver for applications such as flashlight, camara flash or video recording lightening (or torch mode)More detailed descriptions of each sub-block are explained in the following sections.3.2.1 Power-On/Off SequencePower-On/Off of the BUCKs in MT6333 are controlled by HW pin strapping and SW setting. The On/Off sequence of VCORE and VMEM is controlled by pin “BUCK_EN ” as shown in Figure 3-2.VRF18 is controlled by software directly through I 2C. Figure 3-2 also depicts the voltage of VCORE wil be reduced in sleep mode.Power on/off sequenceBUCK_ENVCORE VMEMSLEEP_BFigure 3-2. Power-on/off control sequence is controlled by MT6322/23: through pin BUCK_ENOver-temperature protectionIf the die temperature of PMIC exceeds 150°C, MT6333 VCORE will be set to sleep mode voltage while VMEM is kept the same. Once the over-temperature state is resolved, every block will return to its normal mode operation. Since VRF18 is controlled by software directly, it will not be affected by this thermal protection.3.2.2 Buck ConverterThere are 3 buck converters in MT6333 to efficiently generate regulated power for digital core,LPDDR3 (and LPDDR2) and RF circuit. Figure 3-3 is the block diagram. The buck converters operate with typically 2MHz (VRF18) and 3MHz (VCORE, VMEM) fixed frequency pulse width modulation (PWM) to heavy load currents. At light load currents, the converter automatically enters pulsefrequency modulation (PFM) mode to save power and improve light load efficiency. It also has a force-PWM mode option to allow the converter to remain in the PWM mode regardless of the load current, so that the noise spectrum of the converter can be minimized for certain highly-noise-sensitivehandset applications. The buck converters also have an internal over-current protection (OCP) circuit to limit the maximum high-side power FET current in over-load conditions. It has an internal soft start circuit to control the ramp-up rate of the output voltage during start-up.M E D I A T E K E N T I A L O R z h a o l i f e n g @ v a n m U S E ONTable 3-1. Buck converter brief specifications1. Digital CORE power, VCOREVCORE is a high-current buck converter to provide a highly-efficient power supply for the handset digital core. Powering from a Li-ion battery, VCORE steps down the input voltage from 3.4 ~ 4.4V to the typical output voltage of 1.15V with a maximum load current capability of 2A. The output voltage can be adjusted between 0.7V and 1.4V. In order to optimize the overall system efficiency for digital core, VCORE features a Dynamic Voltage Frequency Scaling (DVFS) function which allows it to dynamically adjust its output voltage between 0.85V and 1.15V under different voltage supply demands from the digital core circuit. For more details, refer to the “Dynamic Voltage Frequency Scaling (DVFS)” section.2. LPDDR2, LPDDR3 power, VMEMVMEM is a high-current buck converter to provide a highly-efficient power supply for the DDR memory. Powering from a Li-ion battery, VMEM steps down the input voltage from 3.4 ~ 4.4V to the typical output voltage of 1.225V with a maximum load current capability of 1.5A.3. RF power, VRF18VRF18 is a buck converter to provide a highly-efficient power supply for the handset RF power. Powering from a Li-ion battery, VRF18 steps down the input voltage from 3.4 ~ 4.4V to the typical output voltage of 1.825V with a maximum load current capability of 0.45A.3.2.3Flash DriverMT6333 has a boost converter with a white LED flash driver which is capable of delivering up to 1.0A and used in camera flash applications. Therefore, there are two modes in flash driver, Flash Mode and T orch (Video) Mode.Figure 3-9 is the block diagram. The power supply of LED flash driver is CHRIN pin and VLED pin is attached LED. R SET =1kΩ is an external resistor, which sets up the LED current in Flash Mode and T orch Mode.Flash ModeIn Flash Mode, the LED current source is activated by RG_FLASH_EN. While the Flash on-sequence is done, the LED current will ramp up to the target current. The range of LED current souce is from 50mA to 1,000mA with 13 options. The Flash currents are programmed by register settings.M E D I A T E K C O N F I D E N T I OR z h a o l i f e n g @ v a n z o t e c .c o m U STorch (Video) ModeIn T orch/Video Mode,the LED current provides 6 options from 50mA to 300mA, and the current level can be adjusted by register settings. The LED current source is activated by RG_TORCH_MODE. The LSB of current level is 50mA.LED Short ProtectMT6333 Flash driver has an LED short protection. A comparator detects the voltage of VLED pin. When the pin VLED is short to GND, the current source will be turned off immediately.LED Open ProtectMT6333 Flash driver also has an LED open protection. When the pin VLED voltage rises to the OVP voltage, the LED current source will immediately be shut down. By reboot the LED current source can be resumed to its normal operation.Figure 3-9. Flash driver block diagram3.3 Register Table and DescriptionModule name: SWCHR Base address: (+0h)CHRIN A T D E N T I A L O g @o m U S E ON00CID0Chip ID status 093Bit(s) Mnemonic Name Description 7:0CID0CID0CID025 STA_CON12STA control register 1200M E A O h a o l i gBit(s) Mnemonic Name Description6 RGS_VLE D_OPENRGS_VLED_OPE NLED open flag 5RGS_VLE D_SHORTRGS_VLED_SH ORTLED short flag31 DIG_CON8DIG control register 800Bit(s) Mnemonic Name DescriptionRG_FLAS H_ENRG_FLASH_ENTurns on flash current 0: Disable 1: E nable32 DIG_CON9DIG control register 900Bit(s) Mnemonic Name Description4RG_TORC H_M ODERG_TORCH_MO DEE nables torch mode 0: Disable 1: E nable35 DIG_CON12DIG control register 1200Bit(s) Mnemonic Name Description3:0RG_FLASH_ISE T RG_FLASH_ISE TISE T current setting 0000: 50mA (default) 0001: 100mA 0010: 150mA 0011: 200mA 0100: 250mA 0101: 300mAM I A T E K O N F I D T I A L O R z h a o e n g @ v o t e c .c U S E OBit(s)Mnemonic NameDescription 0111: 500mA 1000: 600mA 1001: 700mA 1010: 800mA 1011: 900mA 1100: 1000mA 1101: 1100mA 1110: 1200mA 1111: 1300mA37DIG_CON14DIG control register 1400Bit(s) Mnemonic Name Description7:6RG_FLAS H_EN_TIM EOUT_SE LRG_FLASH_EN_TIMEOUT_SELFlash current turn-on time-out protection 00: 200ms 01: 400ms 10: 600ms 11: 800ms3C GPIO_CON0GPIO control register 002Bit(s) Mnemonic Name Description1I2C_DEG_ENI2C_DEG_ENE nables deglitch 0: Disable 1: E nableI2C_CONF IGI2C_CONFIGConfigures I2C SDA IO 0: Open-drain mode 1: Tri-state mode3D GPIO_CON1GPIO control register 111E D I A T C O NF N T I A L O R a o l i f e n g @n z o t e c . U S E ONBit(s) Mnemonic Name Description7 SCL_OUT SCL_OUT SDL_OUT GPIO mode 6 SCL_OE SCL_OE SDL_OE GPIO mode 5:4SCL_MOD ESCL_MODE00: GPIO_MODE 01: I2C10: Reserved 11: Reserved3 SDA_OUT SDA_OUT SDA_OUT GPIO mode 2SDA_OE SDA_OESDA_OE GPIO mode 1:0SDA_MO DESDA_MODE00: GPIO_MODE 01: I2C10: Reserved 11: Reserved3E GPIO_CON2GPIO control register 209Bit(s) Mnemonic Name Description3 INT_OUT INT_OUT INT_OUT GPIO mode 2INT_OE INT_OEINT_OE GPIO mode 1:0 INT_M OD EINT_MODE00: GPIO_MODE 01: EINT10: Debug monitor 11: Reserved44 INT_CON0INT control register 0FFBit(s) Mnemonic Name Description3RG_INT_E N_THERM AL_REG_OUT RG_INT_EN_TH ERMAL_REG_O UTE nables interrupt of THERMAL_REG_OUT 0: Does not issue interrupt 1: Issue interrupt2RG_INT_E N_THERM AL_REG_I NRG_INT_EN_TH ERMAL_REG_INE nables interrupt of THERMAL_REG_IN 0: Does not issue interrupt 1: Issue interrupt1RG_INT_E N_THERM AL_SDRG_INT_EN_TH ERMAL_SDE nables interrupt of THERMAL_SD 0: Does not issue interruptM E D E K C O N E N T I A L O R z h a o l i f e v a n z o t e o m U S E ONBit(s)Mnemonic NameDescription45INT_CON0_SETINT control register 0 SETFFBit(s) Mnemonic Name Description3RG_INT_E N_THERM AL_REG_OUT_SE T RG_INT_EN_TH ERMAL_REG_O UT_SET1'b0: Does not set 1'b1: Set2RG_INT_E N_THERM AL_REG_I N_SE T RG_INT_EN_TH ERMAL_REG_IN _SET1'b0: Does not set 1'b1: Set1RG_INT_E N_THERM AL_SD_S E TRG_INT_EN_TH ERMAL_SD_SET 1'b0: Does not set 1'b1: Set46 INT_CON0_CLRINT control register 0 CLRFFBit(s) Mnemonic Name Description3RG_INT_E N_THERM AL_REG_OUT_CLR RG_INT_EN_TH ERMAL_REG_O UT_CLR1'b0: Does not clear 1'b1: Clear2RG_INT_E N_THERM AL_REG_I N_CLR RG_INT_EN_TH ERMAL_REG_IN _CLR1'b0: Does not clear 1'b1: Clear1RG_INT_E N_THERM AL_SD_C LRRG_INT_EN_TH ERMAL_SD_CLR 1'b0: Does not clear 1'b1: ClearM E D I A K C O N F I D E L O R z h a o l i f e n g n z o t e c .c o m ON47INT_CON1INT control register 1FFBit(s) Mnemonic Name Description7RG_INT_E N_FLASH _VLED_O PEN RG_INT_EN_FLA SH_VLED_OPENE nables interrupt of flash open 0: Does not issue interrupt 1: Issue interrupt6RG_INT_E N_FLASH _VLED_S HORTRG_INT_EN_FLA SH_VLED_SHOR TE nables interrupt of flash short 0: Does not issue interrupt 1: Issue interrupt5RG_INT_E N_FLASH _EN_TIM E OUTRG_INT_EN_FLA SH_EN_TIMEOU TE nables interrupt of flash timeout 0: Does not issue interrupt 1: Issue interrupt4RG_INT_E N_BUCK_THERMAL RG_INT_EN_BU CK_THERMA L E nables interrupt of BUCK_THERMAL 0: Does not issue interrupt 1: Issue interrupt3RG_INT_E N_BUCK_VRF18_O CRG_INT_EN_BU CK_V RF18_OCE nables interrupt of VRF18 OC 0: Does not issue interrupt 1: Issue interrupt2RG_INT_E N_BUCK_VME M_O CRG_INT_EN_BU CK_V MEM_OCE nables interrupt of VME M OC 0: Does not issue interrupt 1: Issue interrupt1RG_INT_E N_BUCK_VCORE _O CRG_INT_EN_BU CK_V CORE_OCE nables interrupt of VCORE OC 0: Does not issue interrupt 1: Issue interruptRG_INT_E N_CHRW DT_FLAGRG_INT_EN_CH RWDT_FLAGE nables interrupt of CHRWDT_FLAG 0: Does not issue interrupt 1: Issue interrupt48 INT_CON1_SETINT control register 1 SETFFBit(s) Mnemonic Name DescriptionD I A TE K C O NF I D E N T I O R z i f e n g @ v a n z o t e c .c o m U SBit(s) Mnemonic Name Description 7RG_INT_E N_FLASH _VLED_O PEN_SE T RG_INT_EN_FLA SH_VLED_OPEN _SET1'b0: Does not set 1'b1: Set6RG_INT_E N_FLASH _VLED_S HORT_SE TRG_INT_EN_FLA SH_VLED_SHOR T_SET1'b0: Does not set 1'b1: Set5RG_INT_E N_FLASH _EN_TIM E OUT_SE T RG_INT_EN_FLA SH_EN_TIMEOU T_SET1'b0: Does not set 1'b1: Set4RG_INT_E N_BUCK_THERMAL _SE T RG_INT_EN_BU CK_THERMA L_S ET1'b0: Does not set 1'b1: Set3RG_INT_E N_BUCK_VRF18_O C_SE T RG_INT_EN_BU CK_V RF18_OC_SET1'b0: Does not set 1'b1: Set2RG_INT_E N_BUCK_VME M_O C_SE T RG_INT_EN_BU CK_V MEM_OC_SET1'b0: Does not set 1'b1: Set1RG_INT_E N_BUCK_VCORE _O C_SE T RG_INT_EN_BU CK_V CORE_OC _SET1'b0: Does not set 1'b1: SetRG_INT_E N_CHRW DT_FLAG _SE TRG_INT_EN_CH RWDT_FLAG_SE T1'b0: Does not set 1'b1: Set49 INT_CON1_CLRINT control register 1 CLRFFBit(s) Mnemonic Name Description7RG_INT_E N_FLASH _VLED_O PEN_CLR RG_INT_EN_FLA SH_VLED_OPEN _CLR1'b0: Does not clear 1'b1: Clear6RG_INT_E N_FLASH _VLED_S HORT_CLRG_INT_EN_FLA SH_VLED_SHOR T_CLR1'b0: Does not clear 1'b1: ClearM E T E K C O N F I D E N T I A L O R z h a o l g @ v a n z o t e c .c o m U S E ONBit(s) Mnemonic Name Description 5RG_INT_E N_FLASH _EN_TIM E OUT_CLR RG_INT_EN_FLA SH_EN_TIMEOU T_CLR1'b0: Does not clear 1'b1: Clear4RG_INT_E N_BUCK_THERMAL _CLR RG_INT_EN_BU CK_THERMA L_C LR1'b0: Does not clear 1'b1: Clear3RG_INT_E N_BUCK_VRF18_O C_CLR RG_INT_EN_BU CK_V RF18_OC_CLR1'b0: Does not clear 1'b1: Clear2RG_INT_E N_BUCK_VME M_O C_CLR RG_INT_EN_BU CK_V MEM_OC_CLR1'b0: Does not clear 1'b1: Clear1RG_INT_E N_BUCK_VCORE _O C_CLR RG_INT_EN_BU CK_V CORE_OC _CLR1'b0: Does not clear 1'b1: ClearRG_INT_E N_CHRW DT_FLAG _CLRRG_INT_EN_CH RWDT_FLAG_CL R1'b0: Does not clear 1'b1: Clear4A INT_CON2INT control register 203Bit(s) Mnemonic Name Description1RG_INT_E N_CHR_P LUG_IN_F LASHRG_INT_EN_CH R_PLUG_IN_FLA SH0: Does not issue interrupt 1: Issue interrupt4B INT_CON2_SETINT control register 2 SET03E D I A T C O NF I D E N T I A L O o l i f e n g @n z o t e c .c o m U S E ONBit(s)Mnemonic Name Description 1RG_INT_E N_CHR_P LUG_IN_F LASH_SE TRG_INT_EN_CH R_PLUG_IN_FLA SH_SET1'b0: Does not set 1'b1: Set4C INT_CON2_CLRINT control register 2 CLR03Bit(s) Mnemonic Name Description1RG_INT_E N_CHR_P LUG_IN_F LASH_CL RRG_INT_EN_CH R_PLUG_IN_FLA SH_CLR1'b0: Does not clear 1'b1: Clear4D CHRWDT_CON0CHRWDT control register 00DBit(s) Mnemonic Name Description7RG_CHR WDT_WR RG_CHRWDT_W RClears timer flag3:1RG_CHR WDT_TDRG_CHRWDT_T DTime-out interval of w atchdog timer 000: 4 sec 001: 32 sec 010: 60 sec 011: 256 sec 100: 480 sec 101: 1,024 sec 110: 1,800 sec 111: 3,000 secRG_CHR WDT_EN RG_CHRWDT_E NE nables w atchdog timer4E CHRWDT_STATUS0CHRWDT status register 000M E D I A T E O N F I D I A L O z h a o l i f e n g @z o t e c .c S E ONBit(s) Mnemonic Name DescriptionRG_CHR WDT_FLA GRG_CHRWDT_F LAGWatchdog timer flag4F INT_STATUS0INT status register 000Bit(s) Mnemonic Name Description7RG_INT_S TATUS_O TG_DRVC DT_SHOR TRG_INT_ST ATUS _OTG_DRV CDT_SHORT0: No interrupt issued 1: Interrupt issued6RG_INT_S TATUS_O TG_CHRI N_SHORT RG_INT_ST ATUS _OTG_CHRIN_S HORT0: No interrupt issued 1: Interrupt issued5RG_INT_S TATUS_O TG_THER MAL RG_INT_ST ATUS _OTG_THERMA L0: No interrupt issued 1: Interrupt issued4RG_INT_S TATUS_O TG_OCRG_INT_ST ATUS _OTG_OC 0: No interrupt issued 1: Interrupt issued 3RG_INT_S TATUS_T HERMAL_REG_OUT RG_INT_ST ATUS _THERMAL_RE G_OUT0: No interrupt issued 1: Interrupt issued2RG_INT_S TATUS_T HERMAL_REG_IN RG_INT_ST ATUS _THERMAL_RE G_IN0: No interrupt issued 1: Interrupt issued1RG_INT_S TATUS_T HERMAL_SDRG_INT_ST ATUS _THERMAL_SD0: No interrupt issued 1: Interrupt issuedM E D I A T E K C O N N T I A O R z h a o l i f e n g @ v a n z o t e U S E50INT_STATUS1INT status register 100Bit(s) Mnemonic Name Description7RG_INT_S TATUS_F LASH_VL ED_OPEN RG_INT_ST ATUS _FLASH_VLED_OPEN0: No interrupt issued 1: Interrupt issued6RG_INT_S TATUS_F LASH_VL ED_SHOR TRG_INT_ST ATUS _FLASH_VLED_SHORT0: No interrupt issued 1: Interrupt issued5RG_INT_S TATUS_F LASH_EN _TIMEOU TRG_INT_ST ATUS _FLASH_EN_TIM EOUT0: No interrupt issued 1: Interrupt issued4RG_INT_S TATUS_B UCK_THE RMAL RG_INT_ST ATUS _BUCK_THERM AL0: No interrupt issued 1: Interrupt issued3RG_INT_S TATUS_B UCK_VRF 18_OCRG_INT_ST ATUS _BUCK_VRF18_OC0: No interrupt issued 1: Interrupt issued2RG_INT_S TATUS_B UCK_VME M_OC RG_INT_ST ATUS _BUCK_V MEM_OC0: No interrupt issued 1: Interrupt issued1RG_INT_S TATUS_B UCK_VCO RE_OCRG_INT_ST ATUS _BUCK_VCORE_OC0: No interrupt issued 1: Interrupt issuedRG_INT_S TATUS_C HRWDT_F LAGRG_INT_ST ATUS _CHRWDT_FLA G0: No interrupt issued 1: Interrupt issued51 INT_STATUS2INT status register 200E D I A T E K C O NF I D E N T I O o l i f e n g @ v a n z o t e c .c o m U SBit(s)Mnemonic Name Description1RG_INT_S TATUS_C HR_PLUG _IN_FLAS HRG_INT_ST ATUS _CHR_PLUG_IN _FLASH0: No interrupt issued 1: Interrupt issued68 VCORE_CON17VCORE control register 1720Bit(s) Mnemonic Name Description4VCORE _E N_CTRL VCORE_EN_CT RLE nables control 0: SW control 1: HW control 3 QI_VCOR E_EN QI_V CORE _ENE nabling signal 2 QI_VCOR E_STBQI_V CORE _STB Soft start1VCORE _E NVCORE_EN0: E nable VCORE 1: Disable V CORE6B VCORE_CON20VCORE control register 2048Bit(s) Mnemonic Name Description6:0VCORE _V OSELVCORE_V OSELSelects VOUT in register mode 0000000: 0.70000V 0000001: 0.70625V 0000010: 0.71250V 0000011: 0.71875V 0000100: 0.72500V 0000101: 0.73125V 0000110: 0.73750V 0000111: 0.74375V 0001000: 0.75000V 0001001: 0.75625V 0001010: 0.76250V 0001011: 0.76875V 0001100: 0.77500V 0001101: 0.78125V 0001110: 0.78750V 0001111: 0.79375VM E D I A T K C O N F I D T I A L O R z h a o l i f e n g a n z o t e c .c o S E ONBit(s)Mnemonic NameDescription0010001: 0.80625V 0010010: 0.81250V 0010011: 0.81875V 0010100: 0.82500V 0010101: 0.83125V 0010110: 0.83750V 0010111: 0.84375V 0011000: 0.85000V 0011001: 0.85625V 0011010: 0.86250V 0011011: 0.86875V 0011100: 0.87500V 0011101: 0.88125V 0011110: 0.88750V 0011111: 0.89375V 0100000: 0.90000V 0100001: 0.90625V 0100010: 0.91250V 0100011: 0.91875V 0100100: 0.92500V 0100101: 0.93125V 0100110: 0.93750V 0100111: 0.94375V 0101000: 0.95000V 0101001: 0.95625V 0101010: 0.96250V 0101011: 0.96875V 0101100: 0.97500V 0101101: 0.98125V 0101110: 0.98750V 0101111: 0.99375V 0110000: 1.00000V 0110001: 1.00625V 0110010: 1.01250V 0110011: 1.01875V 0110100: 1.02500V 0110101: 1.03125V 0110110: 1.03750V 0110111: 1.04375V 0111000: 1.05000V 0111001: 1.05625V 0111010: 1.06250V 0111011: 1.06875V 0111100: 1.07500V 0111101: 1.08125V 0111110: 1.08750V 0111111: 1.09375V 1000000: 1.10000V 1000001: 1.10625V 1000010: 1.11250V 1000011: 1.11875V 1000100: 1.12500V 1000101: 1.13125V 1000110: 1.13750V 1000111: 1.14375V 1001000: 1.15000V 1001001: 1.15625V 1001010: 1.16250VM E D I A T E K C O N F I D E N T I A L O R z h a o l i f e n g @ v a n z o t e c .c o m U S E ONBit(s)Mnemonic NameDescription1001100: 1.17500V 1001101: 1.18125V 1001110: 1.18750V 1001111: 1.19375V 1010000: 1.20000V 1010001: 1.20625V 1010010: 1.21250V 1010011: 1.21875V 1010100: 1.22500V 1010101: 1.23125V 1010110: 1.23750V 1010111: 1.24375V 1011000: 1.25000V 1011001: 1.25625V 1011010: 1.26250V 1011011: 1.26875V 1011100: 1.27500V 1011101: 1.28125V 1011110: 1.28750V 1011111: 1.29375V 1100000: 1.30000V 1100001: 1.30625V 1100010: 1.31250V 1100011: 1.31875V 1100100: 1.32500V 1100101: 1.33125V 1100110: 1.33750V 1100111: 1.34375V 1101000: 1.35000V 1101001: 1.35625V 1101010: 1.36250V 1101011: 1.36875V 1101100: 1.37500V 1101101: 1.38125V 1101110: 1.38750V 1101111: 1.39375V 1110000: 1.40000V 1110001: 1.40625V 1110010: 1.41250V 1110011: 1.41875V 1110100: 1.42500V 1110101: 1.43125V 1110110: 1.43750V 1110111: 1.44375V 1111000: 1.45000V 1111001: 1.45625V 1111010: 1.46250V 1111011: 1.46875V 1111100: 1.47500V 1111101: 1.48125V 1111110: 1.48750V 1111111: 1.49375V6CVCORE_CON21VCORE control register 2148M E D I A T E K C O N F I D E N T I A L O z h a o l i f e n g @ v a n z o t e c .c o m U S E ONBit(s)Mnemonic NameDescription6:0VCORE _V OSEL_ONVCORE_V OSEL_ONSelects VOUT in normal mode 0000000: 0.70000V 0000001: 0.70625V 0000010: 0.71250V 0000011: 0.71875V 0000100: 0.72500V 0000101: 0.73125V 0000110: 0.73750V 0000111: 0.74375V 0001000: 0.75000V 0001001: 0.75625V 0001010: 0.76250V 0001011: 0.76875V 0001100: 0.77500V 0001101: 0.78125V 0001110: 0.78750V 0001111: 0.79375V 0010000: 0.80000V 0010001: 0.80625V 0010010: 0.81250V 0010011: 0.81875V 0010100: 0.82500V 0010101: 0.83125V 0010110: 0.83750V 0010111: 0.84375V 0011000: 0.85000V 0011001: 0.85625V 0011010: 0.86250V 0011011: 0.86875V 0011100: 0.87500V 0011101: 0.88125V 0011110: 0.88750V 0011111: 0.89375V 0100000: 0.90000V 0100001: 0.90625V 0100010: 0.91250V 0100011: 0.91875V 0100100: 0.92500V 0100101: 0.93125V 0100110: 0.93750V 0100111: 0.94375V 0101000: 0.95000V 0101001: 0.95625V 0101010: 0.96250V 0101011: 0.96875V 0101100: 0.97500V 0101101: 0.98125V 0101110: 0.98750V 0101111: 0.99375V 0110000: 1.00000V 0110001: 1.00625V 0110010: 1.01250V 0110011: 1.01875V 0110100: 1.02500V 0110101: 1.03125VM E D I A T E K C O N F I D E N T I A L OR z h a o l i f e n g @ v a n z o t e c .c o m U S E O。
STK600 32 kHz 振荡器修复指南说明书
Fix for STK600 32 kHz OscillatorSome STK ®600 manufactured before July 10’th 2008 has a 32 kHz oscillatorrunning on to high frequency. STK600’s manufactured July 10’th or later does not have this problem.The manufacturing date for the board can be found on the sticker on the bottom side of the board.Figure 1-1. STK600 overview.8-bitMicrocontrollersUser GuideRev. 8177A-AVR-07/082STK6008177A-AVR-07/08Figure 1-2. Manufacturing date.The oscillator can be fixed easily by replacing the circled capacitor, with a 220pF ceramic capacitor. (0603 size), see Figure 1-2. It is also possible to leave the existing capacitor mounted and just solder a new 220pF capacitor on top, either 0603 size SMT or other ceramic type that you can make fit. Figure 1-3. Replace the following capacitor.8177A-AVR-07/08He a dqu a rters Intern a tion a lAtmel Corporation2325 Orchard Parkway San Jose, CA 95131 USATel: 1(408) 441-0311 Fax: 1(408) 487-2600Atmel Asia Room 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778 Fax: (852) 2722-1369Product ContactAtmel Europe Le Krebs8, Rue Jean-Pierre Timbaud BP 30978054 Saint-Quentin-en-Yvelines Cedex FranceTel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11Atmel Japan9F, Tonetsu Shinkawa Bldg. 1-24-8 ShinkawaChuo-ku, Tokyo 104-0033 JapanTel: (81) 3-3523-3551 Fax: (81) 3-3523-7581Web SiteTechnical Support *************Sales Contact/contactsLiterature Request/literatureDisclaimer: The information in this document is provided in connection with Atmel products. N o license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.© 2008 Atmel Corporation. All rights reserved . Atmel®, logo and combinations thereof, AVR®, STK® and others, are the registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.。
Datasheet MLX90614 中文 数据手册 rev008
10-位 PWM 输出模式是连续输出所测物体温度的标准配置，测量物体的温度范围为-20…120 °C，分辨 率为 0.14 °C。PWM 通过修改 EEPROM 内 2 个单元的值，实际上可以根据需求调整至任何温度范围，而这对 出厂校准结果并无影响。
传感器的测量结果均出厂校准化，数据接口为数字式的 PWM 和 SMBus(System Management Bus) 输出。
作为标准，PWM 为 10 位，且配置为-20˚C 至 120 ˚C 内，分辨率为 0.14 ˚C 的连续输出。
传感器出厂默认，上电复位时为 SMBus 通信。
3901090614 Rev 008
PWM 引脚也可配置为热继电器(输入是 To)，这样可以实现简单且性价比高的恒温控制器或温度报警(冰 点/沸点)应用，其中的温度临界值是用户可编程的。在 SMBus 系统里，这个功能可以作为处理器的中断信号， 以此触发读取主线上从动器的值，并确定精度条件。
传感器有两种供电电压选择：5V 或 3V(电池供电)。其中，5V 也可简便的从更高供电电压(例如 8 至 16V)上通过外接元件调制。(具体请参考“应用信息”)
MLX90614 connection to SMBus
图 1: 典型应用电路
2 概述
MLX90614 是一款用于非接触式的红外温度传感器，集成 了红外探测热电堆芯片与信号处理专用集成芯片，全部封装 在 TO-39。
低噪声放大器、17 位 ADC 和强大的 DSP 处理单元的全 集成，使传感器实现了高精度，高分辨率的测量。
西门子S7-300数字输出SM322数据表说明书
Changes preserved © Copyright Siemens AG
Hale Waihona Puke Yes 4 Yes; Optocoupler
75 V DC/60 V AC
6ES7322-1BF01-0AA0 Page 2/3
18.02.2016
Changes preserved © Copyright Siemens AG
Isolation Isolation tested with
Connection method required front connector
Data sheet
6ES7322-1BF01-0AA0
SIMATIC S7-300, DIGITAL OUTPUT SM 322, OPTICALLY ISOLATED, 8 DO, 24V DC, 2A, 1 X 20 PIN
Supply voltage Load voltage L+ ● Rated value (DC) ● permissible range, lower limit (DC) ● permissible range, upper limit (DC)
Permissible potential difference between different circuits
4 kΩ
L+ (-0.8 V)
2A 5 mA 0.5 mA
100 Hz 0.5 Hz 10 Hz
4A 4A
4A
1 000 m 600 m
No
No
No No No No
No No Yes; per channel
Potential separation Potential separation digital outputs ● between the channels ● between the channels, in groups of ● between the channels and backplane bus
MediaTek_MT3332_GPS_Data_Sheet_v1_0
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 2 of 24
MT3332 GNSS Host-Based Solution Technical Brief
Lists of Figures
Figure 1 Pin assignment (top view) ..............................................................................................................7 Figure 2 Timing diagram of RS-232 interface ...........................................................................................18 Figure 3 Timing diagram of SPI interface .................................................................................................. 19 Figure 4 Timing diagram of HOST I2C interface ..................................................................................... 20 Figure 5 Packaging dimensions diagram .................................................................................................. 22 Figure 6 Packaging dimensions tables ...................................................................................................... 23
STK8312 REV 0.9.9.1
STK8312Digital Output 3-axis MEMS Accelerometer Preliminary DatasheetVersion - 0.9.9 2012/12/13STK8312 REV 0.9.91.DescriptionOVERVIEWFeatureLow Voltage Operation: – Analog Voltage: 2.4 V – 3.6 V – Digital Voltage: 1.7V – 3.6V ±1.5g/±6g/±16g dynamically selectable full-scale I2C digital output interface and 1 interrupt pin 6/8 bit data output 10000 g high shock survivability 3mm x 3mm x 0.85mm QFN Package Configurable Samples per second from 3.125 to 400 samples a second. Tilt Orientation Detection for Portrait/Landscape Capability Shake Detection Tap/Double Tap Detection Free Fall Detection RoHS Compliant Halogen Free Environmentally Preferred ProductThe STK8312 is a ±1.5g/±6g/±16g, 3-axis linear accelerometer, with digital output (I2C). It is a very low power, low profile capacitive MEMS sensor featuring, compensation for 0g offset and gain errors, and conversion to 6/8-bit digital values at a user configurable samples per second. The device can be used for sensor data changes and orientation through an interrupt pin (/INT). The STK8312 is available in a small 3mm x 3mm x 0.85mm QFN package and it is guaranteed to operate over an extended temperature range from -40 ° C to +85 ° C.ApplicationsFree-fall detection Intelligent power saving for handheld devices Pedometer Display orientation Gaming and virtual reality input devices Impact recognition and logging Vibration monitoring and compensation1@copyright 2013 Sensortek Technology Corp.STK8312 REV 0.9.92.Pin# 1 2 3 4 5 6 7 8 9 10 Name NC NC AVDD AVSS /INT SCL SDA DVSS DVDD NC NC NCPIN DESCRIPTIONFunctionAnalog Power Device Ground Interrupt/Data Ready I2C Serial Clock I2C Serial Data (Open-Drain) Digital I/O Ground Digital Power NCTop ViewNC NC AVDD AVSS /INT1 2 3 4 510 9 8 7 6NC DVDD DVSS SDA SCL2@copyright 2013 Sensortek Technology Corp.STK8312 REV 0.9.93.FUNCTION BLOCK3@copyright 2013 Sensortek Technology Corp.STK8312 REV 0.9.94.ELECTRICAL SPECIFICATIONSTA = 25° C, VS = 2.8 V, VDD I/O = 2.8 V, acceleration = 0 g, CS = CI/O = 10 µF and 0.1 µFParameter POWER SUPPLY Operating Voltage Range (VS) Interface Voltage Range (VDD I/O) Current consumption in active mode Current consumption in standby mode Digital high level input voltage (VIH) Digital low level input voltage (VIL) High level output voltage (VOH) Low level output voltage (VOL)1 1Test ConditionsMinTypMaxUnit2.4 1.72.83.6 3.6V V µA184 1 0.7 x VDD I/O 0.3 x VDD I/O 0.8 x VDD I/O 0.2 x VDD I/O Each axis in active mode 3.125 ODR/2 400µA V V V VOUTPUT DATA RATE AND BANDWIDTH Output data rate (ODR) Bandwidth (BW)1. IOL = 10mA, IOH = -4mAHz Hz4@copyright 2013 Sensortek Technology Corp.STK8312 REV 0.9.95.MECHANICAL SPECIFICATIONSTA = 25° C, VS = 2.8 V, VDD I/O = 2.8 V, acceleration = 0 g, CS = CI/O = 10 µF and 0.1 µFParameter SENSOR INPUT Measurement Range Nonlinearity Cross-Axis Sensitivity OUTPUT RESOLUTION ±1.5 g Range ±6 g Range ±16 g Range SENSITIVITY Sensitivity at XOUT, YOUT, ZOUT Each axis Full resolution Full resolution Full resolution Each axis ±1.5g, 6-bit resolution ±6g, 8-bit resolution ±16g, 8-bit resolution Sensitivity Change Due to Temperature1Test Conditions Each axis User selectable Percentage of full scaleMinTypMaxUnit±1.5/±6/±16 ±0.28 ±1g % %6 8 8Bits Bits Bits19.62 19.62 721.33 21.33 8 0.02 0.0223.04 23.04 9LSB/g LSB/g LSB/g %/° C %/° CX-, Y-Axes Z-Axis0 g OFFSETEach axis ±50 ±1.5g, 6-bit resolution ODR = 100Hz ±16g, 8-bit resolution ODR = 100Hz mg0 g Output for XOUT, YOUT, ZOUT NOISE X-, Y-Axes and Z-Axis X-, Y-Axes and Z-Axis±1 ±1LSB LSB1. These parameters are tested in production at final test, and could slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress.5@copyright 2013 Sensortek Technology Corp.STK8312 REV 0.9.96.Symbol AVDD DVDD Vin AUNP TOP TSTG ESDABSOLUTE MAXIMUM RATINGSRatings Analog Supply voltage Digital Supply voltage Input voltage on any control pin Acceleration (any axis, unpowered) Operating temperature range Storage temperature range Electrostatic discharge protection Maximum value -0.3 to 3.6 -0.3 to 3.6 -0.3 to 3.6 10000 -40 to +85 -40 to +125 4 (HBM) 500 (CDM) 200 (MM) 100 (Latch Up) Unit V V V g °C °C kV V V mA7.DIGITAL INTERFACEBoth I2C and SPI digital interface are available in STK8BA50. In both cases, the STK8BA50 operates as a slave device. PS (protocol select) pin state is used to select the operation interface. The I2C mode is enabled if the PS pin is tied high to VDDIO. and the SPI mode is enabled when the PS pin is tied to low.7.1I2 CAll registers in STK8312 can be accessed via the I2C bus. All operations can be controlled by the related registers. There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to DVDD through a pull-up external resistor. To reset the STK8312 without having to reset the entire I2C bus, an explicit reset command is provided. If register 0x20 is set to 0x00, STK8312 will reset all register and enter into standby mode. To reset STK8312 after power on is recommended. In following timing chart, it is STK8312 I2C command format description for reading and writing operation between the host and STK8312. Slave Address STK8312 provides the fixed slave address of 0x3D using 7-bit addressing protocol. In following table, it describes the command setting.Slave Address (7-bit) 0x3D (followed by the R/ W bit) R/W Command Bit 0 1 OPERATION Write Data to STK8312 Read Data form STK83126@copyright 2013 Sensortek Technology Corp.STK8312 REV 0.9.9Characteristics of the I2C TimingSymbol fSCLK tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tr tf tSUSTO tBUF SCL clock frequency Hold time after (repeated) start condition. After this period, the first clock is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition-1ParameterStandard Mode Min. 10 4.0 4.7 4.0 4.7 0 250 — — 4.0 4.7 Max. 100 — — — — — — 1000 300 — —Fast Mode Min. 10 0.6 1.3 0.6 0.6 0 100 — — 0.6 1.3 Max. 400 — — — — — — 300 300 — —Unit KHz µs µs µs µs ns ns ns ns µs µsNote 1: fSCLK is the (tSCLK) .Timing Chart of the I2CWrite CommandRead Data7@copyright 2013 Sensortek Technology Corp.STK8312 REV 0.9.9Sequential Read Data8.8.1PRINPICLE OF OPERATIONMode of OperationThe sensor has three power modes: Off Mode, Standby Mode, and Active Mode to offer the customer different power consumption options. Only one mode could be acceptable at a time. The Off Mode offers the lowest power consumption and can only be reached by powering down the analog supply. In this mode, there is no analog supply but digital supply. Therefore some basic register could be accessed by I2C, but no data appear at XOUT, YOUT, ZOUT register. The Standby Mode is ideal for battery operated products. When Standby Mode is active the device outputs are turned off providing a significant reduction in operating current. When the device is in Standby Mode the current will be reduced to less than 1 µA. Standby Mode is entered as soon as both analog and digital power supplies are up. In this mode, the device can read and write to the registers with I2C, but no new measurements can be taken. The mode of the device is controlled through the MODE (0x07) control register by accessing the mode bit in the Mode register. During the Active Mode, continuous measurement on all three axes is enabled. The user can configure the samples per second to any of the following: 3.125 samples/second, 6.25 samples/second, 12.5 samples/second, 25 samples/second, 50 samples/second, 100 samples/second, 200 samples/second, and 400 samples/second. Depending on the samples per second selected the power consumption will vary.Measurement Mode Off Mode Standby Mode I²C Bus STK8312 will respond to I2C bus STK8312 will respond to I2C bus STK8312 will respond to I2C bus DVDD ON ON AVDD OFF ON Function Only I2C available, but no data output. Functions could not be normally set at this mode. STK8312 is powered up in both supplies, so registers can be accessed normally to set STK8312 to Active Mode when desired. STK8312’s sensor measurement system is idle. STK8312 is able to operate sensor measurement system at user programmable samples per second and run all of the digital analysis functions. Tap detection operates in Active Mode.Active ModeONON8@copyright 2013 Sensortek Technology Corp.STK8312 REV 0.9.9DVDD ON AVDD ONDVDD ONOFFAVDD OFF AVDD OFF MODE bit = 1StandbyMODE bit = 0Active Mode8.2Status and Interrupt Event DetectionThe Sensor employs both analog and digital filtering to ensure low noise and accurate output when using the part for Shake, Double-Tap, Tap, Free-Fall, or Orientation Detection. During Active Mode, the data is filtered and stored for each of the 3 axes at the specified following measurement intervals: 3.125 sample/second, 6.25 sample/second, 12.5 sample/second, 25 sample/second, 50 sample/second, 100 sample/second, 200 sample/second, 400 sample/second or indicated in AMSR [2:0]. The measurement data is stored in the XOUT (0x00), YOUT (0x01), and ZOUT (0x02) registers and is used to update the Statue: Shake, Alert, Tap, PoLa[2:0] (updates Up, Down, Left, and Right position), BaFro[1:0] (updates Back and Front position) in the TILT (0x03) register, and FFAL, DTap in the SRST (0x04) register. The Shake status always responds to any measurement data over shake threshold value (STH[2:0] in the STH (0x13) register), and PoLa[2:0], and BaFro[1:0] status respond to orientation. However, the Tap and DTap status will respond only when ZDA, YDA, or XDA in PDET (0x09) register are enabled. The FFAL Status and Interrupt are controlled by FFINT in CTRL (0x14). If FFINT is enabled, the FFAL status and interrupt will simultaneously occur. The customer can configure the part by enabling a number of user desired interrupts in the INTSU (0x06) and CTRL (0x14) register. Once the interrupts are enabled a change in filtered readings will cause an interrupt to occur depending on the output. Interrupt Event SummaryInterrupt Event Orientation Shake Tap Double Tap X, Y, Z Data Update Free Fall Settings When FBINT, PLINT = 1 When SHINTX, SHINTY, SHINTZ = 1 When PDINT = 1 When DPINT = 1 When GINT = 1 When FFINT = 1Status SummaryStatus PoLa[2:0], BaFro[1:0] Shake Tap, DTap FFAL Settings Always available Always available When enable ZDA, YDA, or XDA When FFINT = 1NOTE: Sensor Measurements are NOT taken in Standby Mode.9@copyright 2013 Sensortek Technology Corp.9. REGISTER DEFINATIONAddress Name Definition Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 $00XOUT6/8-bit output value X Rev/XOUT[7]Alert/XOUT[6]XOUT[5]XOUT[4]XOUT[3]XOUT[2]XOUT[1]XOUT[0] $01YOUT6/8-bit output value Y Rev/YOUT[7]Alert/YOUT[6]YOUT[5]YOUT[4]YOUT[3]YOUT[2]YOUT[1]YOUT[0] $02ZOUT6/8-bit output value Z Rev/ZOUT[7]Alert/ZOUT[6]ZOUT[5]ZOUT[4]ZOUT[3]ZOUT[2]ZOUT[1]ZOUT[0] $03TILT Tilt Status Shake Alert Tap PoLa[2]PoLa[1]PoLa[0]BaFro[1]BaFro[0] $04SRST Sampling Rate Status0000FFAL DTap Reserved AMSRS $05 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $06 INTSU Interrupt Setup SHINTX SHINTY SHINTZ GINT Reserved PDINT PLINT FBINT $07 MODE Mode IAH IPP Reserved Reserved Reserved TON Reserved MODE$08 SR Portrait/Landscapesamplesper seconds andDebounceFilterFILT[2] FILT[1] FILT[0]Reserved Reserved AMSR[2]AMSR[1]AMSR[0]$09 PDET Tap Detection ZDA YDA XDA PDTH[4] PDTH[3] PDTH[2] PDTH[1] PDTH[0] $0A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $0B Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $0C OFSX X-Axis offset OFSX[7] OFSX[6] OFSX[5] OFSX[4] OFSX[3] OFSX[2] OFSX[1] OFSX[0] $0D OFSY Y-Axis offset OFSY[7] OFSY[6] OFSY[5] OFSY[4] OFSY[3] OFSY[2] OFSY[1] OFSY[0] $0E OFSZ Z-Axis offset OFSZ[7] OFSZ[6] OFSZ[5] OFSZ[4] OFSZ[3] OFSZ[2] OFSZ[1] OFSZ[0] $0F PLAT Tap Latency PLAT[7] PLAT[6] PLAT[5] PLAT[4] PLAT[3] PLAT[2] PLAT[1] PLAT[0] $10 PWIN Tap Window PWIN[7] PWIN[6] PWIN[5] PWIN[4] PWIN[3] PWIN[2] PWIN[1] PWIN[0] $11 FTH Free-Fall Threshold FTH[7] FTH[6] FTH[5] FTH[4] FTH[3] FTH[2] FTH[1] FTH[0] $12 FTM Free-Fall Time FTM[7] FTM[6] FTM[5] FTM[4] FTM[3] FTM[2] FTM[1] FTM[0] $13 STH Shake Threshold RNG[1] RNG[0] - - - STH[2] STH[1] STH[0] $14 CTRL Control Register - - AOI - FFINT DPINT $20 SWRST Software Reset SWRST[7] SWRST[6] SWRST[5] SWRST[4] SWRST[3] SWRST[2] SWRST[1] SWRST[0] NOTE: To write to the registers the MODE bit in the MODE (0x07) register must be set to 0, placing the device in Standby Mode.$00: 6/8-bits output value X (Read Only)XOUT — X OutputD7 D6 D5 D4 D3 D2 D1 D0 Rev/XOUT[7] Alert/XOUT[6] XOUT[5] XOUT[4] XOUT[3] XOUT[2] XOUT[1] XOUT[0]0 0 0 0 0 0 0 0If the RNG[1:0] of STH register is clear, then D0~D5 is signed byte 6-bit 2’s complement data with allowable range of +31 to -32. XOUT[5] is 0 if the g direction is positive, 1 if the g direction is negative. D6 is used as alert bit. If the Alert bit is set, the register was read at the same time as the device was attempting to update the contents. The register must be read again. D7 is a reserved bit.If the RNG[1:0] of STH register is set, then D0~D7 is signed byte 8-bit 2’s complement data with allowable range of +127 to -128. XOUT[7] is 0 if the g direction is positive. 1 if the g direction is negative.$01: 6/8-bits output value Y (Read Only)YOUT — Y OutputD7 D6 D5 D4 D3 D2 D1 D0 Rev/YOUT[7] Alert/YOUT[6] YOUT[5] YOUT[4] YOUT[3] YOUT[2] YOUT[1] YOUT[0]0 0 0 0 0 0 0 0If the RNG[1:0] of STH register is clear, then D0~D5 is signed byte 6-bit 2’s complement data with allowable range of +31 to -32. YOUT[5] is 0 if the g direction is positive, 1 if the g direction is negative. D6 is used as alert bit. If the Alert bit is set, the register was read at the same time as the device was attempting to update the contents. The register must be read again. D7 is a reserved bit.If the RNG[1:0] of STH register is set, then D0~D7 is signed byte 8-bit 2’s complement data with allowable range of +127 to -128. YOUT[7] is 0 if the g direction is positive. 1 if the g direction is negative.$02: 6/8-bits output value Z (Read Only)ZOUT — Z OutputD7 D6 D5 D4 D3 D2 D1 D0 Rev/ZOUT[7] Alert/ZOUT[6] ZOUT[5] ZOUT[4] ZOUT[3] ZOUT[2] ZOUT[1] ZOUT[0]0 0 0 0 0 0 0 0If the RNG[1:0] of STH register is clear, then D0~D5 is signed byte 6-bit 2’s complement data with allowable range of +31 to -32. ZOUT[5] is 0 if the g direction is positive, 1 if the g direction is negative. D6 is used as alert bit. If the Alert bit is set, the register was read at the same time as the device was attempting to update the contents. The register must be read again. D7 is a reserved bit.If the RNG[1:0] of STH register is set, then D0~D7 is signed byte 8-bit 2’s complement data with allowable range of +127 to -128. ZOUT[7] is 0 if the g direction is positive. 1 if the g direction is negative.$03: Tilt Status (Read only)TILTD7 D6 D5 D4 D3 D2 D1 D0 Shake Alert Tap Pola[2] Pola[1] Pola[0] BaFro[1] BaFro[0]0 0 0 0 0 0 0 0 Shake0: Equipment is not experiencing shake in one or more of the axes enabled by SHINTX, SHINTY, and SHINTZ1: Equipment is experiencing shake in one or more of the axes enabled by SHINTX, SHINTY, and SHINTZAlert0: Register data is valid1: If the Alert bit is set, the register was read at the same time as the device was attempting to update the contents. The register must be read again.Tap1: Equipment has detected a tap0: Equipment has not detected a tapPoLa[2:0]000: Unknown condition of up or down or left or right001: Left: Equipment is in landscape mode to the left010: Right: Equipment is in landscape mode to the right101: Down: Equipment standing vertically in inverted orientation110: Up: Equipment standing vertically in normal orientationBaFro[1:0]00:Unknown condition of front or back01: Front: Equipment is lying on its front10: Back: Equipment is lying on its backNote: When entering active mode from standby mode, if the device is flat (±1g on Z-axis) the value for BaFro will be back (-1g) or front (+1g) but PoLa will be in unknown condition. if the device is being held in an Up/Down/Right/Left position, the PoLa value will be updated with current orientation, but BaFro will be in unknown condition.$04: Sample Rate Status Register (Read only)SRSTD7 D6 D5 D4 D3 D2 D1 D00 0 0 0 FFAL DTap Reserved AMSRS0 0 0 0 0 0 0 0 FFAL1: Equipment has detected free fall0: Equipment has not detected free fallDTap1: Equipment has detected double tap0: Equipment has not detected double tapAMSRS0: Samples per second specified in AMSR[2:0] is not active1: Samples per second specified in AMSR[2:0] is active$06: Interrupt Setup Register (Read/Write)INTSUD7 D6 D5 D4 D3 D2 D1 D0 SHINTX SHINTY SHINTZ GINT Reserved PDINT PLINT FBINT0 0 0 0 0 0 0 0 SHINTX0: Shake on the X-axis does not cause an interrupt or set the Shake bit in the TILT register1: Shake detected on the X-axis causes an interrupt, and sets the Shake bit in the TILT registerSHINTY0: Shake on the Y-axis does not cause an interrupt or set the Shake bit in the TILT register1: Shake detected on the Y-axis causes an interrupt, and sets the Shake bit in the TILT registerSHINTZ0: Shake on the Z-axis does not cause an interrupt or set the Shake bit in the TILT register1: Shake detected on the Z-axis causes an interrupt, and sets the Shake bit in the TILT register.GINT0: There is not an automatic interrupt after every measurement1: There is an automatic interrupt after every measurement, when g-cell readings are updated in XOUT, YOUT, ZOUT registers, regardless of whether the readings have changed or not.PDINT0: Successful tap detection does not cause an interrupt1: Successful tap detection causes an interruptPLINT0: Up/Down/Right/Left position change does not cause an interrupt1: Up/Down/Right/Left position change causes an interruptFBINT0: Front/Back position change does not cause an interrupt1: Front/Back position change causes an interruptThe active interrupt condition (IRQ = 0 if IAH = 0, IRQ = 1 if IAH = 1) is released during the acknowledge bit of the slave address transmission of the first subsequent I2C to STK8312 after the interrupt was asserted.$07: Mode Register (Read/Write)MODED7 D6 D5 D4 D3 D2 D1 D0 IAH IPP Reserved Reserved Reserved Reserved Reserved MODE0 0 0 0 0 0 0 0 NOTE: The device must be placed in Standby Mode to change the value of the registers.Table 1. ModesMode of Operation D0 - MODEStandby Mode0Active Mode 1IAH0: Interrupt output INT is active low1: Interrupt output INT is active highIPP0: Interrupt output INT is open-drain.1: Interrupt output INT is push-pullNOTE: Do NOT connect pull-up resistor from INT to higher voltage than DVDD.TON0: Standby Mode or Active Mode depending on state of MODE1: Test Mode Existing state of MODE bit must be 0, to write TON = 1. Device must be in Standby Mode. In Test Mode (TON = 1),the data in the XOUT, YOUT and ZOUT registers is not updated by measurement, but is instead updated by the user through theI2C interface for test purposes. Changes to the XOUT, YOUT and ZOUT register data is processed by STK8312-000 to changeorientation status and generate interrupts just like Active Mode. Debounce filtering, free-fall, and shake detection are disabled inTest Mode.MODE0: Standby mode1: Active mode. STK8312 always enters Active Mode using the samples per second specified in AMSR[2:0] of the SR (0x08) register.The active interrupt condition (IRQ = 0 if IAH = 0, IRQ = 1 if IAH = 1) is released during the acknowledge bit of the slave addresstransmission of the first subsequent I2C to STK8312 after the interrupt was asserted.$08: Active Mode Portrait/Landscape Samples per Seconds Register (Read/Write)SR — Sample Rate RegisterD7 D6 D5 D4 D3 D2 D1 D0 FILT[2] FILT[1] FILT[0] Reserved Reserved AMSR[2] AMSR[1] AMSR[0]0 0 0 0 0 0 0 0AMSR[2:0]NAME DESCRIPTION000AMPD 400 Samples/Second Active ModeTap Detection:Tap Detection Mode operates under 200Samples/Second in Active Mode. Tap detection: itself compares the two consecutive axis responses described above for each axis. The absolute (unsigned) difference between those axis responses is compared against the tap detection delta threshold value PDTH[4:0] in the PDET (0x09) register.Free-fall Detection: The update rate is 400 samples per second.For portrait/landscape and shake detection:. The update rate is 400 samples per second. These measurements update the XOUT (0x00), YOUT (0x01), and ZOUT (0x02) registers also.001AM64200 Samples/Second Active ModeTap Detection:Tap Detection Mode operates under 200Samples/Second in Active Mode. Tap detection: itself compares the two consecutive axis responses described above for each axis. The absolute (unsigned) difference between those axis responses is compared against the tap detection delta threshold value PDTH[4:0] in the PDET (0x09) register.Free-fall Detection: The update rate is 200 samples per second.For portrait/landscape and shake detection: The update rate is 200 samples per second. These measurements update the XOUT (0x00), YOUT (0x01), and ZOUT (0x02) registers also.010AM32100 Samples/Second Active ModeTap Detection:Tap Detection Mode operates under 200Samples/Second in Active Mode. Tap detection: itself compares the two consecutive axis responses described above for each axis. The absolute (unsigned) difference between those axis responses is compared against the tap detection delta threshold value PDTH[4:0] in the PDET (0x09) register.Free-fall Detection: Function is disabled.For portrait/landscape and shake detection: The update rate is 100 samples per second. These measurements update XOUT (0x00), YOUT (0x01), and ZOUT (0x02) registers also.011AM1650 Samples/Second Active ModeTap Detection:Tap Detection Mode operates under 200Samples/Second in Active Mode. Tap detection: itself compares the two consecutive axis responses described above for each axis. The absolute (unsigned) difference between those axis responses is compared against the tap detection delta threshold value PDTH[4:0] in the PDET (0x09) register.Free-fall Detection: Function is disabled.For portrait/landscape and shake detection: The update rate is 50 samples per second. These measurements update the XOUT (0x00), YOUT (0x01), and ZOUT (0x02) registers also.100AM825 Samples/Second Active ModeTap Detection:Tap Detection Mode operates under 200Samples/Second in Active Mode. Tap detection: itself compares the two consecutive axis responses described above for each axis. The absolute (unsigned) difference between those axis responses is compared against the tap detection delta threshold value PDTH[4:0] in the PDET (0x09) register.Free-fall Detection: Function is disabled.For portrait/landscape and shake detection: The update rate is 25 samples per second. These measurements update the XOUT (0x00), YOUT (0x01), and ZOUT (0x02) registers also.101AM412.5 Samples/Second Active ModeTap Detection:Tap Detection Mode operates under 200Samples/Second in Active Mode. Tap detection: itself compares the two consecutive axis responses described above for each axis. The absolute (unsigned) difference between those axis responses is compared against the tap detection delta threshold value PDTH[4:0] in the PDET (0x09) register.Free-fall Detection: Function is disabled.For portrait/landscape and shake detection: The update rate is 12.5 samples per second. These measurements update the XOUT (0x00), YOUT (0x01), and ZOUT (0x02) registers also.110AM26.25 Samples/Second Active ModeTap Detection:Tap Detection Mode operates under 200Samples/Second in Active Mode. Tap detection: itself compares the two consecutive axis responses described above for each axis. The absolute (unsigned) difference between those axis responses is compared against the tap detection delta threshold value PDTH[4:0] in the PDET (0x09) register.Free-fall Detection: Function is disabled.For portrait/landscape and shake detection: The update rate is 6.25 samples per second. These measurements update the XOUT (0x00), YOUT (0x01), and ZOUT (0x02) registers also.111AM13.125 Sample/Second Active ModeTap Detection:Tap Detection Mode operates under 200Samples/Second in Active Mode. Tap detection: itself compares the two consecutive axis responses described above for each axis. The absolute (unsigned) difference between those axis responses is compared against the tap detection delta threshold value PDTH[4:0] in the PDET (0x09) register.Free-fall Detection: Function is disabled.For portrait/landscape and shake detection: The update rate is 3.125 sample per second. These measurements update the XOUT (0x00), YOUT (0x01), and ZOUT (0x02) registers also.FILT[2:0]DESCRIPTION000Tilt debounce filtering is disabled. The device updates portrait/landscape every reading at the rate set by AMSR[2:0]0012 measurement samples at the rate set by AMSR[2:0] have to match before the device updates portrait/ landscape data in TILT (0x03) register.0103 measurement samples at the rate set by AMSR[2:0] have to match before the device updates portrait/ landscape data in TILT (0x03) register.011 4 measurement samples at the rate set by AMSR[2:0] have to match before the device updates portrait/ landscape data in TILT (0x03) register.100 5 measurement samples at the rate set by AMSR[2:0] have to match before the device updates portrait/ landscape data in TILT (0x03) register.101 6 measurement samples at the rate set by AMSR[2:0] have to match before the device updates portrait/ landscape data in TILT (0x03) register.110 7 measurement samples at the rate set by AMSR[2:0] have to match before the device updates portrait/ landscape data in TILT (0x03) register.1118 measurement samples at the rate set by AMSR[2:0] have to match before the device updates portrait/ landscape data in TILT (0x03) register.$09: Tap/Pulse Detection Register (Read/Write) PDETD7 D6 D5 D4 D3 D2 D1 D0 ZDA YDA XDA PDTH[4]PDTH[3] PDTH[2]PDTH[1] PDTH[0] 0ZDA1: Z-axis is disabled for tap detection 0: Z-axis is enabled for tap detectionYDA1: Y-axis is disabled for tap detection 0: Y-axis is enabled for tap detectionXDA1: X-axis is disabled for tap detection 0: X-axis is enabled for tap detectionPDTH[4:0] DESCRIPTION00000 00001 Tap detection threshold is ±62.5 mg 00010 Tap detection threshold is ±125 mg 00011 Tap detection threshold is ±187.5 mg … ... and so on up to...11101 Tap detection threshold is ±1812.5 mg 11110 Tap detection threshold is ±1875 mg 11111Tap detection threshold is ±1937.5 mg$0C: X-Axis Offset Register (Read/Write) OFSXD7 D6 D5 D4 D3 D2 D1 D0 OFSX[7]OFSX[6] OFSX[5] OFSX[4]OFSX[3] OFSX[2] OFSX[1] OFSX[0] 0The OFSX register is eight bits and offers user-set adjustments in twos complement format with a scale factor of 46.9mg/LSB at ±1.5g and ±6g modes or 125mg/LSB at ±16g mode for x axis. The values stored in the offset register are automatically added to the acceleration data, and the resulting value is stored in the output data registers.$0D: Y-Axis Offset Register (Read/Write) OFSYD7 D6 D5 D4 D3 D2 D1 D0 OFSY[7]OFSY[6] OFSY[5] OFSY[4]OFSY[3] OFSY[2] OFSY[1] OFSY[0] 0The OFSY register is eight bits and offers user-set adjustments in twos complement format with a scale factor of 46.97mg/LSB at ±1.5g and ±6g modes or 125mg/LSB at ±16g mode for y axis. The values stored in the offset register are automatically added to the acceleration data, and the resulting value is stored in the output data registers.。
IC datasheet pdf-TS3A27518E,pdf(6-BIT, 1-of-2 MULTIPLEXER_DEMULTIPLEXER)
4 NC3 IN1 EN NO5 NO3
5 NC6 NC4 NC5 NO4 NO6
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
website at .
LOGIC DIAGRAM
VCC
IN1
Logic
EN
IN2
NC1 NO1 COM1
NC2 NO2 COM2
NC3 NO3 COM3
GND
NC4 NO4 COM4
NC5 NO5 COM5
NC6 NO6 COM6
SUMMARY OF CHARACTERISTICS
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
– ±6-kV Contact Discharge (IEC 61000-4-2) • 24-QFN (4 × 4 mm), 24-BGA (3 × 3 mm) and
ADMV9613 Data Sheet说明书
Data Sheet ADMV961360 GHz Millimeterwave Short Data LinkRev. Sp0Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.FEATURES►Meets V-band worldwide frequency requirements ►Integrated omnidirectional circularly polarized antenna►Integrated high band and low band diplexer for improved multi-path distortion►Full duplex operation ►Simple AM scheme ►Data rate: 100 Mbps ►Ultralow latency►Short link communication distance: 1 cm to 5 cm ►Receiver frequency: 59.85 GHz ►Transmitter frequency: 63.2625 GHz►Transmitter gain setting range: −3 dB to +32 dB ►Integrated transmitter PA power detector ►Receiver gain setting range: −10 dB to +69 dB ►RF, IF, and BB gain control►Integrated receiver and transmitter frequency synthesizers ►Integrated reference clock ►On-chip temperature sensors►DC-coupled baseband input and output ►3-wire digital SPI►34.70 mm × 29.89, 52-terminal printed circuit assembly (PCA)APPLICATIONS►60 GHz short data link for industrial and medical high data rate applications►High speed data for rotating applications, such as slip rings and magnetic resonance imaging systemsGENERAL DESCRIPTIONThe ADMV9613 is a complete millimeterwave (mmWave) wireless connectivity solution in a small printed circuit assembly (PCA)format. All millimeterwave signals are confined to the printed cir-cuit assembly, simplifying implementation. Wireless transmission is achieved using the integrated circularly polarized (CP) omnidirec-tional patch antenna array, which enables communication in many applications, including rotation. Following the antenna array is an integrated diplexer that provides isolation between the separate transmit and receive paths on the board, which reduces multipath distortion. The receive path integrates all components to demodu-late the 59.85 GHz frequency to baseband signals. The flexible receiver gain control is programmable over a wide range to easily accommodate the required link budget. The receiver baseband outputs are dc-coupled and can provide over 500 mV of differential output signal level. Likewise, the transmit path integrates all compo-nents to modulate input baseband signals to 63.2625 GHz. The transmitter has programmable gain control to maintain level trans-mit power. The transmit baseband inputs are dc-coupled and have a broad common-mode input range. Synthesizers are integrated to maintain excellent frequency stability vs. temperature. The simple amplitude modulation (AM) scheme eliminates the need for external data converters, allowing for bit rates of greater than 100 Mbps.On-board power management is integrated to a single 5 V voltage rail to power the ADMV9613.Together with the ADMV9623, the ADMV9613 provides a complete,full duplexed 60 GHz data link for high speed data transmission in the unlicensed 60 GHz industrial, scientific, and medical (ISM)band.For more information on the ADMV9613, contact Analog Devices, Inc., at ****************Data Sheet ADMV9613 NOTES©2023 Analog Devices, Inc. All rights reserved. Trademarks andRev. Sp0 | 2 of 2registered trademarks are the property of their respective owners.One Analog Way, Wilmington, MA 01887-2356, U.S.A.。
BK5863N Data SheetV1.9
BK5863N 5.8ＧHz SoC 专为国标CPC设计博通集成电路（上海）股份有限公司上海浦东新区张江高科技园区张东路1387号41栋电话：(86)21 51086811传真：(86)21 60871277修改历史目录修改历史 (2)目录 (3)1.简介 (7)2.特点 (7)3.管脚定义 (8)3.1.封装 (8)3.2.管脚定义 (10)4.电源管理 (12)4.1.工作模式 (12)4.2.低功耗 (13)4.2.1.进入Standby模式的流程 (13)4.2.2.从Standby唤醒 (13)4.3.时钟系统 (14)4.3.1.时钟开关逻辑 (15)4.4.复位系统 (15)4.5.电源管理框图 (16)5.MCU和存储 (16)5.1.MCU (16)5.2.存储组织 (17)5.3.JTAG和Flash烧录 (17)5.4.中断 (18)6.GPIO (19)7.外围设备 (22)7.1.看门狗 (22)7.1.1.特点 (22)7.2.PWM和Timer (22)7.2.1.特点 (23)7.3.DES加解密 (23)7.3.1.特点 (23)7.4.ADC模拟到数字转换 (23)7.4.1.特点 (24)7.4.2.温度传感器 (24)7.4.3.电压测量 (24)7.5.DAC数字到模拟转换 (25)7.6.Modem FIFO (25)7.6.1.特点 (25)7.7.MFC控制器 (25)7.7.1.特点 (25)8.串口 (26)8.1.UART (26)8.1.1.特点 (27)8.2.SPI (27)8.2.1.特点 (28)8.2.2.时序 (29)8.3.I2C (30)8.3.1.特点 (30)8.3.2.时序 (31)9.非接触卡读写器 (33)9.1.特点 (33)9.2.框图 (34)10.5.8G射频收发器 (34)10.1.5.8G RF 寄存器地址映射表 (34)10.2.5.8G RF和MCU的接口逻辑 (58)10.3.5.8G RF 功能描述 (59)10.3.1.接收机 (59)10.3.2.接收AGC设置 (61)10.3.3.接收CRC设置 (62)10.3.4.接收RSSI (62)10.3.5.接收ＢＥＲ测试模式 (63)10.4.发射机 (64)10.4.1.发射机描述 (64)10.4.2.Transmitter CRC setting (66)10.4.3.Transmitter Power setting (66)10.4.4.Single Carrier setting (66)10.4.5.PN9 Modulation Signal setting (67)10.5.Wake-up Circuit (67)10.5.1.Wakeup mode (67)10.5.2.Wakeup Band Pass Filter (68)10.5.3.No Response Mode (69)10.6.5.8G RF 状态机 (70)11.太阳能充电 (71)12.电器参数 (72)12.1.直流参数 (72)12.2.交流参数 (72)13.封装信息 (77)13.1.QFN68 (77)14.订单信息 (78)1.简介BK5863N是一款应用于ETC系统的低功耗SOC芯片，能够为客户开发快速低成本的ETC系统提供单芯片解决方案。
低功耗、+3.3V、RS-232线驱动器 接收器说明书
REV.AInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication oraADM3202/ADM3222/ADM1385One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: Low Power, +3.3 V, RS-232Line Drivers/Receivers FUNCTIONAL BLOCK DIAGRAMSFEATURES460 kbps Data Rate Specified at +3.3 VMeets EIA-232E Specifications 0.1 F Charge Pump CapacitorsLow Power Shutdown (ADM3222E and ADM1385)DIP, SO, SOIC, SSOP and TSSOP Package Options Upgrade for MAX3222/32 and LTC1385APPLICATIONSGeneral Purpose RS-232 Data Link Portable Instruments PrintersPalmtop Computers PDAsGENERAL DESCRIPTIONThe ADM3202/ADM3222/ADM1385 transceivers are high speed, 2-channel RS-232/V.28 interface devices which operate from a single +3.3 V power supply.Low power consumption and a shutdown facility (ADM3222/ADM1385) makes them ideal for battery powered portable instruments.The ADM3202/ADM3222/ADM1385 conforms to the EIA-232E and CCITT V.28 specifications and operates at data rates up to 460 kbps.Four external 0.1µF charge pump capacitors are used for the voltage doubler/inverter permitting operation from a single +3.3V supply.The ADM3222 contains additional enable and shutdown cir-cuitry. The EN input may be used to three-state the receiver outputs. The SD input is used to power down the chargepump and transmitter outputs reducing the quiescent current to less than 0.5µA. The receivers remain enabled during shutdown unless disabled using EN .The ADM1385 contains a driver disable mode and a complete shutdown mode.The ADM3202 is available in a 16-lead DIP, narrow and wide SOIC as well as a space saving 20-lead TSSOP package. The ADM3222 is available in 18-lead DIP, SO and in 20-lead SSOP and TSSOP. The ADM1385 is available in a 20-lead SSOP package, which is pin compatible with the LTC1385 CG.+3.3V TO +6.6VVOLTAGE DOUBLER C1+C1–C50.1F+V CCV+0.1F 10V++C30.1F 6.3V +3.3V INPUT+6.6V TO –6.6V VOLTAGEINVERTERC2+C2–+V–0.1F 10V+C40.1F 10VT1OUT T1IN T2OUTT2IN EIA/TIA-232OUTPUTSR1OUT R2OUTR1IN R2INEIA/TIA-232INPUTS *CMOS INPUTSCMOS OUTPUTSADM3202GND *INTERNAL 5k ⍀ PULL-DOWN RESISTOR ON EACH RS-232 INPUT+3.3V TO +6.6VVOLTAGE DOUBLER C1+C1–C50.1F+V CCV+0.1F 10V++C30.1F 6.3V +3.3V INPUT+6.6V TO –6.6V VOLTAGE INVERTER C2+C2–+V–0.1F 10V+C40.1F 10VT1OUT T1IN T2OUTT2IN EIA/TIA-232OUTPUTSR1OUT R2OUTR1IN R2INEIA/TIA-232INPUTS *CMOS INPUTSCMOS OUTPUTSADM3222GND*INTERNAL 5k ⍀ PULL-DOWN RESISTOR ON EACH RS-232 INPUTT1T2R2R1T1T2R2R1ENSD+3.3V TO +6.6VVOLTAGEDOUBLER C1+C1–C50.1F +V CCV+0.1F 10V+C30.1F 6.3V+3.3V INPUT+6.6V TO –6.6VVOLTAGEINVERTERC2+C2–+V–0.1F 10V+C40.1F 10VT1OUT T1IN T2OUTT2IN EIA/TIA-232OUTPUTSR1OUT R2OUTR1IN R2INEIA/TIA-232INPUTS *CMOS INPUTS CMOS OUTPUTSADM1385GND*INTERNAL 5k ⍀ PULL-DOWN RESISTOR ON EACH RS-232 INPUTT1T2R2R1DDSD+查询ADM1385供应商捷多邦，专业PCB打样工厂，24小时加急出货ADM3202/ADM3222/ADM1385–SPECIFICATIONS(V CC = +3.3 V ؎ 0.3 V, C1–C4 = 0.1 F. All specifications T MIN to T MAX unless otherwise noted.)Parameter Min Typ Max Unit Test Conditions/CommentsDC CHARACTERISTICSOperating Voltage Range 3.0 3.3 5.5VV CC Power Supply Current 1.3 2.1mA No Load810mA R L = 3 kΩ to GNDShutdown Supply Current0.010.5µALOGICInput Logic Threshold Low, V INL0.8V T INInput Logic Threshold High, V INH 2.0V T INCMOS Output Voltage Low, V OL0.4V I OUT = 1.6 mACMOS Output Voltage High, V OH V CC – 0.6V I OUT = –1 mAInput Leakage Current0.01±1µA T IN = GND to V CC*Output Leakage Current±10µA Receivers DisabledRS-232 RECEIVEREIA-232 Input Voltage Range–30+30VEIA-232 Input Threshold Low0.6 1.2VEIA-232 Input Threshold High 1.6 2.4VEIA-232 Input Hysteresis0.4VEIA-232 Input Resistance357kΩRS-232 TRANSMITTEROutput Voltage Swing (RS-232)±5.0±5.2V V CC = 3.3 V. All Transmitter Outputs Loadedwith 3kΩ to GroundOutput Voltage Swing (RS-562)±3.7V V CC = 3.0 VTransmitter Output Resistance300ΩV CC = 0 V, V OUT = ±2 VRS-232 Output Short Circuit Current±15mAOutput Leakage Current±25µA SD = Low, V OUT = 12 VTIMING CHARACTERISTICSMaximum Data Rate460kbps V CC = 3.3 V, R L = 3 kΩ to 7 kΩ, C L = 50pF to Receiver Propagation Delay1000 pF. One Tx SwitchingTPHL0.41µsTPLH0.41µsTransmitter Propagation Delay300750ns R L = 3 kΩ, C L = 1000 pFReceiver Output Enable Time200nsReceiver Output Disable Time200nsTransmitter Skew30nsReceiver Skew300nsTransition Region Slew Rate Measured from +3 V to –3 V or –3 V to +3 V,V CC = +3.3 V61030V/µs R L = 3 kΩ, C L = 1000 pF, T A = +25°C41030V/µs R L = 3 kΩ, C L = 2500 pF, T A = +25°C*ADM1385: Input leakage current typically –10 µA when T IN = GND.Specifications subject to change without notice.ADM3202/ADM3222/ADM1385ABSOLUTE MAXIMUM RATINGS*(T A = +25°C unless otherwise noted)V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V CC – 0.3 V) to +14 V V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –14 V Input VoltagesT IN . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V+, +0.3 V) R IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±30 V Output VoltagesT OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±15 V R OUT . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V CC + 0.3 V) Short Circuit DurationT OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Power DissipationPower Dissipation N-16 . . . . . . . . . . . . . . . . . . . . . 450 mW (Derate 6 mW/°C above +50°C)θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . 117°C/W Power Dissipation R-16 . . . . . . . . . . . . . . . . . . . . . 450 mW (Derate 6 mW/°C above +50°C)θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . 158°C/W Power Dissipation RU-16 . . . . . . . . . . . . . . . . . . . 500 mW (Derate 6 mW/°C above +50°C)θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . 158°C/W Power Dissipation R-18 . . . . . . . . . . . . . . . . . . . . . 450 mW (Derate 6 mW/°C above +50°C)θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . 158°C/W Power Dissipation RS-20 . . . . . . . . . . . . . . . . . . . . 450 mW (Derate 6 mW/°C above +50°C)θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . 158°C/W Power Dissipation RU-20 . . . . . . . . . . . . . . . . . . . 450 mW (Derate 6 mW/°C above +50°C)θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . 158°C/W Operating Temperature RangeIndustrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<1500 V *This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operation sections of this specificatio n is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.ORDERING GUIDEModel Temperature Range Package Options* ADM3202AN–40°C to +85°C N-16ADM3202ARN–40°C to +85°C R-16AADM3202ARW–40°C to +85°C R-16ADM3202ARU–40°C to +85°C RU-16ADM3222AN–40°C to +85°C N-18ADM3222ARW–40°C to +85°C R-18ADM3222ARS–40°C to +85°C RS-20ADM3222ARU–40°C to +85°C RU-20ADM1385ARS–40°C to +85°C RS-20*N = Plastic DIP; R = Small Outline; RS = Shrink Small Outline; RU = Thin Shrink Small Outline.ADM3202/ADM3222/ADM1385PIN FUNCTION DESCRIPTIONSMnemonic FunctionV CC Power Supply Input: +3.3V ± 0.3 V.V+Internally Generated Positive Supply(+6 V Nominal).V–Internally Generated Negative Supply(–6 V Nominal).GND Ground Pin. Must be connected to 0 V.C1+, C1–External Capacitor 1 is connected between these pins. 0.1 µF capacitor is recommended but largercapacitors up to 47 µF may be used.C2+, C2–External Capacitor 2 is connected between these pins. 0.1 µF capacitor is recommended but largercapacitors up to 47 µF may be used.Tx IN Transmitter (Driver) Inputs. These inputs accept TTL/CMOS levels.Tx OUT Transmitter (Driver)Outputs. These are RS-232 signal levels (typically ±9 V).Rx IN Receiver Inputs. These inputs accept RS-232signal levels. An internal 5 kΩ pull-down resistorto GND is connected on each input.Rx OUT Receiver Outputs. These are CMOS output logic levels.EN(ADM3222) Receiver Enable, Active Low. Whenlow, the receiver outputs are enabled. When high,they are three-stated.SD(ADM3222) Shutdown Control. Active Low.When low, the charge pump is shut down andthe transmitter outputs are disabled.SD(ADM1385) Shutdown Control. When low, thecharge pump is shut down and all transmittersand receivers are disabled.DD(ADM1385) Driver Disable. When low, thecharge pump is turned off and the transmittersare disabled. The receivers remain active.PIN CONNECTIONS DIP (N, R Packages) PIN CONNECTIONS DIP (RS, RU Packages)ADM3202/ADM3222/ADM1385Typical Performance CharacteristicsFigure 1.Transmitter Output Voltage High/Low vs. Load Capacitance @ 230 kbpsV CC – V12103 5.53.54.04.55.08642Figure 2.Transmitter Output Voltage High vs. V CCFigure 3.Transmitter Output Voltage Low/High vs. Load CurrentCURRENT – mA86–4010203040420–2–6–8V –(V)V+ (V)Figure 4.Charge Pump V+, V– vs. CurrentFigure 5.Charge Pump Impedance vs. VCCFigure 6.Power Supply Current vs. Load CapacitanceADM3202/ADM3222/ADM1385GENERAL DESCRIPTIONThe ADM3202/ADM3222/ADM1385 are RS-232 line drivers/ receivers. Step-up voltage converters coupled with level shifting transmitters and receivers allow RS-232 levels to be developed while operating from a single +3.3 V supply.CMOS technology is used to keep the power dissipation to an absolute minimum, allowing maximum battery life in portable applications.The ADM3202/ADM3222/ADM1385 is a modification, en-hancement and improvement to the AD230–AD241 family and its derivatives. It is essentially plug-in compatible and does not have materially different applications.CIRCUIT DESCRIPTIONThe internal circuitry consists of three main sections. These are:1.A charge pump voltage converter2.3.3V logic to EIA-232 transmitters3.EIA-232 to 5V logic receivers.Charge Pump DC-DC Voltage ConverterThe charge pump voltage converter consists of a 200 kHz oscil-lator and a switching matrix. The converter generates a ±6.6V supply from the input +3.3 V level. This is done in two stages using a switched capacitor technique as illustrated below. First, the +3.3V input supply is doubled to +6.6 V using capacitorC1 as the charge storage element. The +6.6V level is then inverted to generate –6.6 V using C2 as the storage element. C3 is shown connected between V+ and V CC, but is equally effec-tive if connected between V+ and GND.Capacitors C3 and C4 are used to reduce the output ripple. Their values are not critical and can be increased if desired. Capacitor C3 is shown connected between V+ and V CC. It is also acceptable to connect this capacitor between V+ and GND. If desired, larger capacitors (up to 10 µF) can be used for capacitors C1–C4.Figure 8.Typical Operating Circuits Figure 7.230 kbps Data TransmissionADM3202/ADM3222/ADM1385OUTLINE DIMENSIONSDimensions shown in inches and (mm).16-Lead Plastic DIP(N-16)16-Lead Thin Shrink Small Outline (TSSOP)(RU-16)PLANE BSC0.0035 (0.090)16-Lead Narrow Body SOIC(R-16A)؇16-Lead Wide Body SOIC(R-16)Figure 9.Charge Pump Voltage DoublerFigure 10.Charge Pump Voltage InverterTransmitter (Driver) SectionThe drivers convert 3.3V logic input levels into RS-232 output levels. With V CC = +3.3V and driving an RS-232 load, the output voltage swing is typically ±6 V.Receiver SectionThe receivers are inverting level-shifters that accept RS-232input levels and translate them into 3 V logic output levels.The inputs have internal 5 k Ω pull-down resistors to ground and are also protected against overvoltages of up to ±30 V. Uncon-nected inputs are pulled to 0 V by the internal 5 k Ω pull-down resistor. This, therefore, results in a Logic 1 output level for unconnected inputs or for inputs connected to GND.The receivers have Schmitt trigger inputs with a hysteresis level of 0.4 V. This ensures error-free reception for both noisy inputs and for inputs with slow transition times.HIGH BAUD RATEThe ADM3202E/ADM3222E feature high slew rates permitting data transmission at rates well in excess of the EIA/RS-232E specifications. RS-232 voltage levels are maintained at data rates up to 460 kbps even under worst case loading conditions. This allows for high speed data links between two terminals or indeed it is suitable for the new generation I SDN modem standards which requires data rates of 230 kbps. The slew rate is internally con-trolled to less than 30 V/µs in order to minimize EMI interference.ADM3202/ADM3222/ADM1385C 00071–0–8/00 (r e v . A )P R I N T E D I N U .S .A .20-Lead Thin Shrink Small Outline (TSSOP)(RU-20)18-Lead Plastic DIP(N-18)18-Lead Wide Body SOIC(R-18)20-Lead Shrink Small Outline (SSOP)(RS-20)。
gdp32tem数据处理流程
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热释红外线传感器PYS3228
DEVICE SPECIFICATIONFOR PYROELECTRIC IR-DETECTORCUSTOMER :TYPE : PYS 3228 TC G2/G20PART-NO. : 3800No. of samples :Thermally compensated two channel single element detector with lithium-tantalate crystal as sensing element, FET in source follower configuration.This specification is provided byPerkinElmer Optoelectronics GmbH & Co. KG, Wiesbaden.It covers the complete technical data of a pyroelectric IR detector. In case of samples attached to this paper, these have been taken randomly from normal production output. All detectors have met the requirements of PerkinElmer test-specifications and passed outgoing inspection.We kindly ask for approval with the return of a signed copy.Checked: Date: 27.11.06Customer approval: Date:Electrical Configuration:source follower circuit, connections "Drain-Source-Ground". It is recommended to use a loadresistor of 47 k Ω. Electrical data:C: Responsivity: min.: 2,2 kV/W typ.: 3,5 kV/WResponsivity is measured within spectral range 7 - 14 µm as per fig. 3 at 1Hz. Temperature coefficient of responsivity typ.: -0.1 %/K.Noise: max.: 50 µV pp typ.: 15 µV ppAfter a 10 minute settling time, noise is monitored for the duration of 1500 sec. at a temperature of 25°C, shut from infrared energy, electrical bandwidth of 0.4 to 10Hz. Operating voltage: V DD = 2-12 V Source voltage: V S = 0.2-1.5 V Drain-source voltage: V DS = min 0.5 VTypical Responsivity vs. Frequency0,11101000,010,1110f [Hz]R [k V /W ]Fig.2: Frequency responseFig.3: Test Set – upSpectral range:The spectral range of the detector is determined by filter built in (window). Substrate: Silicon, multilayer coatedFilter (A;B)Application Centre wave length (µm) Half power bandwidth (µm) G20Reference4.00 ± 0.08 0.09 ± 0.02 G2CO 2 4.26 ± 0.05 0.18 ± 0.021: Black Body Radiator 373K = 100°C 2: 1 Hz Chopper 3: Aperture 4: Cover plate 5: Detector 6: Bandpass filter 1 Hz 7: Rectifier 8: Lowpass filter 9: Temperature compensation 10: DisplayConfiguration:Housing:TO- 5 metal housing with infrared transparent windowElement size: 1.5 x 1.5 mm2, see also drawing: 2/71321Connections:Refer to drawing: 2/71321Fig.5: Field of ViewOperating temperature:-40°C to +85°CThe electrical parameters may vary from specified values accordance with their temperature dependence.Storage temperature:-40°C to +85°CMicrophonic noise:max: 30 µV rms /gPerkinElmer IR-detectors covered herein have passed qualification test for microphonic noise in x-y-z axis, exciting frequencies from 5Hz to 2kHz.Humidity:The IR-detector shall not increase noise or decrease responsivity when exposed to 95% r.H. at 30°C. Operation below dew point might effect performance.Hermetic seal:This IR-detector is sealed to pass a He-leakage test with maximum leak rate of 10-8 mbar.l.s-1. Quality:is a QS 9000certified manufacturer with established SPC and TQM. Detector out-going inspections include the parameters Responsivity, Match, Offset, Noise, Gross leak (Mil Std 883 method 1014C1) on 100%. Individual data are not stored, statistical details can be disclosed on request.Handling:Electrostatic charges may destroy the detector. We recommend to apply precautions necessary for ESD devices to avoid damages. Do not apply physical force to detector leads. Do not expose detector to aggressive detergents such as freon, trichlorethylene, etc.Solder conditions:Hand soldering and standard wave soldering process may be applied. Avoid heat exposure to the top and the window of the detector. Reflow soldering is not recommended.。
三位通用显示模块
三位通用显示模块
陈伟鑫
【期刊名称】《实用影音技术》
【年(卷),期】1994(000)005
【摘要】这个显示模块含有三个BCD一十进制译码驱动区。
可以读入4位二进制数,并将其转换成十进制数,然后将其直接显示在一个7段LED显示器上。
电路图示于图1。
IC1、IC2、IC3是三个74HCT4511BCD译码驱动器集成块。
代表BCD 码的四位数输入到每个集成块的ABCD输入端,这里A是最低位。
每个集成块将输入的BCD码译码成十进制,然后直接显示在7段显示器上。
这里要说明的是大于1001（十进制9或9<sub>1</sub>0）的二进制数不能显示出
【总页数】1页(P104-104)
【作者】陈伟鑫
【作者单位】
【正文语种】中文
【中图分类】TN141
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STK3228 is a highly integrated digital still camera and digital video recorder controller. STK3228 features high quality image processing and H.264 video compression to deliver excellent quality of still image capture and video recording. Syntek proprietary auto white balance and auto exposure algorithms utilize statistical analysis to deliver precise and pleasing colors. Integrated microphone amplifier, AGC and audio codec reduce system component count and deliver clear audio recordings at all sound levels. STK3228 supports major LCD panels via flexible display interface which is also compatible for HDMI transmitter. TV out is available by way of built in TV encoder and DAC. STK3228 supports most popular non-volatile memory cards with DMA for fast storage. STK3228 also support SDIO which may be used as interface to WiFi and BlueTooth controller to enrich product features. STK3228 supports high speed USB to connect PC. Built in ADC, switch and multiplex circuit make touch panel input possible with minimal system cost.
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Data Sheets Version 0.93
January 19, 2012
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Taipei Office 10F, NO.1, Alley 30, Lane 358, Rui-Guang Road, Neihu District, Taipei, Taiwan, R.O.C. TEL: 886-2-2659-0055 FAX: 886-2-2659-0077 Hsinchu Office 3F, No. 24-2, Industry E. Road IV, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C. TEL: 886-3-5773181 FAX: 886-3-5778010