5LS1;中文规格书,Datasheet资料
PI2001-EVAL1;中文规格书,Datasheet资料
IntroductionThe PI2001-EVAL1 allows the user to test the basic principle and operational characteristics of an Active ORing function in a redundant power architecture, while also experiencing the benefits and value of the PI2001 solution versus conventional Active ORing solutions. The PI2001-EVAL1 evaluation board is configured to receive two independent power source inputs,per a typical redundant power architecture, through two Active ORing channels that are combined to form aredundant power output. Each channel contains a PI2001controller and an N-channel power MOSFET. The MOSFET foot print can take an SO-8 or Power SO-8 MOSFET package.Each channel is capable of up to 20 A, for high current Active ORing, above 20 A, the two channels provided on the evaluation board can be paralleled in a master /slave configuration and OR’d with a second evaluation board.The PI2001-EVAL1 evaluation board is designed withoptimized PCB layout and component placement to represent a realistic high density final design for an embedded Active ORing solution for ≤7 Vbus applications requiring up to 20 A.This evaluation board is intended as an easy and simple way to test the electrical and thermal performance of the PI2001Active ORing controller.Both dynamic and steady state testing of the PI2001 can be completed on the PI2001-EVAL1 evaluation board, in addition to using the key features of the product. Dynamic testing can be completed under a variety of system level fault conditions to check for response time to faults.This document provides basic instructions for initial start-up and configuration of the evaluation board. Further information on the functionality of the PI2001 can be found in the PI2001 product data sheet.PI2001-EVAL1Cool-ORing ™ SeriesPI2001-EVAL1 Active ORingEvaluation Board User Guide®PI2001-EVAL1 Evaluation Board featuring the Cool-ORing PI2001 Universal Active ORing controller.Cool-ORing™ SeriesThe PI2001-EVAL1 Evaluation Board is intended to acquaint the user with the benefits and features of the Cool-ORing TM PI2001Universal Active ORing controller. It is not designed to be installed in end-use equipment.Please read this document before setting up the PI2001-EVAL1Evaluation Board and refer to the PI2001 product data sheet for device specifications, functional description and characteristics.During operation, the power devices and surrounding structures can be operated safely at high temperatures.•Remove power and use caution when connecting and disconnecting test probes and interface lines to avoid inadvertent short circuits and contact with hot surfaces.•When testing electronic products always use approved safety glasses. Follow good laboratory practice and procedures.The Cool-ORing PI2001 with an external industry standard N-channel MOSFET provides a complete Active ORing solution designed for use in redundant power systemarchitectures. The PI2001 controller with N-channel MOSFET enables extremely low power loss with fast dynamic response to fault conditions, critical for high availability systems. A master /slave feature allows the paralleling of PI2001solutions for high current Active ORing requirements. The PI2001 can also drive multiple paralleled MOSFETs.The PI2001 controller with a low Rds(on) N-channel MOSFET provides very high efficiency and low power loss during steady state operation. The PI2001 controller provides an active low fault flag output to the system during excessive forward current, light load, reverse current, over-voltage,under-voltage, and over-temperature fault conditions. A temperature sensing function indicates a fault if themaximum junction temperature exceeds 160°C. The under-voltage and over-voltage thresholds are programmable via an external resistor divider.Figure 1 shows a photo of the PI2001-EVAL1 evaluation board, with two PI2001 controllers and two N-channelMOSFETs used to form the two Active ORing channels. The board is built with two identical Active ORing circuits with options and features that enable the user to fully explore thecapabilities of the PI2001 universal Active ORing controller.Figure 1 –PI2001-EVAL1 Evaluation Board (1.8" x 1.8")Terminals RatingVin1, Vin28V / 24 AVaux1, Vaux2, (R2 = R4 = 10 Ω)-0.3 V to 17.3 V / 40 mA SL1, SL2-0.3 V to 8.0 V / 10 mA FT1, FT2-0.3 V to 17.3 V / 10 mATerminal DescriptionVin1Power Source Input #1or bus input designed to accommodate up to 20 A continuous current.Vaux1Auxiliary Input Voltage #1to supply PI2001 VC power. Vaux1 should be equal to Vin1 plus 5 V or higher. See details in Auxiliary Power Supply (Vaux) section of the PI2001 data sheet.Rtn1Vaux1 Return Connection: Connected to Ground planeGnd Vin & Vout Return Connection:Three Gnd connections are available and are connected to a common point, the Ground plane. Input supplies Vin1 & Vin2 and the output load at Vout should all be connected to their respective local Gnd connection.SL1PI2001 (U1) Slave Input-Output Pin: For monitoring U1 slave pin. When U1 is configured as the Master, this pin functions as an output that drives slaved PI2001 devices. When U1 is configured in Slave mode, SL1 serves as an input.SL2PI2001 (U2) Slave Input-Output Pin: For monitoring U2 slave pin. When U2 is configured as the Master, this pin functions as an output that drives slaved PI2001 devices. When U2 is configured in Slave mode, SL2 serves as an input.Vin2Power Source Input #2or bus input designed to accommodate up to 20 A continuous current.Vaux2Auxiliary Input Voltage #2to supply PI2001 VC power. Vaux2 should be equal to Vin2 plus 5 V or higher. See details in Auxiliary Power Supply (Vaux) section of the PI2001 data sheet.Rtn2Vaux2 Return Connection: Connected to Ground plane FT1PI2001 (U1) Fault Pin: Monitors U1 fault conditions FT2PI2001 (U2) Fault Pin: Monitors U2 fault conditionsVoutOutput: Q1 and Q2 MOSFET Drain pins connection, connect to the load high side.Table 1 –PI2001-EVAL1 Evaluation Board terminals descriptionCool-ORing TM PI2001 Product DescriptionJumper DescriptionJ1, J3BK Jumpers: Connect jumper across M for master mode and across S for slave mode. Remove jumper to adjust reverse fault blanking time using Rbk. Rbk is R7 for U1 and R14 for U2 shown in the schematic, Figure 2.J2Slave Jumper: Remove the jumper unless one of the PI2001 is configured in slave mode.Table 2 –PI2001-EVAL1 Evaluation Board jumpers descriptionFigure 2 –PI2001-EVAL1 Evaluation Board schematic.Item QTY Reference Designator Value Description Footprint Manufacturer 12C1, C2 1 µF Capacitor, MLCC X5R, 06031 µF,16 V21C322 µF Capacitor, MLCC X7R,121022 µF, 25 V34C4, C5, C6, C7Not installed120642D1, D2LED, Super Red THIN 0603Lite-On, Inc.,58FT1, FT2, Rtn1, Rtn2, Turret Test point TURRET-1528Keystone SL1, SL2, Vaux1, Vaux2Electronics67Gnd1, Gnd2, Gnd3, Gnd4,Turret Test point TURRET-1502Keystone Vin1, Vin2, Vout1, Vout2Electronics 72J1, J3Header Pins 0.1" pitch 2 x 3mm81J2Header Pins 0.1" pitch 2 x 2mm92Q1, Q2FDS8812NZSO-8Fairchild 30 V, 20 A, N-MOSFET102R1, R88.45 KΩResistor,8.45 KΩ,1%0603112R2, R913.3 KΩResistor,13.3 KΩ,1%0603122R3, R1010 ΩResistor,10 Ω,5%0603132R4, R11 4.99 KΩResistor, 4.99 KΩ,5%0603144R5, R6, R12, R13 2.00 KΩResistor, 2.00 KΩ,1%0603152R7, R14Not Installed0603162U1, U2PI2001Picor Universal Active ORing Controller3mmx3mm; 10-TDFN PICOR Table 3 –PI2001-EVAL1 Evaluation Board bill of materialsInitial Test Set UpTo test the PI2001-EVAL1 evaluation board it is necessary to configure the jumpers (J1, J2 and J3) first based on the required board configuration.Failure to configure the jumpers prior to the testing may result in improper circuit behaviorBaseline Test Procedure (Refer to Figure 3)1.0 Recommended Equipment1.1Two DC power supplies - 0-10 V; 25 A.1.2DC power supply 12 V; 100 mA.1.3DC electronic load - 50 A minimum.1.4Digital Multimeter 1.5Oscilloscope.1.6Appropriately sized interconnect cables.1.7Safety glasses.1.8PI2001 Product Data sheet.Figure 3 –Layout configuration for a typical redundant power application, using PI2001 with both solutions configured in Master Mode.Reference Designator Value Functional Description C1, C2 1 µF VC Bypass Capacitor C322 µF Output (Load) CapacitorC4, C5, C6, C7Not installedSnubber to reduce voltage ringing when the device turns off D1, D2LED To indicate a fault exist when it is onJ1, J3Jumper To select between Master and Slave Modes J2Jumper Connection between SL1 and SL2Q1, Q2N-MOSFET ORing Main SwitchR1, R88.45 K ΩUV Voltage Divider Resistor ( R2UV in Figure 4) R2, R913.3 K ΩOV Voltage Divider Resistor ( R2OV in Figure 4) R3, R1010 ΩVC Bias resistor R4, R11 4.99 K ΩLED Current LimiterR5, R6 2.00 K ΩUV Voltage Divider Resistor ( R1UV in Figure 4) R7, R14Not Installed BK Delay Timer Programmable Resistor U1, U2PI2001Universal Active ORing ControllerTable 4 –Component functional descriptionBefore initial power-up follow these steps to configure the evaluation board for specific end application requirements: 2.0 Undervoltage (UV) and Overvoltage (OV) resistors set up:2.1UV and OV programmable resistors are configuredfor a 3.3 V Vin (BUS voltage) application in atwo-resistor voltage divider configuration as shown inFigure 4. UV is set to 2.6 V and OV is set for 3.8 V,R1OV and R1UV are 2.00KΩ1%. If PI2121-EVAL1 isrequired to be used in a different Vin voltage . .application please follow the following steps tochange the resistor values.2.1.1It is important to consider the maximum currentthat will flow in the resistor divider andmaximum error due to UV and OV input .current.R1UV=V(UV TH)I RUV2.1.2Set R1UV and R1OV value based on systemallowable minimum current and 1% error;I RUV ≥ 100 µAR2UV=R1UV (V(UV)–1)V(UV TH)Where:V(UV TH) : UV threshold voltageV(UV) : UV voltage set (0.5 V typ)I RUV: R1UV currentR2OV=R1OV (V(OV)–1)V(OV TH)Where:V(OV TH) : OV threshold voltageV(OV) : OV voltage set (0.5 V typ)I ROV: R1OV currentFigure 4 –UV & OV two-resistor divider configuration2.1.3Example for 2.0 V Vin (BUS voltage), to set UV and OV for ±10% Vin set UV at 1.8 V and OV at 2.2 V.R2UV= R1UV (V(UV)–1) = 2.00 KΩ*( 1.8 V–1)= 5.20 KΩ(or 5.23 KΩ% standard value)V(UV TH)0.5 VR2OV= R1OV (V(OV)–1) = 2.00 KΩ*( 2.2 V–1)= 6.80 KΩ(or 6.81 KΩ% standard value)V(OV TH)0.5 V3.0Blanking timer setup:3.1The blanking timer provides noise filtering fortypical switching power conversion that mightcause premature reverse current detection bymasking the reverse fault condition. The shortestblanking time is 50 ns when the BK pin isconnected to ground. Connecting an externalresistor (R BK, reference designators R7 for U1 andR14 for U2) between the BK pin and ground willincrease the blanking time as shown in Figure 5.Where:R BK≤ 200 KΩNote:When BK is connected to VC for slave mode .operation,then the blanking time will be 270 ns typically.4.0Auxiliary Power Supply (Vaux):4.1The PI2001 Controller has a separate input (VC) thatprovides power to the control circuitry and the gatedriver. An internal voltage regulator (VC) clamps theVC voltage to 15.5 V typically.4.2Connect independent power source to Vaux inputs ofPI2001-EVAL1 Evaluation Board to supply power tothe VC input. The Vaux voltage should be 5V higherthan Vin (redundant power source output voltage) tofully enhance the MOSFET. If the MOSFET is replacedwith different MOSFET, make sure that Vaux= Vin +0.5 V + required voltage to be enhance the MOSFET.4.310 Ωbias resistors (Rbias, reference designators R3and R10) are installed on the PI2001-EVAL1 betweeneach Vaux input and VC pin of one of the PI2001controller. 4.4If Vaux is higher than the Clamp voltage, 15.5 Vtypical, the Rbias value has to be changed using thefollowing equations:4.4.1Select the value of Rbias using the followingequation:Rbias =Vaux min–VC clampMAXIC max4.4.2Calculate Rbias maximum power dissipation:Pd Rbias= (Vaux max–VC clampMIN)2RbiasWhere:Vaux min: Vaux minimum voltageVaux max: Vaux maximum voltageVC ClampMAX:Maximum controllerclamp voltage, 16.0 VVC ClampMIN:Minimum controllerclamp voltage, 14.0 VIC max: Controller maximum bias current,use 4.2 mA4.4.3For example, if the minimum Vaux = 22 Vand the maximum Vaux = 28 VRbias = Vaux min–VC clampMAX =22 V–16 V = 1.429 KΩIC max 4.2 mA,use 1.43 KΩ1% resistorPd Rbias= (Vaux max–VC clampMIN)2= (28 V–14.0 V)2=137 mWRbias 1.43 KΩNote:Minimize the resistor value for low Vaux voltagelevels to avoid a voltage drop that may reduce the VCvoltage lower than required to drive the gate of theinternal MOSFET. Figure 5 –BK Resistor selection versus Blanking Time5.0Hook Up of the Evaluation Board5.1OV and UV resistors values are configured for a 3.3 Vinput voltage. If you are using the evaluation board ina different input voltage level you have to adjust theresistor values by replacing R1, R2, R8 and R9, orremove R2, R5, R9 and R12 to disable UV and OV.Please refer to the UV/OV section for details to set R1,R2, R8 and R9 proper values.5.2Verify that the jumpers J1 and J3 are installed formaster mode [across M] and no Jumper on J2.5.3Connect the positive terminal of PS1 power supplyto Vin1. Connect the ground terminal of PS1 to itslocal Gnd. Set the power supply to 3.3 V.Keep PS1 output disabled (OFF).5.4Connect the positive terminal of PS2 power supplyto Vin2. Connect the ground terminal of PS2 to itslocal Gnd. Set the power supply to 3.3 V. Keep PS2output disabled (OFF).5.5Connect the positive terminal of PS3 power supplyto Vaux1 and Vaux2. Connect the ground terminalof this power supply to Rtn1 and Rtn2. Set thepower supply to 12 V. Keep PS3 output disabled(OFF).5.6Connect the electronic load to the output betweenVout and Gnd. Set the load current to 10 A.5.7Enable (turn ON) PS1 power supply output.5.8Turn on the electronic load.5.9Verify that the electronic load input voltagereading is one diode voltage drop below 3.3 V.5.10Enable (turn ON) PS3 power supply output.5.11Verify that the electronic load voltage readingincreases to a few millivolts below 3.3 V. This verifiesthat the MOSFET is in conduction mode.5.12D1 should be off. This verifies that there is nofault condition.5.13Reduce PS1 output voltage to 2 V,5.14D1 should turn on, this verifies that the circuit is inan under-voltage fault condition.5.15Increase PS1 output to 3.3 V, D1 should turn off, thenincrease PS1 output to 4 V, D1 should turn onindicating an over-voltage fault condition5.16Verify that Vin2 is at 0V. This verifies that thePI2001 (U2) FET (Q2) is off.5.17D2 should be on. This is due to a reverse voltagefault condition caused by the bus voltage beinghigh with respect to the input voltage (Vin2).5.18Enable (turn ON) PS2 output.5.19Verify that both PS1 and PS2 are sharing loadcurrent evenly by looking at the supply current.5.20Disable (turn OFF) PS1, PS2 and PS3 outputs.5.21Enable (turn ON) PS2 output then Enable PS3 output.5.22Verify that the electronic load voltage reading isfew millivolts below 3.3 V. This verifies that the PI2001(U2) MOSFET (Q2) is in conduction mode.5.23D2 should be off. This verifies that there is nofault condition.5.24Reduce PS2 output voltage to 2 V,5.25D2 should turn on, this verifies that the circuit is inan under-voltage fault condition.5.26Increase PS2 output to 3.3 V, D2 should turn off, thenincrease PS2 output to 4 V, D2 should turn onindicating an over voltage fault condition.5.27Verify that Vin1 is at 0V. This verifies that thePI2001 (U1) FET (Q1) is off.5.28D1 should be on. This is due to a reverse voltagefault condition caused by the bus voltage beinghigh with respect to the input voltage (Vin1).6.0Slave Mode: Slave Mode can be demonstrated in two setups; either by using one PI2001-EVAL1 evaluation board as a single ORing function with both PI2001 effectively in parallel or two PI2001-EVAL1 evaluation boards to demonstrate a true redundant 40A system. The following test steps use a single PI2001-EVAL1 in a slave mode application. Note:In this experiment U1 is configured in master mode andU2 is configured in slave mode.6.1BK pin (J1) of the master device will be connected toground [across M] while the slaved device BK pin (J3)is connected to VCC [across S]. Place a jumper across J2to connect slave pins together.6.2Connect the positive terminal of PS1 power supplyto Vin1. Connect the ground terminal of this powersupply to Gnd. Set the power supply to 3.3 V. KeepPS1 output disabled (OFF).6.3Connect the positive terminal of PS2 power supplyto Vin2. Connect the ground terminal of this powersupply to Gnd. Set the power supply to 3.3 V. KeepPS2 output disabled (OFF).6.4Connect the positive terminal of PS3 power supplyto Vaux1 and Vaux2. Connect the ground terminalof this power supply to Rtn1 and Rtn2. Set thepower supply to 12 V. Keep PS3 output disabled (OFF).6.5Connect the electronic load between Vout andGnd. Set the load current to 10 A.6.6Enable (Turn ON) PS2, and PS3 outputs, and keepPS1 output disabled (OFF).6.7Turn on the electronic load.6.8Verify that electronic load voltage drops to a diodedrop below PS2. This verifies that the Q2 is off due tothe Master (U1) not being on.6.9Enable (turn on) PS1 output:6.10Verify that the electronic load input voltage reading isa few millivolts below 3.3 V and PS1 and PS2 aresharing the load current evenly. This verifies that both MOSFET's, Q1 and Q2, are in conduction mode.7.0Input short circuit test7.1To emulate a real application, the BUS supplies for thistest should have a solid output source such as DC-DC converter that supplies high current and can be connected very close to the evaluation board to reduce stray parasitic inductance. Or use theprospective supply sources of the end application where the PI2001 will be used. 7.2Stray parasitic inductance in the circuit can contributeto significant voltage transient conditions, particularly when the MOSFET is turned-off after a reverse current fault has been detected. When a short is applied at the output of the input power sources and the .evaluation board input (Vin), a large reverse current is sourced from the evaluation board output through the ORing MOSFET. The reverse current in the MOSFET may reach over 60 A in some conditions before the MOSFET is turned off. Such high current conditionswill store high energy even in a small parasitic element, and can be represented as ½ Li2. A 1 nH parasitic inductance with 60 A reverse current will generate 1.8 µJ. When the MOSFET is turned off, the stored energy will be released and will produce a high negative voltage at the MOSFET source and high positive voltage at the MOSFET drain. This event will create a high voltage difference across the drain and source of the MOSFET.7.3Apply a short at one of the inputs (Vin1 or Vin2) whenthe evaluation board is configured with bothcontrollers (U1 and U2) in master mode. The short can be applied electronically using a MOSFET connected between Vin and Gnd or simply by connecting Vin to Gnd. Then measure the response time between when the short is applied and the MOSFET is disconnected (or turned off). An example for PI2001 response time to an input short circuit is shown in Figure 6.Figure 6 –Plot of PI2001 response time to reverse current detectionFigure 7a–PI2001-EVAL1 layout top layer. Scale 2.0:1 Figure 7b–PI2001-EVAL1 layout mid layer 2. Scale 2.0:1Figure 7c–PI2001-EVAL1 layout mid layer 1. Scale 2.0:1 Figure 7d–PI2001-EVAL1 layout Bottom layer. Scale 2.0:1Mechancial Drawing分销商库存信息: VICORPI2001-EVAL1。
WP115VEYW;中文规格书,Datasheet资料
Description
The High Efficiency Red source color devices are made with Gallium Arsenide Phosphide on Gallium Phosphide Orange Light Emitting Diode. The Yellow source color devices are made with Gallium Arsenide Phosphide on Gallium Phosphide Yellow Light Emitting Diode.
-40°C To +85°C 260°C For 3 Seconds 260°C For 5 Seconds
SPEC NO: DSAF2635 APPROVED: WYNEC
REV NO: V.3 CHECKED: Allen Liu
DATE: FEB/28/2011 DRAWN: J.Yu
PAGE: 2 OF 7 ERP: 1101000788
SPEC NO: DSAF2635 APPROVED: WYNEC
REV NO: V.3 CHECKED: Allen Liu
DATE: FEB/28/2011 DRAWN: J.Yu
PAGE: 1 OF 7 ERP: 1101000788
/
Selection Guide
Notes: 1. 1/10 Duty Cycle, 0.1ms Pulse Width. 2. 2mm below package base. 3. 5mm below package base.
High Efficiency Red 75 30 160 5
Yellow 75 30 140
SN54LS01D中文资料
IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1998, Texas Instruments Incorporated。
EIS-2205-中英文说明书-B00-2413-026011
特种计算机Industrial Computer产品说明书User ManualEIS-2205研祥工业服务器EVOC Industrial ServerVersion: B00法律资讯警告提示为了您的人身安全以及避免财产损失，必须注意本手册中的提示。
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MB2065SS1W01;MB2011SS1W01-CA;MB2011SS1W03-CA;MB2011SS1W01;MB2011LS1W03-CC;中文规格书,Datasheet资料
Slow make, slow break
Screw-on Cap (Mom.)
Screw-on Cap (Alt.)
Snap-on Cap (Mom. & Alt.)
.028” (0.71mm)
.110” (2.80mm)
.125” (3.19mm)
.043” (1.09mm)
.043” (1.10mm)
Other Ratings
Contact Resistance: Insulation Resistance:
Dielectric Strength:
Mechanical Life: Electrical Life:
Nominal Operating Force:
Contact Timing: Plunger Travel: Pretravel: Overtravel: Total Travel
Slides
Ta c t i l e s
Tilt
To u c h
Supplement Accessories Indicators
C72 /
w w
To g g l e s
Rockers
Keylocks Programmable Illuminated PB Pushbuttons
50,000 operations minimum for splashproof models; 100,000 for all other models
25,000 operations minimum for silver; 50,000 operations minimum for gold
silver with gold plating (code A)
SEA05LTR;中文规格书,Datasheet资料
Preliminary dataThis is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.February 2011Doc ID 18462 Rev 11/12SEA05LAdvanced constant voltage and constant current controllerwith very efficient LED pilot-lamp driverFeatures■Constant voltage and constant current control ■Very efficient LED pilot-lamp driver ■Wide operating V CC range (3.5 V - 36 V)■Low quiescent consumption: 250 µA ■Voltage reference: 2.5 V■Voltage control loop accuracy ± 0.5%■Current sense threshold: 50 mV ■Current control loop accuracy ± 4%■Low external component count ■Open-drain output stage ■SOT23-6L packageApplications■AC-DC adapter with LED pilot-lamp ■Battery chargers with LED pilot-lamp ■SMPS with LED pilot-lampDescriptionThe device is a highly integrated solution for SMPS applications, with an LED pilot-lamp requiring a dual control loop to perform CV (constant voltage) and CC (constant current) regulation.The IC allows very efficient LED pilot-lamp driving which helps to reduce the standby consumption of the SMPS. It integrates a voltage reference, two op-amps (with OR-ed open-drain outputs), a low-side current sensing circuit and an LED pilot-lamp driver pin implemented with an open-drain mosfet driven by square waveform with 12.5% duty cycle at 1 kHz that allows reducing LED consumption.The voltage reference, along with one op-amp, is the core of the voltage control loop. The current sensing circuit and the other op-amp make up the current control loop.The external components needed to complete the two control loops are:- a resistor divider that senses the output of the power supply and fixes the voltage regulation setpoint at the specified value- a sense resistor that feeds the current sensing circuit with a voltage proportional to the DC output current; this resistor determines the currentregulation setpoint and must be adequately rated in terms of power dissipation- the frequency compensation components (R-C networks) for both loops.The device is ideal for space-critical applications.Table 1.Device summaryOrder code Package Packing SEA05LTRSOT23-6LTape & reelContents SEA05LContents1Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1Voltage and current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.2Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3LD pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112/12Doc ID 18462 Rev 1SEA05L OperationDoc ID 18462 Rev 13/121 OperationTable 2.Absolute maximum ratingsSymbol Pin Parameter Value Unit V CC 6DC supply voltage –0.3 to 38V Vout 5Open-drain voltage –0.3 to V CCV Iout 5Max. sink current 20mA V LD 4Open-drain voltage –0.3 to V CCV I LD 4Max. sink current 15mA Isense 1Analog input –0.3 to V CC V Vctrl3Analog input–0.3 to V CC < 12(1)1.Vctrl cannot exceed V CC and cannot exceed 12 V.VTable 3.Thermal dataSymbol ParameterValue Unit R th j-amb Thermal resistance, junction-to-ambient 250°C/W Tj op Junction temperature operating range –40 to 150°CTstgStorage temperature–55 to 150Table 4.Pin functionsPin numberName Function1IsenseInverting input of the current loop op-amp. The pin is typically used for the current control loop, connecting it to the positive end of the current sense resistor through a decoupling resistor.2GNDGround. Return of the bias current of the device. 0 V reference for allvoltages. The pin has to be tied as close as possible to the ground output terminal of the converter to minimize load current effect on the voltage regulation setpoint.OperationSEA05L4/12Doc ID 18462 Rev 13VctrlInverting input of the voltage loop op-amp. The pin is typically used for the voltage control loop and is connected to the midpoint of a resistor divider that senses the output voltage.4LDOpen-drain output able to sink 5 mA (peak), driven by the internal oscillator at 1 kHz square waveform with 12.5% duty cycle. The internal mosfet starts to switch when V CC is above the turn-on threshold (typ. 3 V) and it is off (LD high impedance) when V CC is below the UVLO of the IC. The pin can be connected to an external LED pilot-lamp with a resistor in series in order to limit the LED current5OUTCommon open-drain output of the two internal op-amps. The pin, only able to sink current, is typically connected to the branch of the optocoupler's photodiode to transmit the error signal to the primary side.6V CCSupply voltage of the device. A small bypass capacitor (0.1 µF typ.) to GND, located as close to the IC pins as possible, might be useful to get a clean supply voltage.Table 4.Pin functions (continued)Pin numberName FunctionSEA05L OperationDoc ID 18462 Rev 15/12Table 5.Electrical characteristics (–25 C° < T j < 125 °C, V CC = 20 V; unless otherwise specified)Symbol ParameterTest conditionMin.Typ.Max.UnitDevice supply V CC Voltage operating range 3.536V I CCQuiescent current(Ictrl = Vsense = 0, OUT = open)250500µAVoltage control loop op-amp Gm v T ransconductance (sink current only)(1) 1 3.5S Vctrl Voltage reference default value (2)T j = 25 °C2.4882.5 2.512V IbiasInverting input bias current25nACurrent control loop Gm i T ransconductance (sink current only) (3) 1.57S V csth Current sense threshold at I(Iout) = 1 mA (4)485052mV IbiasNon-inverting input source current6µAOutput stageV OUTlow Low output level at 2 mA sink current 200400mVLED driver I LD LED driver sink current capability (peak)10mA f LD LED driver current modulation frequency 0.61 1.4kHz V LDlow Low output level at 5 mA sink current (internal mosfet on)450900mV I LD_LKGLED driver leakage current (internal mosfet off)0.5µA1.If the voltage on Vctrl (the negative input of the amplifier) is higher than the positive amplifier input, and it is increased by1mV, the sinking current at the output OUT will be increased by 3.5 mA.2.The internal voltage reference is set at 2.5 V. The voltage control loop precision takes into account the cumulative effects ofthe internal voltage reference deviation as well as the input offset voltage of the transconductance operational amplifier. The internal voltage reference is fixed by bandgap, and trimmed to 0.48 % accuracy at room temperature.3.When the inverting input at Isense is greater than 50 mV, and the voltage is increased by 1 mV, the sinking current at theoutput Out will be increased by 7 mA.4.The internal current sense threshold is triggered when the voltage on pin Isense is 50 mV. The current control loopprecision takes into account the cumulative effects of the internal voltage reference deviation as well as the input offset voltage of the transconductance operational amplifier.6/12Doc ID 18462 Rev 12 Application information2.1 Voltage and current controlVoltage controlThe voltage loop is controlled via a transconductance operational amplifier, the voltage divider R 1, R 2, and the optocoupler which is directly connected to the output. It is possible to choose the values of R 1 and R 2 resistors using Equation 1 and Equation 2:Equation 1Equation 2where V Ois the desired output voltage.As an example, with R 1 = 100 k Ω and R 2 = 15 k Ω V O = 19.17 V.Doc ID 18462 Rev 17/12Current controlThe current loop is controlled via a transconductance operational amplifier, the sense resistor R sense , and the optocoupler.The control equation verifies:Equation 3Equation 4where I Omax is the desired limited current, and V csth is the threshold voltage for the current control loop. As an example, with I omax = 1 A, V csth = 50 mV , then R sense = 50 m Ω.Note that the R sense resistor should be chosen, taking into account the maximum dissipation (P lim ) through it during full load operation.Equation 5As an example, with I Omax = 1 A and V csth = 50 mV , P lim = 50 mW.Therefore, for most adaptor and battery charger applications, a low-power resistor is suitable for the current sensing function.V csth threshold is achieved internally by a voltage divider tied to an internal precise voltage reference. Its midpoint is tied to the positive input of the current control operational amplifier, and its endpoint is connected to GND. The resistors of this voltage divider are matched to provide the best precision possible. The current sinking outputs of the two transconductance operational amplifiers are common (to the output of the IC). This makes an OR function which ensures that whenever the current or the voltage reaches excessively high values, the optocoupler is activated.The relationship between the controlled current and the controlled output voltage can be described with a square characteristic as shown in the following V/I output-power graph (with power supply of the device independent from the output voltage).csthO sense V I R =∗max maxlim O csth I V P ∗=2.2 CompensationThe voltage control transconductance operational amplifier can be fully compensated. Bothits output and negative input are directly accessible for external compensation components.functionpin2.3L DThe device provides a unique feature that allows highly efficient driving of an LED pilot-lamp.The main benefit of this new feature is to allow reducing the standby power consumption ofthe SMPS with the LED pilot-lamp.The LD pin is an open-drain output able to sink 5 mA (peak), driven by the internal oscillatorat 1 kHz (typ.) square waveform with 12.5% duty cycle (see Figure6). The internal mosfetstarts to switch when V CC is above the turn-on threshold (typ 3 V) and it is off (LD highimpedance) when V CC is below the UVLO of the IC.Connecting the LED pilot-lamp, with a resistor in series in order to limit the LED current, topin LD (as shown in Figure5) reduces the power consumption of the LED while keeping thesame driving peak current. The LED driving current modulation frequency of 1 kHz (typ.)eliminates the visual perception of flickering.8/12Doc ID 18462 Rev 1Doc ID 18462 Rev 19/12Package mechanical data SEA05L10/12Doc ID 18462 Rev 13 Package mechanical dataIn order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: . ECOPACK ® is an ST trademark.Note:Dimensions per JEDEC MO178ABTable 6.SOT23-6L (2.90 mm x 2.80 mm) package mechanical dataSymmm inchesMin Typ Max Min Typ MaxA 1.45 0.057 A1 0.00 0.15 0.000 0.006 A2 0.90 1.15 1.30 0.035 0.045 0.051b 0.30 0.50 0.012 0.020c 0.080.22 0.0030.009D 2.90 0.114E 2.80 0.110 E1 1.60 0.063 e 0.95 0.037 e1 1.900.075L 0.30 0.45 0.60 0.012 0.018 0.024 è 0° 4° 8° 0° 4° 8° N 66分销商库存信息: STMSEA05LTR。
OPR5911;中文规格书,Datasheet资料
Surface Mount Quad PhotodiodeOPR5911OPR5911carrier and designed for a variety of encoder and control applications. The single chip construction ensuresexcellent matching and very tight dimensional tolerances between active areas. The custom opaque package shields the photodiodes from stray light and can withstand multiple exposures to the most demanding soldering conditions, while the wraparound gold-plated solder pads offer exceptional storage and wetting characteristics.All cathodes in theOPR5911 are bonded together, which enables the elements to act in unison with limited external circuitry.See Application Bulletin 237 for handling instructions.Ordering InformationPart NumberReceiver Type# ofElementsResponsivity(mA/mW) Min. Reverse Voltage Min.Active Area(mm 2)PackagingOPR5911 Photodiode Array40.45 14 1.61 (each)Chip TrayApplications:• Encoder applications •Control applicationsPin # OPR59119 N. C. / N.C. 10 N. C. / N.C. 11 Common Cathode 12 Anode 4Pin #OPR59111Anode 12 Common Cathode3 N. C. / N.C. 4N. C. / N.C.Pin # OPR5911 5 Common Cathode 6 Anode 2 7 Anode 3 8 Common Cathode Warning : Front Window is pressure sensitive. Do not apply pressure or high vacuum to window.Surface Mount Quad Photodiode OPR5911Electrical Characteristics (T A = 25° C unless otherwise noted)SYMBOL PARAMETER MIN TYP MAX UNITS TEST CONDITIONSR Responsivity .45 - - A/W E e = 10 µW, λ = 890 nm, V = 0 V V BRReverse Breakdown Voltage14--VI R = 100 µAI D Reverse Dark Current - - 30 nA V R = 10 V C T Capacitance - 10 - pf V R = 10 V Lx WActive Area (per diode)-1.27-mm 2(1.0 mm x 1.0 mm)Absolute Maximum Ratings (T A = 25° C unless otherwise noted)Storage and Operating Temperature -55° C to +125° CReverse Breakdown Voltage14 V / minuteSolder reflow time within 5°C of peak temperature is 20 to 40 seconds (1) 250° CNotes:(1) Solder time less than 5 seconds at temperature extreme.Spectral ResponsivityR e l a t i v e R e s p o n s e (%)Wavelength (µm).4 .5 .6 .7 .9 1.0 1.1.8 10080604020分销商库存信息: OPTEK-TECHNOLOGY OPR5911。
VLA500-01;中文规格书,Datasheet资料
Powerex, Inc., 200 E. Hillis Street, Youngwood, Pennsylvania 15697-1800 (724) 925-7272Hybrid ICIGBT Gate Driver +DC/DC ConverterVLA500-011Rev. 2/08Description:VLA500-01 is a hybrid integrated circuit designed for driving IGBT modules. This device is a fully isolated gate drive circuit consist-ing of an optimally isolated gate drive amplifier and an isolated DC-to-DC converter. The gate driver provides an over-current protection function based on desaturation detection.Features:£ Built-in Isolated DC-to-DC Converter for Gate Drive£ SIP Outline Allows More Space on Mounting Area£ Built-in Short-Circuit Protection (With Fault Output)£ Variable Fall Time on Short- Circuit Protection£ Electrical Isolation Voltage Between Input and Output (2500 V rms for 1 Minute)£ TTL Compatible InputApplication:To drive IGBT modules for inverter or AC servo systems applications Recommended IGBT Modules:600V module up to 600A 1200V module up to 1400AOutline Drawing and Circuit Diagram Dimensions InchesMillimeters A 3.27 83.0 B 1.3 33.0 C 0.61 15.5 D 0.2 5.0 E 0.1 2.54 F 0.45 11.5 G0.184.5Note: All dimensions listed are maximums except E.VLA500-01Hybrid IC IGBT Gate Driver + DC/DC ConverterPowerex, Inc., 200 E. Hillis Street, Youngwood, Pennsylvania 15697-1800 (724) 925-72722Rev. 2/08Absolute Maximum Ratings, T a = 25°C unless otherwise specifiedCharacteristics Symbol VLA500-01 Units Supply Voltage, DCV D -1 ~ 16.5 Volts Input Signal Voltage (Applied between Pin 6 - 7, 50% Duty Cycle, Pulse Width 1ms) V i -1 ~ 7 Volts Output Voltage (When the Output Voltage is "H") V O V CC Volts OHP OLP Isolation Voltage (Sine Wave Voltage 60HZ, for 1 Minute)V ISO 2500 V rms Case Temperature1 (Surface Temperature Opto-coupler Location)*** T C1 85 °C Case Temperature2 (Surface Temperature Except Opto-coupler Location) T C2 100 °C Operating Temperature (No Condensation Allowable) T opr -20 to 60 °C Storage Temperature (No Condensation Allowable) T stg -25 to 100*°C Fault Output Current (Applied Pin 28) I FO 20 mA Input Voltage to Pin 30 (Applied Pin 30) V R3050 Volts Gate Drive Current (Average) I drive210**mAElectrical and Mechanical Characteristics, T a = 25°C unless otherwise specified, V D = 15V, R G = 2.2 W )Characteristics Symbol Test ConditionsMin. Typ. Max. Units Supply VoltageV D Recommended Range 14.2 15 15.8 Volts Pull-up Voltage on Input Side V IN Recommended Range 4.75 5 5.25 Volts "H" Input Current I IH Recommended Range 15.2 16 19 mA Switching Frequency f Recommended Range — — 20 kHz Gate Resistance R G Recommended Range1 — — W "H" Input CurrentI IH V IN = 5V — 16 — mA Gate Positive Supply Voltage V CC — 15.2 — 17.5 Volts Gate Negative Supply Voltage V EE —-6 — -11.5 Volts Gate Supply Efficiency E ta Load Current = 210mA60 75 — %E ta = (V CC + |V EE |) x 0.21 / (15 x I D ) x 100"H" Output Voltage V OH 10k W Connected Between Pin 23-20 14 15.3 16.5 Volts "L" Output Voltage V OL 10k W Connected Between Pin 23-20-5.5 — -11 Volts "L-H" Propagation Time t PLH I IH = 16mA 0.3 0.6 1 µs "L-H" Rise Time t r I IH = 16mA — 0.3 1 µs "H-L" Propagation Time t PHL I IH = 16mA 0.6 1 1.3 µs "H-L" Fall Timet fI IH = 16mA—0.31µsT C1 MEASUREMENT POINT (OPTO-COUPLER LOCATION)VLA500-01Hybrid IC IGBT Gate Driver + DC/DC ConverterPowerex, Inc., 200 E. Hillis Street, Youngwood, Pennsylvania 15697-1800 (724) 925-72723Rev. 2/080 100 300 200 400 500 600 800700CONNECTIVE CAPACIT ANCE, C trip , (pF) (Pin: 27 – 21)F A L L T I M E O N A C T I V I T Y O F S H O R T -C I R C U I T P R O T E C T I O N , t 1, t 2, (µs )t 1, t 2 VS. C s CHARACTERISTICS(TYPICAL) -20206040 80AMBIENT TEMPERA TURE, T a , (°C) V C C , |V E E |, (V O L T S )V CC , |V EE | VS. T a CHARACTERISTICS(TYPICAL) 00.050.100.20 0.150.25LOAD CURRENT, I O , (AMPERES) (Pin: 19 – 21, 22)V C C , |V E E |, (V O L T S )V CC , |V EE | VS. I O CHARACTERISTICS(TYPICAL)-200 20 60 40 80AMBIENT TEMPERA TURE, T a , (°C)C O N T R O L L ED T I ME D E T E C T S H O R T -C I R C U I T , t t r i p 1, t t r i p 2, (µs )t trip VS. T a CHARACTERISTICS(TYPICAL)-200 20 60 40 80 AMBIENT TEMPERA TURE, T a , (°C) P R O P A G A T I O N D E L A Y T I M E “L -H ”, t P L H , (µs ) P R O P A G A T I O N D E L A Y T I M E “H -L ”, t P H L , (µs )t PLH , t PHL VS. T a CHARACTERISTICS(TYPICAL)3.54.0 4.55.5 5.06.0 INPUT SIGNAL VOLT AGE, V I , (VOLTS) P R O P A G A T I O N D E L A Y T I M E “L -H ”, t P L H , (µs ) P R O P A G A T I O N D E L A Y T I M E “H -L ”, t P H L , (µs )t PLH , t PHL VS. V I CHARACTERISTICS(TYPICAL) Electrical and Mechanical Characteristics, T a = 25°C unless otherwise specified, V D = 15V, R G = 2.2 W )Characteristics Symbol Test ConditionsMin. Typ. Max. Units timer(Under Input Sign "L")FO Controlled Time Detect Short-Circuit 1 t trip1 Pin 30 : 15V and More, Pin 29 : Open — 2.8 — µs Controlled Time Detect Short-Circuit 2* t trip2 Pin 30 : 15V and More, Pin 29-21, 22 : 10pF—3.2—µs(Connective Capacitance)SC *Length of wiring from C trip to Pins 21, 22, and 29 must be less than 5cm.VLA500-01Hybrid IC IGBT Gate Driver +DC/DC ConverterPowerex, Inc., 200 E. Hillis Street, Youngwood, Pennsylvania 15697-1800 (724) 925-72724Rev. 2/08201086161814124214.014.515.515.016.016.517.0SUPPL Y VOLTAGE, VD, (VOLTS)VIN(PIN 6 TO 7)VO(PIN 23 TO 22)90%50%10%VCC,|VEE|,(VOLTS)V CC, |V EE|VS. V D CHARACTERISTICS(TYPICAL)0.250.200.150.050.10020406080AMBIENT TEMPERATURE, Ta, (°C)GATEDRIVECURRENT,Idrive,(AMPERES)T a VS. I drive CHARACTERISTICS(TYPICAL) 65757060554550SUPPL Y VOLT AGE, VD, (VOLTS)EFFICIENCY,E ta,(%)E ta,VS. V D CHARACTERISTICS(TYPICAL)SWITCHING TIME DEFINITIONS405080706040301020GA TE DRIVE CURRENT, Idrive, (AMPERES)EFFICIENCY,E ta,(%)E ta VS. I drive CHARACTERISTICS(TYPICAL)5987643120255010075125CONNECTIVE CAPACIT ANCE, Ctrip, (pF) (Pin: 29 – 21)CONTROLLEDTIMEDETECTSHORT-CIRCUIT,ttrip,(µs)t trip VS. C trip CHARACTERISTICS(TYPICAL)0.50.60.40.30.10.2LOAD CURRENT, IO, (AMPERES) (Pin: 19 – 21, 22)INPUTCURRENT,ID,(AMPERES)I D VS. I O CHARACTERISTICS(TYPICAL)1422201816121068-20020604080AMBIENT TEMPERA TURE, Ta, (°C)“H”OUTPUTVOLTAGE,VOH,(VOLTS)“L”OUTPUTVOLTAGE,|VOL|,(VOLTS)V OH, |V OL|VS. T a CHARACTERISTICS(TYPICAL)4VLA500-01Hybrid IC IGBT Gate Driver + DC/DC ConverterPowerex, Inc., 200 E. Hillis Street, Youngwood, Pennsylvania 15697-1800 (724) 925-72725Rev. 2/08Control IGBT MODULE +15V Common+5V FaultComponent Selection:Design Typical Value DescriptionD1 0.5AV CE detection diode – fast recovery, V rrm > V CES of IGBT being used (Note 1)DZ130V, 0.5W Detect input pin surge voltage protection (Note 2)DZ2, DZ3 18V, 1.0W Gate surge voltage protectionC1 150µF, 35VV D supply decoupling – Electrolytic, long life, low Impedance, 105°C (Note 3)C2, C3 100-1000µF, 35V DC/DC output filter – Electrolytic, long life, low Impedance, 105°C (Note 3,4)C4 0.01µF Fault feedback signal noise filterCS 0-1000pF Adjust soft shutdown – Multilayer ceramic or film (see application note)C trip 0-200pFAdjust trip time – Multilayer ceramic or film (see application note)R1 4.7k Ω, 0.25W Fault sink current limiting resistorR2 3.3k Ω, 0.25W Fault signal noise suppression resistor R3 1k Ω, 0.25W Fault feedback signal noise filter R4 4.7k Ω, 0.25W Fault feedback signal pull-upOP1 NEC PS2501 Opto-coupler for fault feedback signal isolationB1CMOS Buffer74HC04 or similar – Must actively pull high to maintain noise immunityNotes:(1) The V CE detection diode should have a blocking voltage rating equal to or greater than the V CES of the IGBTbeing driven. Recovery time should be less than 200ns to prevent application of high voltage to Pin 30.(2) DZ1 is necessary to protect Pin 30 of the driver from voltage surges during the recovery of D1.(3) Power supply input and output decoupling capacitors should be connected as close as possible to the pins of the gate driver.(4) DC-to-DC converter output decoupling capacitors must be sized to have appropriate ESR and ripple current capability for the IGBT being driven.Application CircuitVLA500-01Hybrid IC IGBT Gate Driver + DC/DC ConverterPowerex, Inc., 200 E. Hillis Street, Youngwood, Pennsylvania 15697-1800 (724) 925-72726Rev. 2/08General DescriptionThe VLA500-01 is a hybrid integrated circuit designed toprovide gate drive for high power IGBT modules. Thiscircuit has been optimized for use with Powerex NF- Series and A-Series IGBT modules. However, the output characteristics are compatible with most MOSgated power devices. The VLA500-01 features a com-pact single-in-line package design. The upright mount-ing minimizes required printed circuit board space toallow efficient and flexible layout. The VLA500-01converts logic level control signals into fully isolated+15V/-8V gate drive with up to12A of peak drive current.Isolated drive power is provided by a built in DC-to-DCconverter and control signal isolation is provided by anintegrated high speed opto-coupler. Short circuit protec-tion is provided by means of destauration detection.Short Circuit Protection Figure 1 shows a block diagram of a typical desatura-tion detector. In this circuit, a high voltage fast recovery diode (D1) is connected to the IGBT’s collector to moni-tor the collector to emitter voltage. When the IGBT is inthe off state, V CE is high and D1 is reverse biased. WithD1 off the (+) input of the comparator is pulled up tothe positive gate drive power supply (V+) which is nor-mally +15V. When the IGBT turns on, the comparators(+) input is pulled down by D1 to the IGBT’s V CE(sat).The (-) input of the comparator is supplied with a fixedvoltage (V trip ). During a normal on-state condition thecomparator’s (+) input will be less than V trip and it’s out-put will be low. During a normal off-state condition the comparator’s (+) input will be larger than V trip and it’s out-put will be high. If the IGBT turns on into a short circuit, the high current will cause the IGBT’s collector-emitter voltage to rise above V trip even though the gate of theIGBT is being driven on. This abnormal presence of high V CE when the IGBT is supposed to be on is often called desaturation . Desaturation can be detected bya logical AND of the driver’s input signal and the com-parator output. When the output of the AND goes high a short circuit is indicated. The output of the AND can be used to command the IGBT to shut down in order to protect it from the short circuit. A delay (t trip ) must be provided after the comparator output to allow for the nor-mal turn on time of the IGBT. The t trip delay is set sothat the IGBT's V CE has enough time to fall below V tripduring normal turn on switching. If t trip is set too short,erroneous desaturation detection will occur. The maxi-mum allowable t trip delay is limited by the IGBT’s short circuit withstanding capability. In typical applicationsusing Powerex IGBT modules the recommended limit is10µs.Operation of the VLA500-01 Desaturation Detector The Powerex VLA500-01 incorporates short circuitprotection using desaturation detection as describedabove. A flow chart for the logical operation of the short-circuit protection is shown in Figure 2. When a desatura-tion is detected the hybrid gate driver performs a softshutdown of the IGBT and starts a timed (t timer ) 1.5mslock out. The soft turn-off helps to limit the transientvoltage that may be generated while interrupting thelarge short circuit current flowing in the IGBT. During thelock out the driver pulls Pin 28 low to indicate the faultstatus. Normal operation of the driver will resume afterthe lock-out time has expired and the control input signalreturns to its off state.Adjustment of Trip Time The VLA500-01 has a default short-circuit detectiontime delay (t trip ) of approximately 3µs. This will preventerroneous detection of short-circuit conditions as longas the series gate resistance (R G ) is near the mini-mum recommended value for the module being used.The 3µs delay is appropriate for most applications soadjustment will not be necessary. However, in some lowfrequency applications it may be desirable to use alarger series gate resistor to slow the switching ofthe IGBT, reduce noise, and limit turn-off transientINPUT Figure 1. Desaturation DetectorVLA500-01Hybrid IC IGBT Gate Driver + DC/DC ConverterPowerex, Inc., 200 E. Hillis Street, Youngwood, Pennsylvania 15697-1800 (724) 925-72727Rev. 2/08voltages. When R G is increased, the switching delay time of the IGBT will also increase. If the delay be-comes long enough so that the voltage on the detect Pin 30 is greater than V SC at the end of the t trip delay the driver will erroneously indicate that a short circuit has occurred. To avoid this condition the VLA500-01 has provisions for extending the t trip delay by connecting a capacitor (C trip ) between Pin 29 and V EE (Pins 21 and 22). A curve showing the effect of adding C trip on time is given in the characteristic data section of this data sheet. The waveform defining trip time (t trip ) is shown in Figure 3. If t trip is extended care must be exercised not to exceed the short-circuit withstanding capability of the IGBT module. Normally this will be satisfied for Powerex NF and A-Series IGBT modules as long as the total shut-down time does not exceed 10µs.Adjustment of Soft Shutdown SpeedAs noted above the VLA500-01 provides a soft turn-off when a short circuit is detected in order to help limit the transient voltage surge that occurs when large short circuit currents are interrupted. The default shutdown speed will work for most applications so adjustment is usually not necessary. In this case C S can be omitted. In some applications using large modules or parallel connected devices it may be helpful to make the shut-down even softer. This can be accomplished by connecting a capacitor (C S ) at Pin 27. A curve showing the effect of C S on short circuit fall time (t 1, t 2) is given in the characteristic data section of this data sheet. The waveform defining the fall time characteristics is shown in Figure 3.Figure 2. VLA500-01 Desaturation DetectorV Figure 3. Adjustment of t trip and Slow Shutdown Speed分销商库存信息: POWEREXVLA500-01。
LS变频器说明书iS5-中文说明书
安全注意事项
始终遵守安全注意事项可以防止意外事故及潜在危险的发生。
在本使用手册中，安全等级分类如下：
危险 注意
不正确的操作可能导致严重的人身伤害或死亡。 不正确的操作可能导致轻微的人身伤害或物体硬件的损坏。
在本说明书中，全篇使用以下两个图标以使你能明白安全注意事项。
一般性注意事项
本安装手册中大多数图表在表示时，变频器没有安装断路器，外壳或部分开路。变频器决不会像这样运 行。当运行变频器时，总是安装外壳与断路器的，并遵守安装手用户选择指南 (iS5 规范) ...................................................................................................................7
位，否则可能发生意外事故。
不要修改或变动变频器内部任何东西。 变频器的电子热保护功能可能无法保护电机。 在变频器的输入侧不要使用电磁式交流接触器作为变频器频繁启停的开关。 使用噪声滤波器来降低变频器产生的电磁干扰的影响，否则，附近的电子设备可能会受到干扰。 如果输入电压不平衡，需要安装交流电抗器。来自变频器的潜在高次谐波可能会引起电力电容器和发生
试运行
0.0 在运行前检查所有参数，根据负载类型修改参数值。 1.0 始终在本说明书标定的电压范围内使用，否则，可能导致变频器损坏。
操作防范
当选择自动重启动功能时，由于电机会在故障停止后突然再启动，所以应远离设备。 操作面板上的“STOP”键仅在相应功能设置已经被设定时才有效，特殊情况应准备紧急停止开关。 如果故障复位是使用外部端子进行设定，将会发生突然启动。请预先检查外部端子信号是否处于关断
CRD35L01;中文规格书,Datasheet资料
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CRD35L01
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................................. 4 1.1 CS35L01 Hybrid Class-D Amplifier .................................................................................................. 4 1.2 Power Supply ................................................................................................................................... 4 1.3 Operational Modes ........................................................................................................................... 4 1.4 Shutdown Control ............................................................................................................................ 4 1.5 Amplifier Gain .................................................................................................................................. 4 1.5.1 Optional Input Gain Adjustment Resistors .............................................................................. 4 1.6 Differential Analog Inputs ................................................................................................................. 5 1.7 Speaker Outputs .............................................................................................................................. 5 1.7.1 Optional Speaker Output EMI Filter Components ................................................................... 5 2. GROUNDING AND POWER SUPPLY DECOUPLING .......................................................................... 6 2.1 Power Supply Decoupling ................................................................................................................ 6 2.2 Electromagnetic Interference (EMI) ................................................................................................. 6 2.2.1 Suppression of EMI at the Source ........................................................................................... 6 3. SYSTEM CONNECTORS AND JUMPERS ............................................................................................ 7 4. CRD SCHEMATIC .................................................................................................................................. 8 4.1 Bill of Materials ................................................................................................................................. 9 5. CRD LAYOUT ....................................................................................................................................... 10 6. REVISION HISTORY ............................................................................................................................ 14
SY58016LMI;中文规格书,Datasheet资料
SY58016L3.3V, 10Gbps Differential CML Line Driver/Receiver with Internal TerminationMLF and Micro LeadFrame are trademarks of Micrel, Inc.Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • General DescriptionThe SY58016L is a high-speed, current mode logic (CML) differential receiver. It is ideal for interfacing with high frequency sources. It can be used as a Line Receiver, Line Driver, and Limiting Amplifier. The device can be operated from DC to 10Gbps. The input incorporates internal termination resistors, and directly interfaces to a CML logic signal. The output is CML compatible, and includes 50Ω load resistors.Data sheets and support documentation can be found on Micrel’s web site at: .Features• Accepts up to 10.7Gbps data • < 45ps edge rate • Gain ≥ 4V/V• CML/PECL differential inputs • CML outputs • Internal 50Ω input termination • Internal 50Ω output load resistors• Available in die or 16-pin (3mm x 3mm) MLF packageApplications• Backplane buffering• OC-3/OC-192 SONET clock or data distribution/driver • All GigE clock or data distribution/driver • Fibre Channel distribution/driver________________________________________________________________________________________________Package/Ordering InformationPart NumberPackage TypeOperating RangePackage MarkingSY58016LXC DIE 25°C — SY58016LMG MLF-16 Industrial 016L SY58016LMGTR* MLF-16 Industrial016L*Tape and ReelPin DescriptionPin NumberPin NamePin Function1.4D, /D CML, PECL differential inputs with internal 50Ω pull-up resistors.2,3,10,11 VTR Transmission Line Return: Normally connected to the most positive supply. 6, 7, 14, 15 Exposed pad VEE Most negative supply. Exposed pad to be at the same electrical potential as VEE pins.12, 9 Q, /Q CML differential outputs with internal 50Ω pull-up resistors. 5, 8, 13, 16VCCPositive power supply: +3.3V nominal.________________________________________________________________________________________________Functional Block DiagramTypical PerformanceAbsolute Maximum Ratings (1)Supply Voltage (V CC —V EE )..........................................+4.0V Output Voltage (V OUT ).................................Max. V CC +0.5V ............................................................Min. V CC to -1.0V Maximum Input Current (I IN )......................................±25mA Maximum Output Current (I OUT )................................±25mA Lead Temperature (Soldering, 10 sec.).....................220°COperating Ratings (2)Supply Voltage (V IN ) Input Voltage (V CC =0V).........................-1.0V to +0.5V Input Voltage (V EE =0V).............V CC -1.0V to V CC +0.5V Ambient Temperature (T A )...........................-40°C to +85°C Storage Temperature (T S ).........................-65°C to +150°C Package Thermal ResistanceInput Voltage (V CC =0V)................................-1.0V to +0.5V MLF (θJA ) Still Air...........................................................60°C/W 500lfpm..........................................................54°C/W MLF (ψJB) (4)32°Notes:1.Permanent device damage may occur if Absolute Maximum Ratings are exceeded. This is a stress rating only, and functional operation is notimplied at conditions other than those detailed in the operational sections of this data sheet. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.2. The data sheet limits are not guaranteed if the device is operated beyond the operation ratings.3. The device is guaranteed to meet the CD specifications, show in the table above, after thermal equilibrium has been established. The device is tested in a socket such that transverse airflow of ≥500lfpm is maintained.4.Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.DC Electrical Characteristics (4)V EE = GND; V CC =3.3V ±10%.Symbol ParameterCondition Min Typ MaxUnitsI EE Power Supply Current — 50 75 mA R IN Input Resistance 40 50 60 Ω R OUT Output Source Impedance40 50 60Ω V IH Input HIGH Voltage V CC – 0.9 — V CC VV IL Input LOW Voltage V CC – 1.0 — V CC – 0.1 V V OH Output HIGH VoltageV CC – 0.040V CC – 0.010V CC VV OL Output LOW Voltage (1) — V CC – 0.400V CC – 0.325VV OUT(swing)Output Voltage Swing(1)325 400 — mVp-pNote:1. 50Ω output load and input swing is more than 100mVp-p. See Figure 1 for Output Swing definition.Input/Output SwingFigure 1. Input/Output SwingAC Electrical CharacteristicsSymbol Parameter Condition Min Typ Max UnitsfMAX Maximum Data Rate 10.7 — — Gbps t PLH t PHL Propagation Delay—100150psRandom Jitter (1) — — 1.5 ps (rms)t JITTER Deterministic Jitter (2) — — 15 ps (pk-pk) V IN Minimum Input Swing (3) 100 — — mVp-pt r, t fOutput Rise/Fall times (20% to 80%)(4)— 30 45 psNotes:1. Measured with a K28.7 comma detect character pattern, measured at 10Gbps. See Figure 2: Eye Diagram.2. Measured with a K28/5 pattern 223-1PRBS pattern at 10Gbps.3.Minimum input swing for which AC parameters are guaranteed. See Figure 1. Reduced input swing will impact maximum data rate and the resulting eye pattern.4. 50Ω load and input swing is more than 100mVp-p.Eye DiagramFigure 2. Eye Diagram16 LEAD Micro LeadFrame™ (MLF-16)分销商库存信息: MICRELSY58016LMI。
PBLS2021D,115;中文规格书,Datasheet资料
1.Product profile1.1General descriptionPNP low V CEsat Breakthrough In Small Signal (BISS) transistor and NPN Resistor-Equipped T ransistor (RET) in a SOT457(SC-74) small Surface-Mounted Device (SMD)plastic package.1.2FeaturesI Low V CEsat (BISS) and resistor-equipped transistor in one package I Low threshold voltage (<1V) compared to MOSFET I Space-saving solutionI Reduction of component count IAEC-Q101 qualified1.3ApplicationsI Supply line switches I Battery charger switchesI High-side switches for LEDs, drivers and backlights IPortable equipment1.4Quick reference data[1]Pulse test: t p ≤300µs;δ≤0.02.PBLS2021D20 V , 1.8 A PNP BISS loadswitchRev. 02 — 6 September 2009Product data sheetTable 1.Quick reference data Symbol ParameterConditions Min Typ Max Unit TR1; PNP low V CEsat transistorV CEO collector-emitter voltage open base--−20V I C collector current --−1.8A I CM peak collector current single pulse;t p ≤1ms --−3A R CEsatcollector-emitter saturation resistanceI C =−1.8A;I B =−100mA [1]-78117m ΩTR2; NPN resistor-equipped transistor V CEO collector-emitter voltage open base--50V I O output current --100mA R1bias resistor 1 (input) 1.54 2.2 2.86k ΩR2/R1bias resistor ratio0.811.22.Pinning information3.Ordering information4.MarkingTable 2.Pinning Pin Description Simplified outlineGraphic symbol1base TR12input (base) TR23output (collector) TR24GND (emitter) TR25collector TR16emitter TR1132456654123R2TR1TR2R1006aab506Table 3.Ordering informationType numberPackage NameDescriptionVersion PBLS2021DSC-74plastic surface-mounted package (TSOP6); 6leadsSOT457Table 4.Marking codesType number Marking code PBLS2021DKA5.Limiting values[1]Device mounted on an FR4Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.[2]Device mounted on an FR4PCB, single-sided copper, tin-plated, mounting pad for collector 1cm 2.[3]Device mounted on a ceramic PCB, Al 2O 3, standard footprint.Table 5.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol ParameterConditions Min Max Unit TR1; PNP low V CEsat transistorV CBO collector-base voltage open emitter -−20V V CEO collector-emitter voltage open base -−20V V EBO emitter-base voltage open collector -−5V I C collector current -−1.8A I CM peak collector current single pulse;t p ≤1ms-−3A I B base current -−300mA I BM peak base current single pulse;t p ≤1ms -−1A P tottotal power dissipationT amb ≤25°C[1]-370mW [2]-480mW [3]-630mW TR2; NPN resistor-equipped transistor V CBO collector-base voltage open emitter -50V V CEO collector-emitter voltage open base -50V V EBO emitter-base voltage open collector-10V V Iinput voltage positive -+12V negative-−10V I O output current -100mA I CM peak collector current single pulse;t p ≤1ms -100mA P tottotal power dissipationT amb ≤25°C[1][2][3]-200mWPer device P tottotal power dissipationT amb ≤25°C[1]-480mW [2]-590mW [3]-760mW T j junction temperature -150°C T amb ambient temperature −55+150°C T stgstorage temperature−65+150°C6.Thermal characteristics[1]Device mounted on an FR4PCB, single-sided copper, tin-plated and standard footprint.[2]Device mounted on an FR4PCB, single-sided copper, tin-plated, mounting pad for collector 1cm 2.[3]Device mounted on a ceramic PCB, Al 2O 3, standard footprint.(1)Ceramic PCB, Al 2O 3, standard footprint (2)FR4PCB, mounting pad for collector 1cm 2(3)FR4PCB, standard footprintFig 1.Per device: Power derating curvesT amb (°C)−751751252575−25006aab5074006002008001000P tot (mW)0(1)(2)(3)Table 6.Thermal characteristics Symbol ParameterConditionsMin Typ Max Unit Per device R th(j-a)thermal resistance from junction to ambientin free air[1]--260K/W [2]--211K/W [3]--165K/W R th(j-sp)thermal resistance from junction to solder point--100K/WFR4PCB, standard footprintFig 2.TR1(PNP): Transient thermal impedance from junction to ambient as a function of pulse duration;typical valuesFR4PCB, mounting pad for collector 1cm 2Fig 3.TR1(PNP): Transient thermal impedance from junction to ambient as a function of pulse duration;typical values006aab508101102103Z th(j-a)(K/W)10−110−51010−210−410210−1t p (s)10−31031δ = 10.750.500.330.100.050.020.0100.20006aab509101102103Z th(j-a)(K/W)10−110−51010−210−410210−1t p (s)10−31031δ = 10.750.500.330.100.050.020.010.207.CharacteristicsCeramic PCB, Al 2O 3, standard footprintFig 4.TR1(PNP): Transient thermal impedance from junction to ambient as a function of pulse duration;typical values006aab510101102103Z th(j-a)(K/W)10−110−51010−210−410210−1t p (s)10−31031δ = 10.750.500.330.100.050.020.010.20Table 7.CharacteristicsT amb =25°C unless otherwise specified.Symbol ParameterConditionsMin Typ Max Unit TR1; PNP low V CEsat transistorI CBOcollector-base cut-off current V CB =−20V; I E =0A --−100nA V CB =−20V; I E =0A;T j =150°C--−50µA I CES collector-emitter cut-off current V CE =−16V; V BE =0V --−100nA I EBO emitter-base cut-off current V EB =−5V; I C =0A --−100nAh FEDC current gainV CE =−2V; I C =−100mA 220420-V CE =−2V; I C =−500mA [1]220410-V CE =−2V; I C =−1A [1]200320-V CE =−2V; I C =−1.8A[1]160260-V CEsatcollector-emitter saturation voltageI C =−0.5A; I B =−50mA [1]-−45−70mV I C =−1A; I B =−50mA [1]-−85−130mV I C =−1A; I B =−100mA [1]-−80−120mV I C =−1.8A; I B =−100mA[1]-−140−210mV R CEsat collector-emittersaturation resistance I C =−1A; I B =−100mA [1]-80120m ΩI C =−1.8A; I B =−100mA [1]-78117m ΩV BEsatbase-emittersaturation voltageI C =−0.5A; I B =−50mA [1]-−0.85−1V I C =−1.8A; I B =−100mA[1]-−0.93−1.1VV BEon base-emitterturn-on voltageV CE=−10V; I C=−1A [1]-−0.73−1.1Vt d delay time V CC=−10V; I C=−1A;I Bon=−50mA;I Boff=50mA -17-nst r rise time-33-ns t on turn-on time-50-ns t s storage time-270-ns t f fall time-60-ns t off turn-off time-330-ns f T transition frequency I C=−50mA; V CE=−10V;f=100MHz-130-MHzC c collector capacitance V CB=−10V; I E=i e=0A;f=1MHz-45-pF TR2; NPN resistor-equipped transistorI CBO collector-base cut-offcurrentV CB=50V; I E=0A--100nAI CEO collector-emittercut-off current V CE=30V; I B=0A--1µA V CE=30V; I B=0A;T j=150°C--50µAI EBO emitter-base cut-offcurrentV EB=5V; I C=0A--2mA h FE DC current gain V CE=5V; I C=20mA30--V CEsat collector-emittersaturation voltageI C=10mA; I B=0.5mA--150mV V I(off)off-state input voltage V CE=5V; I C=1mA- 1.20.5V V I(on)on-state input voltage V CE=0.3V; I C=20mA2 1.6-V R1bias resistor1 (input) 1.54 2.2 2.86kΩR2/R1bias resistor ratio0.81 1.2C c collector capacitance V CB=10V; I E=i e=0A;f=1MHz -- 2.5pFTable 7.Characteristics …continuedT amb=25°C unless otherwise specified.Symbol Parameter Conditions Min Typ Max Unit[1]Pulse test: t p≤300µs;δ≤0.02.V CE =−2V (1)T amb =100°C (2)T amb =25°C (3)T amb =−55°CT amb =25°CFig 5.TR1(PNP): DC current gain as a function of collector current; typical valuesFig 6.TR1(PNP): Collector current as a function of collector-emitter voltage; typical valuesV CE =−2V (1)T amb =−55°C (2)T amb =25°C (3)T amb =100°CI C /I B =20(1)T amb =−55°C (2)T amb =25°C (3)T amb =100°CFig 7.TR1(PNP): Base-emitter voltage as a function of collector current; typical valuesFig 8.TR1(PNP): Base-emitter saturation voltage as a function of collector current; typical values006aab511400200600800h FE0I C (mA)−10−1−104−103−1−102−10(1)(2)(3)V CE (V)0.0−2.0−1.5−0.5−1.0006aab512−1−2−3I C (A)0I B (mA) = −16.0−12.8−14.4−11.2−9.6−8.0−4.8−6.4−3.2−1.6006aab513−0.6−0.8−0.4−1.0−1.2V BE (V)−0.2I C (mA)−10−1−104−103−1−102−10(1)(2)(3)006aab514−0.6−0.8−0.4−1.0−1.2V BEsat (V)−0.2I C (mA)−10−1−104−103−1−102−10(1)(2)(3)I C /I B =20(1)T amb =100°C (2)T amb =25°C (3)T amb =−55°CT amb =25°C (1)I C /I B =100(2)I C /I B =50(3)I C /I B =10Fig 9.TR1(PNP): Collector-emitter saturation voltage as a function of collector current;typical valuesFig 10.TR1(PNP): Collector-emitter saturationvoltage as a function of collector current;typical valuesI C /I B =20(1)T amb =100°C (2)T amb =25°C (3)T amb =−55°CT amb =25°C (1)I C /I B =100(2)I C /I B =50(3)I C /I B =10Fig 11.TR1(PNP): Collector-emitter saturationresistance as a function of collector current;typical values Fig 12.TR1(PNP): Collector-emitter saturationresistance as a function of collector current;typical values006aab515−10−1−10−2−1V CEsat (V)−10−3I C (mA)−10−1−104−103−1−102−10(1)(2)(3)006aab516−10−1−10−2−1V CEsat (V)−10−3I C (mA)−10−1−104−103−1−102−10(1)(2)(3)I C (mA)−10−1−104−103−1−102−10006aab517110−110210103R CEsat (Ω)10−2(1)(2)(3)I C (mA)−10−1−104−103−1−102−10006aab518110−110210103R CEsat (Ω)10−2(1)(3)(2)V CE =5V (1)T amb =150°C (2)T amb =25°C (3)T amb =−40°CFig 13.TR2(NPN): DC current gain as a function of collector current; typical valuesV CE =0.3V (1)T amb =−40°C (2)T amb =25°C (3)T amb =100°CV CE =5V (1)T amb =−40°C (2)T amb =25°C (3)T amb =100°CFig 14.TR2(NPN): On-state input voltage as afunction of collector current; typical values Fig 15.TR2(NPN): Off-state input voltage as afunction of collector current; typical valuesI C (mA)10−1102101006aaa01510210103h FE1(3)(2)(1)I C (mA)10−1102101006aaa016101102V I(on)(V)10−1(1)(3)(2)006aaa017I C (mA)10−210110−1110V I(off)(V)10−1(1)(2)(3)分销商库存信息: NXPPBLS2021D,115。