M12L128168A-5T中文资料
LM78M12中文资料
LM78M12中⽂资料LM341/LM78MXX Series3-Terminal Positive Voltage RegulatorsGeneral DescriptionThe LM341and LM78MXX series of three-terminal positive voltage regulators employ built-in current limiting,thermal shutdown,and safe-operating area protection which makes them virtually immune to damage from output overloads.With adequate heatsinking,they can deliver in excess of 0.5A output current.Typical applications would include local (on-card)regulators which can eliminate the noise and de-graded performance associated with single-point regulation.Featuresn Output current in excess of 0.5A n No external componentsn Internal thermal overload protection n Internal short circuit current-limitingn Output transistor safe-area compensationnAvailable in TO-220,TO-39,and TO-252D-PAK packagesn Output voltages of 5V,12V,and 15VConnection DiagramsTO-39Metal Can Package (H)DS010484-5Bottom ViewOrder Number LM78M05CH,LM78M12CH or LM78M15CHSee NS Package Number H03ATO-220Power Package (T)DS010484-6Top ViewOrder Number LM341T-5.0,LM341T-12,LM341T-15,LM78M05CT,LM78M12CT or LM78M15CTSee NS Package Number T03BTO-252DS010484-19Top ViewOrder Number LM78M05CDT See NS Package Number TD03BJuly 1999LM341/LM78MXX Series 3-Terminal Positive Voltage Regulators1999National Semiconductor Corporation /doc/96ef4d46852458fb770b5641.htmlAbsolute Maximum Ratings(Note1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Lead Temperature(Soldering,10seconds)TO-39Package(H)300?C TO-220Package(T)260?C Storage Temperature Range?65?C to+150?C Operating Junction TemperatureRange?40?C to+125?C Power Dissipation(Note2)Internally Limited Input Voltage5V≤V O≤15V35V ESD Susceptibility TBDElectrical CharacteristicsLimits in standard typeface are for T J=25?C,and limits in boldface type apply over the?40?C to+125?C operating temperature range.Limits are guaranteed by production testing or correlation techniques using standard Statistical Quality Control(SQC) methods.LM341-5.0,LM78M05CUnless otherwise specified:V IN=10V,C IN=0.33µF,C O=0.1µFSymbol Parameter Conditions Min Typ Max Units V O Output Voltage I L=500mA 4.8 5.0 5.2V5mA≤I L≤500mA 4.75 5.0 5.25P D≤7.5W,7.5V≤V IN≤20VV R LINE Line Regulation7.2V≤V IN≤25V I L=100mA50mVI L=500mA100V R LOAD Load Regulation5mA≤I L≤500mA100I Q Quiescent Current I L=500mA410.0mA ?I Q Quiescent Current Change5mA≤I L≤500mA0.57.5V≤V IN≤25V,I L=500mA 1.0V n Output Noise Voltage f=10Hz to100kHz40µVElectrical CharacteristicsLimits in standard typeface are for T J=25?C,and limits in boldface type apply over the?40?C to+125?C operating temperature range.Limits are guaranteed by production testing or correlation techniques using standard Statistical Quality Control(SQC) methods.(Continued)LM341-12,LM78M12CUnless otherwise specified:V IN=19V,C IN=0.33µF,C O=0.1µFSymbol Parameter Conditions Min Typ Max UnitsV O Output Voltage I L=500mA11.51212.5V5mA≤I L≤500mA11.41212.6P D≤7.5W,14.8V≤V IN≤27VV R LINE Line Regulation14.5V≤V IN≤30V I L=100mA120mVI L=500mA240V R LOAD Load Regulation5mA≤I L≤500mA240I Q Quiescent Current I L=500mA410.0mAI Q Quiescent Current Change5mA≤I L≤500mA0.514.8V≤V IN≤30V,I L=500mA 1.0V n Output Noise Voltage f=10Hz to100kHz75µVRipple Rejection f=120Hz,I L=500mA69dBV IN Input Voltage Required I L=500mA17.6V to Maintain Line RegulationV O Long Term Stability I L=500mA60mV/khrs Note1:Absolute maximum ratings indicate limits beyond which damage to the component may occur.Electrical specifications do not apply when operating the de-vice outside of its rated operating conditions.Note2:The typical thermal resistance of the three package types is:T(TO-220)package:θ(JA)=60?C/W,θ(JC)=5?C/WH(TO-39)package:θ(JA)=120?C/W,θ(JC)=18?C/WDT(TO-252)package:θ(JA)=92?C/W,θ(JC)=10?C/W3/doc/96ef4d46852458fb770b5641.htmlSchematic DiagramDS010484-1 /doc/96ef4d46852458fb770b5641.html 4 Typical Performance CharacteristicsPeak Output CurrentDS010484-10Ripple RejectionDS010484-11Ripple RejectionDS010484-12Dropout VoltageDS010484-13Output Voltage(Normalizedto1V at T J=25?C)DS010484-14Quiescent CurrentDS010484-15/doc/96ef4d46852458fb770b5641.html 5Typical Performance Characteristics(Continued)Design ConsiderationsThe LM78MXX/LM341XX fixed voltage regulator series has built-in thermal overload protection which prevents the de-vice from being damaged due to excessive junction tem-perature.The regulators also contain internal short-circuit protection which limits the maximum output current,and safe-area pro-tection for the pass transistor which reduces the short-circuit current as the voltage across the pass transistor is in-creased.Although the internal power dissipation is automatically lim-ited,the maximum junction temperature of the device must be kept below +125?C in order to meet data sheet specifica-tions.An adequate heatsink should be provided to assure this limit is not exceeded under worst-case operating condi-tions (maximum input voltage and load current)if reliable performance is to be obtained).1.0Heatsink ConsiderationsWhen an integrated circuit operates with appreciable cur-rent,its junction temperature is elevated.It is important to quantify its thermal limits in order to achieve acceptable per-formance and reliability.This limit is determined by summing the individual parts consisting of a series of temperature rises from the semiconductor junction to the operating envi-ronment.A one-dimension steady-state model of conduction heat transfer is demonstrated in The heat generated at thedevice junction flows through the die to the die attach pad,through the lead frame to the surrounding case material,to the printed circuit board,and eventually to the ambient envi-ronment.Below is a list of variables that may affect the ther-mal resistance and in turn the need for a heatsink.R θJC (Component Variables)R θCA (Application Variables)Leadframe Size &Material Mounting Pad Size,Material,&LocationNo.of Conduction Pins Placement of Mounting Pad Die SizePCB Size &Material Die Attach MaterialTraces Length &WidthMolding Compound Size and MaterialAdjacent Heat Sources Volume of Air Air FlowAmbient Temperature Shape of Mounting PadQuiescent CurrentDS010484-16Output ImpedanceDS010484-17Line Transient Response DS010484-7Load Transient ResponseDS010484-8/doc/96ef4d46852458fb770b5641.html6Design Considerations(Continued)The LM78MXX/LM341XX regulators have internal thermal shutdown to protect the device from over-heating.Under all possible operating conditions,the junction temperature of the LM78MXX/LM341XX must be within the range of 0?C to 125?C.A heatsink may be required depending on the maxi-mum power dissipation and maximum ambient temperature of the application.To determine if a heatsink is needed,the power dissipated by the regulator,P D ,must be calculated:I IN =I L +I GP D =(V IN ?V OUT )I L +V IN I Gshows the voltages and currents which are present in the circuit.The next parameter which must be calculated is the maxi-mum allowable temperature rise,T R (max):θJA =TR (max)/P D If the maximum allowable value for θJA ?C/w is found to be ≥60?C/W for TO-220package or ≥92?C/W for TO-252pack-age,no heatsink is needed since the package alone will dis-sipate enough heat to satisfy these requirements.If the cal-culated value for θJA fall below these limits,a heatsink is required.As a design aid,Table 1shows the value of the θJA of TO-252for different heatsink area.The copper patterns that we used to measure these θJA are shown at the end of the Application Note Section.reflects the same test results as what are in the Table 1shows the maximum allowable power dissipation vs.ambi-ent temperature for theTO-252device.shows the maximum allowable power dissipation vs.copper area (in 2)for the TO-252device.Please see AN1028for power enhancement techniques to be used with TO-252package.TABLE 1.θJA Different Heatsink AreaLayoutCopper AreaThermal Resistance Top Sice (in 2)*Bottom Side (in 2)(θJA ,?C/W)TO-25210.0123010320.06608730.306040.5305450.7605261047700.284800.470900.6631000.857110157120.0660.06689130.1750.17572140.2840.28461150.3920.39255160.50.553*Tab of device attached to topside copperDS010484-23FIGURE 1.Cross-sectional view of Integrated Circuit Mounted on a printed circuit board.Note that the case temperature is measured at the point where the leadscontact with the mounting pad surface DS010484-24FIGURE 2.Power Dissipation Diagram/doc/96ef4d46852458fb770b5641.html 7Design Considerations(Continued)Typical ApplicationDS010484-20FIGURE 3.θJA vs.2oz Copper Area for TO-252DS010484-22FIGURE 4.Maximum Allowable Power Dissipation vs.Ambient Temperature for TO-252DS010484-21FIGURE 5.Maximum Allowable Power Dissipation vs.2oz.Copper Area for TO-252DS010484-9*Required if regulator input is more than 4inches from input filter capacitor (or if no input filter capacitor is used).**Optional for improved transient response./doc/96ef4d46852458fb770b5641.html 8 Physical Dimensions inches(millimeters)unless otherwise notedTO-39Metal Can Package(H)Order Number LM78M05CH,LM78M12CH or LM78M15CHNS Package Number H03A9/doc/96ef4d46852458fb770b5641.htmlPhysical Dimensions inches(millimeters)unless otherwise noted(Continued)TO-220Power Package(T)Order Number LM341T-5.0,LM341T-12,LM341T-15,LM78M05CT,LM78M12CT or LM78M15CT NS Package Number T03B/doc/96ef4d46852458fb770b5641.html 10Physical Dimensionsinches (millimeters)unless otherwise noted (Continued)LIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body,or (b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.National Semiconductor Corporation AmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@/doc/96ef4d46852458fb770b5641.htmlNational Semiconductor EuropeFax:+49(0)180-5308586Email:europe.support@/doc/96ef4d46852458fb770b5641.htmlDeutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Fran?ais Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National Semiconductor Asia Pacific Customer Response Group Tel:65-2544466Fax:65-2504466Email:sea.support@/doc/96ef4d46852458fb770b5641.htmlNational Semiconductor Japan Ltd.Tel:81-3-5639-7560Fax:81-3-5639-7507/doc/96ef4d46852458fb770b5641.htmlTO-252Order Number LM78M05CDT NS Package Number TD03BLM341/LM78MXX Series 3-Terminal Positive Voltage RegulatorsNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry andspecifications.。
Micron 产品数据手册说明书
DRAMUpdated Date : 11/06/2006DensityOrganization DescriptionRefreshSpeedPackagePart Number(Pb-free)Sample MP EDO DRAM 5V 51225ns 40L-SOJ M11B416256A-25JP Now Now EDO DRAM 5V 51235ns 44-40L-TSOPII M11B416256A-35TG Now Now EDO DRAM 3.3V 51235ns 40L-SOJ M11L416256SA-35JP Now Now EDO DRAM 3.3V 51235ns 40/44L-TSOPIIM11L416256SA-35TGNowNowSDRAMDensityOrganization DescriptionRefresh SpeedPackagePart Number(Pb-free)Sample MP SDRAM 2.5V 2K 143MHz 50L-TSOPII M12S16161A-7TG Now Now SDRAM 2.5V 2K 143MHz VFBGA M12S16161A-7BG Now Now SDRAM 3.3V 2K 143MHz 50L-TSOPII M12L16161A-7T (I)G Now Now SDRAM 3.3V 2K 200MHz 50L-TSOPII M12L16161A-5T (I)G Now Now SDRAM 3.3V 2K 143MHz VFBGA M12L16161A-7B (I)G Now Now 2M*16SDRAM 3.3V 2K 143MHz 54L-TSOPII M12L32162A-7TG Now Now 1M*32SDRAM 3.3V 2K 143MHz 90-FBGA M12L32321A-7BG Now Now SDRAM 2.5V 4K 100MHz 54L-TSOPII M12S64164A-10TG Now Now SDRAM 3.3V 4K 143MHz 54L-TSOPII M12L64164A-7T (I)G Now Now SDRAM 3.3V 4K 200MHz 54L-TSOPII M12L64164A-5TG Now Now SDRAM 2.5V 4K 143MHz 86L-TSOPII M12S64322A-7TG Now Now SDRAM 3.3V 4K 166MHz 86L-TSOPII M12L64322A-6T (I)G Now Now SDRAM 3.3V 4K 200MHz 86L-TSOPII M12L64322A-5TG Now Now SDRAM 2.5V 4K 143MHz 54L-TSOPII M12S128168A-7TG Now Now SDRAM 2.5V 4K 166MHz 54L-TSOPII M12S128168A-6TG Now Now SDRAM 3.3V 4K 143MHz 54L-TSOPII M12L128168A-7TG Now Now SDRAM 3.3V 4K 166MHz 54L-TSOPII M12L128168A-6TG Now Now SDRAM 2.5V 4K 166MHz 90-FBGA M12S128324A-6BG Now Now SDRAM 2.5V 4K 143MHz 86L-TSOPII M12S128324A-7TG Now Now SDRAM 2.5V 4K 166MHz 86L-TSOPII M12S128324A-6TG Now Now SDRAM 3.3V 4K 143MHz 90-FBGA M12L128324A-7B (I)G Now Now SDRAM 3.3V 4K 166MHz 90-FBGA M12L128324A-6B (I)G Now Now SDRAM 3.3V 4K 143MHz 86L-TSOPII M12L128324A-7T (I)G Now Now SDRAM 3.3V4K166MHz86L-TSOPIIM12L128324A-6T (I)GNowNowDDR SDRAM (Dobule-Date-Rate SDRAM)Density Organization DescriptionRefresh SpeedPackagePart Number(Pb-free)Sample MP DDR-SDRAM 2.5V 4K 166MHz 100-LQFP M13S32321A-6L Now Now DDR-SDRAM 2.5V 4K 200MHz 100-LQFP M13S32321A-5L Now Now DDR-SDRAM 2.5V 4K 166MHz 66L-TSOPII M13S64164A-6TG Q2'07Q3'07DDR-SDRAM 2.5V 4K 200MHz 66L-TSOPII M13S64164A-5TG Q2'07Q3'07DDR-SDRAM 2.5V 4K 166MHz 66L-TSOPII M13S128168A-6TG Now Now DDR-SDRAM 2.5V 4K 200MHz 66L-TSOPII M13S128168A-5TG Now Now DDR-SDRAM 2.5V 4K 166MHz 144-FBGA (12x12mm)M13S128324A-6BG Now Now DDR-SDRAM 2.5V 4K 200MHz 144-FBGA (12x12mm)M13S128324A-5BG Now Now 256Mb16Mx16DDR-SDRAM 2.5V 4K200MHz66L-TSOPIIM13S2561616A-5TGNowNow*Identifier of Pb-free as G or P is shown on outer carton.**Industrial spec : (I) Operating temperature -40ºC ~+85 ºC.2M*3264Mb4Mb*1632Mb4Mb 256Kb*161Mb*1616Mb 128Mb8M*164Mx324M*32128Mb8M*1632Mb 64Mb1M*324M*16Mobile SDRAMDensityOrganizationDescriptionRefresh Speed Package & MCPPart Number(Pb-free)Sample MP Mobile SDRAM 2.5V4K 100MHz 50L-TSOPII M52S16161A-10T (I)G Now Now Mobile SDRAM 2.5V 4K 125MHz 50L-TSOPII M52S16161A-8T (I)G Now Now Mobile SDRAM 1.8V4K 100MHz50L-TSOPIIM52D16161A-10T (I)G Now Now Mobile SDRAM 2.5V 4K 100MHz 54L-TSOPII M52S32162A-10T (I)G Now Now Mobile SDRAM 2.5V 4K 100MHz 54-FBGA M52S32162A-10B (I)G Now Now Mobile SDRAM 2.5V 4K 133MHz 54L-TSOPII M52S32162A-7.5T (I)G Now Now Mobile SDRAM 2.5V 4K 133MHz 54-FBGA M52S32162A-7.5B (I)G Now Now Mobile SDRAM 1.8V 4K 100MHz 54L-TSOPII M52D32162A-10T (I)G Now Now Mobile SDRAM 1.8V 4K 100MHz 54-FBGA M52D32162A-10B (I)G Now Now Mobile SDRAM 1.8V 4K 100MHz 54L-TSOPII M52D32162A-7.5T (I)G Now Now Mobile SDRAM 1.8V 4K 133MHz 54-FBGA M52D32162A-7.5B (I)G Now Now Mobile SDRAM 2.5V 4K 100MHz 90-FBGA M52S32321A-10B (I)G Now Now Mobile SDRAM 2.5V 4K 133MHz 90-FBGA M52S32321A-7.5B (I)G Now Now Mobile SDRAM 1.8V 4K 100MHz 90-FBGA M52D32321A-10B (I)G Now Now Mobile SDRAM 1.8V 4K 133MHz 90-FBGA M52D32321A-7.5B (I)G Now Now Mobile SDRAM 2.5V 4K 100MHz 54L-TSOPII M52S64164A-10T (I)G Q2 '07Q3 '07Mobile SDRAM 2.5V 4K 100MHz 54-FBGA M52S64164A-10B (I)G Q2 '07Q3 '07Mobile SDRAM 2.5V 4K 133MHz 54L-TSOPII M52S64164A-7.5T (I)G Q2 '07Q3 '07Mobile SDRAM 2.5V 4K 133MHz 54-FBGA M52S64164A-7.5B (I)G Q2 '07Q3 '07Mobile SDRAM 1.8V 4K 100MHz 54L-TSOPII M52D64164A-10T (I)G Q2 '07Q3 '07Mobile SDRAM 1.8V 4K 100MHz 54-FBGA M52D64164A-10B (I)G Q2 '07Q3 '07Mobile SDRAM 1.8V 4K 100MHz 54L-TSOPII M52D64164A-7.5T (I)G Q2 '07Q3 '07Mobile SDRAM 1.8V 4K 133MHz 54-FBGA M52D64164A-7.5B (I)G Q2 '07Q3 '07Mobile SDRAM 2.5V 4K 100MHz 86L-TSOPII M52S64322A-10T (I)G Q2 '07Q3 '07Mobile SDRAM 2.5V 4K 100MHz 90-FBGA M52S64322A-10B (I)G Q2 '07Q3 '07Mobile SDRAM 2.5V 4K 133MHz 86L-TSOPII M52S64322A-7.5T (I)G Q2 '07Q3 '07Mobile SDRAM 2.5V 4K 133MHz 90-FBGA M52S64322A-7.5B (I)G Q2 '07Q3 '07Mobile SDRAM 1.8V 4K 100MHz 86L-TSOPII M52D64322A-10T (I)G Q2 '07Q3 '07Mobile SDRAM 1.8V 4K 100MHz 90-FBGA M52D64322A-10B (I)G Q2 '07Q3 '07Mobile SDRAM 1.8V 4K 100MHz 86L-TSOPII M52D64322A-7.5T (I)G Q2 '07Q3 '07Mobile SDRAM 1.8V4K133MHz 90-FBGAM52D64322A-7.5B (I)GQ2 '07Q3 '07*Identifier of Pb-free as G or P is shown on outer carton.**Industrial spec : (I) Operating temperature -40ºC ~+85 ºC.64Mb4Mx162Mx32(1)All Mobile functions are included : PASR,TCSR,DS,Deep power down mode.(2)Max. Icc6 : Self-refresh current with full bank in 70 ºC .1Mx16Max. Icc6= 75uA (1.8V)16Mb32Mb2Mx161Mx32。
M13S128168A-5T中文资料
Revision HistoryRevision 0.1 (15 Jan. 2002)- OriginalRevision 0.2 (19 Nov. 2002)-changed ordering information & DC/AC characteristicsRevision 0.1 Revision 0.2M13S128168A - 5T M13S128168A - 6TM13S128168A - 6T M13S128168A - 7.5AB Revision 0.3 (8 Aug. 2003)-Change IDD6 from 3mA to 5mA.Revision 0.4 (27 Aug. 2003)-Change ordering information & DC / AC characteristics.Revision 1.0 (21 Oct. 2003)-Modify tWTR from 2tck to 1tck.Revision 1.1 (10 Nov. 2003)-Correct some refresh interval that is not revised.-Correct some CAS Lantency that is not revised.Revision 1.2 (12 Jan. 2004)-Correct IDD1; IDD4R and IDD4W test condition.-Correct tRCD; tRP unit-Add tCCD spec.-Add tDAL spec.Revision 1.3 (12 Mar. 2004)-Add Cas Latency=2; 2.5Revision 1.4 (23 Jun. 2005)-Add Pb-free to ordering information-Modify IDD0 and IDD1 spec-Modify some AC timing unit from tCK to ns.Revision 1.5 (29 May. 2006)-Delete CL2 ; CL2.5-Modify tREFI-Delete Non-pb-free form ordering informationRevision 1.6 (3 Jan. 2007)-Add CL2.5Revision 1.7 (12 Apr. 2007)-Add BGA packageRevision 1.8 (01 Jun. 2007)-Delete CL 2.5DDR SDRAM 2M x 16 Bit x 4 BanksDouble Data Rate SDRAMFeaturesz JEDEC Standardz Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLLz Differential clock inputs (CLK and CLK )z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 3z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe (DQS)z DQS is edge-aligned with data for reads; center-aligned with data for WRITE z Data mask (DM) for write masking only z V DD = 2.375V ~ 2.75V, V DDQ = 2.375V ~ 2.75V z Auto & Self refreshz 15.6us refresh interval (64ms refresh period, 4K cycle) z SSTL-2 I/O interface z66pin TSOPII packageOrdering information :PRODUCT NO. MAX FREQ VDDPACKAGECOMMENTS M13S128168A -5TG 200MHz Pb-free M13S128168A -6TG 166MHz 2.5V TSOPIIPb-free M13S128168A -5BG 200MHz Pb-free M13S128168A -6BG166MHz2.5V BGAPb-freeFunctional Block DiagramPin ArrangementDQS12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 PIN TSOP(II)(400mil x 875mil) (0.65 mm PIN PITCH)V DD DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 N CV DDQ LDQS N CV DD N C LDM WE CAS RAS CSN C BA0 BA1A10/A P A0A1A2A3V DDV SSDQ15V SSQDQ14DQ13V DDQDQ12DQ11V SSQDQ10DQ9V DDQDQ8N CV SSQUDQSN CV REFV SSUDMCLKCLKCKEN CN CA11A9A8A7A6A5A4V SS 666564636261605958575655545352515049484746454443424140393837363534x16 x1660 Ball BGAPin Description(M13S128168A)Absolute Maximum RatingUnitValueParameter SymbolVoltage on any pin relative to V SS V IN, V OUT-0.5 ~ 3.6 VVoltage on V DD supply relative to V SS V DD, V DDQ-1.0 ~ 3.6 VVoltage on V DDQ supply relative to V SS V DDQ-0.5 ~ 3.6 VStorage temperature T STG-55 ~ +150 C°Power dissipation P D TBD WShort circuit current I OS 50 mANote : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommend operation condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.DC Operation Condition & SpecificationsDC Operation ConditionRecommended operating conditions (Voltage reference to V SS = 0V, T A = 0 to 70C°)Notes 1. V REF is expected to be equal to 0.5* V DDQ of the transmitting device, and to track variations in the DC level of the same.Peak-to-peak noise on V REF may not exceed 2% of the DC value.2. V TT is not applied directly to the device. V TT is system supply for signal termination resistors, is expected to be set equalto V REF, and must track variations in the DC level of V REF .3. V ID is the magnitude of the difference between the input level on CLK and the input level on CLK.DC SpecificationsNote 1. Enable on-chip refresh and address counters.AC Operation Conditions & Timing SpecificationID2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of thesame.Input / Output Capacitance(V DD = 2.375V~2.75V, V DDQ =2.375V~2.75V, T A = 25C°, f = 1MHz)AC Operating Test ConditionsParameter Value Unit Input reference voltage for clock (V REF ) 0.5*V DDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate1.0V/nsInput levels (V IH /V IL ) V REF +0.31/V REF -0.31 V Input timing measurement reference level V REF V Output timing reference level V TT VAC Timing Parameter & Specifications(V DD = 2.375V~2.75V, V DDQ =2.375V~2.75V, T A =0C ° to 70C °)(Note)AC Timing Parameter & Specifications-continued-5 -6 Parameter Symbolmin max min max Half Clock Period t HP t CL min or t CH min- t CL min or t CH min - nsDQ-DQS output holdtimet QH t HP-0.45 - t HP-0.5 - nsACTIVE to PRECHARGE command t RAS40 120Kns 42 120KnsnsRow Cycle Time t RC60 - 60 -nsAUTO REFRESH Row Cycle Time t RFC70 - 72 -nsACTIVE to READ,WRITE delay t RCD18 - 18 -nsPRECHARGE command period t RP18 - 18 -nsACTIVE to READ withAUTOPRECHARGE command t RAP 18 120K 18 120KnsACTIVE bank A to ACTIVE bank B command t RRD10 - 12 -nsWrite recovery time t WR 2 - 2 -t CKWrite data in to READ command delay t WTR 1 - 1 -t CKCol. Address to Col. Address delay t CCD 1 - 1 -t CKAverage periodic refresh interval t REFI - 15.6 - 15.6usWrite preamble t WPRE0.25 - 0.25 -t CK Write postamble t WPST0.4 0.6 0.4 0.6t CK DQS read preamble t RPRE0.9 1.1 0.9 1.1t CK DQS read postamble t RPST0.4 0.6 0.4 0.6t CKClock to DQS write preamble setup time t WPRES0 - 0 -nsLoad Mode Register /Extended Mode register cycle time t MRD 2 - 1 -t CKExit self refresh to READ command t XSRD200 - 200 -t CKExit self refresh to non-READ command t XSNR75 - 75 -nsAutoprecharge write recovery+Precharge time t DAL(t WR/t CK)+(t RP/t CK)(t WR/t CK)+(t RP/t CK)t CKCommand Truth Table1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS)2. EMRS/MRS can be issued only at all banks precharge state.A new command can be issued 1 clock cycles after EMRS or MRS.3. Auto refresh functions are same as the CBR refresh of DRAM.The automatical precharge without row precharge command is meant by “Auto”..Auto/self refresh can be issued only at all banks precharge state.4. BA0~BA1 : Bank select addresses.If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.6. During burst write with auto precharge, new read/write command can not be issued.Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after end of burst.7. Burst stop command is valid at every burst length.8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).Basic FunctionalityPower-Up and Initialization SequenceThe following sequence is required for POWER UP and Initialization.1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)-Apply VDD before or at the same time as VDDQ.-Apply VDDQ before or at the same time as V TT & V REF).2. Start clock and maintain stable condition for a minimun of 200us.3. The minimun of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high.4. Issue precharge commands for all banks of the device.*1 5. I ssue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the rest address pins, A1~A11 and BA1)*1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.(To issue DLL reset command, provide “High” to A8 and “Low” to BA0)*2 7. Issue precharge commands for all banks of the device.8. Issue 2 or more auto-refresh commands.9. Issue a mode register set command with low to A8 to initialize device operation.*1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.*2 Sequence of 6 & 7 is regardless of the order.Mode Register DefinitionMode Register Set (MRS)The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A11 in the same cycle as CS, RAS, CAS, WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.Bus BA1 BA0 A11 A10A9 A8 A7A6A5A4A3A2A1 A0 AddressBurst Address Ordering for Burst LengthBurst Length StartingAddress (A2, A1,A0)Sequential Mode Interleave Mode xx0 0, 1 0, 1 2xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 4x11 3, 0, 1, 23, 2, 1, 0000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 81117, 0, 1, 2, 3, 4, 5, 67, 6, 5, 4, 3, 2, 1, 0DLL Enable / DisableThe DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.Output Drive StrengthThe normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S128168A also support a weak drive strength option, intended for lighter load and/or point-to-point environments.Mode Register SetExtended Mode Register Set (EMRS)The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0~A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.*QFC is not used; don’t care.PrechargeThe precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, t WR(min.) must be satisfied until the precharge command can be issued. After t RP from the precharge, an active command to the same bank can be initiated.Burst Selection for Precharge by Bank address bitsA10/AP BA1 BA0 PrechargeOnlyABank0 0 0BOnlyBank0 0 1COnlyBank0 1 0OnlyDBank0 1 1AllBanks1 X XNOP & Device DeselectThe device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS, CAS and WE. For both Deselect and NOP the device should finish the current operation when this command is issued.Row ActiveThe Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (t RCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD min).Read BankThis command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS, CAS, and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.Write BankThis command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS, CAS, and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command.Essential Functionality for DDR SDRAMBurst Read OperationBurst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after t RCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst (Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM until the burst length is completed.Burst Write OperationThe Burst Write command is issued by having CS, CAS and WE low while holding RAS high at the rising edge of the clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins t DS (Data-in setup time) prior to data strobe edge enabled after t DQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored.Read Interrupted by a ReadA Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.Read Interrupted by a PrechargeA Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank.1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on therising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after t RP (RAS precharge time).2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edgewhich is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after t RP.3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after t RP where t RPbegins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.4. For all cases above, t RP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between aPrecharge command and a new Bank Activate command to the same bank equals t RP / t CK (where t CK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles.In all cases, a Precharge operation cannot be initiated unless t RAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where t RAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.Write Interrupted by a WriteA Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.The following functionality establishes how a Write command may interrupt a Read burst.1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burstand tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].2. It is illegal for a Write command to interrupt a Read with autoprecharge command.Write Interrupted by a Read & DMA burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (t WTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command.The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the memory.1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case wherethe Write to Read delay is 1 clock cycle is disallowed.2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediatelyprecede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memorycontroller) in time to allow the buses to turn around before the SDRAM drives them during a read operation.4. If input Write data is masked by the Read command, the DQS inputs is ignored by the SDRAM.5. It is illegal for a Read command interrupt a Write with autoprecharge command.Write Interrupted by a Precharge & DMA burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time (t WR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM.Precharge timing for Write operations in DRAMs requires enough time to allow “Write recovery” which is the time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, t WR, is used to indicate the required of time between the last valid write operation and a Precharge command to the same bank.The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronizes with the address path by switching clock domains from the data strobe clock domain to the input clock domain.This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain.t WR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge that strobes in the precharge command.1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for writerecovery is defined by t WR.2. When a precharge command interrupts a Write burst operation, the data mask pin, DQ, is used to mask input data during thetime between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM.The minimum time for write recovery is defined by t WR.3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after t WR + t RP wheret WR + t RP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above.4. In all cases, a Precharge operation cannot be initiated unless t RAS(min) [minimum Bank Activate to Precharge time] has beensatisfied. This includes Write with autoprecharge commands where t RAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst.Burst StopThe burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock (CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation.The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required.1. The BST command may only be issued on the rising edge of the input clock, CLK.2. BST is only a valid command during Read burst.3. BST during a Write burst is undefined and shall not be used.4. BST applies to all burst lengths.5. BST is an undefined command during Read with autoprecharge and shall not be used.6. When terminating a burst Read command, the BST command must be issued L BST ( “BST Latency”) clock cycles before theclock edge at which the output buffers are tristated, where L BST equals the CAS latency for read operations.7. When the burst terminates, the DQ and DQS pins are tristated.The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).DM maskingThe DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe.Read With Auto PrechargeIf a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when t RAS(min) is satisfied. If not, the start point of precharge operation will be delayed until t RAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time (t RP) has been satisfiedAt burst read / write with auto precharge, CAS interrupt of the same bank is illegal.。
TMCM-1210 硬件手册说明书
TRINAMIC Motion Control GmbH & Co. KGHamburg, GermanyHardware Version V 1.10HARDWARE MANUAL+ +TMCM-12101-Axis steppercontroller/drivermax. 0.6A RMS / 24V DC STOP / HOME switch input hall sensorRS485++Table of contents1Life support policy (3)2Features (4)3Order codes (5)4Mechanical and Electrical Interfacing (6)4.1Dimensions and Mounting Holes (6)4.2Board mounting considerations (6)4.3Connectors (7)4.3.1Power, RS485 + HOME connector (8)4.3.2Motor connector (9)4.4Power supply (9)4.5RS485 (10)5Motor driver current (12)6On-Board LEDs (13)7Reset to Factory Default Values (13)8EMC considerations (14)9Operational Ratings (15)10Functional Description (16)11Revision History (17)11.1Document revision (17)11.2Hardware revision (17)12References (17)1Life support policyTRINAMIC Motion Control GmbH & Co. KG does not authorize or warrant any of its products for use in life support systems, without the specific written consent of TRINAMIC Motion Control GmbH & Co. KG.Life support systems are equipment intended to support or sustain life, and whose failure to perform, when properly used in accordance with instructions provided, can be reasonably expected to result in personal injury or death.© TRINAMIC Motion Control GmbH & Co. KG 2015 - 2019Information given in this data sheet is believed to be accurate and reliable. However neither responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties, which may result from its use.Specifications are subject to change without notice.2FeaturesThe TMCM-1210 is a highly compact 20mm x 20mm single axis stepper motor controller and driver board with RS485 interface. It has been designed in order to be mounted on the rear side of a NEMA8 (20mm flange size) stepper motor and offers an integrated hall-sensor based encoder IC in addition to a reference switch input for easy homing / search of reference position. The module supports motor currents up to 0.6A RMS and supply voltages up to 24V DC nominal. It is available with standard TMCL firmware and supports stand-alone operation (TMCL programs with auto-start stored on-board) and remote control via RS485 interface.MAIN CHARACTERISTICSMotion controller∙Motion profile calculation in hardware in real-time∙Motion controller supports linear and sixPoint™ ramps∙On the fly alteration of motor parameters (e.g. position, velocity, acceleration)∙High performance microcontroller (Cortex-M0+) for overall system control and serial communication protocol handlingBipolar stepper motor driver∙Up to 256 microsteps per full step∙Highly integrated and highly-efficient operation∙Dynamic current control∙stallGuard2™ feature for stall detectionInterfaces∙RS485 2-wire communication interface∙Digital input IN0 (+24V compatible), can be used as reference switch or left and/or right stop switch input, alsoOn board hall sensor∙Absolute sensor within one motor rotation∙12bit / 4096 steps / revolution max.∙Low-cost sensor - suitable for low velocity applications (few hundred rpm) –e.g. initial reference search (together with HOME sensor input) after power-upSoftware∙TMCL™ remote (direct mode) and standalone oper ation with memory for up to 876 TMCL commands∙Fully supported by TMCL-IDE (PC based integrated development environment)Electrical data∙Supply voltage: +7V… +30V DC∙Motor current: up to 0.6A RMS (programmable)Mechanical data∙Board size: 20mm x 20mm, overall height 9mm max. (without mating connectors and cables)∙Mounting holes compatible with NEMA 8 stepper motors (for mounting the board to the rear side of a NEMA8 stepper motor using two of the four existing screw)Please see separate TMCM-1210 Firmware Manual for additional information regarding firmware functionality and TMCL programming.3Order codesThe TMCM-1210 is available as:A cable loom set is available for this module, also:Table 3.2: Cable loom order code4 Mechanical and Electrical Interfacing4.1 Dimensions and Mounting HolesThe dimensions of the board are approx. 20mm x 20mm x 9 mm in order to fit on the back side of a 20mm (NEMA8) stepper motor. Maximum component height (height above PCB level) without mating connectors is around 6mm above PCB level and 2 mm below PCB level. There are two mounting holes for M2 screws for mounting to a NEMA8 stepper motor.2xFigure 4.1 Dimensions of TMCM-1210 and position of mounting holes (with comparison of size)4.2 Board mounting considerationsThe TMCM-1210 offers two metal plated mounting holes. Both mounting holes are connected to power supply ground. Please keep this in mind when mounting the board to the rear side of a motor.Figure 4.2: Example of TMCM-1210 mounted to NEMA 8 stepper motor4.3 ConnectorsThe TMCM-1210 offers two connectors including the motor connector which is used for attaching the motor coils to the electronics. The Power, RS485 and HOME connector is used for power supply, RS485 serial wire communication and offers one digital input.4115Power, RS485 + HOME connector HOME 5RS485+RS485-34VDD GND 12IN0STOP_L / STOP_R Motor connectorOA1OA234OB1OB212Figure 4.2 Overview connectorsOverview of connectors and mating connectors types:Table 4.1: Connectors and mating connectors, contacts and applicable wire4.3.1Power, RS485 + HOME connectorThe module offers one combined power, RS485 2-wire serial communication and digital input (HOME) connector (JST PH series).51Table 4.2: Power, RS485 + IN0 connector4.3.2 Motor connectorAs motor connector a 4pin JST PH-series 2mm pitch single row connector is available. The motor connector is used for connecting the four motor wires of the two motor coils of the bipolar stepper motor to the electronics. 14Table 4.4: Motor connector 4.4 Power supplyFor proper operation care has to be taken with regard to power supply concept and design. Due to space restrictions the TMCM-1210 includes just about 20µF/35V of supply filter capacitors. These are ceramic capacitors which have been selected for high reliability and long life time.4.5RS485For remote control and communication with a host system the TMCM-1210 provides a two wire RS485 bus interface. For proper operation the following items should be taken into account when setting up an RS485 network:1.BUS STRUCTURE:The network topology should follow a bus structure as closely as possible. That is, the connection between each node and the bus itself should be as short as possible. Basically, it should be short compared to the length of the bus.termination resistor (120 Ohm)termination resistor (120 Ohm)Figure 4.6: Bus structure2.BUS TERMINATION:Especially for longer busses and/or multiple nodes connected to the bus and/or high communication speeds, the bus should be properly terminated at both ends. The TMCM-1210 does not integrate any termination resistor. Therefore, 120 Ohm termination resistors at both ends of the bus have to be added externally.3.NUMBER OF NODES:The RS485 electrical interface standard (EIA-485) allows up to 32 nodes to be connected to a single bus.The bus transceiver used on the TMCM-1210 unit (SN65HVD3085E) has a significantly reduced bus load and allow a maximum of 255 units to be connected to a single RS485 bus using TMCL firmware. Please note: usually it cannot be expected to get reliable communication with the maximum number of nodes connected to one bus and maximum supported communication speed at the same time. Instead, a compromise has to be found between bus cable length, communication speed and number of nodes. MUNICATION SPEED:The maximum RS485 communication speed supported by the TMCM-1210 hardware is 1Mbit/s. Factory default is 9600 bit/s. Please see separate TMCM-1210 TMCL firmware manual for information regarding other possible communication speeds below the upper limit in hardware.5.NO FLOATING BUS LINES:Avoid floating bus lines while neither the host/master nor one of the slaves along the bus line is transmitting data (all bus nodes switched to receive mode). Floating bus lines may lead to communication errors. In order to ensure valid signals on the bus it is recommended to use a resistor network connecting both bus lines to well defined logic levels.There are actually two options which can be recommended:Add resistor (Bias) network on one side of the bus, only (120R termination resistor still at both ends):termination resistor(120R)RS485- / RS485Btermination resistor (120R)RS485+ / RS485AFigure 4.7: Bus lines with resistor (Bias) network on one side, onlyOr add resistor (Bias) network at both ends of the bus (like Profibus™ termination):termination resistor (220R)RS485- / RS485BRS485+ / RS485A termination resistor (220R)Figure 4.8: Bus lines with resistor (Bias) network at both endsCertain RS485 interface converters available for PCs already include these additional resistors (e.g. USB-2-485 with bias network at one end of the bus).5Motor driver currentThe on-board stepper motor driver operates current controlled. The driver current may be programmed in software with 32 effective scaling steps in hardware.Explanation of different columns in table below:Motor current setting in software (TMCL)These are the values for TMCL axis parameter 6 (motor run current) and 7 (motor standby current). They are used to set the run / standby current using the following TMCL commands:SAP 6, 0, <value> // set run currentSAP 7, 0, <value> // set standby current(read-out value with GAP instead of SAP. Please see separate TMCM-1210 firmware manual for further information)Motor currentI RMS [A]Resulting motor current based on motor current setting6On-Board LEDsThe board offers one LED in order to indicate board status. The function of the LED is dependent on the firmware version. With standard TMCL firmware the green LED should be flashing slowly during operation.GREEN LEDFigure 6.1 On-board LED7Reset to Factory Default ValuesIn order to reset all settings (e.g. incl. address and RS485 baud rate) to factory default values please follow instruction sequence below:1.Switch OFF power supply.2.Short programming pads on bottom of PCB as shown in figure 7.1.3.Switch ON power supply (on-board LED should start flashing fast).4.Switch OFF power supply.5.Remove short circuit.Figure 7.1 Reset to factory default values (bottom view of pcb)8EMC considerationsThe TMCM-1210 contains ferrite beads on-board in line with the positive supply input and all 4 motor windings connections in addition to filter capacitors.Tests have shown that it is possible to meet Class B emission standards using the bare TMCM-1210 (motor and power connected) with the motor running slowly at maximum current (0.7A RMS) and +24V supply voltage without additional / external filters.Figure8.1:SetupwithTMCM-1210andattachedmotor(***************************/24Vsupply,stand-alone mode using on-board TMCL-autostart-program)Figure 8.2: measurement results (example)Please note that these measurement results using a bare TMCM-1210 unit with only motor and power supply connected do not imply any guarantee for a complete system with one or more integrated TMCM-1210 with meeting any emission limits.9Operational RatingsThe operational ratings show the intended or the characteristic ranges and should be used as design values. In no case shall the maximum values be exceeded!Table 9.1 General operational ratings of modulePERATIONAL RATINGS OF SWITCHTable 9.2 Operational ratings of HOME + STOP switches / IN0 inputsPERATIONAL RATINGS OF INTERFACETable 9.3: Operational ratings of RS485 interface10Functional DescriptionThe TMCM-1210 is a highly integrated controller/driver module which can be controlled via several serial interfaces. Communication traffic is kept low since all time critical operations (e.g. ramp calculations) are performed on board. The nominal supply voltage of the unit is 12V or 24V DC. The module is designed for both, standalone operation and direct mode. Full remote control of device with feedback is possible. The firmware of the module can be updated via the RS485 serial interfaces.In Figure 10.1 the main parts of the TMCM-1210 are shown:∙microprocessor, which runs the TMCL operating system (connected to TMCL memory),∙motion controller (part of TMC2130), which calculates ramps and speed profiles internally by hardware, ∙driver (part of TMC2130) with stallGuard2™ and its energy efficient coolStep™ feature and stealthCh o p™ for extremely quiet operation∙hall sensor based encoder which delivers position feedback at low speed (few 100rpm max.) – can be used for reference search e.g. after power-up7…Figure 10.1 Main parts of the TMCM-121011Revision History11.1D ocument revisionTable 11.1: Document revision11.2H ardware revisionTable 11.2: Hardware revision12References[JST] JST connector[TMC2130] TMC2130 datasheetManual available on [TMCL-IDE] TMCL-IDE User ManualManual available on .。
LED日光灯管规格书及灯头型号..
LED日光灯管规格书LED日光灯管规格书型号包括：T4、T5、T8、T9、T10等，表示灯管粗细。
简单地：T后面的数值，表示灯管周长，例如T4的周长为4厘米、T5的周长为5厘米。
算成直径：T8的直径是1英寸(2.54厘米)，T4的直径是0.5英寸(1.27厘米)，….。
T代表灯管的直径1T=1/8″1″=25.4mm1T=3.175mmT4=12.7mmT5=16mmT8=25.4mmT9=28.6mmT10=31.8mm注：日光灯的灯头主要用G5、G13的企业用的三支灯管一组的通常是T5的灯管，很早以前常用的日光灯规格书有T10、T12。
“T”，代表“Tube”，表示管状的，T后面的数字表示灯管直径。
T8就是有8个“T”，一个“T”就是1/8英寸。
一英寸等于25.4毫米。
那么每一个“T”就是25.4÷8＝3.175mmT12灯管的直径规格书就是(12/8)×25.4＝38.1 mmT10灯管的直径规格书就是(10/8)×25.4＝31.8mmT8灯管的直径规格书就是(8/8)×25.4＝25.4mm [T8的刚好是直径一英寸的灯管] (注：统一宽度39mm、高度52mm）常用的日光灯长度与功率：(20w 长620mm; 30w 长926mm; 40w长1230mm) T5灯管的直径就是(5/8)×25.4＝16 mm (注：统一宽度23.5mm、高度39mm）常用的日光灯长度与功率：(8w 长310mm; 14w 长570mm; 21w 长870.5mm; 28w 长1170.5mm; 35w 长1475mm)T4灯管的直径就是(4/8)×25.4＝12.7 mm (注：统一宽度21mm、高度32mm）常用的日光灯长度规格书与功率：(8w 长341mm; 12w 长443mm; 16w 长487mm; 20w 长534mm;22w 长734mm; 24w 长874mm; 26w 长1025mm; 28w 长1172mm)T3.5灯管的直径就是(3.5/8)×25.4＝11.1 mmT2灯管的直径就是(2/8)×25.4＝6.4 mmLed日光灯管规格书是依照普通日光灯规格书制造的，其规格大至相同，可以不更换支架的前提下方便地将LED日光灯替换普通日光灯以达到环保节能，有利于节省更换的成本。
M12L64322A-5BG中文资料
57 NC 56 DQ31 55 VDDQ 54 DQ30 53 DQ29 52 VSSQ 51 DQ28 50 DQ27 49 VDDQ 48 DQ26 47 DQ25 46 VSSQ 45 DQ24 44 VSS
M12L64322A
512K x 32 Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
86 Pin TSOP (TypeII) (400mil x 875mil)
Product No. MAX FREQ. PACKAGE COMMENTS
M12L64322A-5TG 200MHz TSOPII
Revision 1.9(Nov. 04 2005) - Modify tCC / tRCD spec
Revision 2.0(Dec. 08 2005) - Add –5T speed grade
Revision 2.1(Mar. 08 2006) - Modify Inch Dimension Max. A2 from 0.011 to 0.041
E VDDQ DQ31 NC
NC DQ16 VSSQ
F VSS DQM3 A3
A2 DQM2 VDD
G A4 A5 A6
A10 A0 A1
H A7 A8 NC
NC BA1 NC
J CLK CKE A9
BA0 CS RAS
K DQM1 NC NC
CAS WE DQM0
L VDDQ DQ8 VSS
VDD DQ7 VSSQ
Pb-free
SML-812MT中文资料
LEDs, Surface Mount CHIP - standard
Case & Viewing Angle Peak Wavelength nm Typ. Luminous Intensity Chip (IF = 20mA) Height mcd (H) mm
OPTOELECTRONICS
Emitted Colour NORMAL BRIGHTNESS Red Red Orange Yellow Green Green Green Pure-Green HIGH BRIGHTNESS Red Red Orange Orange Yellow Yellow Green Green Green* Green* Blue* Blue* Blue*
Typ. Luminous Intensity Chip (IF = 20mA) Height mcd (H) mm
Manf. Part No. & Order Code
Dimensions (mm)
2.0 1.4
0805 Chip
Red Red Orange Yellow Green Pure-Green HIGH BRIGHTNESS Red Orange Yellow
0.8
1.0 0.8 0.3 1.0
0.3
Viewing angle 170°
Red Orange Yellow Green
white-diffused white-diffused white-diffused white-diffused
632 611 593 570
45 45 45 30
TOL1608MRB TOL1608MOB TOL1608MYB TOL1608MGB
MEMORY存储芯片MAX812TEUS+T中文规格书
RESET is guaranteed to be a logic low for VCC > 1V. Once VCC exceeds the reset threshold, an internal timer keeps RESET low for the reset timeout period; after this interval, RESET goes high.
4-Pin μP Voltage Monitors with Manual Reset Input
Pin Description
PIN
MAX811 MAX812
1
1
2
—
—
2
3
3
4
4
NAME GND RESET
RESET
MR VCC
FUNCTION
Ground
Active-Low Reset Output. RESET remains low while VCC is below the reset threshold or while MR is held low. RESET remains low for the Reset Active Timeout Period (tRP) after the reset conditions are terminated.
施耐德 LC1N1210M5N 接触器 Easy TeSys Control 数据表
Product data sheetCharacteristicsLC1N1210M5NEasy TeSys Control 3P 接触器 (1NO) - AC-3 -<= 440V 12A - 220V 线圈 50Hz主要信息产品系列Easy TeSys 产品系列Easy TeSys Control 产品类型接触器产品短名LC1N接触器应用领域应用于功率因数大于等于0.95的交流负载中应用于无感或微感负载、电阻炉使用类别AC-3 AC-1AC-4极数3P额定工作电压 [Ue]电源回路: <= 690 V AC 50/60 Hz额定工作电流 [Ie]12 A (当运行温度 <=60 °C) 当运行电压<=<= 440 V AC AC-3对于电源回路 25 A (当运行温度 <=60 °C) 当运行电压<=<= 440 V AC AC-1对于电源回路 5 A (当运行温度 <=60 °C) 当运行电压<=<= 440 V AC AC-4对于电源回路控制回路电压 [Uc]220 V AC 50 Hz补充信息电动机功率 (kW)3 KW 当运行电压<=220...230 V AC 50/60 Hz 5.5 KW 当运行电压<=380...400 V AC 50/60 Hz 5.5 KW 当运行电压<=415...440 V AC 50/60 Hz 7.5 KW 当运行电压<=500 V AC 50/60 Hz7.5 KW 当运行电压<=660...690 V AC 50/60 Hz 回路触点类型 3 NO约定发热电流 [Ith]25 A (当运行温度 <=60 °C) 对于电源回路额定接通能力 [Irms]120 A 当运行电压<=380 V AC 对于电源回路 符合 IEC 60947-4-1 140 A AC 对于辅助触点 符合 IEC 60947-5-1额定分断能力96 A 当运行电压<=440 V 对于电源回路 符合 IEC 60947额定短时耐受电流 [Icw]105 A 当运行温度<=40 °C 可持续10 s 对于电源回路 61 A 当运行温度<=40 °C 可持续60 s 对于电源回路 30 A 当运行温度<=40 °C 可持续600 s 对于电源回路与继电器配合使用的熔丝10 A gG 当运行电压<=<= 690 V 配合 1 型, 对于控制回路 符合 IEC 60947-5-1 25 A gG 当运行电压<=<= 690 V 配合 1 型, 对于电源回路平均阻抗 2.5 MΩ - Ith 25 A 50 Hz 对于电源回路每极功耗0.36 W AC-3 1.6 W AC-1额定绝缘电压 [Ui]690 V 符合 IEC 60947-4-1过电压类别III 污染等级3额定冲击耐受电压 [Uimp]6 KV 线圈未连接到电源电路 符合 IEC 60947T h e i n f o r m a t i o n p r o v i d e d i n t h i s d o c u m e n t a t i o n c o n t a i n s g e n e r a l d e s c r i p t i o n s a n d /o r t e c h n i c a l c h a r a c t e r i s t i c s o f t h e p e r f o r m a n c e o f t h e p r o d u c t s c o n t a i n e d h e r e i n .T h i s d o c u m e n t a t i o n i s n o t i n t e n d e d a s a s u b s t i t u t e f o r a n d i s n o t t o b e u s e d f o r d e t e r m i n i n g s u i t a b i l i t y o r r e l i a b i l i t y o f t h e s e p r o d u c t s f o r s p e c i f i c u s e r a p p l i c a t i o n s .I t i s t h e d u t y o f a n y s u c h u s e r o r i n t e g r a t o r t o p e r f o r m t h e a p p r o p r i a t e a n d c o m p l e t e r i s k a n a l y s i s , e v a l u a t i o n a n d t e s t i n g o f t h e p r o d u c t s w i t h r e s p e c t t o t h e r e l e v a n t s p e c i f i c a p p l i c a t i o n o r u s e t h e r e o f .N e i t h e r S c h n e i d e r E l e c t r i c I n d u s t r i e s S A S n o r a n y o f i t s a f f i l i a t e s o r s u b s i d i a r i e s s h a l l b e r e s p o n s i b l e o r l i a b l e f o r m i s u s e o f t h e i n f o r m a t i o n c o n t a i n e d h e r e i n .机械寿命10000000 次电气寿命1400000 次 AC-3300000 次 AC-1250000 次 AC-4控制回路特性AC当50 Hz控制电压限额0.85...1.1 Uc (-5…55 °C 线圈吸合 50 Hz0.3...0.6 Uc (-5…55 °C 线圈释放 50 Hz(~50Hz吸合)功耗 (VA)95 VA 50 Hz cos phi 0.75 (at 20 °C)(~50Hz保持)功耗 (VA)8.5 VA 50 Hz cos phi 0.3 (at 20 °C)热消散2…3 W for 控制回路动作时间12...22 ms 闭合过程4...19 ms 打开过程最大操作频率1800 次/小时当60 °C接线能力电源回路: 螺栓紧固 1 1…4 mm² 电缆类型: 软线 带接线端子电源回路: 螺栓紧固 2 1…2.5 mm² 电缆类型: 软线 带接线端子电源回路: 螺栓紧固 1 1…4 mm² 电缆类型: 硬线 不带接线端子电源回路: 螺栓紧固 2 1…4 mm² 电缆类型: 硬线 不带接线端子控制回路: 螺栓紧固 1 1…4 mm² 电缆类型: 软线 不带接线端子控制回路: 螺栓紧固 2 1…4 mm² 电缆类型: 软线 不带接线端子控制回路: 螺栓紧固 1 1…4 mm² 电缆类型: 软线 带接线端子控制回路: 螺栓紧固 2 1…2.5 mm² 电缆类型: 软线 带接线端子控制回路: 螺栓紧固 1 1…4 mm² 电缆类型: 硬线 不带接线端子控制回路: 螺栓紧固 2 1…4 mm² 电缆类型: 硬线 不带接线端子紧固扭矩电源回路: 1.2 N.m控制回路: 1.2 N.m辅助触点类型 1 NO最小开关电压17 V 对于控制回路最小开关电流 [Imin]5 MA 对于控制回路绝缘电阻> 10 MΩ 对于控制回路不重迭时间 1.5 Ms 得电 确保NC和NO触电之间1.5 Ms 失电 确保NC和NO触电之间安装方式底板安装DIN 导轨安装环境标准EN 60947-4-1IEC 60947-4-1IEC 60947-1GB 14048.4EN 60947-1产品认证CCCIP 保护等级IP20 符合 IEC 60529防护措施TH （污染等级 3) 符合 IEC 60068周围空气温度-5…55 °C 运行-60…80 °C 存储-20…70 °C （运行在Uc下时）工作海拔3000 m 无降容耐火及耐异常高温能力850 °C 符合 IEC 60695-2-1抗冲击、震动性能抗震性能 触点打开时 (1.5 gn (5...300 Hz))抗震性能 触点闭合时 (3 gn (5...300 Hz))抗冲击性能 触点打开时 (7 gn (11ms))抗冲击性能 触点闭合时 (10 gn (11ms))高度74 Mm宽度45 Mm深度80 Mm净重0.3 Kg包装单位Unit Type of Package 1PCENumber of Units in Package 11Package 1 Height 4.82 CmPackage 1 Width7.4 CmPackage 1 Length8.31 CmPackage 1 Weight341.0 GUnit Type of Package 2S02Number of Units in Package 236Package 2 Height15.0 CmPackage 2 Width30.0 CmPackage 2 Length40.0 CmPackage 2 Weight12.5 KgUnit Type of Package 3PALNumber of Units in Package 3576Package 3 Height60.0 CmPackage 3 Width80.0 CmPackage 3 Length60.0 CmPackage 3 Weight196.466 Kg可持续性产品类型Green Premium 产品REACh法规REACh 声明REACh（不含 SVHC）是欧盟ROHS指令符合欧盟ROHS声明无有毒重金属是无汞是中国 ROHS 管理办法中国 ROHS 声明RoHS 豁免信息是环境披露产品环境文件流通资料产品使用寿命终期信息WEEE该产品必须经特定废物回收处理后弃置于欧盟市场，绝不可丢弃于垃圾桶中。
AML8613
L3
H_5V FB Q12 VS2307
HDMI5V
C86 22uF Y
D
Q9 2N3904 VD 39 42 45 46 51 52 59 62 57 56 29 38 55 30 31 43 48 49 54 58 37 33 26 27 34 35 OVDD H_5V U21 VD VD VD VD VD VD VD VD SDA SCL COAST CLAMP A0 HSYNC VSYNC BAIN GAIN SOGIN RAIN REF_BYPASS MIDSCV FILT PVD PVD PVD PVD 63 61 60 53 44 50 47 41 40 36 HDMI_Y
L8
C
R121 HPD 18 R119 41 47K R116 22 22
22
20 21 22 23
L10 FB
HDMI5V
DDCSCL DDCSDA
G1 G2 G3 G4 HDMI_Connector HDMI5V R123 4.7K R124 4.7K
VCC3.3V
AVCC
20 19
R120
22
22K
C139 100uF/16V
A
C140 1OOuF/16V IEC958
C141 0.1uF
1
RESET_n
21 40
4 16 45 59 74 3 15 46 60 73
R114 330 +1.8V C146 0.1uF C147 0.1uF
R109 R
GND GND GND GND GND GND GND GND GND GND
R56 75
R57 3.3K
R59 75
H78M12AT中文资料
current limiting, thermal shut-down and safe operating area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 0.5A output current. Although designed primarily as fixed voltage regulators, this device can be used with external components to obtain adjustable voltages and currents.Description• Output current up to 500mA is available.Page No. : 2/3Electrical Characteristics• H78M12ATVin=19V, Io=350mA, 0°C≤Tj≤125°C, PD≤5W, unless otherwise specifiedSymbol Characteristic Min Typ Max Units Vo Output Voltage (Tj=25°C)11.641212.36V Vo Output Voltage (14.5V≤Vin≤27V, 5mA≤Io≤350mA)11.521212.48V Line Regulation (Tj=25°C, Io=200mA), 14.5V≤Vin≤30V-20100 ReglinemV Line Regulation (Tj=25°C, Io=200mA), 16V≤Vin≤30V-1650Load Regulation (Tj=25°C), 5mA≤Io≤500mA--220 RegloadmV Load Regulation (Tj=25°C), 5mA≤Io≤200mA--110 IB Quiescent Current (Tj=25°C)- 3.26mA Quiescent Current Change (Tj=25°C), 14.5V≤Vin≤30V, Io=200mA--0.8mA ∆IBQuiescent Current Change (Tj=25°C), 5mA≤Io≤350mA--0.5 RR Ripple Rejection, 15V≤Vin≤25V, Io=300mA, f=120Hz55--dB Vi-Vo Dropout Voltage (Io=500mA, Tj=25°C)-2-V VN Output Noise Voltage (Tj=25°C), 10Hz≤f≤100KHz-75160uV Isc Short Circuit Current Limit (Tj=25°C), Vin=35V-300-mA Imax Peak Output Current (Tj=25°C)-700-mA TCVo Average Temperature Coefficient of Output Voltage, Io=5mA--0.5-mV/°C • H78M12BTVin=19V, Io=350mA, 0°C≤Tj≤125°C, PD≤5W, unless otherwise specifiedSymbol Characteristic Min Typ Max Units Vo Output Voltage (Tj=25°C)11.41212.6V Vo Output Voltage (14.5V≤Vin≤27V, 5mA≤Io≤350mA)11.41212.6VLine Regulation (Tj=25°C, Io=200mA), 14.5V≤Vin≤30V-20120 ReglinemV Line Regulation (Tj=25°C, Io=200mA), 16V≤Vin≤30V-1660Load Regulation (Tj=25°C), 5mA≤Io≤500mA--240mV RegloadLoad Regulation (Tj=25°C), 5mA≤Io≤200mA--120 IB Quiescent Current (Tj=25°C)- 3.26mAQuiescent Current Change (Tj=25°C), 14.5V≤Vin≤30V, Io=200mA--1mA ∆IBQuiescent Current Change (Tj=25°C), 5mA≤Io≤350mA--0.6 RR Ripple Rejection, 15V≤Vin≤25V, Io=300mA, f=120Hz55--dB Vi-Vo Dropout Voltage (Io=500mA, Tj=25°C)-2-V VN Output Noise Voltage (Tj=25°C), 10Hz≤f≤100KHz-75180uV Isc Short Circuit Current Limit (Tj=25°C), Vin=35V-300-mA Imax Peak Output Current (Tj=25°C)-700-mA TCVo Average Temperature Coefficient of Output Voltage, Io=5mA--0.5-mV/°CPage No. : 3/3 TO-126 DimensionImportant Notice:• All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of HSMC.• HSMC reserves the right to make changes to its products without notice.•HSMC semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.• HSMC assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. Head Office And Factory :•Head Office (Hi-Sincerity Microelectronics Corp.) : 10F.,No. 61, Sec. 2, Chung-Shan N. Rd. Taipei Taiwan R.O.C.Tel : 886-2-25212056 Fax : 886-2-25632712, 25368454•Factory 1 : No. 38, Kuang Fu S. Rd., Fu-Kou Hsin-Chu Industrial Park Hsin-Chu Taiwan. R.O.CTel : 886-3-5983621~5 Fax : 886-3-5982931。
奇岩读卡器ICMA8121FMA8125CMA8127MA8168MA6116M110E
奇岩(MOAI) 产品线介绍联系人BillTEL: 135****9940。
读卡器IC ：型号接口属性封装支持存储卡类型备注MA8121HMA8121FUSB2.0DiceTF、SD、、mini SD、RS-MMC、MINI SDHC、MMCmobile、MMC、MMC Plus、micro SD单卡免晶振读卡器ICMA8125C USB2.0DiceTF、SD、mini SD、RS-MMC、MINI SDHC、MMCmobile、MMC、MMC Plus、MS Pro Duo、MS Micro(M2)、MS Pro、micro SD、MS Duo双卡免晶振读卡器ICMA8168USB2.0LQFP48(7X7)TF、SD、CF、mini SD、RS-MMC、MINI SDHC、MMCmobile、MMC、MMC Plus、MS Pro Duo、MS Micro(M2)、MS Pro、micro SD、MS Duo多卡读卡器IC MA8168A USB2.0LQFP48(7X7)TF、SD、CF、mini SD、RS-MMC、MINI SDHC、MMCmobile、MMC、MMC Plus、MS Pro Duo、MS Micro(M2)、MS Pro、micro SD、MS Duo多卡免晶振读卡器ICMA8121CThe MA8121C is an USB 2.0 Card Reader controller by a highly integrated single chipsolution designed to deliver high-speed data transmission between USB2.0 and SD, SDHC,miniSD, Micro SD(T-Flash), MMC, RC-MMC, MMC Micro, MMC Mobile flash interfacesspecification. The MA8121C is offered with COB (Chip On Board) Bounding and 28SSOPpackage. MA8121C complies with USB specification Rev. 2.0 and USB Mass Storage Classspecification Rev. 1.0 to support Windows ME/2000/XP/Vista/Win7, Mac OS 10.x above, andLinux Kernel 2.4 above. MA8121C needs fewest external component and bounding cost,thus manufacturers can effectively reduce the BOM and labor cost on PCBA. MA8121C isthe SD card reader with the best C/P value.MA8128MA8128 is a highly integrated USB SIM Card reader controller. The MA8128supports SIM card interface and extra SD card reader slot. MA8128 supports SIMwith proprietary user command and manufacturers can easily create a high-security SIM Card reader by deploying MA8128 and SIM Editor AP. The SD readersupports SD, SDHC, miniSD, Micro SD(T-Flash), MMC, RC-MMC, MMC Micro, MMC Mobile flash interfaces specification. MA8128 is offered with 28SSOP package andsupport Windows ME/2000/XP/Vista/Win7 OS system.MA8168The MA8168 is a single LUN USB2.0 to Flash Card Reader designed to deliveroutstanding performance for data transmission between USB and compatible flash cards such as CF, SD(SDHC), MMC, xD and Memory Stick Micro. Besides, MA8168 supports several operating systems, including MS Windows, LINUX and Mac OS.MA8168 integrate high speed MCU and DMA for highest data transfer. Besides 48pin LQFP package, MA8168 also customize pad design to fit dice base shipping format for cost effective solution. For moreMA8127The MA8127 is an USB 2.0 Card Reader controller by a highly integrated singlechip solution designed to deliver high-speed data transmission between USB and versatile flash card interfaces with up-to-date specification. The MA8127 is packaged with 48-pin LQFP for up to 3 LUNs (SD/MMC/Memory Stick Micro, SD/MMC/Memory Stick Micro, Micro SD/MMC micro /T-Flash) flash card reader.The MA8127 complies with USB specification Rev. 2.0 and USB Mass Storage Class specification Rev. 1.0 to support Windows ME/2000/XP/Vista, Mac OS 10.xabove, and Linux Kernel 2.4 above. MA8127 integrates a high speed 1T 8051 microprocessor and a high efficiency DMA hardware engine for the best data transfer performance between USB and flash card interfaces.MA8125EN MA8125 is a high performance USB 2.0 card reader controller that integratesan USB 2.0 PHY, an SIE (Serial Interface Engine), 8051, and memory cardcontroller logic into a single chip. It supports access to Memory Stick Micro,Micro SD/MMC Micro, Secure Digital™ (SD), Multi Media Card™ (MMC) throughUSB interface.MA8125 is developed with highest performance and fewest external componentsrequirement. The COB and SSOP-28 packaged provide the best cost/performanceratio for manufacturers. For more product information,外接硬盘盒IC型号接口属性封装支持硬盘类型备注MA6116USB2.0SSOP-282.5寸3.5寸硬盘，20G-1.5TB 容量硬盘USB toSATAM110E USB2.0LQFP-482.5寸3.5寸硬盘，20G-120G 容量硬盘USB TOIDEMOAI MA6116A is a bridge chip for USB to SATA interface, translating the host SCSIcommand to ATA/ATAPI command of SATA device, targeting the external HDDapplication. MA6116A complies with the USB Storage Class specifications ver.1.0 Bulkmode protocol and compatible with Windows 98/2000/XP/Vista/Win7, Mac OS 9, LinuxRedhat. With the in-house DMA and Transceiver capability, MA6116A provides themarket most outstanding read/write performance and BOM cost. MOAI providesproprietary password partition and OTB AP.2.1 MA6116 General DescriptionMOAI MA6116 is a bridge chip for USB to SATA interface, translating the host SCSI command to ATA/ATAPI command of SATA device, targeting the external HDD and DVD drives application.MA6116complies with the USB Storage Class specifications ver.1.0 Bulk mode protocol and compatible with Windows 98/2000/XP/Vista, Mac OS 9, Linux Redhat. With the in-house DMA and Transceiver capability, MA6116 provides the market most outstanding read/write performance and BOM cost.2.2 MA6116 Feature2.2.1 USB Featurez Supports USB2.0 specification with USB-IF LOGOz Supports USB2.0 specifications for 480Mbps and 12Mbps transfer ratez Supports Mass Storage Device Class Bulk only transferz Integrated USB 2.0 UTMI transceiver and Serial Interface Engine (SIE)z USB2.0 Self power and Bus power compliancez Endpoint:. Endpoint 0: 64 bytes control transfer.. Endpoint 1: 512 bytes bulk transfer for IN transaction.. Endpoint 2: 512 bytes bulk transfer for OUT transaction.2.2.2 Serial ATA Featurez Supports Gen1 (1.5Gbps) of SATA specification Rev 2.5z Supports ATA/ATAPI command for DMA, UDMA and PIO mode data transferz Supports ATA/ATAPI LBA 48bit addressing modez Support SATAII Asynchronous Recovery Feature. (Hot Plug)z Support SATA tri-state mode for pass through applicationz Supports SATA 1.5G/3G speed negotiation2.2.3 Overall Featurez Embedded 5V to 3.3V; 3.3V to 1.8V regulatorz Supports Windows 98/ME/XP/Vista, Linux Redhat, Mac 10 OS systemz Supports Microsoft WHQL certificationz Maximum data transfer rate at 36MB/secz One 12Mhz crystalz One LED pin for data access indicationz 28 SSOP packageMA6116 应用：1 外接硬盘盒，2外接CD光驱/CD-ROM全新支持DOS直接引导启动2000,xp,Vista系统直接光盘安装SATA串口笔记本USB2.0光驱外置光驱转接卡（转接板）。
M12L16161A-7TG中文资料
Revision HistoryRevision 0.1 (Oct. 23 1998)-OriginalRevision 0.2 (Dec. 4 1998)-Add 200MHZRevision 1.0 (Dec. 10 1999)-Delete Preliminary-Rename the filenameRevision 1.1 (Jan. 26 2000)-Add –5.5 Spec.Revision 1.2 (Apr. 25 2000)-Correct error typing of C1 dimensionRevision 1.3 (Nov. 27 2000)-P5 Number of valid output data CAS Latency 3Æ 2ea -P17. P19. P21 Read Command shift right 1CLK-P15. P19. P20 Precharge Command shift left 1CLK Revision 1.4 (Feb. 22 2001)-P6 modify tOH –6(2ns) & -7(2ns)Revision 1.5 (Jun. 4 2001)-P3. P4 modify DC currentRevision 1.6(Sep. 7 2001)-P5 modify AC parametersRevision 1.7 (Mar. 20 2002)-P28 C1(Nom)=0.15mmÆ0.127mm-P28 delete symbol=ZDRevision 1.8 (Dec. 16 2003)-Modify stand off=0.051~0.203mmRevision 1.9 (Mar. 05 2004)-Correct typing error of timing (tRC; tRP;tRCD)-Add tRRD timing chartRevision 2.0 (May. 10 2005)Add “Pb-free” to ordering informationRevision 2.1 (Jul. 07 2005)-Modify I CC1, I CC2N, I CC3N, I CC4, I CC5 spec-Delete –5.5, -6, -8, -10 AC specRevision 2.2 (Oct. 06 2005)-Add 60V FBGARevision 2.3 (Nov. 15 2005)-Modify VFBGA 60Ball Total high specRevision 2.4 (May. 03 2007)-Delete BGA ball name of packing dimensionsSDRAM 512K x 16Bit x 2BanksSynchronousDRAMFEATURESz JEDEC standard 3.3V power supplyz LVTTL compatible with multiplexed addressz Dual banks operationz MRS cycle with address key programs-CAS Latency (2 & 3 )-Burst Length (1, 2, 4, 8 & full page)-Burst Type (Sequential & Interleave)z All inputs are sampled at the positive going edge of the system clockz Burst Read Single-bit Write operationz DQM for maskingz Auto & self refreshz32ms refresh period (2K cycle)GENERAL DESCRIPTIONThe M12L16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by16 bits, fabricated with high performance CMOS technology.Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.ORDERING INFORMATIONPart NO. MAX Freq. PACKAGE COMMENTSM12L16161A-5TG200MHz TSOP(II) Pb-free M12L16161A-7TG143MHz TSOP(II) Pb-free M12L16161A-7BG143MHz VFBGA Pb-freePIN CONFIGURATION (TOP VIEW)V DD DQ0 DQ1V SSQ DQ2 DQ3V DDQ DQ4 DQ5V SSQ DQ6 DQ7V DDQ LDQMCAS RAS CSBAA10/AP A0A1A2A3V DD V SSDQ15DQ14V SSQDQ13DQ12V DDQDQ11DQ10V SSQDQ9DQ8V DDQN.C/RFUUDQMCLKCKEN.CA9A8A7A6A5A4V SS50PIN TSOP(II)(400mil x 825mil)(0.8 mm PIN PITCH)FUNCTIONAL BLOCK DIAGRAMPIN FUNCTION DESCRIPTIONDQ0 ~ 15 Data Input / Output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved noise immunity.N.C/RFU No Connection/Reserved for Future UseThis pin is recommended to be left No Connection on the device.ABSOLUTE MAXIMUM RATINGSParameter Symbol Value UnitVoltage on any pin relative to V SS V IN,V OUT-1.0 ~ 4.6 VVoltage on V DD supply relative to V SS V DD,V DDQ-1.0 ~ 4.6 VStorage temperature T STG-55 ~ + 150 C°Power dissipation P D 0.7 W Short circuit current I OS 50 MA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, T A=0 to 70C°)Parameter Symbol Min Typ Max Unit NoteSupply voltage V DD,V DDQ 3.0 3.3 3.6 VInput logic high voltage V IH 2.0 3.0V DD+0.3 V 1Input logic low voltage V IL -0.3 0 0.8 V 2 Output logic high voltage V OH 2.4 - - VI OH =-2mAOutput logic low voltage V OL - - 0.4VI OL = 2mAInput leakage current I IL -5 - 5 uA 3 Output leakage current I OL -5 - 5 uA 4 Note : 1.V IH (max) = 4.6V AC for pulse width ≤ 10ns acceptable.2.V IL (min) = -1.5V AC for pulse width ≤ 10ns acceptable.3.Any input 0V≤V IN≤V DD+ 0.3V, all other pins are not under test = 0V.4.Dout is disabled, 0V ≤V OUT≤ VDD.CAPACITANCE (V DD = 3.3V, T A = 25C°, f = 1MHz)DC CHARACTERISTICS°V IH(min)/V IL(max)=2.0V/0.8V) (Recommended operating condition unless otherwise noted, T A = 0 to 70CNote: 1.Measured with outputs open. Addresses are changed only one time during t CC(min).2.Refresh period is 32ms. Addresses are changed only one time during t CC(min).AC OPERATING TEST CONDITIONS (V DD =3.3V ±0.3V,T A = 0 to 70C °)ParameterValue Unit Input levels (Vih/Vil)2.4 / 0.4 V Input timing measurement reference level 1.4 V Input rise and fall timetr / tf = 1 / 1ns Output timing measurement reference level 1.4 V Output load conditionSee Fig.2OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time andthen rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks. (Fig.2) AC Output Load Circuit1.4V(Fig.1) DC Output Load circuitΩAC CHARACTERISTICS (AC operating conditions unless otherwise noted)-5 -7 ParameterSymbol Min Max Min Max UnitNoteCAS Latency =3 5 7 CLK cycle time CAS Latency =2 t CC 710008.61000ns 1CAS Latency =3 - 4.5 - 6CLK to validoutput delayCAS Latency =2t SAC - 5 - 6ns 1Output data hold time t OH 2 2 ns 2 CLK high pulse width t CH 2 2.5 ns 3 CLK low pulse width t CL 2 2.5 ns 3 Input setup time t SS 2 2 ns 3 Input hold time t SH 1 1 ns 3 CLK to output in Low-Z t SLZ 1 1 ns 2 CAS Latency =3 - 5.5 - 6CLK to output in Hi-ZCAS latency =2t SHZ- 5.5 - 6ns*All AC parameters are measured from half to half.Note: 1.Parameters depend on programmed CAS latency.2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.3.Assumed input rise and fall time (tr & tf)=1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter.FREQUENCY vs. AC PARAMENTER RELATIONSHIP TABLEM12L16161A-5T(G)(Unit: number of clock)t RC t RAS t RP t RRD t RCD t CCD t CDL t RDL FrequencyCASLatency 55ns 40ns 15ns 10ns 15ns 5ns 5ns 10ns200MHz(5.0ns) 3 11 8 3 2 3 1 1 2 166MHz(6.0ns) 3 10 7 3 2 3 1 1 2 143MHz(7.0ns) 2 8 6 3 2 3 1 1 2 125MHz(8.0ns) 2 7 5 2 2 2 1 1 2 111MHz(9.0ns) 2 7 5 2 2 2 1 1 2M12L16161A-7T(G)(Unit: number of clock)t RC t RAS t RP t RRD t RCD t CCD t CDL t RDL FrequencyCASLatency 63ns 42ns 20ns 14ns 20ns 7ns 7ns 14ns143MHz(7.0ns) 3 9 6 3 2 3 1 1 2 125MHz(8.0ns) 3 8 6 3 2 3 1 1 2 111MHz(9.0ns) 2 7 5 3 2 3 1 1 2 100MHz(10.0ns) 2 7 5 2 2 2 1 1 2 83MHz(12.0ns) 2 6 4 2 2 2 1 1 2Note : 1. t RDL ≥16.7ns is recommended for M12L16161A.Mode Register11 10 9 8 7 6 5 4 3 2 1 00 0 0 0 1 JEDEC Standard Test Set (refresh counter test) 11 10 9 8 7 6 5 4 3 2 1 0x x 1 0 0 LTMODE WT BL Burst Read and Single Write (for WriteCache)Through11 10 9 8 7 6 5 4 3 2 1 01 0 Use in future11 10 9 8 7 6 5 4 3 2 1 0x x x 1 1 v v v v v v v Vender SpecificMode Register WriteBurst Length and Sequence (Burst of Two)Starting Address(column address A0 binary)Sequential AddressingSequence (decimal)Interleave AddressingSequence (decimal)0 0,10,11 1,01,0 (Burst of Four)Starting Address(column address A1-A0, binary)Sequential AddressingSequence (decimal)Interleave AddressingSequence (decimal)00 0,1,2,30,1,2,301 1,2,3,01,0,3,210 2,3,0,12,3,0,111 3,0,1,23,2,1,0 (Burst of Eight)Starting Address(column address A2-A0, binary)Sequential AddressingSequence (decimal)Interleave AddressingSequence (decimal)000 0,1,2,3,4,5,6,70,1,2,3,4,5,6,7001 1,2,3,4,5,6,7,01,0,3,2,5,4,7,6010 2,3,4,5,6,7,0,12,3,0,1,6,7,4,5011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4100 4,5,6,7,0,1,2,34,5,6,7,0,1,2,3101 5,6,7,0,1,2,3,45,4,7,6,1,0,3,2110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice.POWER UP SEQUENCE1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs.2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.3.Issue precharge commands for all banks of the devices.4.Issue 2 or more auto-refresh commands.5.Issue mode register set command to initialize the mode register.Cf.)Sequence of 4 & 5 is regardless of the order.SIMPLIFIED TRUTH TABLE(V=Valid, X=Don’t Care, H=Logic High , L =Logic Low)Note:1. OP Code: Operation CodeA0~ A10/AP, BA: Program keys.(@MRS)2. MRS can be issued only at both banks precharge state.A new command can be issued after 2 clock cycle of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge command is meant by “Auto”.Auto / self refresh can be issued only at both banks idle state.4. BA: Bank select address.If “Low”: at read, write, row active and precharge, bank A is selected.If “High”: at read, write, row active and precharge, bank B is selected.If A10/AP is “High” at row precharge, BA ignored and both banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued.Another bank read /write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), butmakesHi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1C L O C KC K EC SR A SC A SA D D RW ED QD Q MA10/A P B A*Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.2. Bank active & read/write are controlled by BA.BA Active & Read/Write0 BankAB1 Bank3.Enable and disable auto precharge function are controlled by A10/AP in read/write command.A10/AP BA Operation0 Disable auto precharge, leave bank A active at end of burst.1 Disable auto precharge, leave bank B active at end of burst.10 Enable auto precharge, precharge bank A at end of burst.1 Enable auto precharge, precharge bank B at end of burst.4.A10/AP and BA control bank precharge when precharge command is asserted.A10/AP BA prechargeA0 0 Bank0 1 BankBBanks1 X BothPower Up SequenceC L O C KC K EA D D RD QD Q MA10/A PR o w A c t i v e: D o n 't c a r eBACSRASCASWERead & Write Cycle at Same Bank @Burst Length = 4*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ ) after the clock.3.Access time from Row active command. tcc*(t RCD +CAS latency-1)+t SAC4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst) Burst can’t end in Full Page Mode.Read (A-Bank)(A-Bank)(A-Bank)(A-Bank)W rite (A-Bank)(A-Bank): Don't careQCPage Read & Write Cycle at Same Bank @ Burst Length=4*Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid buscontention.2.Row precharge will interrupt writing. Last data input, t RDL before Row precharge, will be written.3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.CLOCK CKECSRASBAADDR A10/APCL=2CL=3WEDQMRow Active (A-Bank)(A-Bank)(A-Bank)(A-Bank)(A-Bank)(A-Bank)DQPage Read Cycle at Different Bank @ Burst Length=4*Note: 1.CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege.2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.CLOCKCKECSBAADDRA10/AP CL=2CL=3WEDQM(B-Bank)DQPage Write Cycle at Different Bank @Burst Length = 4*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.CLOCKCKE CSRASCASBAADDR A10/AP WEDQMDQ(A-Bank)(B-Bank)Read & Write Cycle at Different Bank @ Burst Length = 4*Note: 1.t CDL should be met to complete write.Read & Write Cycle with auto Precharge @ Burst Length =4*Note: 1.t CDL Should be controlled to meet minimum t RAS before internal precharge start(In the case of Burst Length=1 & 2 and BRSW mode)C L O C KC K EC A SA D D RD QD Q MA10/A P B AC L =2C L =3( B - Bank ): D o n ' t C a r eC SR A SClock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4*Note:1.DQM is needed to prevent bus contention.C L O C KC K EAD D R D Q D Q MA10/A PR e a d D Q MW r i t eS u s p e n s i o n:D o n 't C a r eBAC SR A SC A SW ERead Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page*Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue.2.About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycle”.3.Burst stop is valid at every burst length.C L O C KC K EA D DR D QD Q MA10/A P BAC L =2C L =3CSRASCASWrite Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page*Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue.2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of t RDL .DQM at write interrupted by precharge command is needed to prevent invalid write. Input data after Row precharge cycle will be masked internally. 3.Burst stop is valid at every burst length.C L O C KC K EA D D R D Q D Q MA10/A PC SR A SBABurst Read Single bit Write Cycle @Burst Length=2*Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.2.When BRSW write command with auto precharge is executed, keep it in mind that t RAS should not be violated. Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge command will be issued after two clock cycles.C L O C KC K EA D DR C L =2D Q MA 10/A P BAD QC L =3C SR A SActive/Precharge Power Down Mode @CAS Latency=2, Burst Length=4*Note :1.Both banks should be in idle state prior to entering precharge power down mode.2.CKE should be set high at least 1CLK+tss prior to Row active command.3.Can not violate minimum refresh specification. (32ms)C LA A10Self Refresh Entry & Exit Cycle*Note: TO ENTER SELF REFRESH MODE1. CS ,RAS & CAS with CKE should be low at the same clock cycle.2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.3. The device remains in self refresh mode as long as CKE stays “Low”.cf.) Once the device enters self refresh mode, minimum t RAS is required before exit from self refresh.TO EXIT SELF REFRESH MODE4. System clock restart and be stable before returning CKE high.5. CS Starts from high.6. Minimum t RC is required after CKE going high to complete self refresh exit.7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.C L O C KC K EA D D RD QD Q MA10/A P: D o n 't c a r eBAR A SC SMode Register Set CycleAuto Refresh Cycle*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.MODE REGISTER SET CYCLE*Note: 1.CS ,RAS ,CAS &WE activation at the same clock cycle with address key will set internal mode register.2.Minimum 2 clock cycles should be met before new RAS activation.3.Please refer to Mode Register Set table.C L O C KC K EA D D RC SR A SC A SD QD Q MPACKAGE DIMENSIONS50-LEAD TSOP(II) SDRAM(400mil)PACKING DIMENSIONS60-BALL SDRAM ( 6.4x10.1 mm )Symbol Dimension in mm Dimension in inchMin Norm Max Min Norm MaxA 1.00 0.039A10.20 0.25 0.30 0.0080.0100.012A20.61 0.66 0.71 0.0240.0260.028Φb0.30 0.35 0.40 0.0120.0140.016D 6.30 6.40 6.50 0.2480.2520.256E 10.00 10.1010.200.3940.3980.402D1 3.90 0.154E19.10 0.358e 0.65 0.026Controlling dimension : Millimeter.Important NoticeAll rights reserved.No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT.The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice.The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others.Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs.ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.。
M12L128168A(2L)
SDRAM 2M x 16 Bit x 4 BanksSynchronous DRAMFEATURESy JEDEC standard 3.3V power supplyy LVTTL compatible with multiplexed addressy Four banks operationy MRS cycle with address key programs- CAS Latency ( 2 & 3 )- Burst Length ( 1, 2, 4, 8 & full page )- Burst Type ( Sequential & Interleave )y All inputs are sampled at the positive going edge of the system clocky Burst Read single write operationy DQM for maskingy Auto & self refreshy64ms refresh period (4K cycle)ORDERING INFORMATIONProduct ID Max Freq. Package Comments M12L128168A-5TG2L200MHz 54 Pin TSOP II Pb-free M12L128168A-5BG2L200MHz 54 Ball FBGAPb-freeM12L128168A-6TG2L166MHz 54 Pin TSOP IIPb-freeM12L128168A-6BG2L166MHz 54 Ball FBGA Pb-freeM12L128168A-7TG2L143MHz 54 Pin TSOP II Pb-freeM12L128168A-7BG2L143MHz 54 Ball FBGA Pb-freeGENERAL DESCRIPTIONThe M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.PIN CONFIGURATION (TOP VIEW) BALL CONFIGURATION (TOP VIEW)(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch )(BGA 54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2010BLOCK DIAGRAMPIN DESCRIPTIONDQElite Semiconductor Memory Technology Inc. Publication Date : Jul. 2010ABSOLUTE MAXIMUM RATINGSParameter Symbol Value UnitVoltage on any pin relative to V SS V IN , V OUT -1.0 ~ 4.6 V Voltage on V DD supply relative to V SS V DD , V DDQ -1.0 ~ 4.6 V Storage temperature TSTG -55 ~ +150C ° Power dissipation PD1WShort circuit currentI OS 50 mANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.DC OPERATING CONDITIONRecommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70C °)Parameter Symbol Min Typ Max Unit NoteSupply voltage V DD , V DDQ 3.0 3.33.6VInput logic high voltage V IH 2.0 3.0 V DD +0.3 V 1Input logic low voltage V IL -0.3 0 0.8 V 2Output logic high voltage V OH 2.4 --V I OH= -2mAOutput logic low voltage V OL - - 0.4 V I OL = 2mA Input leakage current I IL -5 - 5 μA 3 Output leakage currentI OL -5 - 5 μA4Note: 1. V IH (max) = 4.6V AC for pulse width ≤ 10ns acceptable.2. V IL (min) = -1.5V AC for pulse width ≤ 10ns acceptable.3. Any input 0V ≤ V IN ≤ V DD , all other pins are not under test = 0V.4. Dout is disabled, 0V ≤ V OUT ≤ V DD .CAPACITANCE (V DD = 3.3V, T A = 25C °, f = 1MHz)DC CHARACTERISTICS°Recommended operating condition unless otherwise noted，T A = 0 to 70CNote: 1. Measured with outputs open.2. Input signals are changed one time during 2 CLKS.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2010AC OPERATING TEST CONDITIONS (V DD = 3.3V ±0.3V ， T A = 0 to 70C °)Parameter Value UnitInput levels (Vih/Vil)2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall-timetr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load conditionSee Fig. 2(Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load CircuitOPERATING AC PARAMETER(AC operating conditions unless otherwise noted)Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and thenrounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.5. A new command may be given t RFC after self refresh exit.6. A maximum of eight consecutive AUTO REFRESH commands (with t RFC (min)) can be posted to any given SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6μs.)Outp utΩElite Semiconductor Memory Technology Inc. Publication Date : Jul. 2010AC CHARACTERISTICS (AC operating condition unless otherwise noted)-5 -6 -7Parameter SymbolMIN MAX MIN MAX MIN MAX Unit NoteCAS latency = 3 5 6 7CLK cycle time CAS latency = 2t CC10 100010 100010 1000ns 1 CAS latency = 3 -4.5-5.4-5.4CLK to validoutput delay CAS latency = 2t SAC- 6 - 6 - 6 ns 1,2CAS latency =32 - 2 - 2 - Output data hold time CAS latency = 2t OH2 - 2 - 2 -ns 2CLK high pulse width t CH 2 - 2.5 - 2.5 - ns 3 CLK low pulse width t CL 2 - 2.5 - 2.5 - ns 3 Input setup time t SS 1.5 - 1.5 - 1.5 - ns 3 Input hold time t SH 0.85- 1 - 1 - ns 3CLK to output in Low-Z t SLZ 1 - 1 - 1 - ns 2 CAS latency = 3 -4.5-5.4-5.4CLK to output in Hi-ZCAS latency = 2 t SHZ- 6 - 6 - 6ns-Note: 1. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.3. Assumed input rise and fall time (tr & tf) =1ns. If tr & tf is longer than 1ns. transient time compensation should be considered. i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.SIMPLIFIED TRUTH TABLE(V =Valid, X =Don’t Care. H =Logic High, L =Logic Low) Note: 1.OP Code: Operating CodeA0~A11 & BA0~BA1: Program keys. (@ MRS)2.MRS can be issued only at all banks precharge state.A new command can be issued after 2 CLK cycles of MRS.3.Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge of command is meant by “Auto”.Auto/self refresh can be issued only at all banks idle state.4.BA0~BA1: Bank select addresses.If BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.If BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selectedIf A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.5.During burst read or write with auto precharge, new read/write command can not be issued.Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after the end of burst.6.Burst stop command is valid at every burst length.7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), butmakes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010MODE REGISTER FIELD TABLE TO PROGRAM MODESRegister Programmed with MRSAddress BA0~BA1 A11~A10/AP A9 A8A7A6A5A4A3 A2 A1 A0Function RFU RFU W.B.L.TM CAS Latency BT Burst LengthTest Mode CAS Latency Burst Type Burst LengthA8 A7 Type A6 A5 A4Latency A3Type A2A1 A0 BT = 0BT = 1Set0 0 0 Reserved0 Sequential0 0 0 1 1 Register0 0 Mode0 1 Reserved 0 0 1 Reserved 1 Interleave0 0 1 2 21 0 Reserved 0 1 02 0 1 0 4 41 3 0 1 1 8 8111 Reserved 0Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved A9 Length 1 0 1 Reserved 1 0 1 Reserved ReservedReserved Reserved0 Burst 111Reserved 1Reserved 1 1 1 FullPage Reserved1Bit 11 Single1Full Page Length: 512Note: 1. RFU (Reserved for future use) should stay “0” during MRS cycle.2. If A9 is high during MRS cycle, “Burst Read single write” function will be enabled.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010BURST SEQUENCE (BURST LENGTH = 4)Initial AddressSequential Interleave A1 A00 0 0 1 2 3 0 1 2 30 1 1 2 3 0 1 0 3 21 023 0 1 2 3 0 11 1 3 0 123 2 1 0BURST SEQUENCE (BURST LENGTH = 8)Initial AddressSequential Interleave A2 A1 A00 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 70 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 60 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 50 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 41 0 0 4 5 6 7 0 1234567 0 1 2 31 0 1 5 6 7 0 12345 4 76 1 0 3 21 1 0 6 7 0 1234567 4 5 2 3 0 11 1 1 7 0 1234567 6 5 4 3 2 1 0Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010DEVICE OPERATIONSCLOCK (CLK)The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V IL and V IH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and I CC specifications.CLOCK ENABLE(CKE)The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least “1CLK + t SS” before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.BANK ADDRESSES (BA0~BA1)This SDRAM is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. The BA0~BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The banks addressed BA0~BA1 are latched at bank active, read, write, mode register set and precharge operations.ADDRESS INPUTS (A0~A11)The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (A0~A11). The 12 row addresses are latched along with RAS and BA0~BA1 during bank active command. The 9 bit column addresses are latched along with CAS, WE and BA0~BA1 during read or with command.NOP and DEVICE DESELECTWhen RAS, CAS and WE are high , The SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored. POWER-UP1.Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at the inputs.2.Maintain stable power, stable clock and NOP input condition for minimum of 200us.3.Issue precharge commands for all banks of the devices.4.Issue 2 or more auto-refresh commands.5.Issue a mode register set command to initialize the mode register.cf.) Sequence of 4 & 5 is regardless of the order.The device is now ready for normal operation.MODE REGISTER SET (MRS)The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE(The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11 and BA0~BA1in the same cycle as CS, RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields into depending on functionality. The burst length field uses A0~A2, burst type uses A3, CAS latency (read latency from column address) use A4~A6, vendor specific options or test mode use A7~A8, A10/AP~A11 and BA0~BA1. The write burst length is programmed using A9. A7~A8, A10/AP~A11 and BA0~BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.BANK ACTIVATEThe bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of t RCD(min) from the time of bank activation. t RCD is the internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t RCD(min) with cycle time of the clock and thenElite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010DEVICE OPERATIONS (Continued)rounding of the result to the next higher integer. The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies to recover before another bank can be sensed reliably. t RRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to t RCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t RAS(min). Every SDRAM bank activate command must satisfy t RAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by t RAS(max) and t RAS(max) can be calculated similar to t RCD specification.BURST READThe burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CSand RAS with WE being high on the positive edge of the clock. The bank must be active for at least t RCD(min)before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length.BURST WRITEThe burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be complete by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and precharge the bank t RDL after the last data input to be written into the active row. See DQM OPERATION also. DQM OPERATIONThe DQM is used mask input and output operations. It works similar to OE during operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. Please refer to DQM timing diagram also. PRECHARGEThe precharge is performed on an active bank by asserting low on clock cycles required between bank activate and clock cycles required between bank activate and CS, RAS, WE and A10/AP with valid BA0~BA1 of the bank to be procharged. The precharge command can be asserted anytime after t RAS(min) is satisfy from the bank active command in the desired bank. t RP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing t RP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t RAS(max). Therefore, each bank has to be precharge with t RAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state.AUTO PRECHARGEThe precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy t RAS(min) and “t RP” for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst write by asserting high on A10/AP, the bank is precharge command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state.FOUR BANKS PRECHARGEFour banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with high on A10/AP after all banks have satisfied t RAS(min)requirement, performs precharge on all banks. At the end of t RP after performing precharge all, all banks are in idle state.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010DEVICE OPERATIONS (Continued)AUTO REFRESHThe storage cells of SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS, RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by t RFC(min). The minimum number of clock cycles required can be calculated by driving t RFC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP’s until the auto refresh operation is completed. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us. SELF REFRESHThe self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption.The self refresh mode is entered from all banks idle state by asserting low on CS, RAS, CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the refresh.The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of t RFC before the SDRAM reaches idle state to begin normal operation. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010Mode register set command(CS,RAS,CAS,WE =Low)The M12L128168A has a mode register that defines how the device operates. Inthis command, A0~A11 and BA0~BA1 are the data input pins. After power on, themode register set command must be executed to initialize the device.The mode register can be set only when all banks are in idle state.During 2CLK following this command, the M12L128168A cannot accept anyother commands.(CS,RAS =Low,CAS,WE= High)The M12L128168A has four banks, each with 4,096 rows.This command activates the bank selected by BA1 and BA0 (BS) and a rowaddress selected by A0 through A11.This command corresponds to a conventional DRAM’s RAS falling.Precharge command(CS,RAS,WE =Low,CAS= High )This command begins precharge operation of the bank selected by BA1 and BA0(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.When A10 is Low, only the bank selected by BA1 and BA0 is precharged.After this command, the M12L128168A can’t accept the activate command to theprecharging bank during t RP (precharge to activate command period).This command corresponds to a conventional DRAM’s RAS rising.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2010Write command(CS ,CAS ,WE = Low, RAS = High)If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst can be input with this command with subsequent data on following clocks.Read command(CS ,CAS = Low, RAS ,WE = High)Read data is available after CAS latency requirements have been met. This command sets the burst start address given by the column address.CBR (auto) refresh command(CS ,RAS ,CAS = Low, WE , CKE = High)This command is a request to begin the CBR refresh operation. The refresh address is generated internally.Before executing CBR refresh, all banks must be precharged.After this cycle, all banks will be in the idle (precharged) state and ready for arow activate command.During t RFCperiod (from refresh command to refresh or activate command), the M12L128168A cannot accept any other command.Self refresh entry command(CS,RAS,CAS, CKE = Low ,WE =High)After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the M12L128168A exits the self refresh mode.During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control.Before executing self refresh, all banks must be precharged.Burst stop command(CS,WE =Low,RAS,CAS =High)This command terminates the current burst operation.Burst stop is valid at every burst length.No operation(CS= Low ,RAS,CAS,WE=High)This command is not a execution command. No operations begin or terminate bythis command.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010BASIC FEATURE AND FUNCTION DESCRIPTIONS1. CLOCK Suspend*Note: 1. CKE to CLK disable/enable = 1CLK.2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.3. DQM masks both data-in and data-out.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 20103. CAS Interrupt (I)*Note: 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.By ”CAS interrupt ”, to stop burst read/write by CAS access ; read and write.2. t CCD:CAS to CAS delay. (=1CLK)3. t CDL: Last data in to new column address delay. (=1CLK)Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 20104. CAS Interrupt (II): Read Interrupted by Write & DQMElite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010*Note: 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.2. To inhibit invalid write, DQM should be issued.3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interruptbut only another bank precharge of four banks operation.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 20106. Precharge*Note: 1. t RDL: Last data in to row precharge delay.2. Number of valid output data after row precharge: 1, 2 for CAS Latency = 2, 3 respectively.3. The row active command of the precharge bank can be issued after t RP from this point.The new read/write command of other activated bank can be issued from this point.At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 20108. Burst Stop & Interrupted by Precharge9. MRS*Note: 1. t BDL: 1 CLK; Last data in to burst stop delay.Read or write burst stop command is valid at every burst length.2. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely.3. Write burst is terminated. t BDL determinates the last data write.4. DQM asserted to prevent corruption of locations D2 and D3.5. Precharge can be issued here or earlier (satisfying t RAS min delay) with DQM.6. PRE: All banks precharge, if necessary.MRS can be issued only at all banks precharge state.Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 201010. Clock Suspend Exit & Power Down Exit*Note: 1. Active power down : one or more banks active state.2. Precharge power down: all banks precharge state.3. The auto refresh is the same as CBR refresh of conventional DRAM.No precharge commands are required after auto refresh command.During t RFC from auto refresh command, any other command can not be accepted.4. Before executing auto/self refresh command, all banks must be idle state.5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.6. During self refresh entry, refresh interval and refresh operation are performed internally.After self refresh entry, self refresh mode is kept while CKE is low.During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.For the time interval of t RFC from self refresh exit command, any other command can not be accepted.4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. Elite Semiconductor Memory Technology Inc.Publication Date: Jul. 2010。
各品牌闪存
现在仍然有很多刚入行的工程师对快闪记忆体的SLC和MLC不知如何识别,只知道价格便宜是MLC，价格高的就是SLC，如何区分还是一知半解。
我们就拿正在走下坡路的MP4作为案例，是买SLC还是MLC快闪记忆体好呢？在这里我先告诉大家，如果你对容量要求不高，但是对机器品质、资料的安全性、读和取速度、机器寿命等多方面要求较高时，那么SLC肯定是你的首选。
但是大容量的SLC记忆体成本要比MLC记忆体成本高很多，所以针对2G以上的大容量市场，低价格的MP4多采用MLC记忆体。
大容量、低价格的MLC记忆体自然是受大家的表睐。
但它也有先天性的缺点，需要我们对其进行详细了解一番。
什么SLC？SLC英文全称（Sigle Level Cell---- SLC）既单层式储存。
主要由三星、海力士、美光、东芝等使用。
SLC技术特点是在浮置栅极与源极之中的氧化薄腊更薄，在写入资料时通过对浮置栅极的电荷加电压，然后通过源极，既可将所储存的电荷消除，通过这样的方式，便可储存1个资讯单元，这种技术能提供快速的程式编程与读取，不过此技术受限于Silicon efficiency的问题，必须要由先进的工艺流程来强化技术，才能向上提升SLC制程技术。
什么是MLC？MLC英文全称（Multi Level Cell——MLC)既多层式储存。
主要由三星、海力士、美光、东芝等使用。
英特尔在1997年9月最先开发成功MLC，其作用是将两个单位的资讯存入一个Floating Gate（快闪记忆体存储单元中存放电荷的部分），然后利用不同电位的电荷，通过记忆体储存的电压精准控制其读写。
MLC通过使用大量的电压等级，每一个单元储存两单元资料，资料密度比较大。
SLC架构有0和1两个值，而MLC架构可以一次储存4个以上的值。
因此，MLC架构可以有比较好的储存密度。
SLC相对于MLC的优势：目前市场上主要以SLC和MLC储存为主，我们多了解下SLC和MLC储存。
超级mini：傻多RB-1602无线路由器评测
【IT168 评测】编者按：我们希望通过一个不受外界因素干扰的，最多的产品横向测试，让用户在购买路由器的时候能有一个参考的标准，从而买到符合自己需求的满意产品，这是我们编辑最朴素的理想。
然而在不知不觉中，我们发现我们创造了一个记录，成为业内首次在同一个测试环境下最大规模的无线路由器横评(100款)，几乎在北京市场上可以买到的产品，都囊括在内了。
投我以木桃，报之以琼瑶，在21世纪第一个10年即将结束的时候，我们以此次100多篇文章的发布，感谢读者多年来对我们的帮助，感谢在横评中帮助我们的朋友们。
▲ 傻多 RB-1602无线路由器符合IEEE 802.11b/g/n无线标准,300M无线传输速率。
支持220V交流电，笔记本USB供电，外置电池以及车载设备供电，机身上的Mini USB埠，让行动不受限，出门在外随时连接笔记本、电池盒、或车充等供电，直接接收公共热点讯号就可以分享网路连线，不需要担心找不到插座。
支持无线桥接功能，延伸无线讯号不用拉线也毋须繁琐设定，只要一个按键立即完成WDS，无线网路从此无死角。
目前此款产品在淘宝网上的价格是199元。
今天，我们IT168网络评测室为您带来关于这款产品的最新全面评测! 产品评测总体评价： 性能总结：傻多 RB-1602在无线信号整体稳定性上表现良好。
信号覆盖还不错，在距离21米并穿过一个房间后，信号强度为40%，信号穿墙性能不错，距离15米穿过两面承重墙后信号强度为39%。
性价比评论：超级小巧的无线路由器，硬件配置较一般，无线传输速度稳定，传输速度也还不错。
对一款如此“不经眼”的mini型路由器来说，其无线性能还是很不错的。
外观设计及材质评论：傻多 RB-1602采用塑料外壳，全白超mini型机身，做工精致，小巧美观。
产品展望及总结：超便携迷你型无线路由器，性能还不错。
对要求较高移动性的购买者吸引力不小。
产品外观及内部介绍▲傻多 RB-1602路由器外观及包装：300Mbps单天线无线路由器。
LM8168LED数码管驱动芯片
LM8168LED数码管驱动芯⽚LM8168 LED数码管驱动芯⽚LM8168是⼀种专门⽤于各种LED显⽰驱动及扫描按键控制芯⽚。
主要应⽤于各种LED显⽰屏、数码管显⽰屏的驱动，具有外围元件少、连线简单、使⽤简易灵活的特点。
⼀、特性：●采⽤三线串⾏通讯输⼊；●移位锁存后直接输出驱动；●10位段输出15mA；●8位公共端输出150 mA；●可级联使⽤扩展驱动多位数码，如⽤4⽚驱动32位数码管；●漏极开路输出，所以可复⽤。
●可代换1628，1638，1629，74HC164●超强抗⼲扰设计，⽆需增加抗⼲扰元件及抗⼲扰处理，甚⾄可去掉电源滤波电容。
⼆、管脚定义：LM8168A（20PIN SOP）LM8168B（24PIN SOP）三、管脚名称及其功能说明：四、LM8168逻辑原理说明：内部电路（D0~-D17~为寄存器CLK上升时改变，D0－－D17为寄存器EN ＝1时等于D0～－D17～，EN＝0不变。
）当CLK上升时DATA－》D0~ , D0~－》D1~,。
D16~->D17~EN=0时，D0、D1。
D17不变。
EN=1时，D0＝D0～，D1＝D1～。
D17=D17~D0通过输出电路直接输出Q0 。
时序图：五、电⽓参数：1、直流电参数：2、极限参数（Ta = 25℃, Vss = 0 V）六、典型应⽤电路1、LM8168A⽤于驱动4位数码管显⽰和24个LED指⽰灯以及16个按键，本应⽤将LM8168A与4位数码管做成⼀个模块，更⽅便构成显⽰和按键单元及易于软件排版。
七、封装规格。