How_to_implement_the_circuit_in_EAB_within_VHDL_coding

How do I implement this within EAB
if (clk'event and clk='1') then library ieee; case present_state is use ieee.std_logic_1164.all; when idle => if (serial_in = '0') then package your_own_type is present_state <= state0; type t_state is (idle,state0,state01,state011, else state0110,state01101, present_state <= idle; state011011); end if; end your_own_type; when state0 => if (serial_in = '1') then present_state <= state01; library ieee; else use ieee.std_logic_1164.all; present_state <= idle; use work.your_own_type.all; end if; Entity stmh is when state01 => if (serial_in = '1') then port (clk, serial_in, reset : in std_logic; present_state <= state011; match : out std_logic); else end stmh; present_state <= idle; end if; architecture body_stmh of stmh is when state011 => if (serial_in = '0') then signal present_state : t_state; present_state <= state0110; begin else process(clk,serial_in, present_state) present_state <= idle; begin end if; if (reset = '1') then when state0110 => if (serial_in = '1') then present_state <= idle; present_state <= state01101; else else Copyright 1997 Altera Corporation 9/28/2010 P.4 present_state <= idle; end if;
Байду номын сангаас
How many Input signal for this design
– Serial_in, State_Machine (3 bits) 4 bits can implement it
Where is the Clock signal use for
– Use for the DFF of the State Machine
Serial_in clk
VHDL State Machine
Match
Copyright 1997 Altera Corporation
9/28/2010
P.2
Sample VHDL coding
if (clk'event and clk='1') then library ieee; case present_state is use ieee.std_logic_1164.all; when idle => if (serial_in = '0') then package your_own_type is present_state <= state0; type t_state is (idle,state0,state01,state011, else state0110,state01101, present_state <= idle; state011011); end if; end your_own_type; when state0 => if (serial_in = '1') then present_state <= state01; library ieee; else use ieee.std_logic_1164.all; present_state <= idle; use work.your_own_type.all; end if; Entity stmh is when state01 => if (serial_in = '1') then port (clk, serial_in, reset : in std_logic; present_state <= state011; match : out std_logic); else end stmh; present_state <= idle; end if; architecture body_stmh of stmh is when state011 => if (serial_in = '0') then signal present_state : t_state; present_state <= state0110; begin else process(clk,serial_in, present_state) present_state <= idle; begin end if; if (reset = '1') then when state0110 => if (serial_in = '1') then present_state <= idle; present_state <= state01101; else else Copyright 1997 Altera Corporation 9/28/2010 P.3 present_state <= idle; end if;
when state01101 => if (serial_in = '1') then present_state <= state011011; else present_state <= idle; end if; when state011011 => present_state <= idle; when others => present_state <= idle; end case; end if; end if; end process; process(present_state) begin if (present_state = state011011) then match <= '1'; else match <= '0'; end if; end process; end body_stmh;
– Idle, State0, State01, State011, State0110, State01101, State011011 7 states, can use 3 bits to implement it
How many output from this design
– Match, State_Machine (3 bits) 4 bit to implement it
Copyright 1997 Altera Corporation
9/28/2010
P.6
Feedback Path
– Use to feedback the output to the input of the state machine
case present_state is when idle => if (serial_in = '0') then present_state <= state0; else present_state <= idle; end if;
Design a state machine that will detect a Serial pattern of “011011”
from a serial_in stream When this pattern is detected set match = ‘1’ output for one cycle Test your design by Input the following pattern “011101”, “011011”
How to implement the circuit in EAB within VHDL coding
Danny Mok Altera HK FAE (dmok@)
Copyright 1997 Altera Corporation
9/28/2010
P.1
State Machine Design
9/28/2010
P.8
Review of EAB of 10K Device
DATA: 8,4,2,1 wide ADDR: 11,10,9,8 wide
D
D
RAM/ROM 256x8 512x4 1024x2 2048x1
D
Q: 8,4,2,1 wide
D
WE
Input CLK
Write Pulse Circuit