MB8501S064AC-67中文资料

168-pin, 1 Clock, 1-bank, based on 1 M × 16 BIT SDRAMs with SPDs DESCRIPTIONThe Fujitsu MB8501S064AB is a fully decoded, CMOS Synchronous Dynamic Random Access Memory (SDRAM) Module consisting of four MB811161622A devices which organized as two banks of 1 M × 16 bits and a 2 K-bit serial EEPROM on a 168-pin glass-epoxy substrate.The MB8501S064AB features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence.The MB8501S064AB is optimized for those applications requiring high speed, high performance and large memory storage, and high density memory organizations.This module is ideally suited for workstations, PCs, laser printers, and other applications where a simple interface is needed.s PRODUCT LINE & FEATURESParameter MB8501S064AC-100MB8501S064AC-84MB8501S064AC-67 Clock Frequency100 MHz max.84 MHz max.67 MHz max.Burst Mode Cycle Time 10 ns max. (CL = 3)15 ns max. (CL = 2)12 ns max. (CL = 3)17 ns max. (CL = 2)15 ns max. (CL = 3)20 ns max. (CL = 2)RAS Access Time54 ns max.56 ns max.60 ns max. CAS Access Time24 ns max.26 ns max.30 ns max.Output Valid from Clock 8.5 ns max. (CL = 3)9 ns max. (CL = 2)8.5 ns max. (CL = 3)9 ns max. (CL = 2)9 ns max. (CL = 3)10 ns max. (CL = 2)Power Dissipation Burst Mode1944 mW max.1800 mW max.1620 mW max. Power Down Mode28.8 mW max.•Un-buffered 168-pin DIMM Socket Type(Lead pitch: 1.27 mm)•Conformed to JEDEC Standard (1 CLK)•Organization: 1,048,576 words × 64 bits•Memory : MB811171622A (1 M × 16, 2-bank) × 4 pcs.•3.3 V ±0.3 V Supply Voltage•All input/output LVTTL compatible •2048 Refresh Cycle every 32.8 ms•Auto and Self Refresh•CKE Power Down Mode•DQM Byte Masking (Read/Write)•Serial Presence Detect (SPD) with Serial EEPROM •Module size:1.0” (height) × 5.25” (length) × 0.110” (thick)2s PACKAGE3s PIN ASSIGNMENTSPin No.Signal Name Pin No.Signal Name Pin No.Signal Name Pin No.Signal Name Pin No.Signal NamePin No.Signal Name1V SS 29DQMB 157DQ 1885V SS 113DQMB 5141DQ 502DQ 030CS 058DQ 1986DQ 32114N.C.142DQ 513DQ 131N.C.59V CC 87DQ 33115RAS 143V CC 4DQ 232V SS 60DQ 2088DQ 34116V SS 144DQ 525DQ 333A 061N.C.89DQ 35117A 1145N.C.6V CC 34A 262N.C.90V CC 118A 3146N.C.7DQ 435A 463N.C.91DQ 36119A 5147N.C.8DQ 536A 664V SS 92DQ 37120A 7148V SS 9DQ 637A 865DQ 2193DQ 38121A 9149DQ 5310DQ 738A 1066DQ 2294DQ 39122A 11150DQ 5411DQ 839N.C.67DQ 2395DQ 40123N.C.151DQ 5512V SS 40V CC 68V SS 96V SS 124V CC 152V SS 13DQ 941V CC 69DQ 2497DQ 41125N.C.153DQ 5614DQ 1042CLK 070DQ 2598DQ 42126N.C.154DQ 5715DQ 1143V SS 71DQ 2699DQ 43127V SS 155DQ 5816DQ 1244N.C.72DQ 27100DQ 44128CKE 156DQ 5917DQ 1345CS 273V CC 101DQ 45129N.C.157V CC 18V CC 46DQMB 274DQ 28102V CC 130DQMB 6158DQ 6019DQ 1447DQMB 375DQ 29103DQ 46131DQMB 7159DQ 6120DQ 1548N.C.76DQ 30104DQ 47132N.C.160DQ 6221N.C.49V CC 77DQ 31105N.C.133V CC 161DQ 6322N.C.50N.C.78V SS 106N.C.134N.C.162V SS 23V SS 51N.C.79N.C.107V SS 135N.C.163N.C.24N.C.52N.C.80N.C.108N.C.136N.C.164N.C.25N.C.53N.C.81N.C.109N.C.137N.C.165SA 026V CC 54V SS 82SDA 110V CC 138V SS 166SA 127WE 55DQ 1683SCL 111CAS 139DQ 48167SA 228DQMB 056DQ 1784V CC112DQMB 4140DQ 49168V CC4s PIN DESCRIPTIONSymbol I/O Function Symbol I/O FunctionA0 to A11I Address Input DQ0 to DQ63I Data Input/Data Output RAS I Row Address Strobe V CC I/O Power Supply (+3.3 V) CAS I Column Address Strobe V SS—Ground (0 V)WEI Write Enable N.C.—No ConnectionDQMB0 to DQMB7I Data (DQ) Mask SA0 to SA2—Serial PD Address Input CLK0I Clock Input SCL I Serial PD ClockCKE I Clock Enable SDA I/OSerial PD Address/DataInput/Output CS0,CS2I Chip Select5s SERIAL-PD INFORMATIONNote:Any write operation must NOT be executed into the addresses of Byte 0 to Byte 127.Some or all data stored into Byte 0 to Byte 127 may be broken.(*) Byte 14 : SDRAM Device Attributes Byte Function DescribedBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit00123456789101112131415161718192021 to 3132 to 6364 to 125126127128+Defines Number of Bytes Written into Serial Memory at Module Manufacture Total Number of Bytes of SPD Memory Fundamental Memory Type Number of Row Addresses Number of Column Addresses Number of Module Banks Data WidthData Width (Continuation)Interface TypeSDRAM Cycle Time SDRAM Access from ClockDIMM Configuration T ype Refresh Rate/T ypeSDRAM Module Attributes SDRAM Device AttributesMinimum Clock Delay Back to Back Random Column AddressBurst Lengths Supported Number of Banks on Each SDRAM Device CAS Latency CS Latency Write Latency Reserved for Future Offerings Superset Information Manufacturer’s Information Intel Specification Frequency Intel Specification CAS Latency Unused Storage Locations 128 Byte 256 Byte SDRAM 1181 bank 64 bit +0LVTTL 10 ns 12 ns 15 ns 8.5 ns 9 ns Non-Parity Self, Norm UN-Buffer(*)1 Cycle1, 2, 4, 82 bank 2, 300–––66 MHz 2, 3–10000000011111010000000000000–00000010001100000000000000010–00000000010100000000000000010–00000000000101000000000000000–01011000000000000001000000000–00100000000010000101010000011–00010000000000000101110000011–00010100100010000011001100000–Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0TBD TBD TBD TBD Supported Single Write/Burst ReadSupported Precharge AllSupported Auto-PrechargeSupported Early RAS Precharge1167s ABSOLUTE MAXIMUM RATINGS (See WARNING)* :Voltages referenced to V SS (= 0 V)WARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current,temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.s RECOMMENDED OPERATING CONDITIONS*1.Voltages referenced to V SS (= 0 V)*2.V IL (min) = –1.5 V AC (Pulse Width ≤ 5 ns)WARNING:Recommended operating conditions are normal operating ranges for the semiconductor device. Allthe device’s electrical characteristics are warranted when operated within these ranges.Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure.No warranty is made with respect to uses , operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.s CAPACITANCE(V CC = +3.3 V , f = 1 MHz, T A = +25°C)ParameterSymbol ValueUnit Min.Max.Supply Voltage*V CC –0.5+4.6V Input Voltage*V IN –0.5+4.6V Output Voltage*V OUT –0.5+4.6V Storage Temperature T STG –55+125°C Power Dissipation P D — 5.2W Output Current (D.C.)I OUT–50+50mAParameterNotesSymbol Value Unit Min.Typ.Max.Supply Voltage*1V CC 3.0 3.3 3.6V V SS 000V Input High Voltage, All Inputs *1V IH 2.0—V CC +0.5V Input Low Voltage, All Inputs *1, 2V IL –0.5—0.8V Ambient T emperatureT A—+70°CParameterSymbol ValueUnit Min.Max.Input CapacitanceA 0 to A 11C IN1—30pF RAS, CAS, WE C IN2—29pF CS 0, CS 2C IN3—15pF CKE C IN4—29pF CLK 0C IN5—29pF DQMB 0 to DQMB 7C IN6—11pF SCLC SCL —6pF SA 0, SA 1, SA 2C SA —5pF Input/Output CapacitanceSDAC SDA —6pF DQ 0 to DQ 63C DQ—11pF8s DC CHARACTERISTICS(At recommended operating conditions unless otherwise noted.)Notes:*1.Voltages referenced to V SS (= 0 V)*2.I CC depends on the output termination, load conditions, clock cycle rate and signal clock rate.The specified values are obtained with the output open and no termination register.*3.An initial pause (DESL on NOP) of 200 µs is required after power-on followed by a minimum of eight Auto-Refresh cycles.*4.DC characteristics is the Serial PD standby state ( V IN = GND or V CC).Parameter Notes Symbol ConditionValueUnitMin.Max.Operating Current(Average PowerSupply Current)*2MB8501S064AC-100I CC1SNo Burst;t CK = mint RC = minOne Bank Active—340mAMB8501S064AC-84320mAMB8501S064AC-67300mAMB8501S064AC-100I CC1DNo Burst;t CK = mint RC = minAll Banks Active—520mAMB8501S064AC-84480mAMB8501S064AC-67440mA Precharge StandbyCurrent (PowerSupply Current)*2I CC2PCKE = V IL, t CK = minAll Banks Idle—8mAI CC2NCKE = V IH, t CK = minAll Banks Idle—120mAActive StandbyCurrent (PowerSupply Current)*2I CC3PCKE = V IL, t CK = minAny Bank Active—120mAI CC3NCKE = V IH, t CK = minAny Bank Active—200mABurst Mode Current(Average PowerSupply Current)*2MB8501S064AC-100I CC4t CK = min—540mAMB8501S064AC-84—500mAMB8501S064AC-67—460mAAuto-refresh Current(Average PowerSupply Current)*2MB8501S064AC-100I CC5Auto Refresht CK = mint RC = mint RRD = min—440mAMB8501S064AC-84—400mAMB8501S064AC-67—360mA Self-refresh Current(Average Power Supply Current)I CC6t CK = V IL—8mA Input Leakage Current (All Inputs)I I (L)0 V ≤ V IN≤ V CCAll other pins notunder test = 0 V3.0 V ≤ V CC≤ 3.6 V–3030µA Output Leakage Current I O (L)Output is disabled (Hi-Z)0 V ≤ V OUT≤ V CC3.0 V ≤ V CC≤ 3.6 V–1010µALVTTL OutputHigh Voltage*1V OH I OH = –2.0 mA 2.4—VLVTTL OutputLow Voltage*1V OL I OL = +2.0 mA—0.4V9s AC CHARACTERISTICS(1)BASE CHARACTERISTICS(At recommended operating conditions unless otherwise noted.)No.ParameterNotesSymbol MB8501S064AC -100MB8501S064AC -84MB8501S064AC-67Unit Min.Max.Min.Max.Min.Max.1Clock Period CL = 3t CK 10—12—15—ns CL =215—17—20—ns 2Clock High Time t CH 4—4—4—ns 3Clock Low Time t CL 4—4—4—ns 4CS Set Up Time t SC3—3—3—ns 5CS Hold Time t HC 1—1—1—ns 6Input Set Up Time t SI 3—3—3—ns 7Input Hold Time t HI 1—1—1—ns 8Data Input Set Up Time t SID 3—3—3—ns 9Data Input Hold Time t HID1—1—1—ns10Output Validfrom Clock (t CLK = min)*1, *2CL = 3t AC —8.5—8.5—9ns CL =2—9—9—1011Output in Low-Z t OLZ3—3—3—ns 12Output in High-Z *3t OHZ 3—3—3—ns 13Output Hold Time t OH 3—3—3—ns 14Time between Refresh t REF —32.8—32.8—32.8ms 15Transition Time t T 0.520.520.52ns 16Power Down Exit Timet PDE3—4—5—ns10(2)BASE VALUES FOR CLOCK COUNT/LATENCY(3)CLOCK COUNT FORMULA (*8)(4)LATENCY (The latency values on these parameters are fixed regardless of clock period.) No.Parameter Notes SymbolMB8501S064AC-100MB8501S064AC-84MB8501S064AC-67UnitMin.Max.Min.Max.Min..Max.1RAS Cycle Time*4t RC90—100—110—ns 2RAS Access Time*5t RAC—54—56—60ns 3CAS Access Time*6, *9t CAC—24—26—30ns 4RAS Precharge Time t RP30—35—40—ns 5RAS Active Time t RAS601000006510000070100000ns 6RAS to CAS Delay Time*7t RCD30—30—30—ns 7Write Recovery Time t WR10—12—15—ns 8Write Precharge Time t RWL10—12—15—ns 9RAS to CAS Bank ActiveDelay Timet RRD30—30—30—nsNo.Parameter Symbol MB8501S064AC-100MB8501S064AC-84MB8501S064AC-67Unit 1CKE to Clock Disable I CKE111Cycle 2DQM to Output in High-Z I DQZ222Cycle 3DQM to Input Data Delay I DQD000Cycle 4Last Output to Write CommandDelayI OWD222Cycle 5Write Command to Input DataDelayI DWD000Cycle 6Precharge toOutput in High-Z DelayCL = 3I ROH333CycleCL = 2222Cycle 7Mode Register Access to BankActive (min)I MRD222Cycle 8CAS to CAS Delay (min)I CCD111Cycle 9CAS Bank Delay (min)I CBD111Cycle Clock ≥Base ValueClock Period(Round off a whole number)Notes:*1.Assumes t RCD and t CAC are satisfied.*2.t AC also specifies the access time at burst mode except for first access.*3.Specified where output buffer is no longer driven.*4.Actual clock count of t RC (I RC) will be sum of clock count of t RAS (I RAS) and t RP (I RP).*5.t RAC is a reference value. Maximum value is obtained from the sum of t RCD (min) and t CAC (max).*6.Assumes t RAC and t AC are satisfied.*7.Operation within the t RCD (min) ensures that t RAC can be met; if t RCD is greater than the specified t RCD (min), access time is determined by t CAC and t AC.*8.All base values are measured from the clock edge at the command input to the clock edge for the next command input.All clock counts are calculated by a simple formula:clock count equals base value divided by clock period (round off to a whole number).*9.The I CAC (CAS latency: CL) is programmed by the mode register.*10.An initial pause ( DESL on NOP ) of 200 µs is required after power-up followed by a minimum of eight Auto-Refresh cycles.*11. 1.4 V or V REF is the reference level for measuring timing of signals.T ransition times are measured between V IH (min) and V IL (max).*12.AC characteristics assume t T = 1 ns and 30 pF of capacitive load.*Source: See MB811171622A Data Sheet for details on the electricals.s AC OPERATING TEST CONDITION (Example of AC Test Load Circuit)s SERIAL PRESENCE DETECT(SPD) FUNCTION1.PIN DESCRIPTIONSSCL (Serial Clock)SCL input is used to clock all data input/output of SPDSDA (Serial Data)SDA is a common pin used for all data input/output of SPD. The SDA pull-up resistor is required due to the open-drain output.SA0, SA1, SA2 (Address)Address inputs are used to set the least significant three bits of the eight bits slave address. The address inputs must be fixed to select a particular module and the fixed address of each module must be different each other.2.SPD OPERATIONSCLOCK and DATA CONVENTIONData states on the SDA can change only during SCL=Low. SDA state changes during SCL=High are indicated start and stop conditions. Refer to Fig.1 below.START CONDITIONAll commands are preceded by a start condition, which is a transition of SDA state from High to Low when SCL=High. SPD will not respond to any command until this condition has been met.STOP CONDITIONAll read or write operation must be terminated by a stop condition, which is a transition of SDA state from Low to High when SCL=High. The stop condition is also used to make the SPD into the state of standby power mode after a read sequence.ACKNOWLEDGEAcknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will put the SDA line to Low in order to acknowledge that it received the eight bits of data.The SPD will respond with an acknowledge when it received the start condition followed by slave address issued by master.In the read operation, the SPD will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is issued by master, the SPD will continue to transmit data. If an acknowledge is not detected, the SPD will terminated further data transmissions. The master must then issue a stop condition to return the SPD to the standby power mode.In the write operation, upon receipt of eight bits of data the SPD will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master.SLAVE ADDRESS ADDRESSINGFollowing a start condition, the master must output the eight bits slave address. The most significant four bits of the slave address are device type identifier. For the SPD this is fixed as 1010[B]. Refer to the Fig.2 below.The next three significant bits are used to select a particular device. A system could have up to eight SPD devices–namely up to eight modules–on the bus. The eight addresses for eight SPD devices are defined by the state of the SA 0, SA 1 and SA 2 inputs.The last bit of the slave address defines the operation to be performed. When R/W bit is “1”, a read operation is selected, when R/W bit is “0”, a write operation is selected.Following the start condition, the SPD monitors the SDA line comparing the slave address being transmitted with its slave address (device type and state of SA 0, SA 1, and SA 2 inputs). Upon a correct compare the SPD outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the SPD will execute a read or write operation.1010R/WSA 2SA 1SA 0DEVICE TYPE IDENTIFIERDEVICE ADDRESSFig.2 – SLAVE ADDRESS3.READ OPERATIONCURRENT ADDRESS READInternally the SPD contains an address counter that maintains the address of the last data accessed,incremented by one. Therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). Upon receipt of the slave address with the R/W bit = “1”,the SPD issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge.Refer to Fig.3 for the sequence of address, acknowledge and data transfer.RANDOM READRandom Read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit = “1”, the master must first perform a “dummy” write operation on the SPD.The master issues the start condition, and the slave address followed by the word address. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit = “1”. This will be followed by an acknowledge from the SPD and then by the eight bits of data. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge.Refer to Fig.4 for the sequence of address, acknowledge and data transfer.Fig.3 – CURRENT ADDRESS READS T O PDA T AA C KSLAVE ADDRESSS T A R TBUS ACTIVITY :MASTER SDA LINEBUS ACTIVITY :SPDFig.4 – RANDOM READS T O PDA T AA C KSLAVE ADDRESSA C K A C K SLAVE ADDRESSWORD ADDRESSS T A R TS T A R TBUS ACTIVITY :MASTER SDA LINE BUS ACTIVITY :SPDSEQUENTIAL READSequential Read can be initiated as either a current address read or random read. The first data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. The SPD continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig.5 for the sequence of address, acknowledge and data transfer.The data output is sequential, with the data from address(n) followed by the data from address(n+1). The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter “rolls over” to address 0 and the SPD continues to output data for each acknowledge received.4.DC CHARACTERISTICSNote:*1. Referenced to V SS .ParameterNoteSymbol Condition Value Unit Min.Max.Input Leakage Current S ILI 0 V ≤ V IN ≤ V CC –1010µA Output Leakage Current S ILO 0 V ≤ V OUT ≤ V CC –1010µA Output Low Voltage *1S VOLIOL = 3.0 mA—0.4V5. AC CHARACTERISTICSNo.Parameter SymbolValueUnit Min.Max.1SCL Clock Frequency f SCL0100KHz2Noise Suppression TimeConstant at SCL, SDA InputsT I—100ns3SCL Low to SDA Data Out Valid t AA— 3.5µs4Time the Bus Must Be Free Beforea New Transmission Can Startt BUF 4.7—µs5Start Condition Hold Time t HD:STA 4.0—µs 6Clock Low Period t LOW 4.7—µs 7Clock High Period t HIGH 4.0—µs 8Start Condition Set Up Time t SU:STA 4.7—µs 9Data In Hold Time t HD:DAT0—µs 10Data In Set Up Time t SU:DAT250—ns 11SDA and SCL Rise Time t R—1µs 12SDA and SCL Fall Time t F—300ns 13Stop Condition Set Up Time t SU:STO 4.7—µs 14Data Out Hold Time t DH100—ns 15Write Cycle Time t WR—15mss PACKAGE DIMENSIONAll Rights Reserved.The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION:Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.。