SY58028UMG资料
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kage Marking SY58028U SY58028U SY58028U with Pb-Free bar-line indicator SY58028Uwith Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Pb-Free NiPdAu Pb-Free NiPdAu
23
Q0 /Q0
Ð1 PRBS)
Q1 /Q1
Output Swing
(100mV/div.)
VT2 50Ω /IN2 VREF-AC2 IN3 50Ω VT3 50Ω /IN3
TIME (100ps/div.)
3
VREF-AC3 SEL0 (CMOS/TTL) SEL1 (CMOS/TTL)
Rev.: C Amendment: /0
32 31 30 29 28 27 26 25
SY58028UMI SY58028UMITR(2) SY58028UMG(3) SY58028UMGTR(2, 3)
IN0 VT0 VREF-AC0 /IN0 IN1 VT1 VREF-AC1 /IN1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Ordering Information(1)
Part Number
GND VCC Q1 /Q1 VCC NC SEL1 VCC
Package Type MLF-32 MLF-32 MLF-32 MLF-32
Operating Range Industrial Industrial Industrial Industrial
1
Issue Date: February 2007
元器件交易网
Micrel, Inc.
Precision Edge® SY58028U
PACKAGE/ORDERING INFORMATION
/IN3 VREF-AC3 VT3 IN3 /IN2 VREF-AC2 VT2 IN2
FUNCTIONAL BLOCK DIAGRAM
IN0 50Ω VT0 50Ω /IN0 VREF-AC0 0 IN1 50Ω VT1 50Ω /IN1 VREF-AC1 IN2 50Ω 2 1 MUX 4:1 MUX 1:2 Fanout
TYPICAL PERFORMANCE
3.2Gbps Output (2
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-020207 hbwhelp@ or (408) 955-1690
DESCRIPTION
The SY58028U is a 2.5V/3.3V precision, high-speed, 4:1 differential CML multiplexer capable of handling clocks up to 7GHz and data streams up to 10.7Gbps. In addition, a 1:2 fanout buffer provides two copies of the selected inputs. The differential input includes Micrel’s unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The result is a clean, stub-free, low-jitter interface solution. The outputs are 50Ω source terminated CML, with extremely fast rise/fall times guaranteed to be less than 60ps. The SY58028U operates from a 2.5V ±5% supply or a 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. For applications that require LVPECL outputs, consider the SY58029U or SY58030U Multiplexers. The SY58028U is part of Micrel’s high-speed, Precision Edge® product line. All support documentation can be found on Micrel’s web site at .
APPLICATIONS
s s s s s Redundant clock and/or data distribution All SONET/SDH clock/data distribution Loopback All Fibre Channel distribution All Gigabit Ethernet clock and/or data distribution
24 23 22 21 20 19 18 17
32-Pin MLF® (MLF-32)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs.
元器件交易网
Micrel, Inc.
ULTRA PRECISION DIFFERENTIAL CML 4:1 MUX WITH 1:2 FANOUT AND INTERNAL I/O TERMINATION
Precision Edge SY58028U
Precision Edge® SY58028U ®
PIN DESCRIPTION
Pin Number 1, 4 5, 8 25, 28 29, 32 Pin Name IN0, /IN0 IN1, /IN1 IN2, /IN2 IN3, /IN3 Pin Function Differential Inputs: These inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. If an input pair is not used, connect one input of the pair to ground through a 1kΩ resistor and the complement to VCC through a 825Ω resistor. Unused VT and VREF-AC may also be left open. Please refer to the “Input Interface Applications” section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pin provides a center-tap to the termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. This single-ended TTL/CMOS compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. Input logic threshold is VCC/2. See “Truth Table” for select control. No Connect. Positive Power Supply: Bypass with 0.1µF0.01µF low ESR capacitors. Differential Outputs: These CML output pairs are copies of the selected input. Unused output pairs may be left floating. See “Output Interface” section for termination guidelines. Ground. Ground pin and exposed pad must be connected to the same ground plane. Reference Voltage: This reference output is equivalent to VCC–1.4V. It is used for AC-coupled inputs. When interfacing to AC input signals, connect VREF-AC directly to the VT pin and bypass with 0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section. Maximum sink/source current is 0.5mA.
FEATURES
s Selects 1 of 4 differential inputs s Provides two copies of the selected input s Guaranteed AC performance over temperature and voltage: • DC-to- > 10.7Gbps data rate throughput • < 350ps IN-to-Out tpd • < 60ps tr / tf times s Ultra low-jitter design: • < 10psPP total jitter (clock) • < 1psRMS random jitter • < 10psPP deterministic jitter • < 0.7psRMS crosstalk-induced jitter s Unique patended input design minimizes crosstalk s Accepts an input signal as low as 100mV s Unique patended input termination and VT pin accepts DC- and AC-coupled inputs (CML, LVPECL, LVDS) s Internal 50Ω output source termination s 400mV CML output swing (RL = 50Ω) s Power supply 2.5V ±5% or 3.3V ±10% s –40°C to +85°C temperature range s Available in 32-pin (5mm × 5mm) MLF® package Precision Edge®
Lead Finish Sn-Pb Sn-Pb Pb-Free NiPdAu Pb-Free NiPdAu
23
Q0 /Q0
Ð1 PRBS)
Q1 /Q1
Output Swing
(100mV/div.)
VT2 50Ω /IN2 VREF-AC2 IN3 50Ω VT3 50Ω /IN3
TIME (100ps/div.)
3
VREF-AC3 SEL0 (CMOS/TTL) SEL1 (CMOS/TTL)
Rev.: C Amendment: /0
32 31 30 29 28 27 26 25
SY58028UMI SY58028UMITR(2) SY58028UMG(3) SY58028UMGTR(2, 3)
IN0 VT0 VREF-AC0 /IN0 IN1 VT1 VREF-AC1 /IN1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Ordering Information(1)
Part Number
GND VCC Q1 /Q1 VCC NC SEL1 VCC
Package Type MLF-32 MLF-32 MLF-32 MLF-32
Operating Range Industrial Industrial Industrial Industrial
1
Issue Date: February 2007
元器件交易网
Micrel, Inc.
Precision Edge® SY58028U
PACKAGE/ORDERING INFORMATION
/IN3 VREF-AC3 VT3 IN3 /IN2 VREF-AC2 VT2 IN2
FUNCTIONAL BLOCK DIAGRAM
IN0 50Ω VT0 50Ω /IN0 VREF-AC0 0 IN1 50Ω VT1 50Ω /IN1 VREF-AC1 IN2 50Ω 2 1 MUX 4:1 MUX 1:2 Fanout
TYPICAL PERFORMANCE
3.2Gbps Output (2
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-020207 hbwhelp@ or (408) 955-1690
DESCRIPTION
The SY58028U is a 2.5V/3.3V precision, high-speed, 4:1 differential CML multiplexer capable of handling clocks up to 7GHz and data streams up to 10.7Gbps. In addition, a 1:2 fanout buffer provides two copies of the selected inputs. The differential input includes Micrel’s unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The result is a clean, stub-free, low-jitter interface solution. The outputs are 50Ω source terminated CML, with extremely fast rise/fall times guaranteed to be less than 60ps. The SY58028U operates from a 2.5V ±5% supply or a 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. For applications that require LVPECL outputs, consider the SY58029U or SY58030U Multiplexers. The SY58028U is part of Micrel’s high-speed, Precision Edge® product line. All support documentation can be found on Micrel’s web site at .
APPLICATIONS
s s s s s Redundant clock and/or data distribution All SONET/SDH clock/data distribution Loopback All Fibre Channel distribution All Gigabit Ethernet clock and/or data distribution
24 23 22 21 20 19 18 17
32-Pin MLF® (MLF-32)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs.
元器件交易网
Micrel, Inc.
ULTRA PRECISION DIFFERENTIAL CML 4:1 MUX WITH 1:2 FANOUT AND INTERNAL I/O TERMINATION
Precision Edge SY58028U
Precision Edge® SY58028U ®
PIN DESCRIPTION
Pin Number 1, 4 5, 8 25, 28 29, 32 Pin Name IN0, /IN0 IN1, /IN1 IN2, /IN2 IN3, /IN3 Pin Function Differential Inputs: These inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. If an input pair is not used, connect one input of the pair to ground through a 1kΩ resistor and the complement to VCC through a 825Ω resistor. Unused VT and VREF-AC may also be left open. Please refer to the “Input Interface Applications” section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pin provides a center-tap to the termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. This single-ended TTL/CMOS compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. Input logic threshold is VCC/2. See “Truth Table” for select control. No Connect. Positive Power Supply: Bypass with 0.1µF0.01µF low ESR capacitors. Differential Outputs: These CML output pairs are copies of the selected input. Unused output pairs may be left floating. See “Output Interface” section for termination guidelines. Ground. Ground pin and exposed pad must be connected to the same ground plane. Reference Voltage: This reference output is equivalent to VCC–1.4V. It is used for AC-coupled inputs. When interfacing to AC input signals, connect VREF-AC directly to the VT pin and bypass with 0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section. Maximum sink/source current is 0.5mA.
FEATURES
s Selects 1 of 4 differential inputs s Provides two copies of the selected input s Guaranteed AC performance over temperature and voltage: • DC-to- > 10.7Gbps data rate throughput • < 350ps IN-to-Out tpd • < 60ps tr / tf times s Ultra low-jitter design: • < 10psPP total jitter (clock) • < 1psRMS random jitter • < 10psPP deterministic jitter • < 0.7psRMS crosstalk-induced jitter s Unique patended input design minimizes crosstalk s Accepts an input signal as low as 100mV s Unique patended input termination and VT pin accepts DC- and AC-coupled inputs (CML, LVPECL, LVDS) s Internal 50Ω output source termination s 400mV CML output swing (RL = 50Ω) s Power supply 2.5V ±5% or 3.3V ±10% s –40°C to +85°C temperature range s Available in 32-pin (5mm × 5mm) MLF® package Precision Edge®