EM680FV16A资料

Document Title
512K x 16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History Draft Date Remark
0.0 Initial Draft May 10, 2007
0.1 0.1 Revision Product code change from
EM680FV16AW to EM680FV16A
June 1, 2007
0.2 0.2 Revision EMLSI Product information update June 14, 2007
0.3 0.3 Revision Fix type error July 3, 2007
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage :
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office.
Name Function Name Function
CS1, CS2 Chip select input Vcc Power Supply OE Output Enable input Vss Ground
WE Write Enable input UB Upper Byte (I/O8~15)
A0~A18 Address Inputs LB Lower Byte (I/O0~7) I/O0~I/O15 Data Inputs/outputs NC No Connected
R
o
w
S
e
l
e
c
t
I/O Circuit
Column Select
Data
Cont
Data
Cont
Pre-charge Circuit
Memory Array
2048 x 4096
A1
A2
A3
A4
A5
A6
A7
A0
A8
A9
A11A12A13A14A15A16A17
WE
OE
UB
LB
CS1
I/O0 ~ I/O7
I/O8 ~ I/O15
V CC
V SS Control Logic
FUNCTIONAL BLOCK DIAGRAM
A10
A18
CS2
PAD DESCRIPTION
1
2
8
5
6
2
9
x
y
+
(0, 0)
EMLSI LOGO
EM680FV16A (Dual C/S)
PAD Size : 70um x 80um
PAD DIAGRAM
FEATURES
- Process Technology : 0.15µm Full CMOS
- Organization : 512K x 16 bit
- Power Supply Voltage
=> EM680FV16A : 2.7V ~ 3.6V
- Low Data Retention Voltage : 1.5V (Min.)
- Three state output and TTL Compatible
- Packaged product designed for 45/55/70ns
GENERAL PHYSICAL SPECIFICATIONS
- Backside die surface of polished bare silicon
- Typical Die Thickness = 725um +/-15um
- Typical top-level metallization :
=> Metal (Ti/AlCu/TiN/ARC SiON/SiO2) : 5.2K Angstroms
- Topside Passivation :
=> Passivation (HDP/pNIT/PIQ) : 5.4K Angstroms
- Typical Pad Size : 70.0um x 80.0um
- Wafer diameter : 8 inch
BONDING INSTRUCTIONS
The 8M full CMOS LP SRAM die has total 56pads. Refer to the bond pad location and identification table for X, Y coordinates. EMLSI recommends using a bond wire on back side of die onto Vss bond pad for improved noise immunity.
BONDING PAD LOCATION AND IDENTIFICATION TABLE
Pad #Function X Y 1NC-17123160 2NC-17122940 3A4-17122720 4A3-17122500 5A2-17122280 6A1-17122060 7A0-17121840 8/CS1-17121620 9NC-17121400 10NC-17121180 11IO0-1712960 12IO1-1712740 13VCC-1712520 14VCC-1712340 15VSS-1712-340 16VSS-1712-520 17IO2-1712-740 18IO3-1712-960 19NC-1712-1180 20NC-1712-1400 21/WE-1712-1620 22NC-1712-1840 23A18-1712-2060 24A17-1712-2280 25A16-1712-2500 26A15-1712-2720 27NC-1712-2940 28NC-1712-3160Pad #Function X Y 56A517123160 55A617122940 54A717122720 53/OE17122500 52/UB17122280 51CS217122060 50/LB17121840 49A817121620 48NC17121400 47NC17121180 46IO71712960 45IO61712740 44VSS1712520 43VSS1712340 42VSS1712-340 41VCC1712-560 40VCC1712-740 39IO111712-960 38IO101712-1180 37IO91712-1400 36IO81712-1620 35A81712-1840 34A91712-2060 33A101712-2280 32A111712-2500 31A121712-2720 30A131712-2940 29NC1712-3160
Note
1. The origin is the center of the die excluding scribe lane.
2. All units are in micrometer
3. Single CS user must be contact to EMLSI marketing
ABSOLUTE MAXIMUM RATINGS *
Parameter Symbol Minimum Unit Voltage on Any Pin Relative to Vss V IN, V OUT -0.2 to 3.6V V Voltage on Vcc supply relative to Vss V CC -0.2 to 4.0V V Power Dissipation P D 1.0 W Operating Temperature T A -40 to 85 o C
*Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS1CS2OE WE LB UB I/O0-7I/O8-15Mode Power
H X X X X X High-Z High-Z Deselected Stand by
X L X X X X High-Z High-Z Deselected Stand by X X X X H H High-Z High-Z Deselected Stand by L H H H L X High-Z High-Z Output Disabled Active L H H H X L High-Z High-Z Output Disabled Active L H L H L H Data Out High-Z Lower Byte Read Active L H L H H L High-Z Data Out Upper Byte Read Active L H L H L L Data Out Data Out Word Read Active L H X L L H Data In High-Z Lower Byte Write Active L H X L H L High-Z Data In Upper Byte Write Active L H X L L L Data In Data In Word Write Active
Note: X means don’t care. (Must be low or high state)
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol Test Conditions Min Typ Max Unit Input leakage current I LI V IN =V SS to V CC
-1-1uA Output leakage current I LO CS1=V IH or CS2=V IL or OE=V IH or WE=V IL or LB=UB=V IH V IO =V SS to V CC
-1-1uA Operating power supply
I CC I IO =0mA, CS1=V IL , CS2=WE=V IH , V IN =V IH or V IL --2mA Average operating current
I CC1
Cycle time=1µs, 100% duty, I IO =0mA,
CS1<0.2V, CS2>V CC -0.2V, LB<0.2V or/and UB<0.2V, V IN <0.2V or V IN >V CC -0.2V
-
-
4 mA
I CC2
Cycle time = Min, I IO =0mA, 100% duty,
CS1=V IL , CS2=V IH , LB=V IL or/and UB=V IL , V IN =V IL or V IH
45ns/55ns
-- 45 / 35mA Output low voltage V OL I OL = 2.1mA --0.4V Output high voltage V OH I OH = -1.0mA
2.2--V Standby Current (TTL)
I SB
CS1=V IH , CS2=V IL , Other inputs=V IH or V IL -
-
0.5
mA
Standby Current (CMOS)
I SB1
CS1>V CC -0.2V, (CS1 controlled; CS2>V CC -0.2V)
or 0v<CS2<0.2V
Other inputs=0 ~ V CC (Typ. condition : V CC
=3.3V @ 25o C)
(Max. condition : V CC =3.6V @ 85o C)
LF -215uA
RECOMMENDED DC OPERATING CONDITIONS 1)
1. T A = -40 to 85o C, otherwise specified
2. Overshoot: V CC +2.0 V in case of pulse width < 20ns
3. Undershoot: -2.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested .
Parameter Symbol
Min
Typ
Max
Unit
Supply voltage V CC 2.7 3.3 3.6 V
Ground
V SS 000
V
Input high voltage V IH 2.2-V CC + 0.22) V
Input low voltage
V IL
-0.23)
-0.6
V
CAPACITANCE 1) (f =1MHz, T A =25o C)
1. Capacitance is sampled, not 100% tested
Item
Symbol Test Condition
Min Max Unit Input capacitance C IN V IN =0V -8pF Input/Ouput capacitance
C IO
V IO =0V
-
10
pF
Low Power, 512Kx16 SRAM
Parameter
Symbol
45ns 55ns
70ns
Unit
Min Max Min Max Min Max Read cycle time t RC 45-55-70-ns Address access time t AA -45-55-70ns Chip select to output t co1, t co2-45-55-70ns Output enable to valid output t OE -30-
35-
35
ns UB, LB access time t BA 45
55 70ns Chip select to low-Z output t LZ1, t LZ25-5-5-ns UB, LB enable to low-Z output t BLZ 1010 10-ns Output enable to low-Z output t OLZ 555
-ns Chip disable to high-Z output t HZ1, t HZ2020020020ns UB, LB disable to how-Z output t BHZ 020020020ns Output disable to high-Z output t OHZ 020020020ns Output hold from address change
t OH
10
-
10-
10
-
ns
Parameter
Symbol
45ns
55ns
70ns
Unit
Min Max Min Max Min Max Write cycle time
t WC 55-55-70-ns Chip select to end of write t CW1, t CW2
45-45-60-ns Address setup time t AS 0-0-0-ns Address valid to end of write t AW 45-45-60-ns UB, LB valid to end of write t BW 45-55-70-ns Write pulse width t WP 45-45-55-ns Write recovery time t WR 0-0-0-ns Write to ouput high-Z t WHZ 020
020
020
ns
Data to write time overlap t DW 2530
30 ns Data hold from write time t DH 0-0-0-ns End write to output low-Z
t OW
5
-5
5
-ns
READ CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40o C to +85o C)
WRITE CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40o C to +85o C)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)Input Pulse Level : 0.4 to 2.4V Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V Output Load (See right) : CL 1) = 30pF + 1 TTL 1. Including scope and Jig capacitance 2. R 1=3070 ohm , R 2=3150 ohm 3. V TM =2.8V
CL 1)
V TM 3)
R 12)
R 22)
TIMING WAVEFORM OF READ CYCLE(2) (WE = V IH )
t RC
Address
t AA Data Valid
t OH
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=V IL , CS2=WE=V IL )
Data Out
TIMING DIAGRAMS
NOTES (READ CYCLE)
1. t HZ and t OHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection.
t RC
Address
CS1CS2
OE
Data Out
t CO
t OH
t OE
High-Z
t OHZ
Data Valid
t OLZ
t LZ
t AA
t HZ
UB,LB
t BHZ
t BA
t BLZ
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)t WR(4)
t WC Address
CS1
CS2
WE Data in Data out
t CW(2)
t AW
t WP(1)
t AS(3)
High-Z
t DW t DH
High-Z
t OW
t WHZ
Data Undefined
Data Valid
t WC
Address
CS1 CS2
WE Data in Data out
t CW(2)t WR(4)
t AW
t WP(1)
t DW t DH t AS(3)
High-Z High-Z
Data Valid
UB,LB
t BW UB,LB
t BW
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED)
t WC
Address
CS1
CS2
WE
Data in Data out
t CW (2)
t WR (4)
t AW t WP (1)
t DW
t DH
High-Z
High-Z
Data Valid
t AS (3)
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(t WP ) of low CS1, a high CS2 and low WE. A write begins at the latest transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition when CS1 goes high, CS2 goes high and WE goes high. The t WP is measured from the beginning of write to the end of write.
2. t CW is measured from the CS1 going low to end of write.
3. t AS is measured from the address valid to the beginning of write.
4. t WR is measured from the end or write to the address change. t WR applied in case a write ends as CS1 or WE going high.
UB,LB
t BW
DATA RETENTION CHARACTERISTICS
NOTES
1. CS1 ≥ Vcc-0.2V , CS2 ≥ Vcc-0.2V (CS1 controlled) or CS2 ≤ 0.2V (CS2 controlled)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
V CC for Data Retention V DR CS1 ≥ Vcc-0.2V 1)
1.5- 3.6V Data Retention Current
I DR V CC =1.5V, CS1 ≥ Vcc-0.2V 1)-
- 4 uA Chip Deselect to Data Retention Time t SDR See data retention wave form
0--ns
Operation Recovery Time
t RDR
t RC
-
-
t SDR
t RDR
Data Retention Mode
CS1 > Vcc-0.2V
V cc 2.7V
2.2V V DR CS GND
DATA RETENTION WAVE FORM t SDR
t RDR
Data Retention Mode
V cc 2.7V CS2
V DR 0.4V GND
CS2 < 0.2V
CS1 Controlled
CS2 Controlled
EM680FV16A
Low Power, 512Kx16 SRAM
EM X XX X X X XX X X - XX XX
SRAM PART CODING SYSTEM
1. EMLSI Memory
2. Product Type
3. Density
5. Technology
6. Operating Voltage
8. Generation
9. Package
10. Speed 7. Organization
1. Memory Component
EM --------------------- Memory
2. Product Type
6 ------------------------ SRAM
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
2 ----------------------- Multiplexed
3 ------------- Single CS / LBB, UBB(tBA=tOE)
4 ------------- Single CS / LBB, UBB(tBA=tCO)
5 ------------- Dual CS / LBB, UBB(tBA=tOE)
6 ------------- Dual CS / LBB, UBB(tBA=tCO)
5. Technology
F ------------------------- Full CMOS
6. Operating Voltage
T ------------------------- 5.0V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V 7. Organization
8 ---------------------- x8 bit
16 ---------------------- x16 bit
8. Generation
Blank ----------------- 1st generation
A ----------------------- 2nd generation
B ----------------------- 3rd generation
C ----------------------- 4th generation
D ----------------------- 5th generation
E ----------------------- 6th generation
F ----------------------- 7th generation
G ---------------------- 8th generation
9. Package
Blank ---------------- KGD, 48&36FpBGA
S ---------------------- 32sTSOP1
T ---------------------- 32 TSOP1
U ---------------------- 44 TSOP2
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 ---------------------- 100ns
12 ---------------------- 120ns
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free & Green) L ---------------------- Low Power
S ---------------------- Standard Power
4. Function 11. Power
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