EDA 4-7线译码器 8-3线编码器 电子时钟
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY decoder47 IS
PORT(DCBA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gfedcba:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
END ENTITY decoder47;
ARCHITECTURE one OF decoder47 IS
BEGIN
PROCESS(DCBA)
BEGIN
CASE DCBA IS
WHEN "0000"=> gfedcba<="0111111";
WHEN "0001"=> gfedcba<="0000111";
WHEN "0010"=> gfedcba<="1011011";
WHEN "0011"=> gfedcba<="1001111";
WHEN "0100"=> gfedcba<="1100110";
WHEN "0101"=> gfedcba<="1101101";
WHEN "0110"=> gfedcba<="1111100";
WHEN "0111"=> gfedcba<="0000111";
WHEN "1000"=> gfedcba<="1111111";
WHEN "1001"=> gfedcba<="1100111";
WHEN OTHERS=> NULL;
END CASE;
END PROCESS;
END ARCHITECTURE one;
仿真波形：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY encoder83 IS
PORT(Y:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
A:OUT STD_LOGIC_VECTOR(2 DOWNTO 0) );
END ENTITY encoder83;
ARCHITECTURE one OF encoder83 IS
BEGIN
PROCESS(Y)
BEGIN
CASE Y IS
WHEN "00000001"=> A<="000";
WHEN "00000010"=> A<="001";
WHEN "00000100"=> A<="010";
WHEN "00001000"=> A<="011";
WHEN "00010000"=> A<="100";
WHEN "00100000"=> A<="101";
WHEN "01000000"=> A<="110";
WHEN "10000000"=> A<="111";
WHEN OTHERS=> NULL;
END CASE;
END PROCESS;
END ARCHITECTURE one;
仿真波形：
电子钟：
层次化设计的最后顶层文件：
仿真波形：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY count10000 IS
PORT(clk1,clks,clr:IN STD_LOGIC;
seg:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
sel:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ENTITY count10000;
ARCHITECTURE one OF count10000 IS
SIGNAL in47:integer range 0 to 9;
SIGNAL q0_tmp,q1_tmp,q2_tmp,q3_tmp:integer range 0 to 9;
BEGIN
PROCESS(clk1,clr)
BEGIN
IF clr='0' THEN
q0_tmp<=0;
q1_tmp<=0;
q2_tmp<=0;
q3_tmp<=0;
ELSIF(clk1'EVENT AND clk1='1') THEN
q0_tmp<=q0_tmp+1;
IF q0_tmp=9 THEN
q0_tmp<=0;q1_tmp<=q1_tmp+1;
IF q1_tmp=9 THEN
q1_tmp<=0;q2_tmp<=q2_tmp+1;
IF q2_tmp=9 THEN
q2_tmp<=0;q3_tmp<=q3_tmp+1;
IF q3_tmp=9 THEN
q3_tmp<=0;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(clks)
V ARIABLE q:integer range 0 to 3;
BEGIN
IF clks'event and clks='1' then
q:=q+1;
END IF;
CASE q IS
WHEN 0 => in47<=q0_tmp;sel<="0001";
WHEN 1 => in47<=q1_tmp;sel<="0010";
WHEN 2 => in47<=q2_tmp;sel<="0100";
WHEN OTHERS => in47<=q3_tmp;sel<="1000";
END CASE;
END PROCESS;
PROCESS(in47)
BEGIN
CASE in47 IS
WHEN 0=> seg<="1000000";
WHEN 1=> seg<="1111001";
WHEN 2=> seg<="0100100";
WHEN 3=> seg<="0110000";
WHEN 4=> seg<="0011001";
WHEN 5=> seg<="0010010";
WHEN 6=> seg<="0000010";
WHEN 7=> seg<="1111000";
WHEN 8=> seg<="0000000";
WHEN 9=> seg<="0010000";
WHEN OTHERS=> NULL;
END CASE;
END PROCESS;
END ARCHITECTURE one;