tpa3118d2规格书

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健伍TK3118说明书资料

KENWOOD TK-2118/3118使用手册开箱和装置检查下列开箱说明仅针对kenwood经销商，经授权的kenwood服务机构或者工厂。

请小心地从包装箱中取出对讲机。

我们建议在您废弃包装材料之前，按照下表清点附件。

如果发现任何物品在运输中丢失或损坏，请立即向送货人提交索赔书。

对另购的NiMH电池组充电另购的电池组在出厂时未充电，请在使用前进行充电(参照电池充电器使用说明书)。

1 如果电池组已经完全充电，请勿再行充电。

否则，电池组的寿命会缩短或者损坏。

2 重新对电池组充电后，请将它从充电器上取下。

如果重新接通充电器电源(关闭电源后再次接通)，充电器将开始再次充电，从而造成电池组的过充电。

在购买后或者长期存放(两个月以上)后第一次对电池组充电不能使电池组达到它的通常使用容量。

在反复充／放电两、三次后，使用容量将增至通常状态。

安装／取下另观的NiMH电池组1 不得短路电池端子，也不得将电池投入到火中。

2 不得试图将电池组的外壳取下。

3 不得在危险环境中安装电池组，火花将引起爆炸。

1 将电池组插入对讲机的底部，推入电池组直到电池组上的闩锁锁定为止。

2 取下电池组时，按下电池组后侧的闩锁，向外侧滑动取出。

安装／取下电池1 不得短路电池端子，也不得将电池投入到火中。

2 不得在危险环境中安装电池组，火花将引起爆炸。

完全充电的nimh电池组可以实现对讲机的最佳性能，尤其是对于长时间发射或着连续使用。

如果没有nimh电池组，也可以使用碱性电池。

我们建议使用高质量的碱性电池。

安装或者取下电池盒时，请按照与上述的“安装／取下另购的nimh电池组”相同的说明操作。

向电池盒装入电池。

1 按下电池盒底郎的闩锁，打开电池盒，将电池盒分为两半。

2 装入5节5号电池(lr6／aa)。

电池的极性应务必与电池盒上的标志一致。

3 将电池盒上部的闩锁对准电池盒下部的锁槽，然后将两半电池盒压紧，直到闩锁锁定为止。

安装天线拿住天线底座，按顺时针方向将天线旋入对讲机顶部的接口上，直到旋紧为止。

柯力 XK3118T1-A1电子称重仪表使用说明书

XK3118T1-A1系列电子称重仪表使用说明书2022年7月版●使用前请仔细阅读本产品说明书●请妥善保管本产品说明书，以备查阅浙制00000577号宁波柯力传感科技股份有限公司仪表使用注意事项▲传感器与仪表的连接必须可靠，传感器的屏蔽线必须可靠接地。

▲在仪表通电状态下，所有连接线不允许进行插拔，防止静电损坏仪表或传感器。

▲传感器和仪表都是静电敏感设备，在使用中必须切实采取防静电措施。

▲在雷雨季节，系统必须落实可靠的避雷措施，防止因雷击造成传感器和仪表的损坏，确保操作人员的人身安全和称重设备及相关设备的安全运行。

▲不得在有可燃性气体或可燃性蒸汽的场合使用，不得在有压力的罐装系统中使用。

▲仪表和传感器须远离强电场强磁场，远离强腐蚀性物体，远离易燃易爆物品。

▲严禁使用强溶剂(如：苯、硝基类油)清洗机壳。

▲不得将液体或其他导电颗粒注入仪表内，以防仪表损坏和触电。

▲本产品非经技术监督部门授权，不得擅自开启铅封，不破坏铅封不能标定。

☆蓄电池属易耗品，不属三包范围。

☆为延长蓄电池的使用寿命，务必先充足电后使用。

☆若长时间不使用，必须每隔2个月充电一次，每次充电约20小时。

☆在搬运或安装时务必小心轻放，避免强烈振动，避免冲击或撞击，防止蓄电池内部电极短路，损坏蓄电池。

◆为保证仪表显示清晰和使用寿命，仪表不宜放在阳光直射下使用，放置地点应较平整。

◆仪表不宜放在粉尘及振动严重的地方使用，避免在潮湿的环境中使用。

◆在插拔仪表与外部设备连接线前，必须先切断仪表及相应设备电源。

◆仪表对外接口须严格按使用说明书中所标注的方法使用，不得擅自更改连接。

◆本仪表不允许随意打开，否则不予保修。

仪表内部有高压强电,非专业人员请不要自行修理以免造成系统更大的损坏、人身伤亡或意外事故。

◆本仪表自销售之日起一年内，在正常使用环境下，出现非人为故障属保修范围，请用户将产品及发票复印件(编号相符)，寄往特约维修点或经销商进行专业维修。

◆超过保修期以及人为故障或其他意外损坏，生产厂对仪表实行收费维修。

tpa3116d2

ProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityTPA3116D2,TPA3118D2,TPA3130D2ZHCS891D–APRIL2012–REVISED JANUARY2015 TPA3116D2具有AM干扰抑制功能的15W、30W、50W无滤波器D类立体声放大器系列1特性3说明•支持多种输出配置TPA31xxD2系列器件是用于驱动扬声器的高效立体声数字放大器功率级，单声道模式下的驱动功率高达–21V电压、4Ω桥接负载(BTL)负载条件下的功率为2×50W(TPA3116D2)100W/2Ω。

TPA3130D2的效率非常高，无需外部散–24V电压、8ΩBTL负载条件下的功率为2×热器即可在单层PCB板上提供2×15W的功率。

30W(TPA3118D2)TPA3118D2甚至可以在不使用外部散热器的情况下在–15V电压、8ΩBTL负载条件下的功率为2×双层PCB上提供2×30W/8Ω的功率。

如果需要更高15W(TPA3130D2)的功率，可以选用TPA3116D2，这款器件在其顶层•宽电压范围：4.5V至26V PowerPAD上连接一个小型散热器后可提供2×•高效D类运行50W/4Ω的功率。

所有这三款器件均使用同一种封–兼具>90%的功率效率与低空闲损耗特性，大装，这样一来，使用同一个PCB板即可满足不同功率幅减小了散热器尺寸级的需求。

–高级调制系统配置TPA31xxD2高级振荡器/PLL电路采用多开关频率选项•多重开关频率来抑制AM干扰；搭配使用主从模式选项时，还可使–AM干扰防止多个器件实现同步。

–主从模式同步–高达1.2MHz的切换频率TPA31xxD2器件针对短路、过热、过压、欠压和直流•采用具有高PSRR的反馈功率级架构，降低了等故障提供了全面保护。

TPA3116D2中文数据表

ＴPＡ3116D2 具有AM干扰抑制功能得１5W、３0W、50Ｗ无滤波器D类立体声放大器系列特性支持多种输出配置21V电压、4Ω桥接负载(BＴＬ) 负载条件下得功率为2×５0W (TPA3１16D2) 24V 电压、８ΩBTＬ负载条件下得功率为2×3０Ｗ(TPA３118D2)１５Ｖ电压、8ΩBTL 负载条件下得功率为 2 ×15Ｗ(ＴPＡ313０D2)宽电压范围:４、５V 至26V高效 D 类运行兼具＞90％得功率效率与低空闲损耗特性,大幅减小了散热器尺寸高级调制系统配置,多重开关频率,AＭ干扰防止,主从模式同步高达１、２MＨz得切换频率采用具有高PSRR 得反馈功率级架构,降低了ＰSU 需求可编程功率限制,差分与单端输入立体声模式与单声道模式(采用单滤波器单声道配置)由单电源供电运行,减少了元件数量集成了具有错误报告功能得自保护电路,其中包括过压、欠压、过热、直流检测与短路等保护,耐热增强型封装DAD(32 位引脚散热薄型小外形尺寸(HTSSOP) 封装,焊盘朝上)DAP(３2 位ＨTSSOP 封装,焊盘朝下)-40°C至85°C环境温度范围应用小型-微型组件、扬声器、扩展坞底座汽车售后阴极射线管(CRT) TV消费类音频应用说明TＰA31xxD２系列器件就是用于驱动扬声器得高效立体声数字放大器功率级,单声道模式下得驱动功率高达1０0Ｗ/２Ω、TPA3130D2 得效率非常高,无需外部散热器即可在单层ＰCB板上提供2×15Ｗ得功率。

TPA３1１8D２甚至可以在不使用外部散热器得情况下在双层ＰCB 上提供 2 ×30W/８Ω得功率。

如果需要更高得功率,可以选用ＴPＡ３１16Ｄ2,这款器件在其顶层PoｗeｒＰAD 上连接一个小型散热器后可提供２×５0Ｗ/４Ω得功率。

所有这三款器件均使用同一种封装,这样一来,使用同一个PCB 板即可满足不同功率级得需求。

TPA3251D2 175W 立体声 350W 单声道 PurePath

ProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityTPA3251D2ZHCSDT9C–JUNE2015–REVISED JUNE2015 TPA3251D2175W立体声/350W单声道PurePath™超高清模拟输入D类放大器1特性•采用推荐的系统设计时，符合电磁干扰(EMI)标准•差分模拟输入2应用•总谐波失真+噪声(THD+N)为10%时的总输出功•蓝光碟磁盘™/DVD接收器率•高端HTiB系统–175W/4Ω，桥接负载(BTL)立体声配置•AV接收机–220W/3Ω，桥接负载(BTL)立体声配置•高端条形音箱–350W/2Ω，并行桥接负载(PBTL)单声道配置•微型Combo系统•THD+N为1%时的总输出功率•有源扬声器和低音炮–140W/4Ω，BTL立体声配置–175W/3Ω，BTL立体声配置3说明–285W/2Ω，PBTL单声道配置TPA3251D2是一款高性能D类功率放大器，它具有•采用高级集成反馈设计，具有高速栅极驱动器错误D类效率并且能够带来真正的高端音质。

该器件特有校正功能高级集成反馈设计和专有高速栅极驱动器错误校正功能（PurePath™超高清）（PurePath™超高清）。

该技术可使器件在整个音频–高达100kHz的单宽带，用于高清(HD)源的高频带内保持超低失真，同时展现完美音质。

该器件最频成分多可驱动2个175W/4Ω负载和2个220W/3Ω负载，–超低THD+N：1W/4Ω时为0.005%；削波时<0.01%并且特有一个2VRMS模拟输入接口，支持与高性能–60dB电源抑制比(PSRR)（BTL，无输入信DAC（例如，TI的PCM5242）的无缝连接。

除了出号）色的音频性能外，TPA3251D2还兼具高功率效率和超–<60µV（A加权）输出噪声低功率级空闲损耗（1W以下）两大优点。

MEMORY存储芯片TPA3118D2DAPR中文规格书

TPA3116D215-W,30-W,50-W Filter-Free Class-D Stereo Amplifier Family With AMAvoidance1Features•Supports Multiple Output Configurations–2×50W Into a4-ΩBTL Load at21V(TPA3116D2)–2×30W Into a8-ΩBTL Load at24V(TPA3118D2)–2×15W Into a8-ΩBTL Load at15V(TPA3130D2)•Wide Voltage Range:4.5V to26V•Efficient Class-D Operation–>90%Power Efficiency Combined With Low Idle Loss Greatly Reduces Heat Sink Size –Advanced Modulation Schemes•Multiple Switching Frequencies–AM Avoidance–Master and Slave Synchronization–Up to1.2-MHz Switching Frequency •Feedback Power-Stage Architecture With High PSRR Reduces PSU Requirements •Programmable Power Limit•Differential and Single-Ended Inputs•Stereo and Mono Mode With Single-Filter Mono Configuration•Single Power Supply Reduces Component Count •Integrated Self-Protection Circuits Including Overvoltage,Undervoltage,Overtemperature,DC-Detect,and Short Circuit With Error Reporting •Thermally Enhanced Packages–DAD(32-Pin HTSSOP Pad Up)–DAP(32-Pin HTSSOP Pad Down)•–40°C to85°C Ambient Temperature Range2Applications•Mini-Micro Component,Speaker Bar,Docks •After-Market Automotive•CRT TV•Consumer Audio Applications 3DescriptionThe TPA31xxD2series are stereo efficient,digital amplifier power stage for driving speakers up to100 W/2Ωin mono.The high efficiency of the TPA3130D2allows it to do2×15W without external heat sink on a single layer PCB.The TPA3118D2can even run2×30W/8Ωwithout heat sink on a dual layer PCB.If even higher power is needed the TPA3116D2does2×50W/4Ωwith a small heat-sink attached to its top side PowerPAD.All three devices share the same footprint enabling a single PCB to be used across different power levels.The TPA31xxD2advanced oscillator/PLL circuit employs a multiple switching frequency option to avoid AM interferences;this is achieved together with an option of either master or slave option,making it possible to synchronize multiple devices.The TPA31xxD2devices are fully protected against faultswith short-circuit protection and thermal protection as well as overvoltage,undervoltage,and DC protection.Faults are reported back to the processor to prevent devices from being damaged during overload conditions.Device Information(1)PART NUMBER PACKAGE BODY SIZE(NOM) TPA3116D2DAD(32)11.00mm×6.20mm TPA3118D2TPA3130D2DAP(32)11.00mm×6.20mm(1)For all available packages,see the orderable addendum atthe end of the datasheet.Simplified Application CircuitCopyright © 2016,Texas Instruments IncorporatedTPA3116D2,TPA3118D2,TPA3130D2SLOS708G–APRIL2012–REVISED DECEMBER2017 7.3.13Efficiency:LC Filter Required with the Traditional Class-D Modulation SchemeThe main reason that the traditional class-D amplifier-based on AD modulation needs an output filter is that the switching waveform results in maximum current flow.This causes more loss in the load,which causes lower efficiency.The ripple current is large for the traditional modulation scheme,because the ripple current is proportional to voltage multiplied by the time at that voltage.The differential voltage swing is2×VCC,and the time at each voltage is half the period for the traditional modulation scheme.An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle,while any resistance causes power dissipation.The speaker is both resistive and reactive,whereas an LC filter is almost purely reactive.The TPA3116D2modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of2×VCC.As the output power increases,the pulses widen,making the ripple current larger.Ripple current could be filtered with an LC filter for increased efficiency,but for most applications the filter is not needed.An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load.The filter has less resistance but higher impedance at the switching frequency than the speaker,which results in less power dissipation,therefore increasing efficiency.7.3.14Ferrite Bead Filter ConsiderationsUsing the Advanced Emissions Suppression Technology in the TPA3116D2amplifier it is possible to design a high efficiency class-D audio amplifier while minimizing interference to surrounding circuits.It is also possible to accomplish this with only a low-cost ferrite bead filter.In this case it is necessary to carefully select the ferrite bead used in the filter.One important aspect of the ferrite bead selection is the type of material used in the ferrite bead.Not all ferrite material is alike,so it is important to select a material that is effective in the10to100MHz range which is key to the operation of the class-D amplifier.Many of the specifications regulating consumer electronics have emissions limits as low as30MHz.It is important to use the ferrite bead filter to block radiation in the30MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals.The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of1000pF to reduce the frequency spectrum of the signal to an acceptable level.For best performance,the resonant frequency of the ferrite bead/capacitor filter should be less than10MHz.Also,it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier.Some ferrite bead manufacturers specify the bead impedance at a variety of current levels.In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier will see.If these specifications are not available,it is also possible to estimate the bead current handling capability by measuring the resonant frequency of the filter output at low power and at maximum power.A change of resonant frequency of less than fifty percent under this condition is desirable.Examples of ferrite beads which have been tested and work well with the TPA3130D2can be seen in the TPA3130D2EVM user guide SLOU341.A high quality ceramic capacitor is also needed for the ferrite bead filter.A low ESR capacitor with good temperature and voltage characteristics will work best.Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to ground.Suggested values for a simple RC series snubber network would be18Ωin series with a330pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp.Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC.Also,make sure the layout of the snubber network is tight and returns directly to the GND pins on the IC.Submit Documentation FeedbackTPA3116D2,TPA3118D2,TPA3130D2 SLOS708G–APRIL2012–REVISED DECEMBER2017Submit Documentation Feedback Figure34.TPA311xD2Radiated Emissions7.3.15When to Use an Output Filter for EMI SuppressionThe TPA3116D2has been tested with a simple ferrite bead filter for a variety of applications including long speaker wires up to125cm and high power.The TPA3116D2EVM passes FCC class-B specifications under these conditions using twisted speaker wires.The size and type of ferrite bead can be selected to meet application requirements.Also,the filter capacitor can be increased if necessary with some impact on efficiency. There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter.These circumstances might occur if there are nearby circuits which are sensitive to noise.In these cases a classic second order Butterworth filter similar to those shown in the figures below can be used.Some systems have little power supply decoupling from the AC line but are also subject to line conducted interference(LCI)regulations.These include systems powered by"wall warts"and"power bricks."In these cases,LC reconstruction filters can be the lowest cost means to pass LCI mon mode chokes using low frequency ferrite material can also be effective at preventing line conducted interference.4- 8W W4- 8W WTPA3116D2,TPA3118D2,TPA3130D2SLOS708G–APRIL2012–REVISED DECEMBER2017Submit Documentation FeedbackFigure35.TPA31xxD2Output Filters7.3.16AM Avoidance EMI ReductionTo reduce interference in the AM radio band,the TPA3116D2has the ability to change the switching frequency via AM<2:0>pins.The recommended frequencies are listed in Table6.The fundamental frequency and its second harmonic straddle the AM radio band listed.This eliminates the tones that can be present due to the switching frequency being demodulated by the AM radio.Table6.AM FrequenciesUS EUROPEANSWITCHING FREQUENCY(kHz)AM2AM1AM0 AM FREQUENCY(kHz)AM FREQUENCY(kHz)522-540540-917540-914500001917-1125914-1122600(or400)0100001125-13751122-13735000011375-15471373-1548600(or400)010000 1547-17001548-1701600(or500)010001TPA3116D2,TPA3118D2,TPA3130D2 SLOS708G–APRIL2012–REVISED DECEMBER2017Submit Documentation Feedback。

TK-3118

This radio is designed for easy servicing. Refer to the schematic diagrams, printed circuit board views, and alignment procedures contained within.
维修服务
Helical Antenna (T90-0759-05)
Knob (VOL) (K29-5442-03)
Knob(ENC) (K29-5443-03)
TK-3118
CONTENTS
Key top (DIAL, SCAN) (K29-9026-13)
Key top(DTMF) (K29-9028-13)
!0 DTMF（双音多频）键盘用于存储和发射 DTMF 号码。
!1 MIC-SP 插孔连接另购的扬声器／麦克风。
■ 显示屏
q Power（电源）开关／Volume（音量）控制器按顺时针方向转动时，接通对讲机的电源。旋转调节音量。关闭对讲机电源时，按逆时针方向旋转到底。
w LED 指示灯发射中时点亮红色，接收中时点亮绿色。接收符合对您的对讲机设定的代码静噪、选择呼叫代码或者 DTMF 信号中时，闪烁橙色。在发射中电池电压变低时闪烁红色。当电池电压降低时闪烁红色。
GENERAL / 概述
INTRODUCTION
SCOPE OF THIS MANUAL This manual is intended for use by experienced technicians
familiar with similar types of commercial grade communications equipment. It contains all required service information for the equipment and is current as of the publication date. Changes which may occur after publication are covered by either Service Bulletins or Manual Revisions. These are issued as required.

KINGTONG 3118使用说明

KINGTONG 3118使用说明set→* 锁/开键盘（非常有用）set→1 频点显示模式set→2 频道显示模式set→3 频道频点显示模式set →4 调整步进单位，每按一次改变一个值，一般用12.5比较合适set→5 搜索set→6 差频方向，- 或者无差频set→7 设置差频值，set→7后直接输入，如为5mhz 则输入set→7→05000 由于直接存储异频收发频点很容易，就没必要使用差频了。

1、开关电源：按顺时针方向转动OFF PWR/VOL控制钮打开对讲机电源。

有“滴”一声，显示屏灯亮，音乐响声。

关掉电源逆向操作即可2、调节音量：按顺时针方向转动OFF PWR/VOL控制钮增大音量，逆向减小音量3、调节静噪电平：按顺时针方向转静噪SOT旋钮使显示屏BUSY与噪音刚好消失时接收灵敏度最好4、步进频率25/12.5KHz选择：按功能键【SET】，再按数字键【4】将进入步进频率25KHz，如果选择12.5KHz 再按数字键【4】5、选择频率使用数字键盘，按顺序输入所需频率。

例如：需输入457.275MHz，必须按数字键4，5，7，2，7，5。

输入时间间隔不超过10秒需出入半频点（12.5KHz），先将步进频率选到12.5再输入频率例如：输入451.637.5MHz，按数字键4，5，1，6，3，7，最后一位5不用按，已自动输入注：输入频率顺符合本机步进频率25KHz和12.5KHz，否则不能正确输入6、全频段工作状态：先按功能键【SET】，再按数字键【1】，将进入全频段工作状态7、扫描：（1）频率扫描：本机处于全频段工作状态时，先按【SET】键，再按数字键【5】，进入频率增大循环扫描。

步进频率定为25/12.5KHz，频率为25/12.5KHz递增循环扫描（2）信道扫描：处于信道存储状态，先按【SET】键，再按数字键【5】，进入信道数增大循环扫描注：按【A】键同样能频率扫描和信道扫描。

静噪功能必须关闭方能进行扫描，按任何键，扫描立即停止。

MEMORY存储芯片TPA3110D2PWPR中文规格书

15W 8W15W 8WTPA3110D215-W Fil ter-Free Stereo Class-D Audio Power Amplifier With Speakerguard™1Features•15-W/ch into an 8-ΩLoads at 10%THD+N From a 16-V Supply•10-W/ch into 8-ΩLoads at 10%THD+N From a 13-V Supply•30-W into a 4-ΩMono Load at 10%THD+N From a 16-V Supply•90%Efficient Class-D Operation Eliminates Need for Heat Sinks•Wide Supply Voltage Range Allows Operation From 8V to 26V •Filter-Free Operation•SpeakerGuard™Speaker Protection Includes Adjustable Power Limiter Plus DC Protection •Flow Through Pin Out Facilitates Easy Board Layout•Robust Pin-to-Pin Short Circuit Protection and Thermal Protection With Auto Recovery Option •Excellent THD+N /Pop-Free Performance •Four Selectable,Fixed Gain Settings •Differential Inputs2Applications•Televisions•Consumer Audio Equipment3DescriptionThe TPA3110D2is a 15-W (per channel)efficient,Class-D audio power amplifier for driving bridged-tied stereo speakers.Advanced EMI Suppression Technology enables the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements.SpeakerGuard™speaker protection circuitry includesan adjustable power limiter and a DC detection circuit.The adjustable power limiter allows the user to set a "virtual"voltage rail lower than the chip supply to limit the amount of current through the speaker.The DC detect circuit measures the frequency and amplitude of the PWM signal and shuts off the output stage if the input capacitors are damaged or shorts exist on the inputs.The TPA3110D2can drive stereo speakers as low as 4Ω.The high efficiency of the TPA3110D2,90%,eliminates the need for an external heat sink when playing music.The outputs are also fully protected against shorts to GND,VCC,and output-to-output.The short-circuit protection and thermal protection includes an auto-recovery feature.Device Information (1)PART NUMBER PACKAGE BODY SIZE (NOM)TPA3110D2HTSSOP (28)9.70mm ×4.40mm(1)For all available packages,see the orderable addendum atthe end of the data sheet.TPA3110D2Simplified Application SchematicTPA3110D2SLOS528F–JULY2009–REVISED APRIL2017Submit Documentation FeedbackLP L S OUTL2R x V R +2x R P =for unclipped power2x R æöæöç÷ç÷ç÷èøèøTPA3110D2SLOS528F –JULY 2009–REVISED APRIL 2017Submit Documentation FeedbackThe PLIMIT circuit sets a limit on the output peak-to-peak voltage.The limiting is done by limiting the duty cycle to fixed maximum value.This limit can be thought of as a virtual voltage rail which is lower than the supply connected to PVCC.This "virtual"rail is 4times the voltage at the PLIMIT pin.This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.Where:•R S is the total series resistance including R DS(on),and any resistance in the output filter.•R L is the load resistance.•V P is the peak amplitude of the output possible within the supply rail.•P OUT (10%THD)=1.25×P OUT (unclipped)(1)Table 3.PLIMIT Typical OperationTEST CONDITIONS PLIMIT VOLTAGEOUTPUT POWER (W)OUTPUT VOLTAGE AMPLITUDE (V P-P )PVCC=24V,Vin=1Vrms,RL=8Ω,Gain=26dB 6.9736.1(thermally limited)43PVCC=24V,Vin=1Vrms,RL=8Ω,Gain=26dB 2.941525.2PVCC=24V,Vin=1Vrms,RL=8Ω,Gain=26dB 2.341020PVCC=24V,Vin=1Vrms,RL=8Ω,Gain=26dB 1.62514PVCC=24V,Vin=1Vrms,RL=8Ω,Gain=20dB 6.9712.127.7PVCC=24V,Vin=1Vrms,RL=8Ω,Gain=20dB 3.001023PVCC=24V,Vin=1Vrms,RL=8Ω,Gain=20dB 1.86514.8PVCC=12V,Vin=1Vrms,RL=8Ω,Gain=20dB 6.9710.5523.5PVCC=12V,Vin=1Vrms,RL=8Ω,Gain=20dB1.765159.3.5GVDD SupplyThe GVDD Supply is used to power the gates of the output full bridge transistors.It can also be used to supply the PLIMIT voltage divider circuit.Add a 1-μF capacitor to ground at this pin.9.3.6PBTL SelectTPA3110D2offers the feature of parallel BTL operation with two outputs of each channel connected directly.If the PBTL pin (pin 14)is tied high,the positive and negative outputs of each channel (left and right)are synchronized and in phase.To operate in this PBTL (mono)mode,apply the input signal to the RIGHT input and place the speaker between the LEFT and RIGHT outputs.Connect the positive and negative output together for best efficiency.The voltage slew rate of the PBTL pin must be restricted to no more than 10V/ms.For higher slew rates,use a 100k Ωresistor in series with the terminals.For an example of the PBTL connection,see the schematic in the APPLICATION INFORMATION section.For normal BTL operation,connect the PBTL pin to local ground.TPA3110D2SLOS528F–JULY2009–REVISED APRIL20179.3.7Thermal ProtectionThermal protection on the TPA3110D2prevents damage to the device when the internal die temperature exceeds150°C.There is a±15°C tolerance on this trip point from device to device.Once the die temperature exceeds the thermal set point,the device enters into the shutdown state and the outputs are disabled.This is not a latched fault.The thermal fault is cleared once the temperature of the die is reduced by15°C.The device begins normal operation at this point with no external system interaction.Thermal protection faults are NOT reported on the FAULT terminal.9.3.8DC DetectTPA3110D2has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs.A DC detect fault will be reported on the FAULT pin as a low state.The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z.To clear the DC Detect it is necessary to cycle the PVCC supply.Cycling S D will NOT clear a DC detect fault.A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds14%(for example, +57%,-43%)for more than420msec at the same polarity.This feature protects the speaker from large DC currents or AC currents less than2Hz.To avoid nuisance faults due to the DC detect circuit,hold the pin low at power-up until the signals at the inputs are stable.Also,take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults.The minimum differential input voltages required to trigger the DC detect are show in table2.The inputs must remain at or above the voltage listed in the table for more than420msec to trigger the DC detect.Table4.DC Detect ThresholdAV(dB)Vin(mV,differential)201122656322836179.3.9Short-Circuit Protection and Automatic Recovery FeatureTPA3110D2has protection from overcurrent conditions caused by a short circuit on the output stage.The short circuit protection fault is reported on the FAULT pin as a low state.The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged.The latch can be cleared by cycling the SD pin through the low state.If automatic recovery from the short circuit protection latch is desired,connect the FAULT pin directly to the SD pin.This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit protection latch.9.4Device Functional Modes9.4.1SD OperationThe TPA3110D2employs a shutdown mode of operation designed to reduce supply current(I CC)to the absolute minimum level during periods of nonuse for power conservation.The SD input terminal should be held high(see specification table for trip point)during normal operation when the amplifier is in use.Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state.Never leave SD unconnected,because amplifier operation would be unpredictable.For the best power-off pop performance,place the amplifier in the shutdown mode prior to removing the power supply voltage.Submit Documentation FeedbackTPA3110D2SLOS528F–JULY2009–REVISED APRIL2017 10Application and ImplementationNOTEInformation in the following applications sections is not part of the TI componentspecification,and TI does not warrant its accuracy or completeness.TI’s customers areresponsible for determining suitability of components for their purposes.Customers shouldvalidate and test their design implementation to confirm system functionality.10.1Application InformationThis section describes a stereo BTL application and a mono PBTL application.In the stereo application the Power Limiter is implemented,however in the mono application this limiter is not used.10.2Typical Applications10.2.1Stereo Class-D Amplifier With BTL Output and Single-Ended Inputs With Power LimitingFigure42.Typical Application Schematic With BTL Output and Single-Ended Inputs With Power LimitingSubmit Documentation Feedback。

TPA3121D2

FEATURES APPLICATIONSDESCRIPTIONMute Control TPA3121D2SIMPLIFIED APPLICATION CIRCUITLeft Channel Right Channel10 V to 26 V Shutdown ControlS0267-01TPA3121D2 SLOS537–MAY 200815-W STEREO CLASS-D AUDIO POWER AMPLIFIER•Flat Panel Display TVs •10-W/Ch Stereo Into an 8-ΩLoad From a 24-V Supply•DLP ®TVs •CRT TVs•15-W/Ch Stereo Into a 4-ΩLoad from a 22-V Supply•Powered Speakers•30-W/Ch Mono Into an 8-ΩLoad from a 22-V Supply•Operates From 10V to 26VThe TPA3121D2is a 15-W (per channel),efficient,class-D audio power amplifier for driving stereo •Can Run From +24V LCD Backlight Supply speakers in a single-ended configuration or a mono •Efficient Class-D Operation Eliminates Need speaker in a bridge-tied-load configuration.The for Heat SinksTPA3121D2can drive stereo speakers as low as 4Ω.•Four Selectable,Fixed-Gain SettingsThe efficiency of the TPA3121D2eliminates the need for an external heat sink when playing music.•Internal Oscillator to Set Class D Frequency (No External Components Required)The gain of the amplifier is controlled by two gain select pins.The gain selections are 20,26,32,and •Single-Ended Analog Inputs36dB.•Thermal and Short-Circuit Protection With Auto RecoveryThe patented start-up and shutdown sequences minimize pop noise in the speakers without additional •Space-Saving Surface Mount 24-Pin TSSOP circuitry.Package•Advanced Power-Off Pop ReductionPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.DLP is a registered trademark of Texas Instruments.System Two,Audio Precision are trademarks of Audio Precision,Inc.PRODUCTION DATA information is current as of publication date.Copyright ©2008,Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.PVCCLSD PVCCLMUTELINRIN BYPASSAGNDAGND PVCCR VCLAMP PVCCR PGNDL PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR PGNDRTPA3121D2SLOS537– These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.PWP(TSSOP)PACKAGE(TOP VIEW)Table1.TERMINAL FUNCTIONSTERMINALI/O/P DESCRIPTION24-PINNAME(PWP)Shutdown signal for IC(low=disabled,high=operational).TTL logic levels with compliance to SD2IAVCCRIN6I Audio input for right channelLIN5I Audio input for left channelGAIN018I Gain select least-significant bit.TTL logic levels with compliance to AVCCGAIN117I Gain select most-significant bit.TTL logic levels with compliance to AVCCMute signal for quick disable/enable of outputs(high=outputs switch at50%duty cycle,low= MUTE4Ioutputs enabled).TTL logic levels with compliance to AVCCBSL21I/O Bootstrap I/O for left channelPVCCL1,3P Power supply for left-channel H-bridge,not internally connected to PVCCR or AVCCLOUT22O Class-D-H-bridge positive output for left channelPGNDL23,24P Power ground for left-channel H-bridgeVCLAMP11P Internally generated voltage supply for bootstrap capacitorsBSR16I/O Bootstrap I/O for right channelROUT15O Class-D-H-bridge negative output for right channelPGNDR13,14P Power ground for right-channel H-bridge.PVCCR10,12P Power supply for right-channel H-bridge,not connected to PVCCL or AVCCAGND9P Analog ground for digital/analog cells in coreAGND8P Analog ground for analog cells in coreReference for preamplifier inputs.Nominally equal to AVCC/8.Also controls start-up time via BYPASS7Oexternal capacitor sizing.AVCC19,20P High-voltage analog power supply.Not internally connected to PVCCR or PVCCLConnect to ground.Thermal pad should be soldered down on all applications to secure the Thermal pad Die pad Pdevice properly to the printed wiring board.2Submit Documentation Feedback Copyright©2008,Texas Instruments IncorporatedProduct Folder Link(s):TPA3121D2ABSOLUTE MAXIMUM RATINGSDISSIPATION RATINGSRECOMMENDED OPERATING CONDITIONS TPA3121D2 SLOS537–MAY2008over operating free-air temperature range(unless otherwise noted)(1)VALUE UNITV CC Supply voltage AVCC,PVCC–0.3to30VV I Logic input voltage SD,MUTE,GAIN0,GAIN1–0.3to V CC+0.3VV IN Analog input voltage RIN,LIN–0.3to7V Continuous total power dissipation See Dissipation Rating TableT A Operating free-air temperature range–40to85°CT J Operating junction temperature range–40to150°CT stg Storage temperature range–65to150°CSE Output Configuration 3.2R L Load resistance(minimum value)ΩBTL Output Configuration 6.4Human body model(all pins)±2kV ESD Electrostatic Discharge Charged-device model(all±500Vpins)(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.PACKAGE(1)(2)T A≤25°C DERATING FACTOR T A=70°C T A=85°C24-pin TSSOP 4.16W33.3mW/°C 2.67W 2.16W(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TIwebsite at .(2)This data was taken using1oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB.The thermal pad mustbe soldered to a thermal land on the printed-circuit board.See the PowerPAD Thermally Enhanced Package application note(SLMA002).MIN MAX UNITV CC Supply voltage PVCC,AVCC1026VV IH High-level input voltage SD,MUTE,GAIN0,GAIN12VV IL Low-level input voltage SD,MUTE,GAIN0,GAIN10.8VSD,V I=V CC,V CC=30V125I IH High-level input current MUTE,V I=V CC,V CC=30V125µAGAIN0,GAIN1,V I=V CC,V CC=24V125SD,V I=0,V CC=30V1I IL Low-level input current MUTE,V I=0V,V CC=30V1µAGAIN0,GAIN1,V I=0V,V CC=24V1T A Operating free-air temperature–4085°CCopyright©2008,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):TPA3121D2DC CHARACTERISTICSAC CHARACTERISTICSTPA3121D2SLOS537–MAY T A =25°C,V CC =24V,R L =8Ω(unless otherwise noted)T A =25°C,V CC =24V,R L =8Ω(unless otherwise noted)PARAMETERTEST CONDITIONSMINTYP MAXUNIT V CC =24,V ripple =200mV PP 100Hz –48ksvr Supply ripple rejection dB Gain =20dB 1kHz–52Output power at 1%THD+N V CC =24V,f =1kHz 8P O WOutput power at 10%THD+N V CC =24V,f =1kHz 10Total harmonic distortion +f =1kHz,P O =5W0.04%THD+N noise125µV 20Hz to 22kHz,A-weighted filter,V nOutput integrated noise floor Gain =20dB–78dBV CrosstalkP O =1W,f =1kHz;gain =20dB –70dB Max output at THD+N <1%,f =1kHz,SNRSignal-to-noise ratio 92dB gain =20dBThermal trip point 150°C Thermal hysteresis30°C f OSC Oscillator frequency 250300350kHz Δt mute Mute delay Time from mute input switches high until 120msec outputs mutedΔt unmuteUnmute delayTime from mute input switches low until 120msecoutputs unmuted4Submit Documentation FeedbackCopyright ©2008,Texas Instruments IncorporatedProduct Folder Link(s):TPA3121D2FUNCTIONAL BLOCK DIAGRAMAVCCLINRINMUTEBYPASSGAIN1GAIN0SDBSLPVCCLLOUTPGNDLVCLAMPBSR PVCCRROUTPGNDRAGNDTPA3121D2 SLOS537–MAY 2008Copyright ©2008,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):TPA3121D2TYPICAL CHARACTERISTICSf − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G00110.01f − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G00210.01f − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G00310.01f − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G00410.01TPA3121D2SLOS537–MAY All tests are made at frequency =1kHz unless otherwise noted.TOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsFREQUENCYFREQUENCYFigure 1.Figure 2.TOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsFREQUENCY FREQUENCYFigure 3.Figure 4.6Submit Documentation FeedbackCopyright ©2008,Texas Instruments IncorporatedProduct Folder Link(s):TPA3121D2P O − Output Power − W 0.010.111040G005P O − Output Power − W0.010.111040G006−100−90−80−70−60−50−40−30−20f − Frequency − HzC r o s s t a l k − d BG008201001k10k 20kP O − Output Power − W0.010.1110T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %40G007TPA3121D2 SLOS537–MAY 2008TYPICAL CHARACTERISTICS (continued)All tests are made at frequency =1kHz unless otherwise noted.TOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsFigure 5.Figure 6.TOTAL HARMONIC DISTORTION +NOISECROSSTALKvsvsOUTPUT POWERFREQUENCYFigure 7.Figure 8.Copyright ©2008,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):TPA3121D2−100−90−80−70−60−50−40−30−20 f − Frequency − HzC r o s s t a l k − d BG009201001k10k 20k−100−90−80−70−60−50−40−30−20f − Frequency − HzC r o s s t a l k − d BG010201001k10k 20kf − Frequency − HzP h a s e − °201001k100k10kG0116005004003002001000−100−2000510152025303540G a i n − d Bf − Frequency − HzP h a s e − °201001k100k10kG0126005004003002001000−100−2000510152025303540G a i n − d BTPA3121D2SLOS537–MAY TYPICAL CHARACTERISTICS (continued)All tests are made at frequency =1kHz unless otherwise noted.CROSSTALKCROSSTALKvsvsFREQUENCYFREQUENCYFigure 9.Figure 10.GAIN/PHASEGAIN/PHASEvsvsFREQUENCYFREQUENCYFigure 11.Figure 12.8Submit Documentation FeedbackCopyright ©2008,Texas Instruments IncorporatedProduct Folder Link(s):TPA3121D2V CC − Supply Voltage − V12345678910101112131415P O − O u t p u t P o w e r − WG013V CC − Supply Voltage − V2468101214101214161820222426P O − O u t p u t P o w e r − WG014P O − Output Power − W010203040506070809010001234567E f f i c i e n c y − %G015P O − Output Power − W102030405060708090100024681012E f f i c i e n c y − %G016TPA3121D2 SLOS537–MAY 2008TYPICAL CHARACTERISTICS (continued)All tests are made at frequency =1kHz unless otherwise noted.OUTPUT POWEROUTPUT POWERvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 14.A.Dashed linerepresentsthermallylimitedregion.Figure 13.EFFICIENCYEFFICIENCYvsvsOUTPUT POWEROUTPUT POWERFigure 15.Figure 16.Copyright ©2008,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):TPA3121D2P O − Output Power − W0.00.30.60.91.21.53691215I C C − S u p p l y C u r r e n t − AG017P O − Output Power − W0.00.20.40.60.81.01.2510152025I C C − S u p p l y C u r r e n t − AG018−100−90−80−70−60−50−40−30−20−100 f − Frequency − HzP o w e r S u p p l y R e j e c t i o n R a t i o −d BG019201001k10k 20k−100−90−80−70−60−50−40−30−20−10f − Frequency − HzP o w e r S u p p l y R e j e c t i o n R a t i o −d BG025201001k10k 20kTPA3121D2SLOS537–MAY TYPICAL CHARACTERISTICS (continued)All tests are made at frequency =1kHz unless otherwise noted.SUPPLY CURRENTSUPPLY CURRENTvsvsOUTPUT POWEROUTPUT POWERFigure 17.Figure 18.POWER SUPPLY REJECTION RATIOPOWER SUPPLY REJECTION RATIOvsvsFREQUENCYFREQUENCYFigure 19.Figure 20.10Submit Documentation FeedbackCopyright ©2008,Texas Instruments IncorporatedProduct Folder Link(s):TPA3121D2f − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G02010.01P O− Output Power − W0.010.1110T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %40G021V CC − Supply Voltage − V05101520253035404550101214161820222426P O − O u t p u t P o w e r −WG023P O − Output Power − W0102030405060708090100024681012E f f i c i e n c y − %G024TYPICAL CHARACTERISTICS (continued)All tests are made at frequency =1kHz unless otherwise noted.TOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsFREQUENCYFigure 21.Figure 22.OUTPUT POWEREFFICIENCYvsvsSUPPLY VOLTAGEOUTPUT POWERFigure 24.A.Dashed linerepresentsthermallylimitedregion.Figure 23.APPLICATION INFORMATIONCLASS-D OPERATIONTraditional Class-D ModulationScheme+V CC 0 VOutput CurrentOutput Current+V CC 0 V+V CC 0 V+V CC0 V–VCCDifferential Voltage Across SpeakerSupply PumpingThis section focuses on the class-D operation of the TPA3121D2.The TPA3121D2operates in AD mode.There are two main configurations that may be used.For stereo operation,the TPA3121D2should be configured in a single-ended (SE)half-bridge amplifier.For mono applications,TPA3121D2may be used as a bridge-tied-load (BTL)amplifier.The traditional class-D modulation scheme,which is used in the TPA3121D2BTL configuration,has a differential output where each output is 180degrees out of phase and changes from ground to the supply voltage,V CC .Therefore,the differential prefiltered output varies between positive and negative V CC ,where filtered 50%duty cycle yields 0V across the load.The class-D modulation scheme with voltage and current waveforms is shown in Figure 25and Figure 26.Figure 25.Class-D Modulation for TPA3121D2SE ConfigurationFigure 26.Class-D Modulation for TPA3121D2BTL ConfigurationOne issue encountered in single-ended (SE)class-D amplifier designs is supply pumping.Power-supply pumping is a rise in the local supply voltage due to energy being driven back to the supply by operation of the class-D amplifier.This phenomenon is most evident at low audio frequencies and when both channels are operating at the same frequency and phase.At low levels,power-supply pumping results in distortion in the audio output due to fluctuations in supply voltage.At higher levels,pumping can cause the overvoltage protection to operate,which temporarily shuts down the audio output.Gain Setting via GAIN0and GAIN1Inputs INPUT RESISTANCEInputSignalf =12Z Cpi i(1)Several things can be done to relieve power-supply pumping.The lowest impact is to operate the two inputs out of phase180°and reverse the speaker connections.Because most audio is highly correlated,this causes the supply pumping to be out of phase and not as severe.If this is not enough,the amount of bulk capacitance on the supply must be increased.Also,improvement is realized by hooking other supplies to this node,thereby, sinking some of the excess current.Power-supply pumping should be tested by operating the amplifier at low frequencies and high output levels.The gain of the TPA3121D2is set by two input terminals,GAIN0and GAIN1.The gains listed in Table2are realized by changing the taps on the input resistors and feedback resistors inside the amplifier.This input impedance(Z i)to be dependent on the gain setting.The actual gain settings are controlled by ratios of resistors,so the gain variation from part-to-part is small.However,the input impedance from part-to-part at the same gain may shift by±20%due to shifts in the actual resistance of the input resistors. For design purposes,the input network(discussed in the next section)should be designed assuming an input impedance of8kΩ,which is the absolute minimum input impedance of the TPA3121D2.At the higher gain settings,the input impedance could increase as high as72kΩ.Table2.Gain SettingINPUT IMPEDANCEAMPLIFIER GAIN(dB),GAIN1GAIN0(kΩ),TYPICALTYPICAL00206001263010321511369Changing the gain setting can vary the input resistance of the amplifier from its smallest value,10kΩ±20%,to the largest value,60kΩ±20%.As a result,if a single capacitor is used in the input high-pass filter,the–3-dB cutoff frequency may change when changing gain steps.The–3-dB frequency can be calculated using e the Z i values given in Table2.INPUT CAPACITOR,C if =c 12Z C p i i–3 dBf c(2)C =i 12Z f p i c(3)Single-Ended Output Capacitor,C OOutput Filter and Frequency ResponseIn the typical application,an input capacitor (C i )is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation.In this case,C i and the input impedance of the amplifier (Z i )form a high-pass filter with the corner frequency determined in Equation 2.The value of C i is important,as it directly affects the bass (low-frequency)performance of the circuit.Consider the example where Z i is 20k Ωand the specification calls for a flat bass response down to 20Hz.Equation 2is reconfigured as Equation 3.In this example,C i is 0.4µF;so,one would likely choose a value of 0.47µF as this value is commonly used.If the gain is known and is constant,use Z i from Table 2to calculate C i .A further consideration for this capacitor is the leakage path from the input source network (C i )and the feedback network to the load.This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom,especially in high-gain applications.For this reason,a low-leakage tantalum or ceramic capacitor is the best choice.When polarized capacitors are used,the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2V,which is likely higher than the source dc level.Note that it is important to confirm the capacitor polarity in the application.Additionally,lead-free solder can create dc offset voltages,and it is important to ensure that boards are cleaned properly.In single-ended (SE)applications,the dc blocking capacitor forms a high-pass filter with the speaker impedance.The frequency response rolls of with decreasing frequency at a rate of 20dB/decade.The cutoff frequency is determined byf c =1/2πC O Z LTable 3shows some common component values and the associated cutoff frequencies:Table mon Filter ResponsesC SE -DC Blocking Capacitor (µF)Speaker Impedance (Ω)f c =60Hz (–3dB)f c =40Hz (–3dB)f c =20Hz (–3dB)4680100022006470680150083304701000For the best frequency response,a flat-passband output filter (second-order Butterworth)may be used.The output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins.There are several possible configurations,depending on the speaker impedance and whether the output configuration is single-ended (SE)or bridge-tied load (BTL).Table 4lists the recommended values for the filter components.It is important to use a high-quality capacitor in A rating of at least X7R is required.LOUT / ROUTLOUTROUTPower-Supply Decoupling,C SPower Supply RejectionTable 4.Recommended Filter Output ComponentsOutput Configuration Speaker Impedance (Ω)Filter Inductor (µH)Filter Capacitor (nF)422680Single Ended (SE)833220Bridge Tied Load (BTL)822680Figure 27.BTL Filter Configuration Figure 28.SE Filter ConfigurationThe TPA3121D2is a high-performance CMOS audio amplifier that requires adequate power-supply decoupling to ensure that the output total harmonic distortion (THD)is as low as possible.Power-supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power-supply leads.For higher-frequency transients,spikes,or digital hash on the line,a good low equivalent-series-resistance (ESR)ceramic capacitor,typically 0.1µF to 1µF,placed as close as possible to the device V CC lead works best.For filtering lower frequency noise signals,a larger aluminum electrolytic capacitor of 470µF or greater placed near the audio power amplifier is recommended.The 470-µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs.The PVCC terminals provide the power to the output transistors,so a 470-µF or larger capacitor should be placed on each PVCC terminal.A 10-µF capacitor on the AVCC terminal is adequate.These capacitors must be properly derated for voltage and ripple-current rating to ensure reliability.TPA3121D2has good power supply rejection due to the closed-loop architecture;however,it is possible to achieve better performance (if desired)by adding a filter between the PVCC supply and the AVCC supply.The following figures illustrate the improvement that can be obtained by adding a 220Ω,220µF filter before pins 19and 20.−100−90−80−70−60−50−40−30−20−100 f − Frequency − HzP o w e r S u p p l y R e j e c t i o n R a t i o − d BG026201001k10k20k−100−90−80−70−60−50−40−30−20−10f − Frequency − HzP o w e r S u p p l y R e j e c t i o n R a t i o − d BG027201001k10k20kVCCBSN and BSP CapacitorsFigure 29.PSRR Without AVCC FilterFigure 30.PSRR With AVCC FilterFigure 31.Application Schematic with 220-Ω/220-µF AVCC FilterThe half H-bridge output stages use only NMOS transistors.Therefore,they require bootstrap capacitors for the high side of each output to turn on correctly.A 220-nF ceramic capacitor,rated for at least 25V,must be connected from each output to its corresponding bootstrap input.Specifically,one 220-nF capacitor must be connected from LOUT to BSL,and one 220-nF capacitor must be connected from ROUT to BSR.The bootstrap capacitors connected between the BSx pins and their corresponding outputs function as a floating power supply for the high-side N-channel power MOSFET gate-drive circuitry.During each high-side switching cycle,the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.VCLAMP CapacitorTo ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded,one internal regulator clamps the gate voltage.One1-µF capacitor must be connected from VCLAMP(pin11)to ground and must be rated for at least16V.The voltages at the VCLAMP terminal may vary with V CC and may not be used for powering any other circuitry.VBYP Capacitor SelectionThe scaled supply reference(VBYP)nominally provides an AVCC/8internal bias for the preamplifier stages.The external capacitor for this reference(C BYP)is a critical component and serves several important functions.During start-up or recovery from shutdown mode,C BYP determines the rate at which the amplifier starts.The start up time is proportional to0.5s per microfarad.Thus,the recommended1-µF capacitor results in a start-up time of approximately500ms.The second function is to reduce noise produced by the power supply caused by coupling with the output drive signal.This noise could result in degraded power-supply rejection and THD+N.The circuit is designed for a C BYP value of1µF for best pop performance.The input capacitors should have the same value.A ceramic or tantalum low-ESR capacitor is recommended.SHUTDOWN OPERATIONThe TPA3121D2employs a shutdown mode of operation designed to reduce supply current(I CC)to the absolute minimum level during periods of nonuse for power conservation.The SHUTDOWN input terminal should be held high(see specification table for trip point)during normal operation when the amplifier is in use.Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state.Never leave SHUTDOWN unconnected,because amplifier operation would be unpredictable.For the best power-up pop performance,place the amplifier in the shutdown or mute mode prior to applying the power-supply voltage.MUTE OperationThe MUTE pin is an input for controlling the output state of the TPA3121D2.A logic high on this terminal causes the outputs to run at a constant50%duty cycle.A logic low on this pin enables the outputs.This terminal may be used as a quick disable/enable of outputs when changing channels on a television or transitioning between different audio sources.The MUTE terminal should never be left floating.For power conservation,the SHUTDOWN terminal should be used to reduce the quiescent current to the absolute minimum level.USING LOW-ESR CAPACITORSLow-ESR capacitors are recommended throughout this application section.A real(as opposed to ideal)capacitor can be modeled simply as a resistor in series with an ideal capacitor.The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit.The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.SHORT-CIRCUIT PROTECTIONThe TPA3121D2has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts and output-to-GND shorts after the filter and output capacitor(at the speaker terminal.) Directly at the device terminals,the protection circuitry prevents damage to device during output-to-output, output-to-ground,and output-to-supply.When a short circuit is detected on the outputs,the part immediately disables the output drive.This is an unlatched fault.Normal operation is restored when the fault is removed.THERMAL PROTECTIONPRINTED-CIRCUIT BOARD (PCB)LAYOUTThermal protection on the TPA3121D2prevents damage to the device when the internal die temperature exceeds 150°C.There is a ±15°C tolerance on this trip point from device to device.Once the die temperature exceeds the thermal set point,the device enters into the shutdown state and the outputs are disabled.This is not a latched fault.The thermal fault is cleared once the temperature of the die is reduced by 30°C.The device begins normal operation at this point with no external system interaction.Because the TPA3121D2is a class-D amplifier that switches at a high frequency,the layout of the printed-circuit board (PCB)should be optimized according to the following guidelines for the best possible performance.•Decoupling capacitors—The high-frequency 0.1-µF decoupling capacitors should be placed as close to the PVCC (pins 1,3,10,and 12)and AVCC (pins 19and 20)terminals as possible.The VBYP (pin 7)capacitor and VCLAMP (pin 11)capacitor should also be placed as close to the device as rge (220-µF or greater)bulk power-supply decoupling capacitors should be placed near the TPA3121D2on the PVCCL and PVCCR terminals.•Grounding—The AVCC (pins 19and 20)decoupling capacitor and VBYP (pin 7)capacitor should each be grounded to analog ground (AGND,pins 8and 9).The PVCCx decoupling capacitors and VCLAMP capacitors should each be grounded to power ground (PGND,pins 13,14,23,and 24).Analog ground and power ground should be connected at the thermal pad,which should be used as a central ground connection or star ground for the TPA3121D2.•Output filter—The reconstruction filter (L1,L2,C9,and C16)should be placed as close to the output terminals as possible for the best EMI performance.The capacitors should be grounded to power ground.•Thermal pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability.The dimensions of the thermal pad and thermal land are described in the mechanical section at the back of the data sheet.See TI Technical Briefs SLMA002and SLOA120for more information about using the thermal pad.For recommended PCB footprints,at this data sheet.For an example layout,see the TPA3121D2Evaluation Module (TPA3121D2EVM)User Manual,(SLOU189).Both the EVM user manual and the thermal pad application note are available on the TI .。

TPA3116D2 PDF

TPA3116D2TPA3118D2TPA3130D2SLOS708B –APRIL 2012–REVISED MAY 201215W,30W,50W Filter-Free Class-D Stereo Amplifier Family with AM AvoidanceCheck for Samples:TPA3116D2,TPA3118D2,TPA3130D2FEATURESDESCRIPTIONThe TPA31xxD2series are stereo efficient,digital •Supports Multiple Output Configurations amplifier power stage for driving speakers up to –2×50-W into a 4-ΩBTL Load at 21V 100W/2Ωin mono.The high efficiency of the (TPA3116D2)TPA3130D2allows it to do 2x15W without external –2×30-W into a 8-ΩBTL Load at 24V heat sink on a single layer PCB.The TPA3118D2can even run 2x30W/8Ωwithout heat sink on a dual layer (TPA3118D2)PCB.If even higher power is needed the TPA3116D2–2×15-W into a 8-ΩBTL Load at 15V does 2x50W/4Ωwith a small heat-sink attached to its (TPA3130D2)top side PowerPad.All three devices share the same •Wide Voltage Range:4.5V –26V footprint enabling a single PCB to be used across different power levels.•Efficient Class-D Operation–>90%Power Efficiency Combined with Low The TPA31xxD2advanced oscillator/PLL circuit Idle Loss Greatly Reduces Heat Sink Size employs a multiple switching frequency option to avoid AM interferences;this is achieved together with –Advanced Modulation Schemes an option of Master/Slave option,making it possible •Multiple Switching Frequencies to synchronize multiple devices.–AM AvoidanceThe TPA31xxD2devices are fully protected against –Master/Slave Synchronizationfaults with short-circuit protection and thermal –Up to 1.2MHz Switching Frequencyprotection as well as over-voltage,under-voltage and DC protection.Faults are reported back to the •Feedback Power Stage Architecture with High processor to prevent devices from being damaged PSRR Reduces PSU Requirements during overload conditions.•Programmable Power Limit•Differential/Single-Ended InputsSimplified Application Circuit•Stereo and Mono Mode with Single Filter Mono Configuration•Single Power Supply Reduces Component Count•Integrated Self-Protection Circuits Including Over-Voltage,Under-Voltage,Over-Temperature,DC-Detect,and Short Circuit with Error Reporting•Thermally Enhanced Packages –DAD (32-pin HTSSOP Pad-up)DEVICE POWER HTSSOP 32-PIN –DAP (32-pin HTSSOP Pad-down)TPA3130D22x 15W/8ΩPad down (DAP)•–40°C to 85°C Ambient Temperature RangeTPA3118D22x 30W/8ΩPad down (DAP)TPA3116D22x 50W/4ΩPad up (DAD)APPLICATIONS•Mini-Micro Component,Speaker Bar,Docks •After-Market Automotive •CRT TV•Consumer Audio ApplicationsPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PACKAGE (TOP VIEW)FAULTZ SDZ SYNCAM0AM1MUTE LINN LINP PLIMIT RINN GVDD RINP AVCCOUTPR PVCC BSPL GND OUTPL PVCC OUTNL BSNL PVCC OUTNR BSNR MODSELBSPR GND GND PVCC GND GAIN/SLVAM2PACKAGE (TOP VIEW)FAULTZ SDZ SYNCAM0AM1MUTE LINN LINP PLIMIT RINN GVDD RINP AVCCOUTPR PVCC BSPL GND OUTPL PVCC OUTNL BSNL PVCC OUTNR BSNR MODSELBSPR GND GND PVCC GND GAIN/SLVAM2TPA3116D2TPA3118D2TPA3130D2SLOS708B –APRIL 2012–REVISED MAY 2012These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.TERMINAL ASSIGNMENTTPA3116D2TPA3130D2and TPA3118D232-PIN HTSSOP PACKAGE (DAD)32-PIN HTSSOP PACKAGE (DAP)Terminal FunctionsPINTYPE (1)DESCRIPTION 1MODSEL I Mode selection logic input (LOW =BD mode,HIGH =1SPW mode).TTL logic levels with compliance to AVCC.2SDZ I Shutdown logic input for audio amp (LOW =outputs Hi-Z,HIGH =outputs enabled).TTL logic levels with compliance to AVCC.3FAULTZDOGeneral fault reporting including Over-temp,DC Detect.Open drain.FAULTZ =High,normal operation FAULTZ =Low,fault condition4RINP I Positive audio input for right channel.Biased at 3V.5RINN I Negative audio input for right channel.Biased at 3V.6PLIMIT I Power limit level adjust.Connect a resistor divider from GVDD to GND to set power limit.Connect directly to GVDD for no power limit.7GVDD PO Internally generated gate voltage supply.Not to be used as a supply or connected to any component other than a 1µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.8GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider.9GND G Ground10LINP I Positive audio input for left channel.Biased at 3V.Connect to GND for PBTL mode.11LINN I Negative audio input for left channel.Biased at 3V.Connect to GND for PBTL mode.12MUTE I Mute signal for fast disable/enable of outputs (HIGH =outputs Hi-Z,LOW =outputs enabled).TTL logic levels with compliance to AVCC.13AM2I AM Avoidance Frequency Selection 14AM1IAM Avoidance Frequency Selection(1)TYPE :DO =Digital Output,I =Analog Input,G =General Ground,PO =Power Output,BST =Boot Strap.TPA3116D2TPA3118D2TPA3130D2 SLOS708B–APRIL2012–REVISED MAY2012Terminal Functions(continued)PINTYPE(1)DESCRIPTION15AM0I AM Avoidance Frequency Selection16SYNC DIO Clock input/output for synchronizing multiple class-D devices.Direction determined by GAIN/SLV terminal. 17AVCC P Analog Supply18PVCC P Power supply19PVCC P Power supply20BSNL BST Boot strap for negative left channel output,connect to220nF X5R,or better ceramic cap to OUTPL21OUTNL PO Negative left channel output22GND G Ground23OUTPL PO Positive left channel output24BSPL BST Boot strap for positive left channel output,connect to220nF X5R,or better ceramic cap to OUTNL25GND G Ground26BSNR BST Boot strap for negative right channel output,connect to220nF X5R,or better ceramic cap to OUTNR27OUTNR PO Negative right channel output28GND G Ground29OUTPR PO Positive right channel output30BSPR BST Boot strap for positive right channel output,connect to220nF X5R or better ceramic cap to OUTPR31PVCC P Power supply32PVCC P Power supply33Thermal Pad G Connect to GND for best system performance.If not connected to GND,leave floating.orPowerPADSDZ GAINRINP RINNFAULTZAVCCGVDDLINN LINPGNDOUTPLBSPLGNDOUTNLGNDGNDBSPRPadTPA3116D2TPA3118D2TPA3130D2SLOS708B –APRIL 2012–REVISED MAY 2012SYSTEM BLOCK DIAGRAMTPA3116D2TPA3118D2TPA3130D2 SLOS708B–APRIL2012–REVISED MAY2012 ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range(unless otherwise noted)(1)VALUE UNIT Supply voltage,V CC PV CC,AV CC–0.3to30VINPL,INNL,INPR,INNR–0.3to6.3V Input voltage,V I PLIMIT,GAIN/SLV,SYNC–0.3to GVDD+0.3VAM0,AM1,AM2,MUTE,SDZ,MODSEL–0.3to PVCC+0.3V Slew rate,maximum(2)AM0,AM1,AM2,MUTE,SDZ,MODSEL10V/msec Operating free-air temperature,T A–40to85°C Operating junction temperature range,T J–40to150°C Storage temperature range,T stg–40to125°C Electrostatic discharge:Human body model,ESD±2kV Electrostatic discharge:Charged device model,ESD±500V (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)100kΩseries resistor is needed if maximum slew rate is exceeded.THERMAL INFORMATIONTPA3130D2TPA3118D2TPA3116D2DAP DAP DADTHERMAL METRIC(1)UNITS1Layer PCB(2)2Layer PCB(3)Heatsink(4)32PINS32PINS32PINSθJA Junction-to-ambient thermal resistance362214ψJT Junction-to-top characterization parameter0.40.3 1.2°C/W ψJB Junction-to-board characterization parameter 5.9 4.8 5.7(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.(2)For the PCB layout please see the TPA3130D2EVM user guide.A1layer90x85mm1oc PCB was used(3)For the PCB layout please see the TPA3130D2EVM user guide.A2layer90x85mm1oc PCB was used(4)The heat sink drawing used for the thermal model data are shown in the application section,size:14mm wide,50mm long,25mm high. RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range(unless otherwise noted)MIN NOM MAX UNIT V CC Supply voltage PV CC,AV CC 4.526VHigh-level inputV IH AM0,AM1,AM2,MUTE,SDZ,SYNC,MODSEL2V voltageLow-level inputV IL AM0,AM1,AM2,MUTE,SDZ,SYNC,MODSEL0.8V voltageLow-level outputV OL FAULTZ,R PULL-UP=100kΩ,PV CC=26V0.8V voltageHigh-level inputI IH AM0,AM1,AM2,MUTE,SDZ,MODSEL(V I=2V,V CC=18V)50µAcurrentTPA3116D2,TPA3118D2 3.24R L(BTL)Output filter:L=10µH,C=680nFTPA3130D2 5.68 Minimum loadΩImpedance TPA3116D2,TPA3118D2 1.6R L(PBTL)Output filter:L=10µH,C=1µFTPA3130D2 3.24Output-filterL o Minimum output filter inductance under short-circuit condition1µH InductanceCopyright©2012,Texas Instruments Incorporated Submit Documentation Feedback5TPA3116D2TPA3118D2TPA3130D2SLOS708B–APRIL2012–REVISED DC ELECTRICAL CHARACTERISTICST A=25°C,AV CC=PV CC=12V to24V,R L=4Ω(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITClass-D output offset voltage(measured|V OS|V I=0V,Gain=36dB 1.515mV differentially)SDZ=2V,No load or filter,PV CC=12V2035I CC Quiescent supply current mASDZ=2V,No load or filter,PV CC=24V3250SDZ=0.8V,No load or filter,PV CC=12V<50 Quiescent supply current in shutdownI CC(SD)µAmode SDZ=0.8V,No load or filter,PV=24V50400CCDrain-source on-state resistance,r DS(on)PV CC=21V,I out=500mA,T J=25°C120mΩmeasured pin to pinR1=open,R2=20kΩ192021dBR1=100kΩ,R2=20kΩ252627G Gain(BTL)R1=100kΩ,R2=39kΩ313233dBR1=75kΩ,R2=47kΩ353637R1=51kΩ,R2=51kΩ192021dBR1=47kΩ,R2=75kΩ252627G Gain(SLV)R1=39kΩ,R2=100kΩ313233dBR1=16kΩ,R2=100kΩ353637t on Turn-on time SDZ=2V10mst OFF Turn-off time SDZ=0.8V2µs GVDD Gate drive supply IGVDD<200µA 6.4 6.97.4VOutput voltage maximum under PLIMITV O V(PLIMIT)=2V;V I=1V rms 6.757.908.75V controlAC ELECTRICAL CHARACTERISTICST A=25°C,AV CC=PV CC=12V to24V,R L=4Ω(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT200mV PP ripple at1kHz,Gain=20dB,Inputs AC-KSVR Power supply ripple rejection–70dBcoupled to GNDTHD+N=10%,f=1kHz,PV CC=14.4V25P O Continuous output power WTHD+N=10%,f=1kHz,PV CC=21V50THD+N Total harmonic distortion+noise V CC=21V,f=1kHz,P O=25W(half-power)0.1%65µV Vn Output integrated noise20Hz to22kHz,A-weighted filter,Gain=20dB–80dBVCrosstalk V O=1V rms,Gain=20dB,f=1kHz–100dBMaximum output at THD+N<1%,f=1kHz,Gain=20dB,SNR Signal-to-noise ratio102dBA-weightedAM2=0,AM1=0,AM0=0376400424AM2=0,AM1=0,AM0=1470500530AM2=0,AM1=1,AM0=0564600636AM2=0,AM1=1,AM0=194010001060f OSC Oscillator frequency kHzAM2=1,AM1=0,AM0=0112812001278AM2=1,AM1=0,AM0=1AM2=1,AM1=1,AM0=0ReservedAM2=1,AM1=1,AM0=1Thermal trip point150+°CThermal hysteresis15°CTPA3130D2 4.5 Over current trip point ATPA3118D2,TPA3116D27.56Submit Documentation Feedback Copyright©2012,Texas Instruments Incorporated0.0010.010.1110Frequency (Hz)T H D +N (%)G0020.0010.010.1110Frequency (Hz)T H D +N (%)G0030.0010.010.1110Frequency (Hz)T H D +N (%)G0040.0010.010.1110Frequency (Hz)T H D +N (%)G005TPA3116D2TPA3118D2TPA3130D2SLOS708B –APRIL 2012–REVISED MAY 2012TYPICAL CHARACTERISTICSf s =400kHz,BD Mode (unless otherwise noted)TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCYFREQUENCYFigure 1.Figure 2.TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCYFREQUENCYFigure 3.Figure 4.Copyright ©2012,Texas Instruments Incorporated Submit Documentation Feedback 70.0010.010.1110Frequency (Hz)T H D +N (%)G006Output Power (W)T H D +N (%)G008Output Power (W)T H D +N (%)G009Output Power (W)T H D +N (%)G010TPA3116D2TPA3118D2TPA3130D2SLOS708B –APRIL 2012–REVISED MAY 2012TYPICAL CHARACTERISTICS (continued)f s =400kHz,BD Mode (unless otherwise noted)TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCYOUTPUT POWERFigure 5.Figure 6.TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsOUTPUT POWEROUTPUT POWERFigure 7.Figure 8.8Submit Documentation Feedback Copyright ©2012,Texas Instruments IncorporatedOutput Power (W)T H D +N (%)G011Output Power (W)T H D +N (%)G012−500−400−300−200−1000100200300Frequency (Hz)G a i n (d B )P h a s e (°)G0141020304050PLIMIT Voltage (V)O u t p u t P o w e r (W )G013TPA3116D2TPA3118D2TPA3130D2SLOS708B –APRIL 2012–REVISED MAY 2012TYPICAL CHARACTERISTICS (continued)f s =400kHz,BD Mode (unless otherwise noted)TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsOUTPUT POWEROUTPUT POWERFigure 9.Figure 10.OUTPUT POWER (BTL)GAIN/PHASE (BTL)vsvsPLIMIT VOLTAGEFREQUENCYFigure 11.Figure 12.Copyright ©2012,Texas Instruments Incorporated Submit Documentation Feedback 95101520253035404550Supply Voltage (V)M a x i m u m O u t p u t P o w e r (W )G0155101520253035404550556065707580859095100Supply Voltage (V)M a x i m u m O u t p u t P o w e r (W )G016102030405060708090100Output Power (W)P o w e r E f f i c i e n c y (%)G017102030405060708090100Output Power (W)P o w e r E f f i c i e n c y (%)G018TPA3116D2TPA3118D2TPA3130D2SLOS708B –APRIL 2012–REVISED MAY 2012TYPICAL CHARACTERISTICS (continued)f s =400kHz,BD Mode (unless otherwise noted)MAXIMUM OUTPUT POWER (BTL)MAXIMUM OUTPUT POWER (BTL)vsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 13.Figure 14.POWER EFFICIENCY (BTL)POWER EFFICIENCY (BTL)vsvsOUTPUT POWEROUTPUT POWERFigure 15.Figure 16.10Submit Documentation Feedback Copyright ©2012,Texas Instruments Incorporated−140−130−120−110−100−90−80−70−60−50−40−30−20−100Frequency (Hz)C r o s s t a l k (d B )G021−140−130−120−110−100−90−80−70−60−50−40−30−20−100Frequency (Hz)C r o s s t a l k (d B )G022−100−90−80−70−60−50−40−30−20−100Frequency (Hz)k S V R (d B )G0230.0010.010.1110Frequency (Hz)T H D +N (%)G024f s =400kHz,BD Mode (unless otherwise noted)CROSSTALKCROSSTALKvsvsFREQUENCYFREQUENCYFigure 17.Figure 18.SUPPLY RIPPLE REJECTION RATIO (BTL)TOTAL HARMONIC DISTORTION +NOISE (PBTL)vsvsFREQUENCYFREQUENCYFigure 19.Figure 20.Output Power (W)T H D +N (%)G02520406080100120140160180Supply Voltage (V)M a x i m u m O u t p u t P o w e r (W )G027102030405060708090100Output Power (W)P o w e r E f f i c i e n c y (%)G028−100−90−80−70−60−50−40−30−20−100Frequency (Hz)k S V R (d B )G030f s =400kHz,BD Mode (unless otherwise noted)TOTAL HARMONIC DISTORTION +NOISE (PBTL)MAXIMUM OUTPUT POWER (PBTL)vsvsOUTPUT POWERSUPPLY VOLTAGEFigure 21.Figure 22.POWER EFFICIENCY (PBTL)SUPPLY RIPPLE REJECTION RATIO (PBTL)vsvsOUTPUT POWERFREQUENCYFigure 23.Figure 24.Output Power (W)T H D +N (%)G0320102030405060708090100110120130140Supply Voltage (V)M a x i m u m O u t p u t P o w e r (W )G034f s =400kHz,BD Mode (unless otherwise noted)TOTAL HARMONIC DISTORTION +NOISE (PBTL)MAXIMUM OUTPUT POWER (PBTL)vsvsOUTPUT POWERSUPPLY VOLTAGEFigure 25.Figure 26.DEVICE INFORMATIONTYPICAL APPLICATIONPVCC DECOUPLINGFigure27.SchematicA2.1solution,U1TPA3116D2in Master mode400kHz,BTL,gain if20dB,power limit not implemented.U2in Slave,PBTL mode gain of20dB.Inputs are connected for differential inputs.In the following sections the TPA3116D2,TPA3118D2,and TPA3130D2are referred to as:TPA31xxD2family.i i 1f 2Z C p =ƒGAIN SETTING AND MASTER /SLAVEThe gain of the TPA31xxD2family is set by the voltage divider connected to the GAIN/SLV control pin.Master or Slave mode is also controlled by the same pin.An internal ADC is used to detect the 8input states.The first four stages sets the GAIN in Master mode in gains of 20,26,32,36dB respectively,while the next four stages sets the GAIN in Slave mode in gains of 20,26,32,36dB respectively.The gain setting is latched during power-up and cannot be changed while device is powered.Table 1shows the recommended resistor values and the state and gain:Table 1.GAIN and MASTER/SLAVEMASTER /SLAVEGAIN R1(to GND)(1)R2(to GVDD)(1)INPUT IMPEDANCEMODEMaster 20dB 5.6k ΩOPEN 60k ΩMaster 26dB 20k Ω100k Ω30k ΩMaster 32dB 39k Ω100k Ω15k ΩMaster 36dB 47k Ω75k Ω9k ΩSlave 20dB 51k Ω51k Ω60k ΩSlave 26dB 75k Ω47k Ω30k ΩSlave 32dB 100k Ω39k Ω15k ΩSlave36dB100k Ω16k Ω9k Ω(1)Resistor tolerance should be 5%or better.In Master mode,SYNC terminal is an output,in Slave mode,SYNC terminal is an input for a clock input.TTL logic levels with compliance to GVDD.INPUT IMPEDANCEThe TPA31xxD2family input stage is a fully differential input stage and the input impedance changes with the gain setting from 9k Ωat 36dB gain to 60k Ωat 20dB gain.Table 1lists the values from min to max gain.The tolerance of the input resistor value is ±20%so the minimum value will be higher than 7.2k Ω.The inputs need to be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during power-ON and power-OFF.The input ac-coupling capacitor together with the input impedance forms a high-pass filter with the following cut-off frequency:(1)If a flat bass response is required down to 20Hz the recommended cut-off frequency is a tenth of that,2Hz.Table 2lists the recommended ac-couplings capacitors for each gain step.If a -3dB is accepted at 20Hz 10times lower capacitors can used –for example,a 1µF can be used.Table 2.Recommended Input AC-Coupling CapacitorsGAIN INPUT IMPEDANCEINPUT CAPACITANCEHIGH-PASS FILTER20dB 60k Ω 1.5µF 1.8Hz 26dB 30k Ω 3.3µF 1.6Hz 32dB 15k Ω 5.6µF 2.3Hz 36dB9k Ω10µF1.8HzInput SignalThe input capacitors used should be a type with low leakage,like quality electrolytic,tantalum or ceramic.If a polarized type is used the positive connection should face the input pins which are biased to 3Vdc.START-UP/SHUTDOWN OPERATIONThe TPA31xxD2family employs a shutdown mode of operation designed to reduce supply current (Icc)to the absolute minimum level during periods of nonuse for power conservation.The SDZ input terminal should be held high (see specification table for trip point)during normal operation when the amplifier is in use.Pulling SDZ low will put the outputs to mute and the amplifier to enter a low-current state.It is not recommended to leave SDZ unconnected,because amplifier operation would be unpredictable.For the best power-off pop performance,place the amplifier in the shutdown mode prior to removing the power supply.The gain setting is selected at the end of the start-up cycle.At the end of the start-up cycle,the gain is selected and cannot be changed until the next power-up.PLIMIT OPERATIONThe TPA31xxD2family has a built-in voltage limiter that can be used to limit the output voltage level below the supply rail,the amplifier simply operates as if it was powered by a lower supply voltage,and thereby limits the output power.Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin.An external reference may also be used if tighter tolerance is required.Add a 1µF capacitor from pin PLIMIT to ground to ensure stability.It is recommended to connect PLIMIT to GVDD when using 1SPW-modulation mode.Figure 28.POWER LIMIT ExampleThe PLIMIT circuit sets a limit on the output peak-to-peak voltage.The limiting is done by limiting the duty cycle to a fixed maximum value.This limit can be thought of as a "virtual"voltage rail which is lower than the supply connected to PVCC.This "virtual"rail is approximately 4times the voltage at the PLIMIT pin.This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.2LP L S OUTLR V R +2R P =for unclipped power2R æöæö´ç÷ç÷ç÷´èøèø´(2)Where:R S is the total series resistance including R DS(on),and output filter resistance.R L is the load resistance.V P is the peak amplitudeV P =4×PLIMIT voltage if PLIMIT <4×V P P OUT (10%THD)=1.25×P OUT (unclipped)Table 3.POWER LIMIT ExamplePV CC (V)PLIMIT VOLTAGE (V)(1)R to GND R to GVDD OUTPUT VOLTAGE (V rms )24V GVDD Short Open 17.9024V 3.345k Ω51k Ω12.6724V 2.2524k Ω51k Ω9.0012V GVDD Short Open 10.3312V 2.2524k Ω51k Ω9.0012V1.518k Ω68k Ω6.30(1)PLIMIT measurements taken with EVM gain set to 26dB and input voltage set to 1V rms .GVDD SUPPLYThe GVDD Supply is used to power the gates of the output full bridge transistors.It can also be used to supply the PLIMIT and GAIN/SLV voltage dividers.Decouple GVDD with a X5R ceramic 1µF capacitor to GND.The GVDD supply is not intended to be used for external supply.It is recommended to limit the current consumption by using resistor voltage dividers for GAIN/SLV and PLIMIT of 100k Ωor more.BSPx AND BSNx CAPACITORSThe full H-bridge output stages use only NMOS transistors.Therefore,they require bootstrap capacitors for the high side of each output to turn on correctly.A 220nF ceramic capacitor of quality X5R or better,rated for at least 16V,must be connected from each output to its corresponding bootstrap input.(See the application circuit diagram in Figure 27.)The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry.During each high-side switching cycle,the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.DIFFERENTIAL INPUTSThe differential input stage of the amplifier cancels any noise that appears on both input lines of the channel.To use the TPA31xxD2family with a differential source,connect the positive lead of the audio source to the RINP or LINP input and the negative lead from the audio source to the RINN or LINN input.To use the TPA31xxD2family with a single-ended source,ac ground the negative input through a capacitor equal in value to the input capacitor on positive and apply the audio source to either input.In a single-ended input application,the unused input should be ac grounded at the audio source instead of at the device input for best noise performance.For good transient performance,the impedance seen at each of the two differential inputs should be the same.The impedance seen at the inputs should be limited to an RC time constant of 1ms or less if possible.This is to allow the input dc blocking capacitors to become completely charged during the 10ms power-up time.If the input capacitors are not allowed to completely charge,there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched.MONO MODE (PBTL)The TPA31xxD2family can be connected in MONO mode enabling up to 100W output power.This is done by:•Connect INPL and INNL directly to Ground (without capacitors)this sets the device in Mono mode during power up.•Connect OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for the negative terminal•Analog input signal is applied to INPR and INNRDEVICE PROTECTION SYSTEMThe TPA31xxD2family contains a complete set of protection circuits carefully designed to make system design efficient as well as to protect the device against any kind of permanent failures due to short circuits,overload,over temperature,and under-voltage.The FAULTZ pin will signal if an error is detected according to the fault table below:Table 4.Fault ReportingTRIGGERING CONDITIONLATCHED/SELF-FAULT FAULTZ ACTION(typical value)CLEARINGOver Current Output short or short to PVCC or GNDLow Output high impedance Latched Over Temperature T j >150°C Low Output high impedance Latched Too High DC Offset DC output voltage Low Output high impedance Latched Under Voltage onPVCC <4.5V –Output high impedance Self-clearing PVCC Over Voltage onPVCC >27V–Output high impedanceSelf-clearingPVCCDC DETECT PROTECTIONThe TPA31xxD2family has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs.A DC detect fault will be reported on the FAULT pin as a low state.The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z.If automatic recovery from the short circuit protection latch is desired,connect the FAULTZ pin directly to the SDZ pin.This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the DC Detect protection latch.A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 60%for more than 420msec at the same polarity.Table x below shows some examples of the typical DC Detect Protection threshold for several values of the supply voltage.This feature protects the speaker from large DC currents or AC currents less than 2Hz.To avoid nuisance faults due to the DC detect circuit,hold the SD pin low at power-up until the signals at the inputs are stable.Also,take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults.The minimum output offset voltages required to trigger the DC detect are show in Table 5.The outputs must remain at or above the voltage listed in the table for more than 420msec to trigger the DC detect.Table 5.DC Detect ThresholdPV CC (V)V OS -OUTPUT OFFSET VOLTAGE (V)4.50.966 1.3012 2.60183.90SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATUREThe TPA31xxD2family has protection from over current conditions caused by a short circuit on the output stage.The short circuit protection fault is reported on the FAULTZ pin as a low state.The amplifier outputs are switched to a high impedance state when the short circuit protection latch is engaged.The latch can be cleared by cycling the SDZ pin through the low state.If automatic recovery from the short circuit protection latch is desired,connect the FAULTZ pin directly to the SDZ pin.This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the short-circuit protection latch.In systems where a possibility of a permanent short from the output to PVDD or to a high voltage battery like a car battery can occur,pull the MUTE pin low with the FAULTZ signal with a inverting transistor to ensure a high-Z restart,like shown in the figure below:Figure 29.MUTE Driven by Inverted FAULTZ Figure 30.Timing Requirement for SDZTHERMAL PROTECTIONThermal protection on the TPA31xxD2family prevents damage to the device when the internal die temperature exceeds 150°C.There is a ±15°C tolerance on this trip point from device to device.Once the die temperature exceeds the thermal trip point,the device enters into the shutdown state and the outputs are disabled.This is a latched fault.Thermal protection faults are reported on the FAULTZ terminal as a low state.If automatic recovery from the thermal protection latch is desired,connect the FAULTZ pin directly to the SDZ pin.This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermal protection latch.。

建伍对讲机Tk-2118,3118手动制频

--------- 4
按LOW
455.050 4
旋轉ENC
1. 按SCAN改變5/6.25KHz步進 2. 按1 + ENC改變1MHz步進
465.050 4
按PTT
OFF 5
按PTT
設定QT, DQT 按LOW選擇可選信令
9. QT d. DQT (按DIAL選擇+ -) OFF 0:無 1 : DTMF
QT / DQT + DTMF
FILE : USER\RPOON\TWIN\CHART\TK-2118/3118
信道設定模式按【 LOW】 CH 1 1 旋轉ENC, 選擇CH1~CH50
000
0
若選擇呼叫功能有效時, 則進入0000, 輸入000~999 按PTT
若選擇呼叫功能無效時, 則進入ON1 按PTT ,旋轉ENC 設定峰鳴聲 ON : 有聲 ON 1 OFF : 無聲按PTT ,旋轉ENC 設定監聽鍵值 O : 靜噪關閉 NO2 1 O 1 : 監聽觸發 2 : 監聽瞬時 OFF : 關按PTT End 結束
O
6
按PTT 繁忙信道鎖定 OFF : 關 1 : 載波按PTT 2 : QT / DQT 3 : DTMF 拍頻編移 OFF : 不編移 8 OFF ON : 偏移按PTT 刪除 / 追加掃描Add : 掃描 Add 9 dEL : 不掃描按PTT 寬 / 窄帶選擇 0:窄帶 1 10 O6 1 : 寬帶按PTT SP不靜音 0:載波或QT / DQT 0 11
OFF 7 O6
FILE : USER\RPOON\TWIN\CHART\TK-2118/3118
注 : 06設定 1 : 載波 + DTMF或QT / DQT + DTMF ON才有效按PTT 高 / 低功率選擇H : 高功率 H 12 L : 低功率

MEMORY存储芯片TPA3118D2DAPR中文规格书

健伍TK-3118说明书

KENWOOD TK-2118/3118使用手册开箱和装置检查下列开箱说明仅针对kenwood经销商，经授权的kenwood服务机构或者工厂。

请小心地从包装箱中取出对讲机。

我们建议在您废弃包装材料之前，按照下表清点附件。

如果发现任何物品在运输中丢失或损坏，请立即向送货人提交索赔书。

对另购的NiMH电池组充电另购的电池组在出厂时未充电，请在使用前进行充电(参照电池充电器使用说明书)。

1 如果电池组已经完全充电，请勿再行充电。

否则，电池组的寿命会缩短或者损坏。

2 重新对电池组充电后，请将它从充电器上取下。

如果重新接通充电器电源(关闭电源后再次接通)，充电器将开始再次充电，从而造成电池组的过充电。

在购买后或者长期存放(两个月以上)后第一次对电池组充电不能使电池组达到它的通常使用容量。

在反复充／放电两、三次后，使用容量将增至通常状态。

安装／取下另观的NiMH电池组1 不得短路电池端子，也不得将电池投入到火中。

2 不得试图将电池组的外壳取下。

3 不得在危险环境中安装电池组，火花将引起爆炸。

1 将电池组插入对讲机的底部，推入电池组直到电池组上的闩锁锁定为止。

2 取下电池组时，按下电池组后侧的闩锁，向外侧滑动取出。

安装／取下电池1 不得短路电池端子，也不得将电池投入到火中。

2 不得在危险环境中安装电池组，火花将引起爆炸。

完全充电的nimh电池组可以实现对讲机的最佳性能，尤其是对于长时间发射或着连续使用。

如果没有nimh电池组，也可以使用碱性电池。

我们建议使用高质量的碱性电池。

安装或者取下电池盒时，请按照与上述的“安装／取下另购的nimh电池组”相同的说明操作。

向电池盒装入电池。

1 按下电池盒底郎的闩锁，打开电池盒，将电池盒分为两半。

2 装入5节5号电池(lr6／aa)。

电池的极性应务必与电池盒上的标志一致。

3 将电池盒上部的闩锁对准电池盒下部的锁槽，然后将两半电池盒压紧，直到闩锁锁定为止。

安装天线拿住天线底座，按顺时针方向将天线旋入对讲机顶部的接口上，直到旋紧为止。

TLK3118中文资料

• Redundancy: Fast Switching from Primary to Secondary XAUI channel with Provisionable Error Character or Local Code Fault Insertion at Switch Time
• XAUI: Transmit Pre-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach
The TLK3118 can be configured as a redundant XAUI transceiver or a full duplex XAUI re-timer. TLK3118 supports a 32-bit data path, 4-bit control, 10 Gigabit Media Independent Interface (XGMII) to the protocol device. Figure 1 shows an example system block diagram for TLK3118 used to provide the 10-Gbps Ethernet Physical Coding Sublayer to Coarse Wave-length Division Multiplexed optical transceiver or parallel optics.
The TLK3118 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface. The TLK3118 provides two complete XGXS/PCS functions defined in Clause 47/48 of the IEEE P802.3ae 10Gbps Ethernet standard. The serial transmitter is implemented using differential Current Mode Logic (CML) with integrated termination resistors.

TPAD中文数据表

T P A D中文数据表Revised on July 13, 2021 at 16:25 pmTPA3116D2 具有AM 干扰抑制功能的15W、30W、50W无滤波器D类立体声放大器系列特性支持多种输出配置21V 电压、4Ω桥接负载 BTL 负载条件下的功率为 2 × 50W TPA3116D224V 电压、8Ω BTL 负载条件下的功率为 2 × 30W TPA3118D215V 电压、8Ω BTL 负载条件下的功率为 2 × 15W TPA3130D2宽电压范围：4.5V 至 26V高效 D 类运行兼具 > 90% 的功率效率与低空闲损耗特性;大幅减小了散热器尺寸高级调制系统配置;多重开关频率;AM 干扰防止;主从模式同步高达 1.2MHz 的切换频率采用具有高 PSRR 的反馈功率级架构;降低了 PSU 需求可编程功率限制;差分和单端输入立体声模式和单声道模式采用单滤波器单声道配置由单电源供电运行;减少了元件数量集成了具有错误报告功能的自保护电路;其中包括过压、欠压、过热、直流检测和短路等保护;耐热增强型封装DAD32 位引脚散热薄型小外形尺寸 HTSSOP 封装;焊盘朝上DAP32 位 HTSSOP 封装;焊盘朝下-40°C 至 85°C 环境温度范围应用小型-微型组件、扬声器、扩展坞底座汽车售后阴极射线管 CRT TV消费类音频应用说明TPA31xxD2 系列器件是用于驱动扬声器的高效立体声数字放大器功率级;单声道模式下的驱动功率高达 100W/2Ω.. TPA3130D2 的效率非常高;无需外部散热器即可在单层 PCB 板上提供 2 × 15W 的功率.. TPA3118D2 甚至可以在不使用外部散热器的情况下在双层 PCB 上提供 2 × 30W/8Ω的功率.. 如果需要更高的功率;可以选用 TPA3116D2;这款器件在其顶层PowerPAD 上连接一个小型散热器后可提供 2 × 50W/4Ω的功率.. 所有这三款器件均使用同一种封装;这样一来;使用同一个 PCB 板即可满足不同功率级的需求..TPA31xxD2 高级振荡器/PLL 电路采用多开关频率选项来抑制 AM 干扰；搭配使用主从模式选项时;还可使多个器件实现同步..TPA31xxD2 器件针对短路、过热、过压、欠压和直流等故障提供了全面保护.. 在过载情况下;器件会将故障情况报告给处理器;从而避免自身遭到损坏..器件信息1详细描述概述tpa31xxd2装置是一种高效的D类音频放大器集成120mΩMOSFET;允许输出电流高达7.5 A 的高效率允许放大器提供一个极好的音频性能不需要一个庞大的散热片..该装置可配置为使用同步引脚的主从操作..这有助于防止声音节拍噪音..功能块图特征描述增益设置和主人和奴隶家庭的tpa31xxd2增益设置连接增益/ SLV控制引脚的电压分压器..硕士或从属模式也由同一个引脚控制..一个内部的ADC是用于检测8个输入状态..前四阶段设置在主模式中获得的收益为20;26;32;36分贝;而下一个四个阶段集在从模式增益为20;26;32;36分贝增益..增益设置在电源锁存当设备供电时;不能改变..表1列出推荐的电阻值和状态增益：（1）电阻公差应为5%或更好..在主模式;同步终端是一个输出;在从模式;同步终端是一个输入时钟输入..TTL逻辑电平与符合GVDD..输入阻抗家庭的tpa31xxd2输入级是一个全差分输入级;输入阻抗的变化增益设置从9 KΩ在增益36分贝至60 KΩ在20 dB的增益..表1列出从最小到最大增益值..这的输入电阻值误差±20%最小值将高于7.2 KΩ..输入需要AC耦合到输出直流偏移和确保斜坡的输出电压在电源正确—论与权力..输入交流耦合电容与输入阻抗形成一个高通滤波器有以下截止频率：如果一个平坦的低音响应是必需的下降到20赫兹的建议截止频率为十分之一;2赫兹..表2 列出了建议的交流耦合电容器的每一个增益步..如果一个- 3分贝是接受在20赫兹10倍低电容器可以使用;例如;可以使用1μf所使用的输入电容应是一种低泄漏;如优质电解;钽或陶瓷的类型..如果一个偏光式是用积极的连接应面偏3 VDC输入引脚..启动和关闭操作tpa31xxd2家庭使用操作旨在降低电源电流关断模式ICC的绝对最低水平在电力节约使用期..SDZ输入端应举行在正常运行时;在正常运行时;在正常运行时;在正常运行时见表..拉低作用将输出静音和放大器进入低电流状态..不建议离开SDZ无关的;因为放大器的操作将是不可预知的..最流行的性能将放大器断电;在关断模式;消除电源之前供应..在启动周期结束时选择增益设置..在启动周期结束时;增益是选定并不能更改;直到下一次电源..plimit操作tpa31xxd2家族有一个内置的电压限制器可用于限制输出电压水平以下电源轨;放大器的简单地工作;如果它是由一个较低的电源电压供电;从而限制了输出功率..加一个电阻分压器的GVDD地面设置的电压在plimit销..一个外部的如果需要更严格的公差;也可使用参考..添加一个1μF的电容μ针plimit地保证稳定性..建议连接到使用1spw plimit GVDD调制方式时..plimit电路上设置输出电压峰峰值限制..限制是通过限制的占空比以一个固定的最大值..这个极限可以被认为是一个“虚拟”的电压轨道;这是低于供应连接到PVCC..这个“虚拟”的轨道大约是4倍的电压在plimit销..此输出电压可用于计算最大输出功率为给定的最大输入电压和扬声器阻抗..在哪儿输出功率10%的THD= 1.25×输出功率移除RL负载电阻..RS是总串联电阻RDSON;包括输出过滤器的阻力..副总裁是峰值幅度VP = 4×plimit电压如果plimit＜4×VP（1）plimit taken with EVM测量增益集to 26dB与输入电压set to 1Vrms..GVDD供应用于电力供应的GVDD的全桥式输出晶体管的大门..它也可以用来供应plimit和增益/ SLV 电压分压器..解耦GVDD与X5R陶瓷1μμF的电容到GND..这GVDD供应不可用于外部电源..建议限制当前消费采用电阻分压器的增益/ SLV和100 KΩ或更plimitbspx和bsnx电容器全桥输出阶段只使用NMOS晶体管..因此;他们需要为每个输出的高边依次打开..220 nF陶瓷电容器质量X5R或更好;额定电压至少16伏;必须从每个输出连接到其相应的引导输入..见应用电路在图37图..bsxx引脚连接和相应的输出函数之间的自举电容器;作为一个浮动电源的高侧N通道功率MOSFET的栅极驱动电路..在每一个高边开关周期;自举电容保持的栅极至源极电压高到足以保持高边MOSFET的开启..差分输入该放大器的差分输入级取消任何出现在通道的输入线的噪声..以使用tpa31xxd2家庭和一个差分源;连接音频源正导致RINP或linp输入和音频源负导致里恩或属输入..使用tpa31xxd2家庭用一个单一的结束源;交流地负输入通过一个电容等于输入电容论积极的和适用的音频源;无论是输入..在单端输入应用程序中;未使用的输入应该是交流接地在音频源;而不是在设备输入的最佳噪声性能..为了好瞬态性能;在每一个差分输入看到的阻抗应该是相同的..在输入阻抗的阻抗应该被限制在一个钢筋混凝土的时间常数为1毫秒或更少;如果可能的话..这是允许输入直流阻挡电容器成为完全充电在10毫秒的时间..如果输入电容器是不允许完全充电;将有一些额外的灵敏度组件匹配如果输入组件没有很好的匹配;它会导致弹出..设备保护系统tpa31xxd2家族包括一套完整的保护电路;精心设计;使系统的设计有效的;以及保护设备免受任何类型的永久性故障;由于短路;过载;过温、欠压..的faultz引脚信号如果按照表4中检测到错误：直流检测保护tpa31xxd2家庭电路将保护扬声器免受直流电流可能发生的印刷电路板上的输入或短路上有缺陷的电容器..一个直流检测故障将报告故障引脚为低状态..直流检测故障也会导致放大器关机改变输出状态为高阻..如果从短路保护自动恢复所需的锁存器;连接faultz引脚直接到SDZ销..这让faultz引脚功能来自动驱动SDZ引脚低清除直流检测保护锁..直流检测故障时;输出差分占空比任何一个通道超过60%;超过420毫秒在相同的极性..下面的表格显示了典型的直流检测保护的一些例子电源电压的几个值的阈值..此功能保护扬声器从大的直流电流或交流电流小于2Hz..为了避免滋扰故障由于直流检测电路;将SD引脚低电直到输入信号稳定..此外;要小心;以匹配的阻抗看到的正面和负输入;以避免扰直流检测故障..表5列出的最小输出偏置电压需要触发直流检测..输出必须保持在或上面的电压表中列出了420多毫秒触发的直流检测..短路保护和自动恢复功能tpa31xxd2家庭保护过电流条件下的短路引起的输出级..短路保护故障报告的faultz引脚为低状态..放大器输出切换当短路保护锁存器的时候;可以在高阻抗状态下进行..锁存器可通过循环清零SDZ引脚通过低状态..如果从短路保护自动恢复所需的锁存器;连接faultz引脚直接到SDZ销..这让faultz引脚功能来自动驱动SDZ引脚低清除短路保护锁..在系统中;可能永久短从输出PVDD或高电压电池一样汽车电池可以发生;与逆变晶体管保证高的faultz信号拉低静音引脚—重新启动;如下图所示：热保护在tpa31xxd2家庭热保护防止设备损坏时;模内温度超过150°C;有一个15°C的公差;从设备到设备..一旦模具温度超过热行程点;该设备进入关机状态和输出被禁用..这是一个锁存故障..热保护故障报告的faultz终端低状态..如果从热保护锁自动恢复的需要;将faultz引脚直接到SDZ销..这让faultz引脚功能来自动驱动SDZ引脚低清除热保护锁..装置调制方案tpa31xxd2家族在BD调制或1spw调制运行选项；这是由模式销..模式= GND：BD调制这是一个调制方案;允许在没有经典的液晶重建滤波器的运算放大器用短喇叭线驱动感应负载..每一个输出开关从0伏到电源电压..的outpx和outnx是相互不输入;在很少或没有电流演讲者..outpx的占空比是大于50% outnx小于正输出电压50%..outpx的占空比小于50%;outnx大于负输出电压的50%..这个在负载电压在0V在大多数的开关周期;降低开关电流;这减少在任何负载的I2R损耗..模式=高：1spw调制1spw模式改变了正常的调制方案;以轻微的刑罚实现更高的效率在THD降解和更多的关注在输出滤波器的选择要求..在1spw模式的输出操作在空闲状态下的15%调制..当一个音频信号被施加一个输出将减少和一个将增加..降低输出信号将很快轨到GND;此时所有的音频调制发生通过不断上升的输出..其结果是;只有一个输出是在大多数的音频周期切换..在这种模式下;由于减少开关损耗的效率提高..在1spw模式THD处罚最小化的高性能反馈回路..由此产生的音频信号在每个半输出间断每次到GND输出轨..这可能会导致在音频重建过滤器;除非在选择过滤器组件和使用过滤器的类型..效率：LC滤波器所要求的与传统的D类调制方案最主要的原因;基于AD调制需要输出滤波器的传统的D类放大器;最大电流流量的开关波形..这会导致更多的损失;这会导致更低的负荷效率..对于传统的调制方案;纹波电流较大;因为纹波电流较大电压乘以电压乘以时间..差分电压摆幅为2×VCC;和在每个电压的时间是一半的周期为传统的调制方案..一个理想的液晶过滤器是必要的存储每一个周期为下一个周期的纹波电流;而任何电阻会导致功耗..这个扬声器是电阻和反应性;而一个液晶滤波器几乎是纯粹的反应性..的tpa3116d2调制方案无滤波器在负载损耗小;因为脉冲短电压变化而不是2×VCC VCC..随着输出功率的增加;脉冲展宽;使纹波电流较大..纹波电流可以用液晶过滤器过滤;以提高效率;但对于大多数应用该过滤器是不需要的..LC滤波器的截止频率小于D类开关频率允许开关电流通过过滤器来代替负载..该过滤器具有较小的电阻;但更高的阻抗在切换频率比扬声器;这导致在功耗较小;因此提高效率..磁珠滤波器的考虑采用先进的排放抑制技术在tpa3116d2放大器能够设计高效率D类音频放大器的同时最大限度地减少干扰周边电路..这也是可能的用低成本的铁氧体珠来实现这一..在这种情况下;它是必要的仔细选择铁素体在过滤器中使用..铁素体的选择的一个重要方面是在铁素体中使用的材料的类型珠..不是所有的铁素体材料是一样的;所以重要的是选择一个在10到100兆赫的材料是有效的范围是关键的D类放大器的操作..规范消费的许多规范电子产品的排放限制低至30兆赫..重要的是要使用的铁素体珠过滤器;以阻止辐射在30兆赫和以上的范围内;从扬声器电线和电源线;这是好的出现这些信号的天线..铁氧体的阻抗可以与一个小电容器一起使用在1000个范围内的值;以减少到一个可接受的水平的信号的频谱的范围..最好的性能;谐振频率的铁素体珠/电容滤波器应小于10兆赫..此外;重要的是;铁素体的珠是足够大;以维持其在峰值电流的阻抗对于放大器..一些铁氧体珠制造商在不同的电流水平指定珠阻抗..在这种情况下;它是可能的;以确保铁氧体珠保持足够量的阻抗在峰值电流放大器将看到..如果这些规格不可用;也可以估算出胎圈在低功耗和最大限度的滤波器输出的谐振频率测量的电流处理能力权力..在这种情况下;小于百分之五十的谐振频率的变化是可取的..实例铁氧体磁珠进行与tpa3130d2工作可以在tpa3130d2evm看到用户指南slou341..一种高质量的陶瓷电容器也需要的铁氧体珠过滤器..一个好的低ESR电容器温度和电压特性将工作最好..额外的EMC改进可以通过增加电路网络的每个D类输出得到地..一个简单的RC串联电路网络建议值将在330ΩPF系列1电容器虽然缓冲网络设计是具体到每一个应用和设计必须以考虑印刷电路板的寄生电抗;以及音频放大器..照顾评估应力对构件在缓冲网络特别是如果功放是运行在高氯化聚氯乙烯..也做确定缓冲网络布局紧凑;直接返回到IC的GND引脚..何时使用输出滤波器抑制电磁干扰tpa3116d2已经用一个简单的铁氧体磁珠滤波器的各种应用;包括久经考验的扬声器电线高达125厘米;高功率..的tpa3116d2 EVM通过FCC B类规格下这些条件用扭曲的喇叭线..的大小和类型的铁素体珠可以选择以满足应用需求..此外;如果必要的话;过滤器电容器可以增加一些对效率的影响..有可能是一些电路实例;有必要添加一个完整的液晶重建过滤器..这些如果有附近的电路;这是敏感的噪音可能会发生的情况..在这些情况下经典二阶Butterworth滤波器类似下图所示可以用..有些系统几乎没有电源去耦;从交流线路;但也受到线进行干涉LCI条例..这些措施包括：“墙疣”和“动力砖”的系统..例;LC重构滤波器可以是成本最低的方式通过LCI试验..共模扼流圈使用低频铁氧体材料也可有效防止线路传导干扰..避免电磁干扰减少在AM广播频段的干扰;这tpa3116d2拥有改变开关频率的能力经是<< 2:0 >引脚..推荐的频率是在表6上市..基频及其秒谐波在AM波段上市..这消除了由于切换而导致的音调频率的AM收音机解调..设备功能模式单模式PBTLtpa31xxd2家庭可以连接在单声道模式使输出功率100W..这是通过：连接装置和innl直接接地无电容这套装置在单声道模式中上电..连接outpr和outnr一起积极发言终端和outnl和outpl一起负脚..模拟输入信号的应用效果和innr..应用与实现注：in the following应用信息部分is not part of the TI组件规范和Ti does not权证及其精度金完备..ti' S customers areresponsible for测定的适宜性of components for their用途..客户应他们的设计实现与测试validate to confirm系统功能..8.1应用信息这部分有硕士学位和斯拉夫describes 2.1应用..大师是构型有立体声输出and the你是pbtl斯拉夫构型单输出..典型的应用..解决了2.1;U1 tpa3116d2硕士模式在400千赫;BTL增益20dB;如果不实施;权力的限制..U2 in 斯拉夫语、pbtl增益20db模式..输入是连通for差动输入..典型应用8.2.1设计要求8.2.2详细设计过程tpa31xxd2的家庭是一个非常灵活和易于使用的D类放大器；因此设计过程直截了当..在开始设计之前;收集以下有关音频系统的信息..PVCC铁路计划的设计扬声器或负载阻抗最大输出功率要求所需的脉宽调制频率选择PWM频率采用AM0设置PWM频率;AM1;AM2引脚..选择放大器的增益和主/从模式为了选择放大器增益设置;设计人员必须确定最大功率目标和扬声器阻抗..一旦这些参数已被确定;计算所需的输出电压摆幅提供最大输出功率..选择最低的模拟增益设置;对应于产生一个输出电压摆幅比所需的最大功率输出摆幅..模拟增益和主/从模式可以通过选择设置电压分压电阻R1和R2的增益/ SLV销..选择输入电容选择大容量电容器在PVCC输入适当的电压裕度和足够的容量来支持功率要求..在实践中;一个设计良好的电源;两个100μF轴;应将电容充足..一个电容应放置在设备两侧PVCC输入..PVCC电容器应该是一个低ESR的类型;因为他们被用在高速开关应用..选择去耦电容质量好的去耦电容需要在每个PVCC输入添加到提供良好的可靠性;良好的音频性能;并符合法规要求..X5R或更好的评级应采用应用..考虑温度;纹波电流和电压过冲;当选择去耦电容..同时;这些去耦电容应靠近PVCC和GND连接为设备为了减少串联电感..选择自举电容器每个输出需要启动电容器提供高侧FET的栅极驱动输出..为此设计;使用0.22μF;25-V X5R或更高质量的电容器应用曲线电源推荐为tpa3116d2电源要求由一个高电压功率输出扬声器放大器的阶段..几片上稳压器;包括在tpa3116d2生成音频路径的内部电路所需的电压..重要的是要注意的是;电压调节器已被集成的大小只提供必要的电源的内部电路的电流..这个外部引脚只提供作为一个连接点的芯片旁路电容器来过滤电源..连接外部电路;这些调节器输出可能会导致性能降低和损坏的装置..高压电源;在4.5 V和26 V;提供模拟电路内部和功率阶段PVCC..AVCC供应饲料内部LDO包括GVDD..该LDO输出连接外部引脚用于过滤的目的;但不应该连接到外部电路..GVDD LDO输出为内部函数提供当前所需的大小;但不提供外部负载..布局布局指南tpa3116d2可以用一个小的;廉价的铁氧体磁珠输出滤波器对于大多数应用程序..不过由于D类开关边缘快速;需要照顾的时候打印布局规划电路板..以下建议将有助于满足电磁兼容的要求..电容器的高频去耦电容应尽量靠近放置PVCC解耦尽可能计算机终端..大100μF或更大的散装的电源去耦电容应被放置在PVCC供应tpa3116d2..本地;高频旁路电容应靠近PVCC引脚尽可能..这些限制可以连接到集成电路直接接地垫一个极好的接地连接..考虑添加一个小的;质量好的低ESR陶瓷电容器之间100 pF和1核因子和一个更大的中间频率上限值在220个核因子和1μF之间也有良好的质在芯片两端PVCC连接..保持电流环从每一个输出;通过铁素体珠和小过滤器帽和回GND和紧尽可能小..电流环的大小决定了其作为天线的有效性..接地去耦电容应连接到GND PVCC..所有地面应连接集成电路的接地;应作为一个中央接地或星地面的tpa3116d2..输出滤波器的铁氧体电磁干扰滤波器见图35应放置在靠近输出端的可能对于最好的电磁干扰性能..该过滤器应放置在接近输出..用电容器铁氧体和液晶过滤器应接地..布局指南比如布局;看到tpa3116d2评价模块tpa3116d2evm用户指南slou336..两EVM用户手册和热垫的应用报道;SLMA002和slma004;可在钛在网站..布局实例散热器上使用的EVM热沉零件号ats-ti 10 op-521-c1-r1使用的EVM是一个14x25x50毫米铝型材散热片有三散热片见下图..在散热器的附加信息;去..这个大小的散热片已显示出足够的连续输出功率..音乐的顶峰因素气流将降低散热片大小的要求;可以使用较小的类型..11 器件和文档支持11.2 商标All trademarks are the property of their respective owners.11.3 静电放电警告ESD 可能会损坏该集成电路..德州仪器TI 建议通过适当的预防措施处理所有集成电路..如果不遵守正确的处理措施和安装程序;可能会损坏集成电路..ESD 的损坏小至导致微小的性能降级; 大至整个器件故障..精密的集成电路可能更容易受到损坏; 这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符..11.4 术语表SLYZ022 —TI 术语表..这份术语表列出并解释术语、首字母缩略词和定义..12 机械、封装和可订购信息以下页中包括机械、封装和可订购信息..这些信息是针对指定器件可提供的最新数据..这些数据会在无通知且不对本文档进行修订的情况下发生改变..欲获得该数据表的浏览器版本;请查阅左侧的导航栏..重要声明德州仪器TI 及其下属子公司有权根据JESD46 最新标准; 对所提供的产品和服务进行更正、修改、增强、改进或其它更改; 并有权根据JESD48 最新标准中止提供任何产品和服务..客户在下订单前应获取最新的相关信息; 并验证这些信息是否完整且是最新的..所有产品的销售都遵循在订单确认时所提供的TI 销售条款与条件..TI 保证其所销售的组件的性能符合产品销售时TI 半导体产品销售条件与条款的适用规范..仅在TI 保证的范围内;且TI 认为有必要时才会使用测试或其它质量控制技术..除非适用法律做出了硬性规定;否则没有必要对每种组件的所有参数进行测试..TI 对应用帮助或客户产品设计不承担任何义务..客户应对其使用TI 组件的产品和应用自行负责..为尽量减小与客户产品和应用相关的风险;客户应提供充分的设计与操作安全措施..TI 不对任何TI 专利权、版权、屏蔽作品权或其它与使用了TI 组件或服务的组合设备、机器或流程相关的TI 知识产权中授予的直接或隐含权限作出任何保证或解释..TI 所发布的与第三方产品或服务有关的信息;不能构成从TI 获得使用这些产品或服务的许可、授权、或认可..使用此类信息可能需要获得第三方的专利权或其它知识产权方面的许可;或是TI 的专利权或其它知识产权方面的许可..对于TI 的产品手册或数据表中TI 信息的重要部分;仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况下才允许进行复制..TI 对此类篡改过的文件不承担任何责任或义务..复制第三方的信息可能需要服从额外的限制条件..在转售TI 组件或服务时;如果对该组件或服务参数的陈述与TI 标明的参数相比存在差异或虚假成分;则会失去相关TI 组件或服务的所有明示或暗示授权;且这是不正当的、欺诈性商业行为..TI 对任何此类虚假陈述均不承担任何责任或义务..客户认可并同意;尽管任何应用相关信息或支持仍可能由TI 提供;但他们将独力负责满足与其产品及在其应用中使用TI 产品相关的所有法律、法规和安全相关要求..客户声明并同意;他们具备制定与实施安全措施所需的全部专业技术和知识;可预见故障的危险后果、监测故障及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施..客户将全额赔偿因在此类安全关键应用中使用任何TI 组件而对TI 及其代理造成的任何损失..在某些场合中;为了推进安全相关应用有可能对TI 组件进行特别的促销..TI 的目标是利用此类组件帮助客户设计和创立其特有的可满足适用的功能安全性标准和要求的终端产品解决方案..尽管如此;此类组件仍然服从这些条款.. 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TK3118设置说明

TK2118-3118调频率方法1，按住MONI键+DIAL键开机至显示SELF;2，按一下LOW显CH 1----1，转动频道旋钮"ENC"选择所需信道;3，按一下PTT键显xxx.xxx----2（接收频率）。

按一下LOW键清除频率，按一下LOW键恢复频率。

按住数字键"1"并转动频道旋钮"ENC"调整MHz大数，松开数字键"1"并转动频道旋钮"ENC"调小数。

4，按PTT显示OFF---3，发射亚音频。

按一下LOW显示q 67.0----3（模拟亚音），再按一下LOW显示d 023----3（数字亚音）。

5，按PTT键直到显示xxx.xxx----4（发射频率），按一下LOW键清除频率，按一下LOW 键恢复频率。

调整方法与调整接收频率相同。

按PTT键直到显示CH 2。

此时一信道已存好。

6，选择其他信道的设置，请重复以上的步骤。

按FUNC显示SELF，关机■TK3118调选呼方法写完频率，调至（可选信令），选择DTMF，调至于》》3符号，显示频道编辑---频道1。

选择第六项，XP不静音选择（载波+DTMF）点击确认。

点击编缉，选择DTMF（双音多频）（D），点击编缉，选择DTMF键制式或（12键或16键）点确认。

点解码，选择：DTMF信令。

选择呼叫中间代码#组代码关：选择（ABCD*#）呼叫报警常规或连续自动应答自动复位定时器（妙）ID代码输入自身码■TK3118调VOX方法1.开机;2.长按FUNC两秒至"F"闪烁;3.按"LOW"---VOX闪烁；4.旋钮选择等级，建议设置为1，不然延时过长。

KENWOOD TK-2118 编程方法按键：DIAL、FUNC、SCAN、LOW按下PTT+DIAL并打开电源，显示SELF。

按下LOW显示编程表1-12，按PTT或旋转CH按钮可更改编程内容。