通过米字型数码管显示至少四页的自定义英文和数字符号。(每页4(精)
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使用 VHDL 使米字型数码管显示至少四页的自定义英文和数字符号。
(每页 4个字符
相应程序:
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity zjf2 is
port( clk : in std_logic;
WX : out std_logic_vector (3 downto 0; DX : out std_logic_vector (15 downto 0; End entity zjf2;
Architecture mi of zjf2 is
Type state is(st0,st1,st2,st3;
Signal current_state:state :=st0;
Signal next_state:state;
Signal shu1 : integer range 0 to 3;
Signal shu2 : std_logic_vector(9 downto 0; Signal A,B,C,D:std_logic_vector(15 DOWNTO 0; Begin
process (clk is
Begin
If (clk'event and clk='1' then
shu2<=shu2+"0000000001";
If shu2="1111111111"then
current_state<=next_state;-- yeqiehuan
else
current_state<=current_state;
End if;
End if;
End process;
Process (current_state
Begin
Case current_state is
when
st0=>A<="0000111100000000";B<="00110000000110 10";
C<="1111111100000000";D<="0011000000000000";N EXT_STATE<=ST1;
when
st1=>A<="1101110110001000";B<="00110011100010 00";
C<="1100110000100001";D<="1110111010001000";N EXT_STATE<=ST2; when
st2=>A<="0011001110001000";B<="00110000000110 10";
C<="1111111100000000";D<="1111110010001000";N EXT_STATE<=ST3; when
st3=>A<="1100110000010010";B<="11000110001000 01";
C<="1100001110001000";D<="0000000110101001";N EXT_STATE<=ST0; End case;
End process;
Process (clk is
Begin
if rising_edge(clk then
if shu1>3 then
shu1<=0;
else
shu1<=shu1+1;
end if;
case shu1 is
WHEN 0 =>WX<="0111";DX<=A; WHEN 1 =>WX<="1011";DX<=B; WHEN 2 =>WX<="1101";DX<=C; WHEN 3 =>WX<="1110";DX<=D; End case;
End if;
End process;
End architecture mi;。