EBD11UD8ADFB-5中文资料

Mounted devices EDD5108ADTA-5B EDD5108ADTA-5B, -5C
Pin Configurations
Front side 1 pin 52 pin 53 pin 92 pin
93 pin Back side
144 pin 145 pin 184 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
DATA SHEET
1GB Unbuffered DDR SDRAM DIMM
EBD11UD8ADFB-5 (128M words × 64 bits, 2 Ranks)
Description
The EBD11UD8ADFB is 128M words × 64 bits, 2 ranks Double Data Rate (DDR) SDRAM unbuffered module, mounting 16 pieces of 512M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
• 184-pin socket type dual in line memory module (DIMM) PCB height: 31.75mm Lead pitch: 1.27mm • 2.6V power supply • Data rate: 400Mbps (max.) • 2.5 V (SSTL_2 compatible) I/O • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs and outputs are synchronized with DQS • 4 internal banks for concurrent operation (Component) • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Auto precharge option for each burst access • Programmable burst length: 2, 4, 8 • Programmable /CAS latency (CL): 3 • Programmable output driver strength: normal/weak • Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval • 2 variations of refresh Auto refresh Self refresh
Bank select address
Data Sheet E0403E30 (Ver. 3.0)
4
EBD11UD8ADFB-5
Serial PD Matrix
Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM ranks Module data width Module data width continuation Bit7 1 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 Bit5 Bit4 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 Bit3 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 Bit2 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 Bit1 Bit0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Hex value 80H 08H 07H 0DH 0BH 02H 40H 00H 04H 50H 70H 00H 82H 08H 00H 01H 0EH 04H 1CH 01H 02H 20H C0H 60H 70H 75H 75H 3CH 48H 28H 3CH 48H 28H 80H Comments 128 bytes 256 bytes DDR SDRAM 13 11 2 64 0 SSTL2 5.0ns*1 0.7ns*1 None. 7.6µs ×8 None. 1 CLK 2,4,8 4 2, 2.5, 3 0 1 Differential Clock VDD ± 0.2V 6.0ns*1 0.7ns*1 0.75ns*1 0.75ns*1 15ns 18ns 10ns 15ns 18ns 40ns 512M bytes
Data Sheet E0403E30 (Ver. 3.0)
3
EBD11UD8ADFB-5
Pin Description
Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 to CK2 /CK0 to /CK2 DQS0 to DQS7 DM0 to DM7/DQS9 to DQS16 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS VDDID NC Function Address input Row address Column address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground VDD identification flag No connection A0 to A12 A0 to A9, A11
2
EBD11UD8ADFB-5
Pin No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Pin name VDD DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 NC NC VDD Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Pin name CK2 VDD DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin No. 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin name A8 DQ23 VSS A6 DQ28 DQ29 VDD DM3/DQS12 A3 DQ30 VSS DQ31 NC NC VDD CK0 /CK0 Pin No. 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin name VDD DM6/DQS15 DQ54 DQ55 VDD NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDD SA0 SA1 SA2 VDDSPD