GS74108AX-10I中文资料
s710说明书
G781中文资料
±1°C Remote and Local Temperature Sensor with SMBus Serial InterfaceFeaturesTwo Channels: Measures Both Remote andLocal Temperatures No Calibration RequiredSMBus 2-Wire Serial InterfaceProgrammable Under/Overtemperature Alarms Supports SMBus Alert Response Accuracy:±1°C (+60°C to +100°C, remote) ±3°C (+60°C to + 100°C, local)320µA (typ) Average Supply Current During Conversion+3V to +5.5V Supply Range Small 8-Lead SO PackageApplications Desktop and Notebook Central Office Computers Telecom Equipment Smart Battery Packs Test and Measurement LAN Servers Multi-Chip Modules Industrial Controllers General DescriptionThe G781 is a precise digital thermometer that reports the temperature of both a remote sensor and its own package. The remote sensor is a diode-connected transistor typically a low-cost, easily mounted 2N3904 NPN type that replace conventional thermistors or thermocouples. Remote accuracy is ±1°C with no cali-bration needed. The remote channel can also meas-ure the die temperature of other ICs, such as micro-processors, that contain an on-chip, diode-connected transistor.The 2-wire serial interface accepts standard System Management Bus (SMBus) Write Byte, Read Byte, Send Byte, and Receive Byte commands to program the alarm thresholds and to read temperature data.The data format is 11bits plus sign, with each bit cor-responding to 0.125°C, in two’s-complement format. Measurements can be done automatically and autonomously, with the conversion rate programmed by the user or programmed to operate in a single-shot mode. The adjustable rate allows the user to control the supply current drain.The G781 is available in a small, 8-pin SOP sur-face-mount package.Ordering InformationPART* TEMP. RANGE PIN-PACKAGEG781-20°C to +120°C8-SOPPin ConfigurationTypical Operating Circuit3V TO 5.5VEACHCLOCK DATAINTERRUPT TO µCSMBDATA SMBCLK GNDG781ALERTAbsolute Maximum RatingsVCC to GND………….….……..………….-0.3V to +6V DXP to GND……….……………..…-0.3V to VCC + 0.3V DXN to GND……………..……………..-0.3V to +0.8V SMBCLK, SMBDATA,ALERT to GND..…-0.3V to +6V SMBDATA,ALERT Current………….-1mA to +50mA DXN Current……………………..………………….±1mA ESD Protection (SMBCLK, SMBDATA,ALERT , humanbody model).……………………………………….2000V ESD Protection (other pins, human body model)..2000V Continuous Power Dissipation (T A = +70°C) ..SOP (derate 8.30mW/°C above +70°C)…………......667mW Operating Temperature Range………-20°C to +120°C Junction Temperature………………….………..+150°C Storage temperature Range………….-65°C to +165°C Lead Temperature (soldering, 10sec)……..……...+300°CStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the opera-tional sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Electrical Characteristics(VCC = + 3.3V, T A = 0°C to +85°C, unless otherwise noted.)PARAMETER CONDITIONS MIN TYP MAX UNITST R = +60°C to +100°C, VCC = 3.0V to 3.6V-1+1Temperature Error, Remote Di-ode (Note 1)T R = 0°C to +125°C (Note 2)-3 +3 °CT A = +60°C to +100°C-3 +3Temperature Error, Local DiodeT A = 0°C to +85°C (Note 2)-5 +5°CSupply-Voltage Range3.0 5.5 V Undervoltage Lockout Threshold VCC input, disables A/D conversion, rising edge 2.8 V Undervoltage Lockout Hysteresis 50 mV Power-On Reset Threshold VCC, falling edge 1.7 V POR Threshold Hysteresis 50 mVSMBus static3Standby Supply Current Logic inputs forced to VCC or GND Hardware or softwarestandby, SMBCLK at 10kHz4 µA0.5 conv/sec 35Average Operating Supply CurrentAuto-convert mode. Logic inputs forced to VCC or GND 8.0 conv/sec 320 µAConversion Time From stop bit to conversion complete (both channels) 125 ms Conversion Rate Timing Conversion-Rate Control Byte=04h, 1Hz 1 sec High level176Remote-Diode Source CurrentDXP forced to 1.5VLow level11µAElectrical Characteristics (continued)(VCC = + 3.3V, T A = 0 to +85°C, unless otherwise noted.)Note 1: A remote diode is any diode-connected transistor from Table1. T R is the junction temperature of the remote of the remote diode. See Remote Diode Selection for remote diode forward voltage requirements.Note 2: Guaranteed by design but not 100% tested.Pin DescriptionDetailed DescriptionThe G781 is a temperature sensor designed to work in conjunction with an external microcontroller (µC) or other intelligence in thermostatic, process-control, or monitoring applications. The µC is typically a power- management or keyboard controller, generating SMBus serial commands by “bit-banging” general- purpose input-output (GPIO) pins or via a dedicated SMBus interface block.Essentially an serial analog-to digital converter (ADC) with a sophisticated front end, the G781 contains a switched current source, a multiplexer, an ADC, an SMBus interface, and associated control logic (Figure 1). Temperature data from the ADC is loaded into two data registers, where it is automatically compared with data previously stored in several over/under- tem-perature alarm registers.ADC and MultiplexerThe ADC is an averaging type that integrates over a 60ms period (each channel, typical), with excellent noise rejection.The multiplexer automatically steers bias currents through the remote and local diodes, measures their forward voltages, and computes their temperatures. Both channels are automatically converted once the conversion process has started, either in free-running or single-shot mode. If one of the two channels is not used, the device still performs both measurements, and the user can simply ignore the results of the un-used channel. If the remote diode channel is unused, tie DXP to DXN rather than leaving the pins open. The worst-case DXP-DXN differential input voltage range is 0.25V to 0.95V.Excess resistance in series with the remote diode causes about +0.6°C error per ohm. Likewise, 240µV of offset voltage forced on DXP-DXN causes about 1°C error.Figure 1. Functional DiagramSMBDATA SMBCLKA/D Conversion SequenceIf a Start command is written (or generated automati-cally in the free-running auto-convert mode), both channels are converted, and the results of both meas-urements are available after the end of conversion. A BUSY status bit in the status byte shows that the de-vice is actually performing a new conversion; however, even if the ADC is busy, the results of the previous conversion are always available.Remote Diode SelectionTemperature accuracy depends on having a good- quality, diode-connected small-signal transistor. The G781 can also directly measure the die temperature of CPUs and other integrated circuits having on-board temperature-sensing diodes.The transistor must be a small-signal type with a rela-tively high forward voltage; otherwise, the A/D input voltage range can be violated. The forward voltage must be greater than 0.25V at 10µA; check to ensure this is true at the highest expected temperature. The forward voltage must be less than 0.95V at 300µA; check to ensure this is true at the lowest expected temperature. Large power transistors don’t work at all. Also, ensure that the base resistance is less than 100Ω. Tight specifications for forward-current gain (+50 to +150, for example) indicate that the manufac-turer has good process controls and that the devices have consistent V be characteristics.Thermal Mass and Self-HeatingThermal mass can seriously degrade the G781’s ef-fective accuracy. The thermal time constant of the SOP- package is about 140 in still air. For the G781 junction temperature to settle to within +1°C after a sudden +100°C change requires about five time con-stants or 12 minutes. The use of smaller packages for remote sensors, such as SOT23s, improves the situa-tion. Take care to account for thermal gradients be-tween the heat source and the sensor, and ensure that stray air currents across the sensor package do not interfere with measurement accuracy. Self-heating does not significantly affect measurement accuracy. Remote-sensor self-heating due to the diode current source is negligible. For the local diode, the worst-case error occurs when auto-converting at the fastest rate and simultaneously sinking maximum current at the ALERT output. For example, at an 8Hz rate and with ALERT sinking 1mA, the typical power dissipation isVCC x 320µA plus 0.4V x 1mA. Package theta J-A is about 120°C /W, so with VCC = 3.3V and no copper PC board heat-sinking, the resulting temperature rise is:dT =1.45mW x 120°C /W =0.17°CEven with these contrived circumstances, it is difficultto introduce significant self-heating errors.Table 1. Remote-Sensor Transistor Manufacturers MANUFACTURER MODELNUMBER Philips PMBS3904Motorola(USA) MMBT3904 National Semiconductor (USA) MMBT3904Note:Transistors must be diode-connected (baseshorted to collector).ADC Noise FilteringThe ADC is an integrating type with inherently good noise rejection. Micropower operation places con-straints on high-frequency noise rejection; therefore, careful PC board layout and proper external noise fil-tering are required for high-accuracy remote meas-urements in electrically noisy environments.High-frequency EMI is best filtered at DXP and DXNwith an external 2200pF capacitor. This value can be increased to about 3300pF(max), including cable ca-pacitance. Higher capacitance than 3300pF introduces errors due to the rise time of the switched current source.Nearly all noise sources tested cause the ADC meas-urements to be higher than the actual temperature, typically by +1°C to 10°C, depending on the frequencyand amplitude.PC Board LayoutPlace the G781 as close as practical to the remote diode. In a noisy environment, such as a computer motherboard, this distance can be 4 in. to 8 in. (typical)or more as long as the worst noise sources (such as CRTs, clock generators, memory buses, and ISA/PCI buses) are avoided.Do not route the DXP-DXN lines next to the deflection coils of a CRT. Also, do not route the traces across a fast memory bus, which can easily introduce +30°C error, even with good filtering, Otherwise, most noise sources are fairly benign.Route the DXP and DXN traces in parallel and in close proximity to each other, away from any high-voltage traces such as +12V DC. Leakage currents from PC board contamination must be dealt with carefully, since a 10MΩ leakage path from DXP to ground causes about +1°C error.Connect guard traces to GND on either side of the DXP-DXN traces (Figure 2). With guard traces in place, routing near high-voltage traces is no longer an issue.Route through as few vias and crossunders as possible to minimize copper/solder thermocouple ef-fects.When introducing a thermocouple, make sure that both the DXP and the DXN paths have matching thermocouples. In general, PC board-induced ther-mocouples are not a serious problem, A copper-solder thermocouple exhibits 3µV/°C, and it takes about 240µV of voltage error at DXP-DXN to cause a +1°C measurement error. So, most parasitic thermocouple errors are swamped out.Use wide traces. Narrow ones are more inductive and tend to pick up radiated noise. The 10 mil widths and spacing recommended on Figure 2 aren’t absolutely necessary (as they offer only a minor improvement in leakage and noise), but try to use them where practi-cal.Keep in mind that copper can’t be used as an EMI shield, and only ferrous materials such as steel work will. Placing a copper ground plane between the DXP-DXN traces and traces carrying high-frequency noise signals does not help reduce EMI.PC Board Layout ChecklistPlace the G781 close to a remote diode.Keep traces away from high voltages (+12V bus).Keep traces away from fast data buses and CRTs. Use recommended trace widths and spacing.Place a ground plane under the tracesUse guard traces flanking DXP and DXN and con necting to GND.Place the noise filter and the 0.1µF VCC bypass capacitors close to the G781.Figure 2. Recommended DXP/DXN PC Traces Twisted Pair and Shielded CablesFor remote-sensor distances longer than 8 in., or in particularly noisy environments, a twisted pair is rec-ommended. Its practical length is 6 feet to 12feet (typi cal) before noise becomes a problem, as tested in a noisy electronics laboratory. For longer distances, the best solution is a shielded twisted pair like that used for audio microphones. Connect the twisted pair to DXP and DXN and the shield to GND, and leave the shield’s remote end unterminated.Excess capacitance at DX_limits practical remote sen-sor distances (see Typical Operating Characteristics), For very long cable runs, the cable’s parasitic capaci-tance often provides noise filtering, so the 2200pF ca-pacitor can often be removed or reduced in value. Ca-ble resistance also affects remote-sensor accuracy; 1Ωseries resistance introduces about + 0.6°C error.Low-Power Standby ModeStandby mode disables the ADC and reduces the supply-current drain to about 10µA. Enter standby mode by forcing high to the RUN/STOP bit in the con-figuration byte register. Software standby mode be-haves such that all data is retained in memory, and the SMB interface is alive and listening for reads and writes.Software standby mode is not a shutdown mode. With activity on the SMBus, extra supply current is drawn (see Typical Operating Characteristics). In software standby mode, the G781 can be forced to perform A/D conversions via the one-shot command, despite the RUN/STOP bit being high.10 MILSMINIMUM10 MILS10 MILSIf software standby command is received while a con-version is in progress, the conversion cycle is trun-cated, and the data from that conversion is not latched into either temperature reading register. The previous data is not changed and remains available.Supply-current drain during the 125ms conversion period is always about 320µA. Slowing down the con-version rate reduces the average supply current (see Typical Operating Characteristics). In between con-versions, the instantaneous supply current is about 25µA due to the current consumed by the conversion rate timer. In standby mode, supply current drops to about 3µA. At very low supply voltages (under the power-on-reset threshold), the supply current is higher due to the address pin bias currents. It can be as high as 100µA, depending on ADD0 and ADD1 settings. SMBus Digital InterfaceFrom a software perspective, the G781 appears as a set of byte-wide registers that contain temperature data, alarm threshold values, or control bits, A stan-dard SMBus 2-wire serial interface is used to read temperature data and write control bits and alarm threshold data.Each A/D channel within the device responds to the same SMBus slave address for normal reads and writes.The G781 employs four standard SMBus protocols: Write Byte, Read Byte, Send Byte, and Receive Byte (Figure 3). The shorter Receive Byte protocol allows quicker transfers, provided that the correct data regis-ter was previously selected by a Read Byte instruction. Use caution with the shorter protocols in multi-master systems, since a second master could overwrite the command byte without informing the first master.The temperature data format is 11bits plus sign in twos-complement form for remote channel, with each data bit representing 0.125°C (Table 2,Table 3), transmitted MSB first. Table 2. Temperature Data Format(Two’s-Complement)DIGITAL OUTPUTDATA BITSTEMP.(°C)SIGN MSB LSB EXT+127.875 0 111 1111 111+126.375 0 111 1110 011+25.5 0 001 1001 100+1.75 0 000 0001 110+0.5 0 000 0000 100+0.125 0 000 0000 001-0.125 1 111 1111 111-1.125 1 111 1110 111-25.5 1 110 0110 100-55.25 1 100 1000 110-65.000 1 011 1111 000Table 3. Extended Temperature Data FormatEXTENDEDRESOLUTIONDATA BITS0.000°C 000000000.125°C 001000000.250°C 010000000.375°C 011000000.500°C 100000000.625°C 101000000.750°C 110000000.875°C 11100000Slave AddressThe G781 appears to the SMBus as one device hav-ing a common address for both ADC channels. The G781 device address is set to 1001100.The G781 also responds to the SMBus Alert Re-sponse slave address (see the Alert Response Ad-dress section).One-Shot RegisterThe One-shot register is to initiate a single conversion and comparison cycle when the device is in standby mode and auto conversion mode. The write operation to this register causes one-shot conversion and the data written to it is irrelevant and is not stored.Serial Bus Interface ReinitializationWhen SMBCLK are held low for more than 30ms (typical) during an SMBus communication the G781 will reinitiateits bus interface and be ready for a new transmission. Alarm Threshold RegistersFour registers store alarm threshold data, with high-temperature (T HIGH) and low-temperature (T LOW) registers for each A/D channel. If either measured temperature equals or exceeds the corresponding alarm threshold value, an ALERT interrupt is as-serted.The power-on-reset (POR) state of both T HIGH registers is full scale (01010101, or +85°C). The POR state of both T LOW registers is 0°C.Diode Fault AlarmThere is a fault detector at DXP that detects whether the remote diode has an open-circuit condition. At the beginning of each conversion, the diode fault is checked, and the status byte is updated. This fault de-tector is a simple voltage detector. If DXP rises above VCC – 1V (typical) due to the diode current source, a fault is detected and the device alarms through pulling ALERT low while the remote temperature reading doesn’t update in this condition. Note that the diode fault isn’t checked until a conversion is initiated, so im-mediately after power-on reset the status byte indicates no fault is present, even if the diode path is broken.If the remote channel is shorted (DXP to DXN or DXP to GND), the ADC reads 1000 0000(-128°C) so as not to trip either the T HIGH or T LOW alarms at their POR settings. ALERT InterruptsThe ALERT interrupt output signal is latched and canonly be cleared by reading the Alert Response ad-dress. Interrupts are generated in response to T HIGHand T LOW comparisons and when the remote diode is disconnected (for fault detection). The interrupt doesnot halt automatic conversions; new temperature datacontinues to be available over the SMBus interfaceafter ALERT is asserted. The interrupt output pin isopen-drain so that devices can share a common in-terrupt line. The interrupt rate can never exceed theconversion rate.The interface responds to the SMBus Alert Responseaddress, an interrupt pointer return-address feature(see Alert Response Address section). Prior to takingcorrective action, always check to ensure that an in-terrupt is valid by reading the current temperature.Alert Response AddressThe SMBus Alert Response interrupt pointer providesquick fault identification for simple slave devices thatlack the complex, expensive logic needed to be a busmaster. Upon receiving an ALERT interrupt signal,the host master can broadcast a Receive Byte trans-mission to the Alert Response slave address (0001100). Then any slave device that generated an inter-rupt attempts to identify itself by putting its own ad-dress on the bus (Table 4).The Alert Response can activate several differentslave devices simultaneously, similar to the SMBusGeneral Call. If more than one slave attempts to re-spond, bus arbitration rules apply, and the device withthe lower address code wins. The losing device doesnot generate an acknowledge and continues to holdthe ALERT line low until serviced (implies that thehost interrupt input is level-sensitive). Successfulreading of the alert response address clears the inter-rupt latch.Table 4. Read Format for Alert Response Address(0001 100)BIT NAME7(MSB) ADD76 ADD65 ADD54 ADD43 ADD32 ADD21 ADD10(LSB) 1Command Byte FunctionsThe 8-bit command byte register (Table 5) is the mas-ter index that points to the various other registers within the G781. The register’s POR state is 0000 0000, so that a Receive Byte transmission (a protocol that lacks the command byte) that occurs immediately after POR returns the current local temperature data.The one-shot command immediately forces a new conversion cycle to begin. In software standby mode (RUN/STOP bit = high), a new conversion is begun, after which the device returns to standby mode. If a conversion is in progress when a one-shot command is received in auto-convert mode (RUN/STOP bit = low) between conversions, a new conversion begins, the conversion rate timer is reset, and the next auto-matic conversion takes place after a full delay elapses.Configuration Byte FunctionsThe configuration byte register (Table 6) is used to mask interrupts and to put the device in software standby mode. The other bits are empty. Status Byte FunctionsThe status byte register (Table 7) indicates which (if any) temperature thresholds have been exceeded. This byte also indicates whether or not the ADC is converting and whether there is an open circuit in the remote diode DXP-DXN path. After POR, the normal state of all the flag bits is zero, assuming none of the alarm conditions are present. The status byte is cleared by any successful read of the status, unless the fault persists. Note that the ALERT interrupt latch is not automatically cleared when the status flag bit is cleared.When reading the status byte, you must check for in-ternal bus collisions caused by asynchronous ADC timing, or else disable the ADC prior to reading the status byte (via the RUN/STOP bit in the configura-tion byte). In one-shot mode, read the status byte only after the conversion is complete, which is approxi-mately 125ms max after the one-shot conversion is commanded.Table 5. Command-Byte Bit Assignments*If the device is in standby mode at POR, both temperature registers read 0°C.Table 6. Configuration-Byte Bit AssignmentsTable 7. Status-Byte Bit Assignments*These flags stay high until cleared by POR, or until the status byte register is read.Table 8. Conversion-Rate Control ByteDATA CONVERSION RATE (Hz)00h 0.062501h 0.12502h 0.2503h 0.504h 105h 206h 407h 808h 16 09h to FFh RFUTo check for internal bus collisions, read the status byte. If the least significant seven bits are ones, dis-card the data and read the status byte again. The status bits LHIGH, LLOW, RHIGH, and RLOW are refreshed on the SMBus clock edge immediately fol-lowing the stop condition, so there is no danger of los-ing temperature-related status data as a result of an internal bus collision. The OPEN status bit (diode con-tinuity fault) is only refreshed at the beginning of a conversion, so OPEN data is lost. The ALERT inter-rupt latch is independent of the status byte register, so no false alerts are generated by an internal bus colli-sion. When auto-converting, if the THIGH and TLOW limits are close together, it’s possible for both high-temp and low-temp status bits to be set, depending on the amount of time between status read operations (espe-cially when converting at the fastest rate). In these circumstances, it’s best not to rely on the status bits to indicate reversals in long-term temperature changes and instead use a current temperature reading to es-tablish the trend direction.For bit 1 and bit 0, a high indicates a temperature alarm happened for remote and local diode respec-tively. THERM pin also asserts. These two bits wouldn’t be cleared when reading status byte.Conversion Rate ByteThe conversion rate register (Table 8) programs the time interval between conversions in free-running auto-convert mode. This variable rate control reduces the supply current in portable-equipment applications. The conversion rate byte’s POR state is 08h (16Hz). The G781 looks only at the 4 LSB bits of this register, so the upper 4 bits are “don’t care” bits, which should be set to zero. The conversion rate tolerance is ±25% at any rate setting.Valid A/D conversion results for both channels are available one total conversion time (125ms,typical) after initiating a conversion, whether conversion is initiated via the RUN/STOP bit, one-shot command, or initial power-up.POR AND UVLOThe G781 has a volatile memory. To prevent ambiguous power-supply conditions from corrupting the data in memory and causing erratic behavior, a POR voltage detector monitors VCC and clears the memory if VCC falls below 1.7V (typical, see Electrical Characteristics table). When power is first applied and VCC rises above 1.7V (typical), the logic blocks begin operating, although reads and writes at V CC levels below 3V are not recom-mended. A second VCC comparator, the ADC UVLO comparator, prevents the ADC from converting until there is sufficient headroom (VCC= 2.8V typical).ALERT Fault QueueTo suppress unwanted ALERT triggering the G781 em-bedded a fault queue function. The ALERT won’t as-sert until consecutive out of limit measurements have reached the queue number. The mapping of fault queue register (ALERTFQ, 22h) value to fault queue number is shown in the Table 9.Table 9. Alert Fault QueueALERTFQVALUEFAULT QUEUE NUMBER XXXX000X 1XXXX001X 2XXXX010X 3XXXX011X 3XXXX100X 4XXXX101X 4XXXX110X 4XXXX111X 4 Operation of The THERM FunctionA local and remote THERM limit can be programmed into the G781 to set the temperature limit above which the THERM pin asserts low and the bit 1, of status byte will be set to 1 corresponding to remote and local over temperature. These two bits won’t be cleared to 0 by reading status byte it the over temperature condi-tion remain. A hysteresis value is provided by writing the register 21h to set the temperature threshold to release the THERM pin alarm state, The releasing temperature is the value of register 19h, 20h minus the value in register 21h. The format of register 21h is 2’s complement. The THERM signal is open drain and requires a pull-up resistor to power supply.Figure 4. SMBus Write Timing DiagramA = start condition H = LSB of data clocked into slaveB = MSB of address clocked into slave I = slave pulls SMBDATA line lowC = LSB of address clocked into slave J = acknowledge clocked into masterD = R/W bit clocked into slave K = acknowledge clocked pulseE = slave pulls SMBDATA line low L = stop condition data executed by slaveF = acknowledge bit clocked into master M = new start conditionG = MSB of data clocked into slaveFigure 5. SMBus Read Timing DiagramA = start condition G = MSB of data clocked into masterB = MSB of address clocked into slave H = LSB of data clocked into masterC = LSB of address clocked into slave I = acknowledge clocked pulseD = R/W bit clocked into slave J = stop conditionE = slave pulls SMBDATA line low K= new start conditionF =acknowledge bit clocked into master。
ADF4107中文资料
PLL Frequency SynthesizerADF4107FEATURES7.0 GHz bandwidth2.7 V to3.3 V power supplySeparate charge pump supply (V P) allows extended tuning voltage in 3 V systemsProgrammable dual-modulus prescaler8/9, 16/17, 32/33, 64/65Programmable charge pump currentsProgrammable antibacklash pulsewidth3-wire serial interfaceAnalog and digital lock detectHardware and software power-down modeAPPLICATIONSBroadband wireless accessSatellite systemsInstrumentationWireless LANsBase stations for wireless radio GENERAL DESCRIPTIONThe ADF4107 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider(N = BP + A). In addition, the 14-bit reference counter(R counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.FUNCTIONAL BLOCK DIAGRAM CLKLEREF INRF IN ARF IN BFigure 1.Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2003 Analog Devices, Inc. All rights reserved.ADF4107TABLE OF CONTENTSADF4107—Specifications (3)Timing Characteristics (5)Absolute Maximum Ratings (5)Pin Configurations and Functional Descriptions (6)Typical Performance Characteristics (7)Functional Description (9)Reference Input Stage (9)RF Input Stage (9)Prescaler (P/P + 1) (9)A and B Counters (9)R Counter (9)Phase Frequency Detector and Charge Pump (10)MUXOUT and Lock Detect (10)Input Shift Register (10)Latch Summary (11)Reference Counter Latch Map (12)AB Counter Latch Map (13)Function Latch Map (14)Initialization Latch Map (15)Function Latch (16)Initialization Latch (17)Applications (18)Local Oscillator for LMDS Base Station Transmitter (18)Interfacing (19)PCB Design Guidelines for Chip Scale Package (19)Outline Dimensions (20)ESD Caution (20)Ordering Guide (20)REVISION HISTORYRevision 0: Initial VersionRev. 0 | Page 2 of 20ADF4107ADF4107—SPECIFICATIONSTable 1. (AV DD = DV DD = 3 V ± 10%, AV DD ≤ V P ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R SET = 5.1 kΩ, dBm referred to 50 Ω, T A = T MAX to T MIN , unless otherwise noted.)Parameter B Version 1B Chips 2 (Typ)Unit Test Conditions/Comments RF CHARACTERISTICS RF Input Frequency (RF IN )3 1.0/7.0 1.0/7.0 GHz min/max See Figure 18 for input circuit. RF Input Sensitivity –5/+5 –5/+5 dBm min/maxMaximum Allowable PrescalerOutput Frequency 4300 300 MHz max REFIN CHARACTERISTICS REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, use dc-coupled square wave (0 to V DD ). REFIN Input Sensitivity 5 0.8/V DD 0.8/V DD V p-p min/max AC-coupled; when dc-coupled, 0 to V DD , max (CMOScompatible).REFIN Input Capacitance 10 10 pF max REFIN Input Current ±100 ±100 µA max PHASE DETECTOR Phase Detector Frequency 6 104 104 MHz max CHARGE PUMP Programmable; see Figure 25. I CP Sink/Source High Value 5 5 mA typ With R SET = 5.1 kΩ Low Value 625 625 µA typ Absolute Accuracy 2.5 2.5 % typ With R SET = 5.1 kΩ R SET Range 3.0/11 3.0/11 kΩ typ See Figure 25. I CP Three-State Leakage 1 1 nA typSink and Source CurrentMatching 2 2 % typ 0.5 V ≤ V CP ≤ V P – 0.5 V I CP vs. V CP 1.5 1.5 % typ 0.5 V ≤ V CP ≤ V P – 0.5 V I CP vs. Temperature 2 2 % typ V CP = V P /2 LOGIC INPUTS V IH , Input High Voltage 1.4 1.4 V min V IL , Input Low Voltage 0.6 0.6 V max I INH , I INL , Input Current ±1 ±1 µA max C IN , Input Capacitance 10 10 pF max LOGIC OUTPUTS V OH , Output High Voltage 1.4 1.4 V min Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V. V OH , Output High Voltage V DD – 0.4 V DD – 0.4 V min CMOS output chosen. I OH 100 100 µA max V OL , Output Low Voltage 0.4 0.4 V max I OL = 500 µA POWER SUPPLIES AV DD 2.7/3.3 2.7/3.3 V min/V max DV DD AV DD AV DD V P AV DD /5.5 AV DD /5.5 V min/V max AV DD ≤ V P ≤5.5V I DD 7(AI DD + DI DD ) 17 15 mA max 15 mA typ I P 0.4 0.4 mA max T A = 25°CPower-Down Mode 8(AI DD + DI DD ) 10 10 µA typRev. 0 | Page 3 of 20ADF4107Rev. 0 | Page 4 of 20Parameter B Version 1B Chips 2 (Typ)Unit Test Conditions/Comments NOISE CHARACTERISTICS ADF4107 Phase Noise Floor 9 –174 –174 dBc/Hz typ @ 25 kHz PFD Frequency –166 –166 dBc/Hz typ @ 200 kHz PFD Frequency –159 –159 dBc/Hz typ @ 1 MHz PFD FrequencyPhase Noise Performance 10@ VCO Output900 MHz Output 11–93 –93 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD Frequency 6400 MHz Output 12 –76 –76 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD Frequency6400 MHz Output 13–83 –83 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD Frequency Spurious Signals900 MHz Output 11–90/–92 –90/–92 dBc typ @ 200 kHz/400kHz and 200 kHz PFD Frequency 6400 MHz Output 12 –65/–70 –65/–70 dBc typ @ 200 kHz/400kHz and 200 kHz PFD Frequency6400 MHz Output 13–70/–75 –70/–75 dBc typ @ 1 MHz/2MHz and 1 MHz PFD Frequency1Operating temperature range (B Version) is –40°C to +85°C. 2The B Chip specifications are given as typical values. 3Use a square wave for lower frequencies, below the minimum stated. 4This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 5AV DD = DV DD = 3 V. 6Guaranteed by design. Sample tested to ensure compliance. 7T A = 25°C; AV DD = DV DD = 3 V; P = 32; RF IN = 7.0 GHz. 8T A = 25°C; AV DD = DV DD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RF IN = 7.0 GHz. 9The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 10The phase noise is measured with the EVAL-ADF4107EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f REFOUT = 10 MHz @ 0 dBm). 11f REFIN = 10 MHz; f PFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 12f REFIN = 10 MHz; f PFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 6400 MHz; N = 32000; Loop B/W = 20 kHz. 13f REFIN = 10 MHz; f PFD = 1 MHz; Offset Frequency = 1 kHz; f RF = 6400 MHz; N = 6400; Loop B/W = 100 kHz.ADF4107TIMING CHARACTERISTICSTable 2. (AV DD = DV DD = 3 V ± 10%, AV DD ≤ V P ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R SET = 5.1 kΩ, dBm referred to 50 Ω, T A = T MAX to T MIN , unless otherwise noted.) 1Parameter Limit 2 (B Version) Unit Test Conditions/Comments t 1 10 ns min DATA to CLOCK Setup Time t 2 10 ns min DATA to CLOCK Hold Time t 3 25 ns min CLOCK High Duration t 4 25 ns min CLOCK Low Duration t 5 10 ns min CLOCK to LE Setup Time t 6 20ns minLE Pulsewidth1Guaranteed by design but not production tested.2Operating temperature range (B Version) is –40°C to +85°C.CLOCKDATALELEFigure 2. Timing DiagramABSOLUTE MAXIMUM RATINGSTable 3. (T A = 25°C, unless otherwise noted.)Parameter Rating AV DD to GND 1 –0.3 V to +3.6 V AV DD to DV DD –0.3 V to +0.3 V V P to GND –0.3 V to +5.8 V V P to AV DD –0.3 V to +5.8 V Digital I/O Voltage to GND –0.3 V to V DD + 0.3 V Analog I/O Voltage to GND –0.3 V to V P + 0.3 V REFIN, RF IN A, RF IN B to GND –0.3 V to V DD + 0.3 VOperating Temperature RangeIndustrial (B Version) –40°C to +85°CStorage Temperature Range –65°C to +125°CMaximum Junction Temperature 150°CTSSOP θJA Thermal Impedance 150.4°C/W CSP θJA Thermal Impedance 122°C/W Lead Temperature, SolderingVapor Phase (60 sec) 215°CInfrared (15 sec) 220°CTransistor CountCMOS 6425 Bipolar 303Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV , and it is ESD sensitive. Proper precautions should be taken for handling and assembly.1GND = AGND = DGND = 0 V.Rev. 0 | Page 5 of 20ADF4107Rev. 0 | Page 6 of 20PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONSR CP CPGND MUXOUTLEDATACLK CE DGNDRF IN RF IN A AV REF V P DV DD TSSOPFigure 3. ADF4107 TSSOP (Top View)15 MUXOUT 14LE 13 DATA 12 CLK CPGND 1AGND 2AGND 320 C P 11 CE6 7 8D G N D 9D G N D 104519181716RF IN B RF IN A R S E T V P D V D D D V D DA V D D A V D D R E F I N CSP(Chip Scale Package)Figure 4. ADF4107 Chip Scale PackageTable 4. Pin Functional DescriptionsADF4107TYPICAL PERFORMANCE CHARACTERISTICSFigure 5. Parameter Data for the RF InputRF INPUT FREQUENCY – GHzR F I N P U T P O W E R – d B mFigure 6. Input Sensitivity–60–10–50–70–90–30–40–80–20FREQUENCYO U T P U T P O W E R – d BFigure 7. Phase Noise (900 MHz, 200 kHz, 20 kHz) FREQUENCY OFFSET FROM 900MHz CARRIERP H A S E N O I S E – d B c /H zFigure 8. Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz)O U T P U T P O W E R – d BFREQUENCYFigure 9. Reference Spurs (900 MHz, 200 kHz, 20 kHz)–60–10–50–70–90–30–40–80–20–100O U T P U T P O W E R – d BFigure 10. Phase Noise (6.4 GHz, 1 MHz, 100 kHz)Rev. 0 | Page 7 of 20ADF4107–40–50–60–70–80–90–100–110–120–130–140FREQUENCY OFFSET FROM 6400MHz CARRIERP H A S E N O I S E – d B c /H zFigure 11. Integrated Phase Noise (6.4 GHz, 1 MHz, 100 kHz) 0–60–10–50–70–90–30–40–80–20–100O U T P U T P O W E R – d BFREQUENCYFigure 12. Reference Spurs (6.4 GHz, 1 MHz, 100 kHz) TEMPERATURE –oCP H A S E N O I S E – d B c /H zFigure 13. Phase Noise (6.4 GHz, 1 MHz, 100 kHz) vs. TemperatureTUNING VOLTAGE – VF I R S T R E F E R E N C E S P U R – d B c–105Figure 14. Reference Spurs vs. V TUNE (6.4 GHz, 1 MHz, 100 kHz)–120–130–18010k100M100k 1M 10M –140–150–160–170PHASE DETECTOR FREQUENCY – HzP H A S E N O I S E – d B c /H zV DD = 3V V P = 5VFigure 15. Phase Noise (referred to CP output) vs. PFD FrequencyV CP – VI C P – m AFigure 16. Charge Pump Output CharacteristicsRev. 0 | Page 8 of 20ADF4107Rev. 0 | Page 9 of 20FUNCTIONAL DESCRIPTIONReference Input StageThe Reference Input stage is shown in Figure 17. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REF IN pin on power-down.POWER-DOWNFigure 17. Reference Input StageRF Input StageThe RF input stage is shown in Figure 18. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler.RF IN RF INFigure 18. RF Input StagePrescaler (P/P + 1)The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is based on asynchronous 4/5 core. A minimum divide ratio is possible for fully contiguous output frequencies. This minimum isdetermined by P , the prescaler value, and is given by: (P 2 – P).A andB CountersThe A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with an RF input frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid.Pulse Swallow FunctionThe A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is as follows: ()[]Rf A B P f REFINVCO ×+×= f VCO Output frequency of external voltage controlledoscillator (VCO).P Preset modulus of dual-modulus prescaler (8/9, 16/17, etc.).B Preset divide ratio of binary 13-bit counter (3 to 8191).APreset divide ratio of binary 6-bit swallow counter (0 to 63).f REFIN External reference frequency oscillator.FROM RF INPUT STAGEFigure 19. A and B CountersR CounterThe 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.ADF4107Phase Frequency Detector and Charge PumpThe phase frequency detector (PFD) takes inputs from the R counter and N counter (N = BP + A) and produces an outputproportional to the phase and frequency difference between them. Figure 20 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch, ABP2 and ABP1, control the width of the pulse. See Figure 23.CPV PFigure 20. PFD Simplified Schematic and Timing (in Lock) MUXOUT and Lock DetectThe output multiplexer on the ADF4107 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 25 shows the full truth table. Figure 21 shows the MUXOUT section in block diagram form.Lock DetectMUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect.Digital lock detect is active high. When the lock detect precision (LDP) bit in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector (PD) cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It will stay set high until a phase error of greater than25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, this output will be high with narrow, low-going pulses.DVANALOG LOCK DETECTDIGITAL LOCK DETECTR COUNTER OUTPUTN COUNTER OUTPUTSDOUTFigure 21. MUXOUT CircuitInput Shift RegisterThe ADF4107 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 19-bit N counter, comprising a 6-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in the timing diagram of Figure 2. The truth table for these bits is shown in Table 5. Figure 22 shows a summary of how the latches are programmed.Table 5. C2, C1 Truth TableControl BitsC2 C1Data Latch0 0 RCounter0 1 N Counter (A and B)1 0 Function Latch (Including Prescaler)1 1 nitializationLatchRev. 0 | Page 10 of 20Latch SummaryREFERENCE COUNTER LATCHINITIALIZATION LATCHFigure 22. Latch SummaryReference Counter Latch MapXFigure 23. Reference Counter Latch MapAB Counter Latch MapFigure 24. AB Counter Latch MapFunction Latch MapFigure 25. Function Latch MapInitialization Latch MapFigure 26. Initialization Latch Mapi iFunction LatchThe on-chip function latch is programmed with C2 and C1 set to 1 and 0, respectively. Figure 25 shows the input data format for programming the function latch.Counter ResetDB2 (F1) is the counter reset bit. When this bit is 1, the R counter and the AB counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit needs to be disabled (set to 0). Then, the N counter resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle).Power-DownDB3 (PD1) and DB21 (PD2) provide programmable power-down modes. They are enabled by the CE pin.When the CE pin is low, the device is immediately disabled regardless of the states of PD2 and PD1.In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into the PD1 bit, with the condition that PD2 has been loaded with a 0.In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into PD1 (on condition that a 1 has also been loaded toPD2), then the device will go into power-down on the occurrence of the next charge pump event.When a power-down is activated (either synchronous or asynchronous mode, including CE pin activated power-down), the following events occur:• All active dc current paths are removed.• The R, N, and timeout counters are forced to their load state conditions.• The charge pump is forced into three-state mode.• The digital lock detect circuitry is reset.• The RF IN input is debiased.• The reference input buffer circuitry is disabled.• The input register remains active and capable of loading and latching data.MUXOUT ControlThe on-chip multiplexer is controlled by M3, M2, M1 on the ADF4107. Figure 25 shows the truth table.Fastlock Enable B tDB9 of the function latch is the fastlock enable bit. Fastlock is enabled only when this bit is 1. Fastlock Mode BitDB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, then Fastlock Mode 1 is selected; and if the fastlock mode bit is 1, then Fastlock Mode 2 is selected.Fastlock Mode 1The charge pump current is switched to the contents of Current Setting 2.The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch. Fastlock Mode 2The charge pump current is switched to the contents of Current Setting 2.The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4–TC1, the CP gain bit in the AB counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Figure 25 for the timeout periods.T mer Counter ControlThe user has the option of programming two charge pump currents. The intent is that Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed).The normal sequence of events is as follows:The user initially decides what the preferred charge pump currents are going to be. For example, the choice may be 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2.At the same time it must be decided how long the secondary current is to stay active before reverting to the primary current. This is controlled by the timer counter control bits, DB14–DB11 (TC4–TC1) in the function latch. The truth table is given in Figure 25.Now, to program a new output frequency, the user simply programs the AB counter latch with new values for A and B. At the same time, the CP gain bit can be set to 1, which sets the charge pump with the value in CPI6–CPI4 for a period of time determined by TC4–TC1. When this time is up, the charge pump current reverts to the value set by CPI3–CPI1. At the same time the CP gain bit in the AB counter latch is reset to 0 and is now ready for the next time that the user wishes to change the frequency.Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the fastlock mode bit (DB10) in the function latch to 1.Charge Pump CurrentsCPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Figure 25. Prescaler ValueP2 and P1 in the function latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 MHz. Thus, with an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid.PD PolarityThis bit sets the phase detector polarity bit. See Figure 25.CP Three-StateThis bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled.Initialization LatchThe initialization latch is programmed when C2 and C1 are set to 1 and 1. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0).However, when the initialization latch is programmed an additional internal reset pulse is applied to the R and AB counters. This pulse ensures that the AB counter is at load point when the AB counter data is latched and the device will begin counting in close phase alignment.If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes.When the first AB counter data is latched after initialization, the internal reset pulse is again activated. However, successive AB counter loads after this will not trigger the internal reset pulse. Device Programming after Initial Power-UpAfter initially powering up the device, there are three ways to program the device. Initialization Latch MethodApply V DD.Program the initialization latch (11 in two LSBs of input word). Make sure that the F1 bit is programmed to 0.Next, do a function latch load (10 in two LSBs of the control word), making sure that the F1 bit is programmed to a 0. Then do an R load (00 in two LSBs).Then do an AB load (01 in two LSBs).When the Initialization Latch is loaded, the following occurs:1. The function latch contents are loaded.2. An internal pulse resets the R, AB, and timeout counters toload-state conditions and also three-states the chargepump. Note that the prescaler band gap reference and theoscillator input buffer are unaffected by the internal resetpulse, allowing close phase alignment when countingresumes.3. Latching the first AB counter data after the initializationword will activate the same internal reset pulse. Successive AB loads will not trigger the internal reset pulse unlessthere is another initialization.CE Pin MethodApply V DD.Bring CE low to put the device into power-down. This is an asychronous power-down in that it happens immediately. Program the function latch (10).Program the R counter latch (00).Program the AB counter latch (01).Bring CE high to take the device out of power-down. The R and AB counters will now resume counting in close alignment. Note that after CE goes high, a duration of 1 µs may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state.CE can be used to power the device up and down in order to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after V DD was initially applied.Counter Reset MethodApply V DD.Do a Function Latch Load (10 in two LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset.Do an R counter load (00 in two LSBs).Do an AB counter load (01 in two LSBs).Do a Function latch load (10 in two LSBs). As part of this,load 0 to the F1 bit. This disables the counter reset.This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down.APPLICATIONSLocal Oscillator for LMDS Base Station TransmitterFigure 27 below shows the ADF4107 being used with a VCO to produce the LO for an LMDS base station.The reference input signal is applied to the circuit at FREF IN and, in this case, is terminated in 50 Ω. A typical base station system would have either a TCXO or an OCXO driving the reference input without any 50 Ω termination.To have a channel spacing of 1 MHz at the output, the 10 MHz reference input must be divided by 10, using the on-chip reference divider of the ADF4107.The charge pump output of the ADF4107 (Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45°.Other PLL system specifications are: K D = 5.0 mA K V = 80 MHz/VLoop Bandwidth = 70 kHz F PFD = 1 MHz N = 6300Extra Reference Spur Attenuation = 10 dBAll of these specifications are needed and used to derive the loop filter component values shown in Figure 27.Figure 27 gives a typical phase noise performance of−83 dBc/Hz at 1 kHz offset from the carrier. Spurs are better than −70 dBc.The loop filter output drives the VCO, which, in turn, is fed back to the RF input of the PLL synthesizer and also drives the RF output terminal. A T-circuit configuration provides 50 Ω matching between the VCO output, the RF output, and the RF IN terminal of the synthesizer.In a PLL system, it is important to know when the system is in lock. In Figure 27, this is accomplished by using the MUXOUT signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer. One of these is the LD or lock detect signal.FREF V DDV PΩΩOUTFigure 27. 6.3 GHz Local Oscillator Using the ADF4107。
【工贝电子】GS700智能双模供水一体机说明书
【工贝电子】GS700智能双模供水一体机说明书
GS700智能双模供水一体机产品特点说明：
1、控制灵活：无负压变频供水模式、水箱恒压变频供水模式，双模式，一机合成。
可实现1－4台水泵的自动控制，全面满足各种复杂的供水系统。
2、界面美观：采用7英寸彩色触摸屏显示。
参数设定、运行状态一目了然，操作简单、显示美观大方、提升设备档次。
3、功能齐全：集成了人机界面触摸屏、PLC、模拟量模块、控制程序为一体。
省却了触摸屏组态与PLC编程，节约成本、提高性能、缩短安装调试时间。
4、完美性能：自适应PID控制算法，恒压控制更稳定。
一键远程启停、远程485启停两种远程控制方式任意选择。
5、安全可靠：模拟、数字信号全部采用光电隔离，抗干扰能力强；整体控制器采用DC24V人体安全电压设计。
6、简单易用：高度简单方便丰富而完美的中文提示。
使一般的操作人员无需经过复杂的培训，也能对各项操作应用自如。
7、维护方便：独有的系统故障检测、使工程人员能清楚地了解故障所在，帮助维修人员检查故障发生的部位和原因。
8、自动切泵：自动休眠唤醒、水泵定时轮换，延长水泵寿命，实现节能功能。
9、分时控制：全自动、多时段、带星期选择启停水泵，更适应学校、政府企业等办公场景。
10、保护全面：具有上限压力保护、无负压欠压保护、水箱低液位和缺水保护，启用保护自动停泵，故障消除自动启动水泵。
AC781x 数据手册说明书
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AC781x 数据手册适用于以下产品：型号 子型号环境温度AC7811xxxx AC7811QBGE, AC7811OBGE, AC7811MBGE,AC7811QBFE, AC7811OBFE, AC7811MBFE, AC7811JBFE, AC7811QJGE, AC7811OJGE, AC7811MJGE, AC7811OJFE, AC7811MJFE, AC7811JJFE-40~125°CAC7813xxxx AC7813QBGE, AC7813OBGE, AC7813MBGE, AC7813OBFE, AC7813MBFE, AC7813JBFE -40~85°C AC7815xxxx AC7815QBGE, AC7815OBGE, AC7815MBGE, AC7815QBFE, AC7815OBFE, AC7815MBFE, AC7815JBFE-40~85°C修订记录文档目录修订记录 (2)文档目录 (3)1主要特性 (5)2器件标识 (6)2.1说明 (6)2.2格式 (6)2.3字段 (6)2.4示例 (6)3参数分类 (7)4额定值 (8)4.1热学操作额定值 (8)4.2湿度操作额定值 (8)4.3ESD 操作额定值 (8)4.4电压和电流操作额定值 (9)5通用 (10)5.1静态电气规格 (10)5.1.1电源和地引脚 (10)5.1.2DC 特性 (10)5.1.3电源电流特性 (13)5.2动态规格 (14)5.2.1控制时序 (14)5.2.2PWM模块时序 (15)5.3热规格 (16)5.3.1热特性 (16)6外设工作要求和行为 (18)6.1内核模块 (18)6.1.1SWD 电气规格 (18)6.2外部振荡器 (OSC) 和 ICS 特性 (18)6.2.1外部振荡器(OSC) 特性 (18)6.2.2内部RC 特性 (19)6.2.3PLL 特性 (19)6.3片内Flash 规格 (20)6.4模拟 (21)6.4.1ADC 特性 (21)6.4.2模拟比较器（ACMP）电气规格 (22)6.5通信接口 (22)6.5.1SPI 开关规格 (22)6.5.2CAN特性 (25)7尺寸 (26)7.1LQFP64封装信息 (26)7.2LQFP80封装信息 (28)8引脚分配 (30)8.1信号多路复用和引脚分配 (30)8.2器件引脚分配 (34)1主要特性∙操作特性电压范围：2.7 到5.5 V温度范围 (环境)： -40 到125°C∙性能高达100 MHz的 ARM® Cortex-M3内核单周期 32位 x 32位乘法器快速I/O访问接口∙存储器和存储器接口最高256 KB的片内Flash最高 64 KB的静态随机存储器∙时钟振荡器 (Oscillator) –支持4 MHz到 30 MHz 石英晶体振荡器；可选择低功耗或高增益振荡器内部时钟源 (ICS) –内部PLL ，集成内部或外部基准时钟源， 8 MHz预校准内部基准时钟源，可用于100 MHz系统时钟内部32 kHz低功耗振荡器 (LPO)∙系统外设电源管理模块(PMC) 有三个功率模式：运行、待机和停止低压检测复位电路 (LVD)带独立时钟源的看门狗(WDOG)可编程循环冗余校验(CRC)模块串行线调试(SWD) & JTAG 接口Cortex®-M3 嵌入式跟踪宏单元™SRAM 位处理映射区域 (BIT-BAND) 1个12 通道 DMA ∙人机接口68 个通用输入输出接口 (GPIO)外部中断 (IRQ)模块∙模拟模块1个多达 16通道、12位的SAR ADC，工作在停止模式，可选硬件触发器 (ADC)2个包含6位DAC和可编程参考输入的模拟比较器(ACMP)∙定时器1个6通道脉宽调制（PWM）单元3个双通道 PWM1个8通道周期性中断定时器(TIMER)1个脉宽定时器 (PWDT)1个实时时钟 (RTC)∙通信接口2个 SPI 模块6个 UART模块（其中一路兼容Software LIN）2个I2C 模块2个CAN 模块1个硬件 LIN 模块∙封装选项80引脚 LQFP64引脚LQFP2器件标识2.1说明芯片器件型号包含可识别具体器件的字段。
联想旭日410系列笔记本电脑说明书
联想旭日410系列笔记本电脑说明书一、产品介绍1.1 外观设计联想旭日410系列笔记本电脑以简约时尚的外观设计融入了高科技元素，给用户带来全新的视觉享受。
机身采用精选金属材质，银色拉丝工艺使其更具质感，同时也提供了出色的整体耐久性。
1.2 配置参数该系列笔记本电脑搭载了强大的配置，为用户提供卓越的性能和流畅的使用体验。
处理器选用英特尔酷睿 i5 四核处理器，主频高达2.5 GHz，同时拥有8GB 内存和256GB SSD硬盘，充分满足用户在办公、娱乐和学习中对于速度和容量的需求。
1.3 显示效果联想旭日410系列笔记本电脑配备了一块15.6英寸全高清显示屏，分辨率达到1920x1080，色彩饱满且清晰度极佳。
用户可以尽情享受高清影片、游戏和图片的细腻画质，带来身临其境的视觉体验。
1.4 操作系统与软件支持该系列笔记本电脑搭载了最新版本的Windows操作系统，为用户提供更流畅、更安全的操作环境。
同时，联想还提供了一系列实用软件，如办公软件套件、多媒体播放器等，以满足不同用户的各种需求。
二、使用说明2.1 开机与关闭在使用联想旭日410系列笔记本电脑之前，请确认电源适配器已连接电源，并检查电池是否已安装。
长按电源键开启电脑，系统将自动启动；点击开始菜单，选择关机，系统将执行关机操作。
在电脑开启或关闭过程中，请不要强制断电，以免损坏数据或硬件。
2.2 连接外部设备联想旭日410系列笔记本电脑支持多种外部设备的连接，请依据以下步骤进行操作：- 鼠标：将鼠标的USB接口插入电脑的USB接口，系统将自动识别并安装鼠标驱动。
- 打印机：连接好打印机和电脑，并确保打印机已开机。
在系统设置中添加打印机，完成驱动安装后即可正常使用。
- 外接显示器：通过HDMI接口或VGA接口将外接显示器连接至电脑，然后按下Win+P组合键，选择所需的显示模式。
2.3 无线网络连接联想旭日410系列笔记本电脑支持Wi-Fi连接，用户可以根据以下步骤连接到无线网络：- 打开无线网络开关，确保Wi-Fi功能处于启用状态。
飞龙 wi
持续电流(散热良好)瞬间电流（散热良好）BEC尺寸(供参考)重量(供参考)20A 30A 40A 60A 30A 40A 55A 80A 锂电池型号79g 35g 36g 76g 49x23.5x13.5mm 65.5x34x21mm● 反推功能，支持飞行过程中切换电机正反向，达到减速目的（WinDragon wifi 80-130A 支持此功能）。
2-4S 2-4S 2-6S 2-6S 8.4V/7.4V/6V/5V ,5A 80A 100A 119g 2-6S 100A 120A 125g 2-6S 130A150A130g82.5x39.5x23.5mm2-6S航模无刷电子调速器WinDragon wifi 130AWinDragon wifi 100A WinDragon wifi 80A WinDragon wifi 60A WinDragon wifi 30A WinDragon wifi 40A WinDragon wifi 20A 8.4V/7.4V/6V/5V ,5A 8.4V/7.4V/6V/5V ,5A 8.4V/7.4V/6V/5V,5A8.4V/7.4V/6V/5V ,5A 82.5x39.5x23.5mm 82.5x39.5x23.5mm 65.5x34x21mm 49x23.5x13.5mm 02 产品规格04 操作说明1.正常工作模式2.油门行程设定3.通过遥控器进行参数编程设定推荐使用Flycolor Wi-Fi Trans 通过Flycolor App 进行参数编程设定。
另外可通过编程卡进行参数编程设定1. 刹车: [1] 无刹车 [2]软刹车 [3]重刹车 [4]很重刹车 (出厂默认值为无刹车)2.电池类型： [1]LiPo(锂电) [2] NiCb/NiMh(镍氢/镍隔) （默认值为Li Po ）3.低压保护阈值：低/中/高 [1] 2.8V [2]3.0V [3]3.2V ；默认值为中（3.0V）对于Ni-xx电池组：低/中/高中止电压是电池组初始电压值的50%/65%/75%对于Li-xx电池组：可自动计算电池数量，除了确定电池 类型外无需用户设置。
GS10中文说明书(1)
开机 .......................................................................................................................................................................... 5 关机 .......................................................................................................................................................................... 5 调零 .......................................................................................................................................................................... 5 标定 .......................................................................................................................................................................... 6 充电 .......................................................................................................................................................................... 6
三菱调试手册
目录一：E60，M64的联接 (2)1：E60-NC联接 (2)2：基本I/O联接 (3)3：M64S-NC (6)4：伺服系统的联接 (8)5：E60,M60系列系统联接总图 (9)二：外围线路的检查及上电注意事项 (11)三：参数的设定 (11)1：基本参数的设定 (11)2：轴参数的设定 (13)3：原点复归参数 (13)4：伺服参数的设定 (14)5：主轴参数的设定 (16)6：机械误差 (17)7：PLC (17)8：巨程式，位置开关详见操作手册 (18)四．PLC程序的输入 (18)1：PLC4B格式PLC传输 (18)2：GPPW格式PLC程序输入 (19)3：PLC系统部分运行测试 (20)五：资料备份及恢复 (21)1：RS-232C传输方式 (21)2：资料备份卡存储方式 (22)六：附录 (23)1：伺服参数标准设定表（未列明的系列请参照手册） (23)2：主轴参数（未列明的请参照手册） (24)3：SVJ2伺服参数的优化 (26)4：模具加工经验参数及高速高精度的使用 (28)5：三菱相关软件 (29)一：E60，M64的联接1：E60-NC 联接（1）E60-NC （FCU6-MU071）接口图：CRTLCDNCKB（2）控制单元联接系统图（3）*紧急停止按钮的配线：三菱E60及64系列以后的紧急停止的配线与以往系统的配线有本质区别，现在急停端口内部为有源输出，如果外部贸然接入电源，有可能造成短路而烧毁NC。
望用户引起注意。
例：2：基本I/O联接(1)HR341/HR351端口图：CF31/CF32/CF33/CF34插头DI：CF31/CF32注1：漏/源改变联接，请给COM提供以下电压漏：DC24V源：0V注2：I/O口的电源与基本I/O的DCIN回路不同，请单独加载直流电源。
DO：CF33/CF34注1：±10V模拟电压输出，与基本I/O单元AO端口功能相同。
GSN系列运动控制器用户手册说明书
GSN系列运动控制器用户手册R1.12019.03版权申明固高科技有限公司 保留所有权力固高科技有限公司（以下简称固高科技）保留在不事先通知的情况下，修改本手册中的产品和产品规格等文件的权力。
固高科技不承担由于使用本手册或本产品不当，所造成直接的、间接的、特殊的、附带的或相应产生的损失或责任。
固高科技具有本产品及其软件的专利权、版权和其它知识产权。
未经授权，不得直接或者间接地复制、制造、加工、使用本产品及其相关部分。
运动中的机器有危险！使用者有责任在机器中设计有效的出错处理和安全保护机制，固高科技没有义务或责任对由此造成的附带的或相应产生的损失负责。
联系我们固高科技（深圳）有限公司地 址：深圳市高新技术产业园南区深港产学研基地西座二楼W211室电 话：************* 26737236 26970824 传 真：*************电子邮件：********************** 网 址：固高科技（香港）有限公司地 址：香港九龍觀塘偉業街108號絲寶國際大廈10樓1008-09室電 話：+(852) 2358-1033 傳 真：+(852) 2719-8399 電子郵件：******************* 網 址：臺灣固高科技股份有限公司地 址：台中室西屯區台中港路三段97號7樓之3 電 話：+886-4-23588245 傳 真：+886-4-23586495電子郵件：***********************文档版本前言感谢选用固高运动控制器为回报客户，我们将以品质一流的运动控制器、完善的售后服务、高效的技术支持，帮助您建立自己的控制系统。
固高产品的更多信息固高科技的网址是。
在我们的网页上可以得到更多关于公司和产品的信息，包括：公司简介、产品介绍、技术支持、产品最新发布等等。
您也可以通过电话（0755－26970817）咨询关于公司和产品的更多信息。
技术支持和售后服务您可以通过以下途径获得我们的技术支持和售后服务：电子邮件：**********************；电话：0755－26970843发函至：深圳市高新技术产业园南区园深港产学研基地西座二楼W211室固高科技（深圳）有限公司邮编：518057用户手册的用途用户通过阅读本手册，能够了解GSN系列运动控制器的基本结构，正确安装运动控制器，连接控制器与电机控制系统，完成运动控制系统的基本调试。
潮流网络 GXW4104 4108 网关常见问题与解答说明书
深圳市潮流网络技术有限公司GXW4104/4108网关白皮书深圳市潮流网络技术有限公司目录1安装常见问题 (1)1.1网关的电源规格 (1)1.2如何连线启动设备 (1)1.3如何查询网关IP (2)2实际应用常见问题 (2)2.1如何实现与SIP Server对接（中继对等） (2)2.2出现UNKNOW或者UNDETECT的来显问题，如何解决 (7)2.3出现打进来的话机挂机后，网关侧话机还没有挂断的现象，如何解决72.4指定端口出局 (8)3功能应用 (9)3.1如何登陆Web页面 (9)3.2WEB GUI配置 (9)3.2.1如何查看状态页面 (9)3.2.2如何使用多条PSTN线自动检测功能 (11)3.2.3如何使用一条PSTN线自动检测功能 (14)3.2.4如何设置网关的IP (15)3.2.5如何设置日期时间 (18)3.2.6如何实现注册 (20)3.2.7如何设置网关的入局 (21)3.2.8如何实现与SIP Server对接（账号注册） (22)3.2.9如何实现升级固件 (23)3.2.10如何设置传真功能 (25)3.2.11如何实现配置文件升级 (26)3.2.12如何抓取系统日志 (28)i3.2.13如何抓包 (29)3.2.14如何恢复出厂 (30)更多支持 (30)11安装常见问题1.1网关的电源规格●GXW4104/4108标配电源规格：12V/0.5A 。
1.2如何连线启动设备●GXW4104/4108（以GXW4108为例）S1：用以太网线一端连接GXW410X 的WAN 口，一端连接上行网络如交换机，路由器。
S2：接入电源，网关启动后，对应的接口LED 灯会亮，如电源接口，网络接口。
S3：连接PSTN 线到FXO 口。
（GXW4104具有4个FXO 口，GXW4108具有8个FXO口。
）1.3如何查询网关IPIP Query---IP查询工具适用于静态IP和动态IP的查询。
USR-G781 4G公专网工业路由器系列规格书说明书
产品说明USR-G781是一款集4G路由器和4G DTU功能为一体的无线传输设备，集成了4G LTE、串口、以太网端口（1LAN和1WAN/LAN）和VPN等技术。
为设备提供先进的互联网连接和高速数据访问。
G781提供RS485和RS232接口。
这意味着串口设备，如电表、传感器、可编程控制器以及Modbus RTU设备可以通过G781直接连接到互联网。
该产品系列支持公网三大运营商2/3/4G全覆盖以及1.4/1.8G专网版本，可为油田、公安、交通等明确使用专网行业提供专网下的安全数据传输。
它帮助企业客户实现高效的大规模网络部署和管理，非常适合M2M和工业物联网应用。
如智能快递柜、充电桩、换电柜、车载设备联网、环保设备定位、智慧停车场、城市安防监控、智慧工地、智慧交通、塔楼监控、城市能耗监控、环境监测、气象监测、智能抄表、污染源监测、大气环境监测、温室远程控制、水产养殖监测、电力、水利、环保等。
USR-G781规格书产品特点⏹稳定可靠●全工业设计，金属外壳，防护等级IP30；●支持水平桌面放置、挂壁式安装方式；●宽电压DC9-36V输入，具备电源反向保护；●静电、浪涌、电快速脉冲群等多重防护；●基于高性能ARM9处理器，嵌入式Linux系统；●内置硬件看门狗，故障自检测、自修复，确保系统稳定。
⏹组网灵活●提供4G网络，向下兼容3G/2G网络制式；●支持1.4G/1.8G专网版本；●支持自动检网、4G/3G/2G制式切换、支持APN/VPDN专网卡；●支持有线/4G多网同时在线、多网智能切换备份功能.⏹功能强大●接口丰富：包括1*WAN/LAN、1*LAN、1*RS485、1*RS232等；●支持有人云服务，方便设备系统集中化管理，提高运维效率；●支持发送注册包、心跳包功能；●支持串口透传、Modbus互转、HTTPD协议；●支持多种种VPN(PPTP、L2TP、OpenVPN、IPSec、GRE、SSTP)和多重VPN加密功能；●支持远程管理平台服务，具备远程监控和远程升级功能；●WAN口支持PPPoE、静态IP、DHCP Client多种接入方式；●支持防火墙，NAT、DMZ、端口转发等；●支持花生壳服务，易于客户实现内网穿透功能；●支持AT指令：串口、网络、AT指令配置查看设备信息；●选配GPS 功能、可接入有人云、客户私有化服务器。
CHC CGI-410厘米级组合导航系统说明书
CHC®CGI-410厘米级组合导航系统1目录前言 (4)说明书简介 (4)修订说明 (4)手册约定 (4)免责声明 (5)技术与服务 (5)安全信息 (5)1产品介绍 (6)1.1简介 (6)1.2产品特点 (6)1.3产品参数表 (7)1.4数据协议 (9)1.4.1GPCHC数据协议 (9)1.4.2CAN数据协议 (11)1.4.3外接轮速协议 (18)1.5用户接口 (18)1.5.1前面板接口 (19)1.5.2后面板 (19)1.5.3正面 (20)1.6配件 (21)1.6.1配置清单 (21)1.6.2数据线接口定义 (22)1.6.3辅助硬件设备 (24)1.6.4辅助软件 (24)1.7环境注意事项 (25)1.7.1温度范围 (25)1.7.2湿度 (25)1.8安装说明 (25)1.8.1车辆安装 (25)1.8.2主机安装 (26)1.8.3SIM卡安装 (27)1.8.4机构尺寸 (28)2网页界面介绍 (29)2.1接收机状态界面： (30)2.2卫星界面 (31)2.3接收机配置界面 (33)2.4数据记录 (36)22.5IO设置 (37)2.6网络设置 (37)2.7模块设置 (38)2.8固件 (38)2.9惯导 (40)2.10惯导-选择配置 (41)3简易操作说明 (45)3.1设置差分数据 (45)3.2惯导设置 (46)3.3设备初始化 (49)3.4数据输出 (50)3.5里程计配置 (51)3.6com口命令配置 (54)4固件升级 (57)5设备常见问题分析 (58)3前言说明书简介欢迎使用CGI-410产品使用说明书。
本说明书主要是以CGI-410接收机为例，对如何安装、设置和使用该系列产品进行描述。
修订说明修订日期修订编次修订说明2020年03月Ⅰ产品使用说明书手册约定示例描述【文件】→【退出】点击“文件”菜单后再点击下级菜单“退出”点名称阴影内容表示对话框、窗口中的输入区域或标签确定按下或点击标有确定的按钮或按键提示有助于系统、设备维护和设置的补充信息。
SIMATIC PCS 7 CPU 410-5H 处理自动化中心单元数据表说明书
Yes Yes; all data No
370 µA; Valid up to 40°C 2.1 mA Dealt with in the module data manual with the secondary conditions and the factors of influence No
CPU-blocks DB ● Number, max. ● Size, max. FB ● Number, max. ● Size, max. FC ● Number, max. ● Size, max. OB ● Number, max.
32 Mbyte 16 Mbyte 16 Mbyte No
16 kbyte 16 kbyte 16 kbyte 16 kbyte 244 byte Yes
15
131 072; max. 131 072; max. 131 072; max. 131 072; max. 131 072
8 192; max. 8 192; max. 8 192; max. 8 192; max. 8 192
24 2
2 048
Yes
0 999
Yes SFB Unlimited (limited only by RAM capacity)
2 048
Yes
10 ms 9 990 s
Yes SFB Unlimited (limited only by RAM capacity)
Total working and load memory (with backup battery)
● Feeding of external backup voltage to CPU
GS10手持机
内置扬声器和麦克风；支持蓝牙无线耳机
重量
0.74kg（不含电池）
接口
SD卡插槽/CF卡插槽/USB接口
通讯连接
Lemo (USB和串口)、USB、7针接口、电源
内置无线连接
5个Bluetooth，无线局域网，内置2.4 GHz FHSS全站仪遥控电台及天线
接收机和天线
通道
14
支持卫星系统
GPS, GLONASS
其他软件
osoft Windows Media? Player，照相软件，在线帮助
电源管理
工作时间
10小时
电池型号
GEB212可拆卸充电锂电池
环境指标
操作温度
-30 ~＋60℃
存储温度
-40 ~＋80℃
防水防尘
IP67
防潮
软件
系统软件
Viva全功能版系统软件
应用程序
标配程序包括测量、放样、定义坐标系、COGO计算、定线工具包、DXF输入输出、测图通、道路通、电力通、管线通、台站通、GPS测量计算器、面积测量、平均点测量、坐标输入输出
参考线、参考面、道路测设、铁路测设、DTM放样、横断面测量、体积计算、LandXML输入等
外接天线
AS05单频天线
定位和原始数据记录采样率
5Hz
初始化时间（典型）
冷启动120秒，热启动35秒
RTK数据格式
Leica, Leica 4G, RTCM 2.x, RTCM 3.0, CMR, CMR+
RTK精度
SBAS<1.2m，DGPS典型<0.4m (rms)
后处理精度
基线模式L1相位：10mm + 2ppm (rms)，基线模式L1编码：<0.4m (rms)
GS 系列(SHINKO)
功能设定：
1．按住[FUNCTION]不放直到显示[Func]时松开按键,进入功能设定菜单,首选项是[1.b.G.1].
2．按[FUNCTION]进入下一功能,按[ZERO/TARE]改变功能参数内容.
3．按[SET]存储功能参数并回到秤重状态.
功能
功能指令及数值
说明
横杠显示
0 . GLP
0★关闭GLP打印1源自开启GLP打印输出控制
7. 1. o.c
0
停止输出
1
所有时间连续数据输出
2
仅在稳定时连续数据输出
3
按下[MEMORY]键时输出
4
仅在稳定时输出一个数据(不包括零位)
5
仅在稳定时输出一个数据(包括零位)
6
稳定时输出一个数所据,不稳定连续输出
7★
按下[MEMORY]键输出一个数据(稳定时)
3.零位校正完成后,显示会出现[on FS],此时表示满量程校正准备就绪.加放校准砝码于秤盘中心,显示屏开始闪烁,满量程校准开始进行.
4.当校正完成后,显示屏回到正常秤重状态,.
5.GS-W型号内置砝码,校正时只须将砝码升降旋钮逆时针方向旋转即表示内置砝码放下,顺时针方向表示内置砝码升高.
6.校正错误信息:
01★
G克
14★
Ct克拉
15
Oz盎司
16
Lb英磅
17
Ozt金衡盎司
18
Dwt英钱
19
Grain英厘
1A
Tl hong kong香港两
1B
Tl singrapore,malaysia新加坡两
1C
Tl taiwan台湾两
1D
中国重汽豪沃07款08款09款A7款10款参数对照表
拉式、推式、Φ430C
拉式、推式、Φ430C
高地板驾驶室：包括加长驾驶室和 高顶驾驶室。
无标准驾驶室
加长驾驶室：10款驾驶室比09款驾 驶室提升改进部分，有EGR驾驶室和 低地板驾驶室：包括标准驾驶室、 共轨驾驶室，改进型前面罩，导风罩 加长驾驶室、高顶驾驶室。 、带上车踏板保险杆，保险杆支架， 前大灯、后视镜、牵引车驾驶室抬高 114.5毫米。
高顶驾驶室（79／ 79R）双卧铺。可前后调 节普通座椅、固定式方向 盘、筒式减震器后悬架
铝制中冷器
发动机附 件 变速箱 操作装置 制动 转向 传动
加粗圆形空滤器 铝制方形燃油箱 杆式挂挡装置 鼓刹 鼓刹（窄体）
加强拉式、Φ420 、Φ430 标准驾驶室：08款 驾驶室比07款驾驶 室提升改进部分，, 新款座椅：可上下 、前后调节、带靠 背腰部气囊,方向盘 可以前后调节，四 点悬浮式悬架＋减 震装置及驾驶室横 向稳定装置 加长驾驶室：比07 款驾驶室提升改进 部分，新款座椅， 可上下、前后调节 、背靠带腰部气囊, 方向盘上下可以调 节，四点悬浮式悬 架＋减震装置及驾 驶室横向稳定装置 。 高顶驾驶室：比07 款驾驶室提升改进 部分，新款座椅， 带靠背腰部气囊， 方向盘上下、左右 可以调节，四点悬 浮式悬架＋减震装 置及驾驶室横向稳 定装置。08款翼子 板，保险杠。 铝制中冷器 双管螺旋加粗圆形 空滤器 不锈钢D形燃油箱 与07款通用
重汽变速箱：工程车：HW18709 HW13710 、、HW19710
重汽变速箱：工程车：HW18709 HW13710 、、HW19710
重汽变速箱：公路用车： HW18709HW13710、 HW14710、HW18710、 HW19710
重汽变速箱：公路用车： HW18709HW13710、HW14710 、HW18710、HW19710
MSI 10th Gen Intel Core i7 系列游戏台式机说明书
© 2023 Micro-Star Int'l Co.Ltd. MSI is a registered trademark of Micro-Star Int'l Co.Ltd. All rights reserved.Intel, the Intel logo, the Intel Inside logo and Intel Core are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. SPECIFICATIONSSOWindows 10 HomeWindows 10 ProFREE Upgrade to Windows 11*CPU Up to 10th Gen Intel® Core™ i7-10700 processorsChipset Intel® H410Memória 2 x DDR4 2666MHz SO-DIMM, up to 64GBVGA Up to MSI GeForce® RTX 2060 8GB GDDR6Sem fio Intel® WiFi6 AX200Armazenamento1 x M.2 2280 SSD (SATA/PCIe Combo)1 x 2.5" Driver Bay1 x 3.5" Driver BayBluetooth 5.1LAN (RJ45)Intel I219-VSistema de refrigeração Air CoolerE/S (Traseiros)1 x HDMI™ out (1.4)4 x USB 3.2 Gen 1 Type A1 x S/PDIF1 x RJ452 x USB 2.0 Type A5 x Audio jacks*Tips: The display function is only available onnon F series processors.Audio7.1 Channel HD Audio (ALC1220)E/S1 x USB 2.0 Type A1 x USB 2.0 Type C1 x Mic-in1 x Headphone-outFonte de alimentação350W 80 Plus Bronze Certified PSU450W 80 Plus Bronze Certified PSUTamanho10L / 21.13ptDimensões128 x 348 x 244 mm5.03 x 13.70 x 9.61 inchPeso6.4kg /7.4kg14.11 lbs / 16.31 lbsAcessórios1 x Manual (optional)1 x Quick guide1 x Warranty card1 x Power cordSoftwareDragon CenterBurnRecoveryMSI Remind ManagerNorton SymSilentNorton Internet Security (60-day Trial)several separated chambers for component cooling.Easy to upgradeEasy to access and upgrade components to keep the system upto date with the latest hardware.Vertical graphics designVertical placed graphics card to prevent bending of the card ordamage to the PCIe slot during transport.Mystic LightMake your build look on fire or cold as ice. You are in control.Customize colors and effects with RGB LED.Compact sizeThe same performance as a big gaming rig but in a powerfulsmall sized chassis so you can take it anywhere.CONNECTIONS1. 1 x USB2.0 Tyoe C3. 1 x Headset out / Mic in5. 2 x USB 3.2 Gen 1 Type A7. 1 x HDMI™2. 1 x USB 2.0 Type A4. 5 x Audio jacks / 1x S/PDIF6. 2 x USB 3.2 Gen 1 Type A / 1 xRJ458. 2 x USB 2.0 Type AGenerated223-3-31,checkforthelatestversionwww.msi.com/datasheet.Theinformationprovidedinthisdocumentisintendedforinformationalpurposesonlyandissubjecttochangewithoutnotice.。
超同步调试手册
0：运转+方向 I0：运转信号 I1：方向信号
1：正传/反转 I0：正传信号 I1：反转信号
0:双极性（-10V— —+10V）
1:单极性（0 —— +10V）
0：电机内置编码 器
1：主轴编码器 此值设错会导致
准停无法完成 0：逆时针为正传 1：顺时针为正传 0：正方向旋转准 停 1：反方向旋转准 停 0：方向加脉冲 1：正交脉冲 0：脉冲跟随模式 1：脉冲同步模式
5
零速伺服
I3
6
准停
I2
7
主轴摆动
I6
8
主轴运转使能
I0
9
运动方向
I1
10
铰孔/电子换挡
I7
8
三、 基本参数
参数类型
功能码
初始化参数
A01
A02
基本控制参数
A03 Bn01
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GS74108ATP/J/X512K x 84Mb Asynchronous SRAM8, 10, 12 ns 3.3 V V DDCenter V DD and V SSSOJ, TSOP, FP-BGA Commercial Temp Industrial Temp Features• Fast access time: 8, 10, 12 ns• CMOS low power operation: 120/95/85 mA at minimum cycle time• Single 3.3 V power supply• All inputs and outputs are TTL-compatible • Fully static operation• Industrial Temperature Option: –40° to 85°C • Package line upJ: 400 mil, 36-pin SOJ packageGJ:RoHS-compliant 400 mil, 36-pin SOJ package TP: 400 mil, 44-pin TSOP-II packageGP:RoHS-compliant 400 mil, 44-pin TSOP-II package X: 6 mm x 10 mm FPBGA packageGX: RoHS-compliant 6 mm x 10 mm FPBGA package • RoHS-compliant packages availableDescriptionThe GS74108A is a high speed CMOS Static RAM organized as 524,288 words by 8 bits. Static design eliminates the need for external clocks or timing strobes. The GS74108A operates on a single 3.3 V power supply and all inputs and outputs are TTL-compatible. The GS74108A is available in 400 mil SOJ, 400 mil TSOP-II, and 6 mm x 10 mm FPBGA packages.Pin DescriptionsSymbolDescriptionA 0–A 18Address input DQ 1–DQ 8Data input/output CE Chip enable input WE Write enable input OE Output enable input V +3.3 V power supplyV Ground NCNo connect3635343332313029282726252423222112345678910111213141516A 4A 3A 2A 1A 0CE DQ 1DQ 2V DD V SS DQ 3DQ 4WE A 17A 16A 15NC A 5A 6A 7A 8OE DQ 8DQ 7V SS V DD DQ 6DQ 5A 9A 10A 11A 1236-pin 400 mil SOJ1718A 14A 132019NCA 18SOJ 512K x 8-Pin Configuration123456A NC OE A 2A 6A 7NCB DQ 1NC A 1A 5CE DQ 8C DQ 2NC A 0A 4NC DQ 7D V SS NC A 18A 3NC V DDE V DD NC A 17A 9NC V SSF DQ 3NC A 13A 10NC DQ 6G DQ 4NC A 14A 11WE DQ 5HNCA 16A 15A 12A 8NCFP-BGA 512K x 8 Bump Configuration (Package X)6 mm x 10 mmDD SS *All GSI Technology packages are at least 5/6 RoHS compliant.Packages listed with the additional “G” designator are 6/6 RoHS compliant.424140393837363534333231302928273456789101112131415161718A 4A 3A 2A 1A 0CE DQ 1DQ 2V DD V SS DQ 3DQ 4WE NC A 5A 6A 7A 8OE DQ 8DQ 7V SS V DD DQ 6DQ 5A 10A 11A 12A 1844-pin 400 mil TSOP II19202625NC 2122NC NC2423NC NC12NC NC 4443NC NC A 9A 13A 17A 16A 15A 14GS74108ATP/J/XTSOP-II 512K x 8-Pin ConfigurationMemory ArrayRow DecoderColumn DecoderAddress Input BufferControlI/O BufferA 0CE WE OEDQ 1A 18DQ 8Block Diagra mTruth TableCEOEWEDQ 1 to DQ 8V DD CurrentH X X Not Selected ISB 1, ISB 2L L H Read I DDL X L Write L HHHigh ZGS74108ATP/J/XNote:X: “H” or “L”Absolute Maximum RatingsParameterSymbolRatingUnitSupply Voltage V DD –0.5 to +4.6V Input Voltage V IN –0.5 to V DD +0.5(≤ 4.6 V max.)V Output Voltage V OUT –0.5 to V DD +0.5(≤ 4.6 V max.)V Allowable power dissipation PD 0.7WStorage temperatureT STG–55 to 150oCNote:Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.Recommended Operating ConditionsParameterSymbolMinTypMaxUnitSupply Voltage for -8/-10/-12V DD 3.0 3.3 3.6V Input High Voltage V IH 2.0—V DD +0.3V Input Low Voltage V IL –0.3—0.8VAmbient Temperature, Commercial Range T Ac 0—70oC Ambient Temperature,Industrial RangeT A I–40—85oCNotes:1.Input overshoot voltage should be less than V DD +2 V and not exceed 20 ns.2.Input undershoot voltage should be greater than –2 V and not exceed 20 ns.CapacitanceParameterSymbolTest ConditionMaxUnitInput Capacitance C V = 0 V 5pF Output CapacitanceC V = 0 V7pFGS74108ATP/J/XNotes:1.Tested at T A = 25°C, f = 1 MHz2.These parameters are sampled and are not 100% tested.DC I/O Pin CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current I IL V IN = 0 to V DD – 1 uA 1 uA Output LeakageCurrent I LO Output High Z V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH I = –4 mA 2.4—Output Low VoltageV OLI = +4 mA—0.4 VPower Supply CurrentsParameterSymbolTest Conditions 0 to 70°C–40 to 85°C 8 ns10 ns12 ns8 ns10 ns12 nsOperating Supply CurrentI CE ≤ V All other inputs ≥ V or ≤ V Min. cycle time I = 0 mA 120 mA 95 mA 85 mA 130 mA 105 mA 95 mAStandby CurrentI CE ≥ V All other inputs ≥ V or ≤V Min. cycle time 30 mA 25 mA 22 mA 40 mA 35 mA 32 mAStandby CurrentI CE ≥ V - 0.2V All other inputs ≥ V - 0.2V or ≤ 0.2V10 mA 20 mAIN IN OUTOUT OH LO DD IL IH IL OUT SB1IH IH IL SB2DD DDDQVT = 1.4 V50Ω30pF1DQ3.3 VOutput Load 1Output Load 2589Ω434Ω5pF 1Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Output load 2 for t LZ , t HZ , t OLZ and t OHZParameterConditionsInput high level V IH = 2.4 V Input low level V IL = 0.4 V Input rise time tr = 1 V/ns Input fall time tf = 1 V/ns Input reference level 1.4 V Output reference level1.4 V Output loadFig. 1& 2GS74108ATP/J/XAC Test ConditionsAC Characteristics Read CycleParameter Symbol -8-10-12Unit Min Max Min Max Min Max Read cycle time t 8—10—12—ns Address access time t —8—10—12ns Chip enable access time (CE)t —8—10—12ns Output enable to output valid (OE)t — 3.5—4—5ns Output hold from address change t 3—3—3—ns Chip enable to output in low Z (CE)t *3—3—3—ns Output enable to output in low Z (OE)t *0—0—0—ns Chip disable to output in High Z (CE)t *—4—5—6ns Output disable to output in High Z (OE)t *—3.5—4—5ns* These parameters are sampled and are not 100% tested.RC AA AC OE OH LZ OLZ HZ OHZt AAt OHtRCAddressData OutPrevious DataData validGS74108ATP/J/XRead Cycle 1: CE = OE = V IL , WE = V IHt AAt RCAddresst ACt LZt OEt OLZCEOEData Outt HZt OHZD ATA VALIDHigh impedanceRead Cycle 2: WE = V IHWrite CycleParameter Symbol -8-10-12Unit Min Max Min Max Min Max Write cycle time tWC 8—10—12—ns Address valid to end of write tAW 5.5—7—8—ns Chip enable to end of writetCW 5.5—7—8—ns Data set up time tDW 4—5—6—ns Data hold time tDH 0—0—0—ns Write pulse width tWP 5.5—7—8—ns Address set up time tAS 0—0—0—ns Write recovery time (WE)tWR 0—0—0—ns Write recovery time (CE)tWR10—0—0—ns Output Low Z from end of write tWLZ *3—3—3—ns Write to output in High ZtWHZ *—3.5—4—5nsGS74108ATP/J/X* These parameters are sampled and are not 100% tested.t WCAddressCEWEData InOEData Outt AWt CWt ASt WPt WRt DWt DHt WLZt WHZD ATA VALIDH IGH IMPEDANCEWrite Cycle 1: WE controltWCAddressCEWEData InOEData Outt AWt WPt ASt CWt WR1t DWt DHD ATA VALIDH IGH IMPEDANCEGS74108ATP/J/XWrite Cycle 2: CE control1eB1DA 1A 2yE H EQcL G EDetail AAB ANotes:1. Dimension D& E do not include interlead flash.2. Dimension B1 does not include dambar protrusion/intrusion.Symbol Dimension in inchDimension in mm min nom max min nom max A ——0.146—— 3.70A10.026——0.66——A20.1050.1100.115 2.67 2.80 2.92B 0.0130.0170.0210.330.430.53B10.0240.0280.0320.610.710.81c 0.0060.0080.0120.150.200.30D 0.9200.9240.92923.3723.4723.60E 0.3950.4000.40510.0410.1610.28e—0.05—— 1.27—H E 0.4300.4350.44010.9311.0511.17G E 0.3540.3660.3789.009.309.60L 0.082—— 2.08——y ——0.004——0.10Q0o—10o0o—10o36-Pin SOJ, 400 milD1222344eBQAA 1A 2ycDetail AEH ELL 1ANotes:1.Dimension D& E do not include interlead flash.2.Dimension B does not include dambar protrusion/intrusion.3.Controlling dimension: mmSymbol Dimension in inch Dimension in mmmin nom max min nom maxA——0.047—— 1.20A10.002——0.05——A20.0370.0390.0410.95 1.00 1.05B 0.010.0140.0180.250.350.45c —0.006——0.15—D 0.7210.7250.72918.3118.4118.51E 0.3960.4000.40410.0610.1610.26e—0.031——0.80—H E 0.4550.4630.47111.5611.7611.96L 0.0160.0200.0240.400.500.60L1—0.031——0.80—y ——0.004——0.10Q0o—5o0o—5oGS74108ATP/J/X44-Pin, 400 mil TSOP-IIIndexA1Side ViewAaaaPin A1IndexE1Bottom ViewD1ce eSolder Ballf b Symbol Unit: mm A 1.10±0.10A10.20~0.30f b f 0.30~0.40c 0.36(TYP)D 10.0±0.05D1 5.25E 6.0±0.05E13.75e 0.75(TYP)aaa0.10A B C D E F G H123456GS74108ATP/J/X6 mm x 10 mm FPBGAGS74108ATP/J/XOrdering InformationPart Number1Package2Access Time Temp. Range Status3 GS74108ATP-8400 mil TSOP-II8 ns Commercial MPGS74108ATP-10400 mil TSOP-II10 ns Commercial MPGS74108ATP-12400 mil TSOP-II12 ns Commercial MPGS74108ATP-8I400 mil TSOP-II8 ns Industrial MP GS74108ATP-10I400 mil TSOP-II10 ns Industrial MP GS74108ATP-12I400 mil TSOP-II12 ns Industrial MPGS74108AGP-8RoHS-compliant 400 mil TSOP-II8 ns Commercial PQ GS74108AGP-10RoHS-compliant 400 mil TSOP-II10 ns Commercial PQ GS74108AGP-12RoHS-compliant 400 mil TSOP-II12 ns Commercial PQGS74108AGP-8I RoHS-compliant 400 mil TSOP-II8 ns Industrial PQ GS74108AGP-10I RoHS-compliant 400 mil TSOP-II10 ns Industrial PQ GS74108AGP-12I RoHS-compliant 400 mil TSOP-II12 ns Industrial PQGS74108AJ-8400 mil SOJ8 ns Commercial MPGS74108AJ-10400 mil SOJ10 ns Commercial MPGS74108AJ-12400 mil SOJ12 ns Commercial MPGS74108AJ-8I400 mil SOJ8 ns Industrial MPGS74108AJ-10I400 mil SOJ10 ns Industrial MPGS74108AJ-12I400 mil SOJ12 ns Industrial MPGS74108AGJ-8RoHS-compliant 400 mil SOJ8 ns Commercial PQGS74108AGJ-10RoHS-compliant 400 mil SOJ10 ns Commercial PQGS74108AGJ-12RoHS-compliant 400 mil SOJ12 ns Commercial PQGS74108AGJ-8I RoHS-compliant 400 mil SOJ8 ns Industrial PQ GS74108AGJ-10I RoHS-compliant 400 mil SOJ10 ns Industrial PQ GS74108AGJ-12I RoHS-compliant 400 mil SOJ12 ns Industrial PQGS74108AX-8 6 mm x 10 mm FPBGA8 ns Commercial MPGS74108AX-10 6 mm x 10 mm FPBGA10 ns Commercial MPGS74108AX-12 6 mm x 10 mm FPBGA12 ns Commercial MPGS74108AX-8I 6 mm x 10 mm FPBGA8 ns Industrial MPGS74108AX-10I 6 mm x 10 mm FPBGA10 ns Industrial MPGS74108ATP/J/XNotes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS74108ATP-8T.2.All GSI Technology packages are at least 5/6 RoHS compliant. Packages listed with the additional “G” designator are 6/6 RoHS compliant.3.MP = Mass Production. PQ = Pre-Qualification.GS74108AX-12I 6 mm x 10 mm FPBGA12 ns Industrial MP GS74108AGX-8RoHS-compliant 6 mm x 10 mm FPBGA 8 ns Commercial PQ GS74108AGX-10RoHS-compliant 6 mm x 10 mm FPBGA 10 ns Commercial PQ GS74108AGX-12RoHS-compliant 6 mm x 10 mm FPBGA 12 ns Commercial PQ GS74108AGX-8I RoHS-compliant 6 mm x 10 mm FPBGA 8 ns Industrial PQ GS74108AGX-10I RoHS-compliant 6 mm x 10 mm FPBGA 10 ns Industrial PQ GS74108AGX-12IRoHS-compliant 6 mm x 10 mm FPBGA12 nsIndustrialPQOrdering InformationPart Number 1Package 2Access TimeTemp. RangeStatus 34M Asynchronous Datasheet Revision HistoryRev. Code: Old;NewTypes of Changes Format or ContentPage #/Revisions/Reason74108A_r1Format/Content • Creation of new datasheet 74108A_r1; 74108A_r1_01Content • Added 6 ns speed bin• Updated all power numbers74108A_r1_01; 74108A_r1_02Content • Updated Recommended Operating Conditions table on page 4• Added 7 ns bin to entire document • Added X package74108A_r1_02; 74108A_r1_03Content • Removed 6 ns speed bin from entire document • Corrected “X” package pinout74108A_r1_03; 74108A_r1_04Content • Removed 7 ns speed bin from entire document 74108A_r1_04; 74108A_r1_05Content • Updated format• Added Pb-free information for TSOP-II package 74108A_r1_05; 74108A_r1_06Content • Added Pb-free information for FP-BGA package 74108A_r1_06; 74108A_r1_07Content• Added RoHS-compliant information for SOJ • Changed Pb-free references to RoHS-compliant • Added status to ordering information tableGS74108ATP/J/X。