FPGA补充

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity test is port(clk:in std_logic; a,b:in std_logic_vector(3 downto 0); s:buffer std_logic_vector(3 downto 0); y:out std_logic_vector(3 downto 0)); end entity test; architecture one of test is begin process(clk) begin if clk='1'and clk'event then s<=a+b; s<=a; y<=s+1; end if; end process; end architecture one;
信号与源自文库量的区别
4，赋值行为的不同 信号赋值延时更新数值，一般生成时序电路 变量赋值立即更新数值，一般生成组合电路 5，信号的多次赋值 a 一个进程中：仅最后一次赋值有效 b 多个进程中：称为多源驱动（如总线结构） 能综合成硬件电路的多源驱动有三种：线与，线或，三态
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor_sig is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; X : out STD_LOGIC; Y : out STD_LOGIC); end xor_sig; architecture Behavioral of xor_sig is signal D: STD_LOGIC; begin SIG:process (A,B,C) begin D <= A; -- ignored !! X <= C xor D; D <= B; -- overrides !! Y <= C xor D; end process; end Behavioral;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity test is port(clk:in std_logic; a,b:in std_logic_vector(3 downto 0); s:buffer std_logic_vector(3 downto 0); y:out std_logic_vector(3 downto 0)); end entity test; architecture one of test is begin process(a,b,s) begin s<=a; y<=s+1; s<=a+b; end process; end architecture one;
信号与变量的区别
VHDL变量与信号的差异 1，赋值方式的不同 变量 := 表达式; 信号 <= 表达式; 2，硬件实现的功能不同 信号代表电路单元，功能模块间的互联，代表实际的硬件连线 变量代表电路单元内部的操作，代表暂存的临时数据
3，有效范围不同 信号（全局量）：程序包，实体，结构体 变量（局部量）：进程，子程序 注：在进程和子程序中，信号只能被使用，不能被定义说明
library ieee; use ieee.std_logic_1164.all; entity mux21 is port(a,b:in std_logic; s:in std_logic; y:out std_logic); end entity mux21; architecture one of mux21 is begin process(s,a,b) begin with s select y<=a when '0', b when '1'; end process; end architecture one;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity test is port(a,b:in std_logic_vector(3 downto 0); s:buffer std_logic_vector(3 downto 0); y:out std_logic_vector(3 downto 0)); end entity test; architecture one of test is begin s<=a; y<=s+1; s<=a+b; end architecture one;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity test is port(a,b:in std_logic_vector(3 downto 0); s:buffer std_logic_vector(3 downto 0); y:out std_logic_vector(3 downto 0)); end entity test; architecture one of test is begin y<=s+1; s<=a+b; end architecture one;
library ieee; use ieee.std_logic_1164.all; entity mux21 is port(a,b:in std_logic; s:in std_logic; y:out std_logic); end entity mux21; architecture one of mux21 is begin process(s,a,b) begin y<=a when s='0' else b when s='1'; end process; end architecture one;