SIMULATION OF D-STATCOM AND DVR IN POWER SYSTEMS
动态电压恢复器的原理及控制综述
动态电压恢复器的原理及控制综述KONG Shuhong, YIN Zhongdong，SHANRenzhongNorth China Electric Power UniversityBeijing , Chinae-mail: kshsh043@SHANG WeidongKaifeng Power Supply CompanyHenan，China摘要随着自动化技术信息化的发展，动态电压问题日益凸显。
动态电压恢复器（DVR）是现代配电系统中重要的缓解电压暂降的电力设备。
DVR的工作原理、结构和控制方法在许多DVR相关的学术会议和期刊上被引用和比较。
同时对未来DVR在电力系统中的应用和一些问题提出了建议。
关键词：电压暂降;动态电压恢复器（DVR）；控制技术；电能质量；优化的补偿；储能I引言最近几年，社会对于高功率质量（PQ）和电压稳定性的要求显著增加。
PQ 特性包括频率变化，电压变化，电压波动，不平衡三相电压，电压突变和谐波失真。
对于敏感的设备的一个严重威胁是持续10至100毫秒的电压暂降（60％至90％的额定电压的下降）。
电压暂降是因为大功率电机并网或切换操作时由动物接触，暴风雨，设备故障，绝缘故障，短路冲击电流较大等因素引起的。
这将导致巨大的财产和经济损失。
众所周知的保护关键负载不受干扰的定制功率器件有：STA TCOM分布（静止同步补偿器DSTATCOM），动态电压恢复器（DVR）和统一电能质量调节器（UPQC）。
DVR主要用于解决电压暂降问题。
1996年8月，Westinghouse电气公司在加利福尼亚州南部的Anderson在12.47KV变电站安装了世界上第一台DVR。
它主要为自动生产的工厂提供保护。
随后，ABB，西门子等其他公司也开发了自己的的产品来保证敏感负载的电压质量。
所以，在DVR的结构，参数检测，闭锁，补偿和控制技术等方面进行了大量的电力系统的研究。
在这片论文里，将对DVR的控制技术和结构进行调查和比较。
罗姆解决方案模拟器电源器件用户指南 (PFC 篇)说明书
ROHM Solution Simulator Power Device用户指南(PFC篇)User’s Guide ROHM Solution SimulatorPower Device 用户指南(PFC篇)前言本用户指南是为了便于充分灵活运用「Power Device Solution circuit」的PFC电路，对各参数的基本调整方法和知识的总结。
对于PFC电路设计时遇到的各个难题，这里分别介绍具体的解決方法，请在面对「不能正常运行」「进一步优化条件」等课题时作为参考。
此外，「PFC篇」的后续还有「逆变器篇」「DC-DC转换器篇」等篇章会在今后依次公开，请一同在电路设计中灵活运用。
目次■ 1. PFC电路一览・・・・・・・・・・・・・・・・・p.1■ 2. 电感值L的调整・・・・・・・・・・・・・・・・p.2■ 3. Switching频率fsw的调整・・・・・・・・・・・・・・・p.4■ 4. 栅极驱动电圧Vgs值的检讨・・・・・・・・・・・p.6■ 5. 栅极电阻Rg的变更・・・・・・・・・・・・・・・p.8■ 6. Dead time最佳值的检讨・・・・・・・・・・・・・p.101. PFC电路一览Table 1.是「Power Device Solution circuit」的PFC电路的总结。
表中包含通常使用的临界(BCM)、连续(CCM)、不连续(DCM)各动作模式，以及大功率３相PFC电路。
从基本的单机驱动，到交错式驱动、同步整流、无桥、Totem-pole等，我们针对不同情况均准备了介绍内容，请根据实际用途参考并应用。
Table 1. Power Device Solution Circuit PFC电路一览2. 电感值L的调整这里介绍的是通过调整线圈电感值来调整电感电流的波动率的方法。
调整的前提是动作模式为CCM（连续模式）。
2-1. 电路举例这里以Figure 1.的电路「A-4 PFC CCM Vin=200V Iin=2.5A」为例，变更黄色方框内的条件，并针对变更后的条件来调整L值。
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Advanced Circuit Simulation软件用户指南说明书
.SNNOISERuns periodic AC noise analysis on nonautonomous circuits in a large-signal periodic steady state..SNNOISE output insrc frequency_sweep [N1, +/-1]+ [LISTFREQ=(freq1 [freq2 ... freqN ]|none|all]) [LISTCOUNT=num ]+ [LISTFLOOR=val ] [LISTSOURCES=on|off].HBAC / .SNACRuns periodic AC analysis on circuits operating in a large-signal periodic steady state..HBAC frequency_sweep .SNAC frequency_sweep.HBXF / .SNXFCalculates transfer function from the given source in the circuit to the designated output..HBXF out_var frequency_sweep .SNXF out_var frequency_sweep.PTDNOISECalculates the noise spectrum and total noise at a point in time..PTDNOISE output TIME=[val |meas |sweep ] +[TDELTA=time_delta ] frequency_sweep+[listfreq=(freq1 [freq2 ... freqN ]|none|all)] [listcount=num ]+[listfloor=val ] [listsources=on|off]RF OptionsSIM_ACCURACY=x Sets and modifies the size of the time steps. The higher the value, thegreater the accuracy; the lower the value, the faster the simulation runtime. Default is 1.TRANFORHB=n 1 Forces HB analysis to recognize or ignore specific V/I sources, 0 (default) ignores transient descriptions of V/I sources.HBCONTINUE=n Specifies whether to use the sweep solution from the previous simulation as the initial guess for the present simulation. 0 restarts each simulation in a sweep from the DC solution, 1 (default) uses the previous sweep solution as the initial guess.HBSOLVER=n Specifies a preconditioner for solving nonlinear circuits. 0 invokes the direct solver. 1 (default) invokes the- matrix-free Krylov solver. 2 invokes the two-level hybrid time-frequency domain solver.SNACCURACY=n Sets and modifies the size of the time steps. The higher the value, the greater the accuracy; the lower the value, the faster the simulation runtime. Default is 10.SAVESNINIT=”filename ” Saves the operating point at the end of SN initialization.LOADSNINIT=”filename ” Loads the operating point saved at end of SN initialization.Output Commands.BIASCHK .MEASURE .PRINT .PROBEFor details about all commands and options, see the HSPICE ® Reference Manual: Commands and Control Options.Synopsys Technical Publications 690 East Middlefield Road Mountain View, CA 94043Phone (650) 584-5000 or (800) Copyright ©2017 Synopsys, Inc. All rights reserved.Signal Integrity Commands.LINCalculates linear transfer and noise parameters for a general multi-port network..LIN [sparcalc [=1|0]] [modelname=modelname ] [filename=filename ]+ [format=selem|citi|touchstone|touchstone2] [noisecalc [=1|0]]+ [gdcalc [=1|0]] [dataformat=ri|ma|db]+ [listfreq=(freq1 [freq2 ... freqN ]|none|all)] [listcount=num ]+ [listfloor=val ] [listsources=1|0|yes|no].STATEYEPerforms Statistical Eye Diagram analysis..STATEYE T=time_interval Trf=rise_fall_time [Tr=rise_time ] + [Tf=fall_time ] Incident_port=idx1[, idx2, … idxN ]+ Probe_port=idx1[, idx2, … idxN ] [Tran_init=n_periods ] + [V_low=val ] [V_high=val ] [TD_In=val ] [TD_PROBE=val ]+ [T_resolution=n ] [V_resolution=n ] [VD_range=val ]+ [EDGE=1|2|4|8] [MAX_PATTERN=n ] [PATTERN_REPEAT=n ] + [SAVE_TR=ascii] [LOAD_TR=ascii] [SAVE_DIR=string ]+ [IGNORE_Bits=n ] [Tran_Bit_Seg=n ]+ [MODE=EDGE|CONV|TRAN] [XTALK_TYPE = SYNC|ASYNC|DDP|NO|ONLY]+ [Unfold_Length=n ] [TXJITTER_MODE = 1|2]RF Analysis Commands.ACPHASENOISEHelps interpret signal and noise quantities as phase variables for accumulated jitter for closed-loop PLL analysis..ACPHASENOISE output input [interval ] carrier=freq+ [listfreq=(freq1 [freq2 ... freqN ]|none|all)][listcount=num ]+ [listfloor=val ] [listsources=1|0].HBRuns periodic steady state analysis with the single and multitone Harmonic Balance algorithm..HB TONES=F1[,F2,…,FN ] [SUBHARMS=SH ] [NHARMS=H1[,H2,…,HN ]]+ [INTMODMAX=n ] [SWEEP parameter_sweep ].SNRuns periodic steady state analysis using the Shooting Newton algorithm..SN TRES=Tr PERIOD=T [TRINIT=Ti ] [MAXTRINITCYCLES=integer ]+ [SWEEP parameter_sweep ] [NUMPEROUT=val ].SN TONE=F1 [TRINIT=Ti ] NHARMS=N [MAXTRINITCYCLES=integer ]+ [NUMPEROUT=val ] [SWEEP parameter_sweep ].HBOSC / .SNOSCPerforms analysis on autonomous oscillator circuits..HBOSC TONE=F1 NHARMS=H1+ PROBENODE=N1,N2,VP [FSPTS=NUM,MIN,MA X]+ [SWEEP parameter_sweep ] [SUBHARMS=I ] [STABILITY=-2|-1|0|1|2].SNOSC TONE=F1 NHARMS=H1 [TRINIT=Ti ]+ [OSCTONE=N ] [MAXTRINITCYCLES=N ]+ [SWEEP parameter_sweep ].PHASENOISEInterprets signal / noise quantities as phase variables for accumulated jitter in closed-loop PLL analysis..PHASENOISE output frequency_sweep [method= 0|1|2]+ [listfreq=(freq1 [freq2 ... freqN ]|none|all)] [listcount=num ]+ [listfloor=val ] [listsources=1|0] [carrierindex=int ].HBNOISEPerforms cyclo-stationary noise analysis on circuits in a large-signal periodic steady state..HBNOISE output insrc parameter_sweep [N1, N2, ..., NK ,+/-1]+ [LISTFREQ=(freq1 [freq2 ... freqN ]|none|all]) [LISTCOUNT=num ]+ [LISTFLOOR=val ] [LISTSOURCES=on|off].NOISERuns noise analysis in frequency domain..NOISE v(out ) vin [interval ] [listckt[=1|0]]+ [listfreq=freq1 [freq2 ... freqN ]|none|all]) [listcount=num ]+ [listfloor=val ] [listsources=1|0|yes|no]] [listtype=1|0].ALTERReruns a simulation using different parameters and data from a specified sequence or block. The .ALTER block can contain element commands and .AC, .ALIAS, .DATA, .DC, .DEL LIB, .HDL, .IC (initial condition), .INCLUDE, .LIB, .MODEL, .NODESET, .OP, .OPTION, .PARAM, .TEMP, .TF, .TRAN, and .VARIATION commands..ALTER title_string.DCPerforms DC analyses..DC var1 START=start1 STOP=stop1 STEP=incr1Parameterized Sweep.DC var1 start1 stop1 incr1 [SWEEP var2 type np start2 stop2].DC var1 START=[par_expr1] STOP=[par_expr2] STEP=[par_expr3]Data-Driven Sweep.DC var1 type np start1 stop1 [SWEEP DATA=datanm (Nums )].DC DATA=datanm [SWEEP var2 start2 stop2 incr2].DC DATA=datanm (Nums )Monte Carlo Analysis.DC var1 start1 stop1 incr1 [SWEEP MONTE=MCcommand ].DC MONTE=MCcommand.OPCalculates the operating point of the circuit..OP format_time format_time ... [interpolation].PARAMDefines parameters. Parameters are names that have associated numeric values or functions..PARAM ParamName = RealNumber | ‘AlgebraicExpression’ | DistributionFunction (Arguments ) | str(‘string’) | OPT xxx (initial_guess, low_limit, upper_limit )Monte Carlo Analysis.PARAM mcVar = UNIF(nominal_val , rel_variation [, multiplier ]) | AUNIF(nominal_val , abs_variation [, multiplier ])| GAUSS(nominal_val , rel_variation , num_sigmas [, multiplier ]) | AGAUSS(nominal_val , abs_variation , num_sigmas [, multiplier ]) | LIMIT(nominal_val , abs_variation ).STOREStarts creation of checkpoint files describing a running process during transient analysis..STORE [file=checkpoint_file ] [time=time1]+ [repeat=checkpoint_interval ].TEMPPerforms temperature analysis at specified temperatures..TEMP t1 [t2 t3 ...].TRANPerforms a transient analysis.Single-Point Analysis.TRAN tstep1 tstop1 [START=val ] [UIC]Multipoint Analysis.TRAN tstep1 tstop1 [tstep2 tstop2 ... tstepN tstopN ]+ RUNLVL =(time1 runlvl1 time2 runlvl2...timeN runlvlN )+ [START=val ] [UIC] [SWEEP var type np pstart pstop ]Monte Carlo Analysis.TRAN tstep1 tstop1 [tstep2 tstop2 ... tstepN tstopN ]+ [START=val ] [UIC] [SWEEP MONTE=MCcommand ]Invoking HSPICESimulation Modehspice [-i] input_file [-o [output_file ]] [-hpp] [-mt #num ][-gz] [-d] [-case][-hdl filename ] [-hdlpath pathname ] [-vamodel name ]Distributed-Processing Modehspice [-i] input_file [-o [output_file ]] -dp [#num ][-dpconfig [dp_configuration_file ]] [-dplocation [NFS|TMP][-merge]Measurement Modehspice -meas measure_file -i wavefile -o [output_file ]Help Modehspice [-h] [-doc] [-help] [-v]Argument Descriptions-i input_file Specifies the input netlist file name.-o output_file Name of the output file. HSPICE appends the extension .lis.-hpp Invokes HSPICE Precision Parallel.-mt #num Invokes multithreading and specifies the number of processors. Works best when -hpp is used.-gz Generates compression output on analysis results for these output types: .tr#, .ac#, .sw#, .ma#, .mt#, .ms#, .mc#, and .print*.-d (UNIX) Displays the content of .st0 files on screen while running HSPICE.-case Enable case sensitivity.-hdl filename Specifies a Verilog-A file.-hdlpath pathname Specifies the search path for Verilog-A files.-vamodel name Specifies the cell name for Verilog-A definitions.-dp #num -dpconfig dpconfig_file -dplocation [NFS|TMP] Invokesdistributed processing and specifies number of processes, the configuration file for DP, and the location of the output files.-merge Merge the output files in the distributed-processing mode.-meas measure_file Calculates new measurements from a previous simulation.-h Outputs the command line help message.-doc Opens the PDF documentation set for HSPICE (requires Adobe Acrobat Reader or other PDF document reader).-help Invokes the online help system (requires a Web browser).-v Outputs HSPICE version information.HSPICE is fully integrated with the Synopsys® Custom Compiler™ Simulation and Analysis Environment (SAE). See the Custom Compiler™ Simulation and Analysis Environment User Guide .To use the HSPICE integration to the Cadence® Virtuoso® Analog Design Environment, go to /$INSTALLDIR/interface/ and follow the README instructions.Analysis Commands.ACPerforms AC analyses.Single / Double Sweep.AC type np fstart fstop.AC type np fstart fstop [SWEEP var+ [START=]start [STOP=]stop [STEP=]incr ].AC type np fstart fstop [SWEEP var type np start stop ]Sweep Using Parameters.AC type np fstart fstop [SWEEP DATA=datanm (Nums )].AC DATA=datanm.AC DATA=datanm [SWEEP var [START=]start [STOP=]stop [STEP=]incr ].AC DATA=datanm [SWEEP var type np start stop ]Monte Carlo Analysis.AC type np fstart fstop [SWEEP MONTE=MCcommand ].LSTBInvokes loop stability analysis..LSTB [lstbname ] mode=[single|diff|comm + vsource=[vlstb |vlstbp,vlstbn ]Data-Driven Sweep.TRAN DATA=datanm.TRAN DATA=datanm [SWEEP var type np pstart pstop ].TRAN tstep1 tstop1 [tstep2 tstop2 ... tstepN tstopN ]+ [START=val ] [UIC] [SWEEP DATA=datanm (Nums )]Time Window-based Speed/Accuracy Tuning by RUNLVL.TRAN tstep tstop [RUNLVL=(time1 runlvl1...timeN runlvlN )]Circuit Block-based Speed/Accuracy Tuning by RUNLVL.TRAN tstep tstop+ [INST=inst_exp1 RUNLVL=(time11 runlvl11...time1N runlvl1N )]+ [SUBCKT=subckt_exp2 RUNLVL=(time21 runlvl21...time2N runlvl2N )]Time Window-based Temperature Setting.TRAN tstep tstop [tempvec=(t1 Temp1 t2 Temp2 t3 Temp3...)+[tempstep=val ]].TRANNOISEActivates transient noise analysis to compute the additional noise variables over a standard .TRAN analysis..TRANNOISE output [METHOD=MC] [SEED=val ] [SAMPLES=val ] [START=x ]+ [AUTOCORRELATION=0|1|off|on] [FMIN=val ] [FMAX=val ] [SCALE=val ]+ [PHASENOISE=0|1|2] [JITTER=0|1|2] [REF=srcName ] [PSD=0|1]HSPICE Options.OPTION opt1 [opt2 opt3 …]opt1 opt2 … Specify input control options.General OptionsALTCC=n Enables reading the input netlist once for multiple .ALTER statements. Default is 0.LIS_NEW=x Enables streamlining improvements to the *.lis file. Default is 0. SCALE=x Sets the element scaling factor. Default is 1.POSTTOP=n Outputs instances up to n levels deep. Default is 0.POSTLVL=n Limits data written to the waveform file to the level of nodes specified by n .POST=n Saves results for viewing by an interactive waveform viewer. Default is 0.PROBE=n Limits post-analysis output to only variables specified in .PROBE and .PRINTstatements. Default is 0.RC Reduction OptionsSIM_LA=name Starts linear matrix (RC) reduction to the PACT, PI, or LNE algorithm. Defaultis off.Transient OptionsAUTOSTOP=n Stops transient analysis after calculating all TRIG-TARG, FIND-WHEN, andFROM-TO measure functions. Default is 0.METHOD=name Sets numerical integration method for a transient analysis to GEAR, or TRAP(default), or BDF.RUNLVL=n Controls the speed and accuracy trade-off; where n can be 1 through 6. The higher the value, the greater the accuracy; the lower the value, the faster the simulation runtime. Default is 3.Variability and Monte Carlo Analysis.AC .DC .TRAN .MEASURE .MODEL .PARAM .ACMATCHCalculates the effects of variations on the AC transfer function, with one or more outputs..ACMatch Vm(n1) Vp(n1) Vr(n1) Vi(n1) Vm(n1,n2) Im(Vmeas ).DCMATCHCalculates the effects of variations on the DC operating point, with one or more outputs..DCMatch V(n1) V(n1,n2) I(Vmeas )。
simulation and design of integrated magnetics for power converters
Simulation and Design of Integrated Magneticsfor Power ConvertersYim-Shu Lee,Senior Member,IEEE,Leung-Pong Wong,Member,IEEE,and David Ki-Wai Cheng,Member,IEEEAbstract—We introduce a method touse-parameter two-port network model.We use a single-switch reg-ulator with power-factor-correction and a single integrated mag-netic component as an example to demonstrate the practical appli-cations of integrated magnetics in modern power converters.For the same example,we analyze the problem of uneven magnetic flux density in an integrated magnetic component and propose a pos-sible solution to the problem.Index Terms—Integrated magnetics,modeling of magnetic com-ponents,simulation of integrated magnetics.I.I NTRODUCTIONI NTEGRATED magnetics have been in existence for morethan half a century[1]–[7].They appear in different forms such as coupled inductors,integrated transformers(two or more transformers sharing a common magnetic core),and integrated inductor and transformer.The purposes of using integrated mag-netics are:•to reduce the number of magnetic components;•to achieve special functions such as removing cur-rent/voltage ripples or reducing voltage/current stress. The analysis,design,and manufacture of integrated mag-netics require special techniques.The problems encountered in the development of these techniques and the relatively weak demand for integrated magnetics in the past had prevented integrated magnetics from being popularly used.In the modern power electronics industry the demand for in-tegrated magnetics has become much stronger because of the following reasons.•Modern power supplies,such as ac to dc converters with power-factor correction and regulators with multiple out-puts,often require more than one magnetic components.Through integration,the number of magnetic components can be reduced.•By using integrated magnetics,the size and cost of power electronic circuits can be reduced.•Sometimes a controlled coupling between magnetic com-ponents is required to achieve special functions[5],[8].Manuscript received October30,2000;revised November12,2002.This work was supported by the Research Committee of The Hong Kong Polytechnic University,Hong Kong.The authors are with the Department of Electronic and Information Engi-neering,The Hong Kong Polytechnic University,Kowloon,Hong Kong(e-mail: enyslee@.hk).Digital Object Identifier10.1109/TMAG.2003.808579Fig.1.Inductor circuit.Electrical parameters:v,R.Magnetic parameters: mmf, ,S.The principle of operation of integrated magnetics is actu-ally not difficult to understand.But the analysis of complex and nonlinear magnetic components can be difficult.In[9]–[13], the Gyrator–Capacitor approach was proposed to model the be-havior of magnetic components.In this approach,the of a magnetic core is modeled as a current and the interface between an electric circuit and a magnetic component is modeled as a gy-rator.By doing this,the equivalent circuit of a complex magnetic component can be more easily developed for computer simula-tion purposes.However,one problem with this approach is that electronics engineers may find the concept of gyrators,and the techniques of analyzing circuits with gyrators,unfamiliar.This hinders the potentially wide application of the gyrator concept in the analysis and design of integrated magnetics.In Section II of this paper,we shall proposeusing-parameter two-port network model will be presented.In Section IV,a prac-tical example of Single-Stage Isolated Power-factor-corrected Power supply(SSIPP)using a single magnetic component will be examined.In Section V,the problem of uneven flux density in integrated magnetics will be studied.A design example to reduce the unevenness in flux density will be reported in Sec-tion VI.II.B EHA VIOR M ODELING OF I NTERFACE B ETWEEN ANE LECTRIC C IRCUIT AND A M AGNETIC C OMPONENT Consider the inductor circuit shown in Fig.1.The objec-tive here is to develop a“purely electrical”equivalent circuit to model the behavior of the magnetic component.There is a natural tendency for engineers to model magneticflux as a current andreluctance(a)(b)Fig.2.(a)Electric–magnetic interface.(b)Z -parameter two-port network model of (a).tween the electric circuit and the magnetic component.There-fore,a different approach of modeling is used here.A.Modeling of Electric–Magnetic InterfaceIn this new approach of modeling,we start with the assump-tion that the electric–magnetic interface is to be modeled asa-parameter two-port net-work shown in Fig.2(b),where parameters to be determined.To startwithohms,ohms.Equation (2)truly reflects the induced back electromotive force of the circuit.Theparameter(3)where=N ohms.magnetic short circuit (magnetic material with zero reluctance).The(6)where(9)-parameter two-port network modelof the electric–magnetic interface as shown in Fig.4.It should be noted that although the terminologies of “input port”and “output port”are used,the(a)(b)Fig.5.Modeling of (a)inductor and (b)transformer by equivalent circuit.TABLE IE QUIV ALENCE B ETWEEN M AGNETIC AND E LECTRICAL PARAMETERSone for an inductor as shown in (a),and the other for a trans-former as shown in (b).B.Modeling of Magnetic SaturationWhen the flux density in a nonlinear magnetic core reaches saturation,a large increase in magnetizing force will result in only a small increase in the flux density.Based on the equivalence given in Table I,the magnetic satu-ration phenomenon stated above can be translated into the elec-trical equivalent of:When the charge on a nonlinear capacitor reaches “satura-tion,”a large increase in voltage (across the capacitor)will re-sult in only a small increase in the charge on the capacitor.In [13]and [14],the above-stated phenomenon can be modeled by an equivalent circuit as shown in Fig.6.In this equivalent circuit,the dependent voltagesource(a)(b)Fig.6.(a)Modeling of nonlinear capacitor.(b)Equivalent circuit of nonlinear capacitor.Vn n nnn n nn nn nn n n C.Modeling of Losses in Magnetic ComponentsIn [14]and [15],Eaton proposed adding a core loss resistor tothe Gyrator–Capacitor model to represent the lossy component of a magnetic core.The modified model is referred to as the Gyrator Re-Cap model.When such a lossy component is added tothe––Fig.8.More complete model of transformer.•are used to model the series resistances of thewindings.•are numbers of turns of the primary and sec-ondary windings.III.D ESIGNOF I NTEGRATEDM AGNETICS USING).(a)Possible windingarrangement of an inductorL(a)(b)Fig.10.Integrated inductor (L).(a)Integrated magneticwith two independent (uncoupled)inductors (L(L ).(a)Windingarrangement.(b)Z -parameter two-port network model of (a).Note thatto the center limb of themagnetic core,as shown in Fig.11,inductorand(a)(b)Fig.12.Integrated transformer (T ).(a)Winding arrangement.(b)Z -parameter two-port network model of (a).IV .A PPLICATION E XAMPLEPSpice simulations (based onthe26.9mm,I.D.and a 3C85ETD-39Fig.13.Circuit diagram of Boost–Flyback SSIPP with regenerative clamping.TABLE IIP ARAMETERS OF M AGNETIC C ORES ETD-49AND ETD-39U SED INSSIPPcore is used for thetransformer,a larger magnetic core,3C85ETD-49forboth-param-eter two-port network model ofintegratednF,nF.•nF,nF.•.•are the primary and secondary numbers of turns of the transformer.(The nearest integer numbers closest to the calculated ones are used.The inductance values can be achieved more exactly by adjusting the air gaps.)•are insignificant and ignored in this example.Before putting the circuit to an ac line test,the dc operation was first studied.The input voltage used was 110VDC and the output voltage was regulated at 28VDC.The simulated waveforms of the SSIPP (withseparatedFig.14.Z -parameter two-port network model of integratedLandT=TandT(4A/div);4)i=T (4A/div);4)iFig.19.Experimental waveforms of input line current (1A/div)and line voltage (50V/div)of the SSIPP [with separatedL=TT ini I iL=T=TTh i i i T is icore ETD-39(with an integrated L=T=TFig.27.Simulated waveforms of the SSIPP (with the newL=T(4A/div);4)i=T=T=Ti i i i i i i Th i i i i i i i i i i Th i in i i1018IEEE TRANSACTIONS ON MAGNETICS,VOL.39,NO.2,MARCH2003[7]M.Archer,“Integrated magnetic resonant power converter,”U.S.Patent4774649,Sept.27,1988.[8]P.W.Lee,Y.S.Lee,D.K.W.Cheng,and X.C.Liu,“Steady-stateanalysis of an interleaved boost converter with coupled inductors,”IEEE Trans.Ind.Electron.,vol.47,pp.787–795,Aug.2000.[9] B.D.H.Tellegen,“The gyrator,A new electric network element,”Philips Res.Rep.,vol.3,pp.81–101,Apr.1948.[10]R.W.Buntenbach,“Improved circuit models for inductors wound ondissipative magnetic cores,”in Conf.Rec.2nd Asilomar Conf.Circuits and Systems,Pacific Grove,CA,Oct.1968,pp.229–236.[11],“Analogs between magnetic and electrical circuits,”Electron.Prod.,pp.108–113,Oct.1969.[12] D.C.Hamill,“Lumped equivalent circuits of magnetic components:Thegyrator–capacitor approach,”IEEE Trans.Power Electron.,vol.8,pp.97–103,Apr.1993.[13],“Gyrator–capacitor modeling:A better way of understandingmagnetic components,”in Proc.APEC’94,vol.1,Orlando,FL,Feb.13–17,1994,pp.326–332.[14]M.E.Eaton,“Modeling magnetic devices using the gyrator re-cap coremodel,”in Conf.Rec.,Northcon’94,1994,pp.60–66.[15],“Adding flux paths to SPICE’s analytical capability improves thecase and accuracy of simulating power circuits,”in Proc.APEC’98,vol.1,1998,pp.386–392.[16] D.K.W.Cheng,L.P.Wong,and Y.S.Lee,“Design,modeling,and anal-ysis of integrated magnetics for power converters,”in Proc.PESC’00, vol.1,2000,pp.320–325.[17]Y.S.Lee,K.W.Siu,and B.T.Lin,“Novel single-stage isolatedpower-factor-corrected power supplies with regenerative clamping,”IEEE Trans.Ind.Applicat.,vol.34,pp.1299–1308,Nov./Dec.1998.Yim-Shu Lee(SM’98)received the M.Sc.degree from the University of Southampton,U.K.,in1974,and the Ph.D.degree from the University of Hong Kong in1988.He had been with Cable and Wireless,Rediffusion Television,and the Gen-eral Post Office,all in Hong Kong,before joining The Hong Kong Polytechnic University,Kowloon,in December1969.Currently,he is the Chair Professor of Electronic Engineering in the Department of Electronic and Information En-gineering.He has published more than130technical papers on the design of electronic circuits and is the author of the book Computer-Aided Analysis and Design of Switch-Mode Power Supplies(New York:Marcel Dekker,1993).His current research interests include power electronics and computer-aided design of analog circuits.Dr.Lee is a Fellow of the Institution of Electrical Engineers,U.K.,and the Hong Kong Institution of Engineers.Leung-Pong Wong(S’96–M’98)received the B.Eng.(Hons)degree in electronic engineering in1998from The Hong Kong Polytechnic University, Kowloon,Hong Kong,where he is currently pursuing the Ph.D.degree.His research interests include modeling,simulation,and design of switching power converters,magnetics,and current sensors.David Ki-Wai Cheng(M’90)received the B.Sc.degree with First Class Honor in electronic engineering from Brighton University,U.K.,in1975,and the Ph.D. degree from the University of Hong Kong in1992.He held appointments with Pye Ether Ltd.(U.K.)from1975to1978and Bic-cotest(U.K.)from1978to1983.Currently,he is an Associate Professor with the Department of Electronic and Information Engineering,The Hong Kong Poly-technic University,Kowloon.His research interests include power electronics and computer-aided design of electronic circuits.Dr.Cheng was presented the IEEE Third Millennium Medal in recognition and appreciation of valued services and outstanding contributions.。
电力系统
IEEE PES, Panel SessionDigital Simulation of FACTS and Custom-Power controllersWinter Meeting, New York, January 2002Simulation of FACTS controllers using the MATLAB Power System Blocksetand Hypersim real-time simulatorGilbert Sybille, Pierre GirouxIREQ, Hydro-Québec 1800 Lionel-Boulet,Varennes, Québec, Canada J3X 1S1Keywords : FACTS, custom power, power electronics, controllers, transients, real-time, SimulinkThis presentation explains the simulation tools and the solution methods used in the Hydro-Quebec Power System Simulation laboratory for the design and real-time testing of FACTS controllers.1. The Simulation ToolsDuring the last 20years IREQ has been extensively using its hybrid (analog/digital)real-time simulator to test con-ventional FACTS controllers based on line-commutated power electronics (SVC and HVDC)as well as the new gen-eration based on forced-commutated power electronics (AEP Inez UPFC,NYPA Marcy Convertible Static Compensator (CSC)). In addition to the hybrid simulator, the following digital tools are now currently used:•Matlab/Simulink &Power System Blockset (PSB )for off-line simulation.PSB uses the state variable repre-sentation to simulate both power systems and control systems.Specialized PSB libraries contain power elements as well as control blocks necessary to design FACTS and custom power devices (such as IGBT or GTO bridges,PLL, square wave or PWM pulse generators).•Matlab Real-Time Workshop (RTW).The Real-Time Workshop is used to generate C code of control systems developed in the PSB/Simulink environment.The C code is then compiled and interfaced with the Hypersim real-time platform or with EMTP.Experience with large FACTS controllers has demonstrated that RTW gener-ates highly efficient code that could be embedded in industrial type controllers.•Hypersim real-time simulator.Hypersim is used to simulate large power systems off-line or real-time.It is based on the EMTP nodal method.Real time is achieved by automatic task mapping on a CC-NUMA multipro-cessor system (Origin 3000SGI computer).The simulator is equipped with fast inputs/outputs for closed-loop testing of real controls.Its graphical user interface and automatic testing environment allow efficient testing of FACTS controllers.Although Hypersim has built-in control blocks,the preferred approach for complex control-lers is to use Simulink and C code generated by RTW.The design cycle of a FACTS controller, using these simulation tools, is presented in Figure 1.Figure 1 Typical PSB/Hypersim cycle used in the design of FACTS controllersTheabove simulation approach has been successfully applied for the design and testing of FACTS controllers (SVC,STATCOM, UPFC) and custom power devices (Static transfer switch, D-STATCOM, DVR).2. The Simulation MethodsOff-line simulation is an important part of the design of FACTS and custom power controllers.In order to optimize simulation speed,different solution techniques can be used,depending on the maximum frequency of interest.Three solution methods are currently used in the PSB. They are presented below by increasing oder of frequency ranges.PSB (off line)Simplified Power System+Detailed ControlsHypersim(real-time or off-line)Detailed Power System&ControlsRTWfor the control systemDesign Optimization•Phasor solution method .This technique used by transient stability softwares for study of electromechanical oscillations (in the 0.02Hz -2Hz range)is the fastest method.Differential equations are used to represent the low frequency modes related to generators,prime movers and regulators,whereas the network and voltage-sourced converters are simulated by a set of algebraic equations and voltage or current sources at fundamental frequency. For these low frequencies a time step of one cycle is sufficient.•Average modeling technique.For study of switching transients and interaction of controls with power system (10Hz to a few kHz),state-space modelling must be used for the entire system.In addition,each time a switch is operated the state-space model of the linear system must be reevaluated.One particularity of FACTS and PQ devices is the large number of switchings required at every cycle,thus increasing the computation load.For example,a UPFC using two 48-pulse,3-level GTO converters requires a minimum of 72switches operated at every cycle.For custom power devices the converter topology is much simpler but the switching frequency is relatively high (For example,in an IGBT,PWM,2-level inverter using 6switches operated at 1.8kHz,there are up to 180switchings per cycle).If the high order harmonics generated by voltage-sourced converters is not important,these devices can be replaced by simple voltage sources producing the same average voltage over one cycle of the switching frequency. This method allows using relatively large time steps (in the order of 50µs).•Detailed modelling .The most accurate method requiring simulation of all switches is obtained at the expense of reduced time step.For example,with a PWM converter using a 2kHz switching frequency,harmonics are mod-elled with an acceptable accuracy with ideal switches and 2µs time steps.If switching losses have to be simu-lated precisely,detailed switch models such as those available in PSpice must be used,requiring time steps as low as 0.1µs.During this presentation,the three solution methods will be illustrated with a FACTS controller (SVC using the pha-sor solution method) and with a custom power controller (DSTATCOM using the average and detailed modelling).3. Example of transient stability study using the “Phasor solution” methodThe PSB diagram of Figure 2shows a simple 500-kV transmission system with two power plants and a 200-Mvar SVC providing voltage support at the middle point of the 700-km transmission line.The two hydraulic power plants are modeled by equivalent machines including detailed representation of turbine,speed regulator,voltage regulator and power system stabilizer (PSS).The phasor approach has been used to study the transient stability of this system and to optimize SVC controls and rating.Figure 2 PSB diagram of a 500-kV transmission system used for transient stability studyof two power plants with SVC and PSSSimulation results obtained with SVC and without SVC for a 3-phase,6-cycle fault applied at the machine 1side of the transmission line are compared on Figure 3.Waveforms show that the system is unstable without SVC.In order to show how the phasor solution dramatically speeds up simulation,the same simulation without SVC has been per-formed both with the phasor solution method (variable time step with a maximum time step of 1cycle)and with the detailed model using discretization (50µs time steps).For simulating 5seconds on a Pentium III 500MHz,simula-tion times are 10 s and 218 s respectively, corresponding to a 22X gain speed for the phasor method.Powergui −PhasorsVabc Mag & AnglemPrefPm VfTurbine &Regulators M2mPref PmVf Turbine &Regulators M1STOPStop Simulation if loss of synchronismU (E)U (E)A BC B (p u )V 1m e a s (p u )SVC 200 MvarsSVC0.8110Pref20.9526Pref1Machinesd_theta1_2w1 w2Vt1 Vt2stopMachine SignalsPmVfAB C m_puM2 5000 MVAPm VfAB C m_puM1 1000 MVAA B CLoad5000 MW1231 2 3L2 350 km1231 2 3L1 350 kmA B CFault A −G Fault BreakerA B C AB C b c b cB2A B Ca b c5000MVA 13.8 kV/500 kVA B Ca b c1000 MVA 13.8 kV/500 kVV SVC (pu)B SVC (pu /200 MVA)w1 w2 (pu)d_theta1_2 (deg)Vt1 Vt2 (pu)Figure 3 Impact of SVC on stability of the two-machine system for a 3-phase fault4. DSTATCOM simulation using the average and detailed modeling techniquesThe second example uses a custom power controller to compare the average and detailed modeling techniques.The PSB diagram shown in Figure 4represents a 25-kV distribution network with a load connected at bus B4(600V).A 3-Mvar D-STATCOM is connected at bus B3.The D-STATCOM is used to regulate the bus voltage by absorbing or generating reactive power to the network.The PSB diagram shows the following components:• a 25/2.5-kV coupling transformer which ensures the coupling between the PWM inverter and the network•a voltage-source PWM inverter consisting of two IGBT bridges.This twin inverter configuration produces less harmonics resulting in smaller filters and improved dynamic response.In this case,the inverter modulation fre-quency is 1.68 kHz so that the first harmonics will be around 3.36 kHz.•a group of filters consisting of a series inductance of 800µH connected at the output of “Bridge 1”and a capaci-tor of 100µF in series with a resistance to provide a quality factor of 40at 60Hz.This RC filter is connected to the secondary side of the coupling transformer.• a 10000-µF capacitor acting as a DC voltage source for the inverter • a voltage regulator that controls the voltage at Bus B3• a PWM pulse generator using a modulation frequency of 1.68 kHz • anti-aliasing filters used for voltage and current acquisitionFigure 4 PSB diagram of a 3 Mvar DSTATCOM on a 25-kV distribution network00.51 1.52 2.53 3.54 4.55100200d t h e t a 1−2 (d e g )00.51 1.52 2.53 3.54 4.5512V S V C (p u )00.51 1.522.533.544.55−11B S VC (p u /200 M V A )Time (s)00.51 1.52 2.53 3.54 4.550.9811.02w 1 (p u )with SVCwith SVCwith SVCwith SVCNo SVC ; PSS (unstable)No SVC (unstable)No SVCNo SVCRotor Angle DifferenceSpeed of Machine 1Voltage at SVC BusSVC SusceptanceD STATCOM 25kV, +/ 3MvarTs=1/60/360/8A B CVariable LoadA 1+A 1B 1+B 1C 1+C 1A 2+A 2B 2+B 2C 2+C 2A B Ca b c nTr1VabcIabcVdcP1P2Statcom controllerSig2Sig1A B CPSBProg. Source1Multimeter (DC Link)Iabc_B3Vabc_B3A +B +C +A −B −C − A +A −B +B −C +C −FilterA B CA B CFeeder 21 km A B CA B CFeeder 2 kmDiscrete system Ts=5.787e−006VaIaVa_Inv Iq_IqrefPQ Vdc mData AcquisitionDC Link +−pulsesA B CBridge2+−pulsesA B CBridge1A B CA B C B4A B C ABCB3AB CA B C B2A B CA B C B1A B C3 MW 0.2 MvarA B CA B C25 kV, 100MVASystem A B CLoad (Y)1 MWVaIa (pu)Va Inv (V)Vdc (V)P,Q (MVA)Iq,Iqref (pu)mWaveforms of Figure 5show the dynamic performance of the DSTATCOM when a voltage step is applied on the 25-kV equivalent .The reactive current component Iq and the instantaneous current waveform are shown respectively on traces 1and 3.Trace 2shows the DC bus voltage variation and trace 4shows the output voltage of the voltage con-verter.Two simulations have been performed:1)simulation using the average modeling technique (IGBT converter simulated by voltage sources,using a 5.8µs time step and 2)detailed simulation including all IGBT switches using a time step 8times larger (46.3or µs).Results are compared on each trace of Figure 5.The difference between the two simulation methods is clearly shown on the last trace showing the PWM chopped voltage superimposed with its aver-age value.Result show no noticeable difference during transients,proving that the average modeling technique pro-vides a substantial speed gain, while preserving the network/control interactions.Figure 5 Comparison of responses to a step change of source voltage5. ConclusionThis presentation has described the real-time and off-line simulation tools used in Hydro-Quebec Power System Sim-ulation laboratory.Hypersim is the ultimate simulation method because it allows real-time testing of FACTS control-lers (either prototypes developed with RTW or industrial controllers)or fast off-line simulation on a multiprocesseur system.Also,the three simulation methods available in PSB are efficient techniques for design and analysis of com-plex control systems found in FACTS and custom power controllers.0.180.1850.190.1950.20.2050.210.2150.220.2250.23−101I q (p u )0.180.1850.190.1950.20.2050.210.2150.220.2250.23220024002600V d c (V )0.180.1850.190.1950.20.2050.210.2150.220.2250.23−101I a S T A T0.180.1850.190.1950.20.2050.210.2150.220.2250.23−20002000V a I n v (V )。
Distributed Simulation
Distributed SimulationDistributed simulation lets you run multiple discrete event simulations at the same time on one or more computers (or multiple processors in the same computer). You can use distributed simulation for several purposes, such as:∙Performing parametric studies more quickly by executing multiple simulations concurrently∙Using a powerful remote computer to run simulations that need more memory or processing power than areavailable on your local computerWhen running a simulation with distributed simulation enabled, OPNET Modeler tries to start the specified number of simulations on each specified computer. As each processor finishes a simulation, OPNET Modeler uses it to start another one. This process continues until all simulations have been run. Simulation progress is reported in the DES Execution Manager dialog box (see DES Execution Manager).Requirements and Limitations for Distributed SimulationsConsider these items when running a distributed simulation:∙The directory containing the model being simulated must be shared by the local and remote computers. The output(.ov) files produced by the simulation are created in theshared model directory.∙Distributed simulation requires either a simulation site license or one simulation runtime license for each CPU. Ifthe simulation uses licensed modules or specializedmodels, each CPU requires licenses for these productsas well.∙Distributed simulation is intended to speed up production runs; therefore, debugging with ODB is disabled.∙Distributed simulations can be run across platforms (for example, OPNET Modeler on Windows andop_des_server on Linux) provided that both platformshave the same endianness.∙OPNET Modeler (or other OPNET analysis softwarecapable of discrete event simulation) must be installed oneach computer used for distributed simulation. On remotecomputers, op_des_server normally will use the sameenvironment database as the OPNET analysis softwareon that computer.∙There are several preferences which, if specified on the command line when launching OPNET Modeler on thelocal computer, are passed to op_des_server on theremote computers. These preferences are env_db,opnet_dir, opnet_user_home, license_server, andlicense_port. The local and remote computers must all beconfigured to deal with the effects of any of thesepreferences that you specify on the command line.For example, if you specify the env_db preference on thecommand line, all computers (local and remote) must beable to access the environment database in the specifiedlocation and also must be able to access all paths in themod_dirs preference (which is specified in theenvironment database). Thus, in this case, the paths forcore directories and model installation directories must beidentical on all computers.∙OPNET analysis software and models can be installed in different locations on the local and remote computers(unless the env_db preference is specified on thecommand line when launching OPNET Modeler, asdiscussed in the preceding item). The only restrictionsconcern the model directory that contains the networkand associated models to be simulated. This directoryo must be in a shared location (to ensure thatsimulation results are available to the GUI), ando must be specified in the mod_dirs preference on allcomputers (local and remote)Running Distributed SimulationsUse this procedure to execute a discrete event simulation with multiple runs on two or more processors of the same or different computers.Procedure 3-141 Running Distributed SimulationsNote—OPNET Modeler (or otherOPNET analysis software that supports discrete eventsimulation) must be installed on every computer used fordistributed simulation.1. On the local computer, set the following preferencevalues:o Set des.distributed_mode to TRUE.o Set des.distributed_server_host_info to a list of the computers available to run distributed simulations.If desired, also specify the port and number ofconcurrent runs for each server.Example:wtn11166:7012:2, wtn12120The preceding specification lets up to threesimulations run concurrently, two on wtn11166 andone (the default number) on wtn12120. wtn11166 iscontacted on port 7012.Optionally, set thedes.distributed_server_port_default anddes.distributed_server_num_runs_defaultpreferences.2. On every remote computer listed indes.distributed_server_host_info:o Run op_des_server. This program is located in the <reldir>/sys/<arch>/bin directory.Note—You must restart this program after acomputer is rebooted.3. On every computer listed indes.distributed_server_host_info (including the localcomputer):o Set the mod_dirs preference to include the directory on the local computer that contains the projectbeing simulated.Note—The directory containing the modelbeing simulated must be shared by allcomputers running a distributed simulation.You might need to set permissions on themodel directory to allow this.4. On the local computer, configure and run the simulation.End of Procedure 3-141Preferences for Distributed SimulationThe distributed simulation feature uses these preferences.Allow Simulation Runs on Multiple HostsSpecifies whether discrete event simulations are run consecutively on the local computer or concurrently on one or more processors. When TRUE, distributed simulation is enabled and simulations are run concurrently on the computers listed in thedes.distributed_server_host_info preference.Tag des.distributed_modeType booleanDefault Value F ALSEDistributed Simulation HostsSpecifies a list of computers on which to run distributed simulations. OPNET Modeler launches simulations on each specified computer in the listed order. Computers are specified by triplets with the format<name>:<port>:<num_runs>; for example, "wtn1234:7012:2". The port and number of concurrent runs can be omitted, in which case OPNET Modeler uses the default values specified by thedes.distributed_server_port_default anddes.distributed_server_num_runs_default preferences.This preference has no effect unless des.distributed_mode is set to TRUE.Tag des.distributed_server_host_infoType string listDefault Value ""Distributed Simulation Host Port NumberSpecifies the port number to use when connecting to the DES server process on a target computer if the number is not specified in the des.distributed_server_host_info preference. This preference has no effect unless des.distributed_mode is set to TRUE.Tag des.distributed_server_port_defaultType integerDefault Value 7007Distributed Simulation Runs per HostSpecifies the maximum number of concurrent simulations to run on a target computer if the number is not specified in thedes.distributed_server_host_info preference. Ideally, the number of concurrent simulations to run on a computer should not exceed the number of processors available on that computer. You can run more, but performance will suffer. This preference has no effect unless des.distributed_mode is set to TRUE.Tag des.distributed_server_num_runs_defaultType integerDefault Value 1。
S7-200模拟器使用说明
VBO软件操作手册
1.硬件 (4)1.1硬件` (4)1.2新手上路 (5)1.3LED 解释 (7)1.4电池 (7)1.5连接图 (8)1.6蜂鸣器声音 (10)2.使用技巧 (11)3.操作手则 (12)4.设置 VBOX (15)VBOX安装 (15)4.2Misc Channels其它通道 (16)4.4设置 (17)4.5Info (19)5.软件—新手上路 (20)5.1怎样做加速试验 (20)5.2怎样做制动实验 (20)5.3怎样通过图形化的界面查看测试结果 (20)5.5怎样在没有手提计算机连接的情况下进行试验 (21)6.软件–开始使用 (22)6.1主屏幕 (22)6.1.1用户设置前面板 (23)7.软件主菜单 (24)7.1File 文件 (24)7.1.1File load 文件载入 (24)7.1.2File save 文件保存 (24)7.1.3Replay file 文件回放 (24)7.1.4Repair/expand file 修补/扩充文件 (24)7.1.5Language语言 (24)7.2Options 选项 (24)7.2.1Unit of measurement测量单位 (24)7.2.2GPS cold start GPS 冷启动 (24)7.2.3 com口选择 (25)7.2.4Lock results until manually reset锁定结果直到手动复位 (25)7.2.5VBOX II & Pro Rev 4 (25)7.2.6 Measure distance using external trigger 使用外部触发器测量距离 (25)7.2.7Accel table columns 加速表纵列 (26)7.2.8Reset time when stationary 停止时把时间复位 (26)7.2.9Enable Slip angle calculations on Yaw sensor data 允许在偏航传感器数据上进行偏离角计算 (26)7.2.10Show Real Time Scope 显示实时范围 (26)7.2.11Put radius of turn in channel data 把转弯半径放到通道数据中 (26)7.2.12Delimiter for text files 文本文件的分隔符 (26)7.2.13Use target speed 1 for MFDD 使用的目标速度给MFDD (26)7.3Target speeds 目标速度 (26)7.3.1Test range 1 试验范围1 (26)7.3.2Test range 2试验范围2 (26)7.3.30 to 100 to 0 range 零到100到零范围 (27)7.4Real time plot 实时绘图 (27)7.5Select Run 选择运行 (28)7.5.1Default setups 缺省设置 (29)7.5.2Manual setup 手动设置 (31)7.6VBOX Setup VBOX 设置 (31)7.7Graph 图形 (31)7.8Start Finish 起点终点 (31)7.8.1Load start finish line and splits载入起/终点线和分离位置 (31)7.8.2Save start/finish line and splits保存起/终点线和分离位置 (32)7.8.3Start finish line length起/终点线的长度 (32)7.8.4Start finish line tolerance起终点线的公差 (32)7.8.5Accumulative split times 累计分离时间 (32)7.9.1Enable log file creation 允许记录文件产生 (32)7.9.2Include MFDD in logfile 在记录文件中包括MFDD (32)7.9.3Include test range 2 in logfile 在记录文件中包括试验范围2 (32)7.10Help 帮助 (32)8.GRAPH图形 (33)8.1概述 (33)8.2选择通道 (34)8.3设置外部输入信号的比例大小 (35)8.4键盘和鼠标指令 (36)8.5快捷键 (36)8.6定义起点/终点线和分离点。
ROHM 解决方案模拟器 7.0 V 至 26.0 V 输入，1 A 集成 MOSFET 单阶段同步
User’s Guide ROHM Solution Simulator7.0 V to 26.0 V Input, 1 A Integrated MOSFET Single Synchronous Buck DC/DC Converter BD9E104FJ / Frequency ResponseThis circuit simulates the frequency response of BD9E104FJ. You can customize the simulation conditions by changing the parameters of components highlighted in blue.General CautionsCaution 1: The values from the simulation results are not guaranteed. Please use these results as a guide for your design.Caution 2: These model characteristics are specifically at Ta=25°C. Thus, the simulation result with temperature variances may significantly differ from the result with the one done at actual application board (actual measurement).Caution 3: Please refer to the datasheet for details of the technical information.Caution 4: The characteristics may change depending on the actual board design and ROHM strongly recommend to double check those characteristics with actual board where the chips will be mounted on.1 Simulation SchematicFigure 1. Simulation Circuit2 How to simulateThe simulation settings, such as frequency range or convergence options, areconfigurable from the ‘Simulation Settings’ shown in Figure 2, and Table 1 showsthe default setup of the simulation.In case of simulation convergence issue, you can changeadvanced options to solve.The parameters V_VIN, V_VO, I_IO, L, and bias are defined inthe ‘Manual Options’.Figure 2. Simulation Settings and execution Table 1.Simulation settings default setupParameters Default NoteSimulation Type Frequency-Domain (Do not change Simulation Type)Start Frequency 100 Hz Simulate the frequency response for the frequency range from 100 Hz to 1 MHz.End Frequency 1.0e6 Hz Advanced options BalancedManual Options “.param V_VIN=12 V_VO=5 I_IO=1.0 L=6.8ubias=0.5”See “Simulation Condition” for detailsSimulationSettingsSimulateVOUTIOUTVIN3 Simulation Conditions3.1 How to define V IN, V OUT, I OUT, L, and biasThese parameters are used to setup the simulation conditions and BD9E104FJ_Average model parameters, therefore these are defined in the Manual Options as the common variables.Table 2 shows the default value of V IN, V OUT, I OUT, L, and bias. Those values are defined and can be set in the ‘Manual Options’ text box from Simulation Settings as shown in Figure 3.The load resistance RL are automatically set according to those parameters.Table 2. Simulation ConditionsParameters Variable Name Default Value Units DescriptionsV IN V_VIN 12 V Input VoltageV OUT V_VO 5 V Output VoltageI OUT I_IO 1.0 A Output CurrentL L 6.8 µH Output Inductorbias factor bias 0.5 - Bias factor to Output CapacitanceSet V_VIN, V_VO, I_IO, L, and biasFigure 3. Definition of V IN, V OUT, I OUT, L, and bias3.2 Resistive Load RLRL is the resistive load and its resistance is determined from V OUT and I OUT. The resistance value is defined as the equation below.Table 3. Resistive loadInstance Name Default Value UnitRL { V_VO / I_IO } Ω4 BD9E104FJ_Average modelThe simulation model in this circuit is designed for frequency response, and the functions not related to frequency response are not implemented.Table 4. BD9E104FJ_Average model terminals used for frequency responseTerminals DescriptionVIN Power supply inputEN Enable inputCOMP Input pin for the gm error amplifier output and the output for the PWM comparatorFB Output voltage feedback pinSW Switching nodeAGND, PGND GroundTable 5. BD9E104FJ_Average model terminals NOT used for frequency responseTerminals DescriptionBOOT Input is ignore (no switching operation in this model)(Note 1) This model is not compatible with the influence of ambient temperature.(Note 2) This model is not compatible with the external synchronization function.(Note 3) Use the simulation results only as a design guide and the data reported herein is not a guaranteed value.4.1 BD9E104FJ_Average Model ParametersBD9E104FJ_Average model has its parameters shown in Table 6. All the parameters are pre-defined and fixed in the simulation. V_VIN is substituted to V_VIN as shown in Table 6.Table 6. Parameter ListParameters Values DescriptionV_VIN V_VIN VIN voltageV_VO V_VO VOUT voltageL L Output InductorFigure 4. Property Editor of BD9E104FJ_Average model5 Peripheral ComponentsTo set parameters of components, open ‘property’ by double click or right click on a component. You can input a value toa property text box if available. Please refer to the hands-on manual for more details.5.1 Bill of MaterialTable 7 shows the list of components used in the simulation schematic. Each of the capacitor and inductor has the parameters of equivalent circuit shown below. The default value of equivalent components are set to zero except for the parallel resistance of L and series resistance of capacitors. You can modify the values of each component.Table 7. List of components used in the simulation circuitType Instance Name Default Value UnitsCapacitorC1 10 µFC2 0.1 µFC3 0.1 µFC4 390 pFCFB 12 pF COUT1, COUT2,COUT310 x 3 µFInductor L 6.8 µHResistor R2 430 kΩR3 82 kΩR4 82 kΩ5.2 Capacitor Equivalent Circuits(a) Property editor (b) Equivalent circuitFigure 5. Capacitor property editor and equivalent circuit5.3 Inductor Equivalent Circuits(a) Property editor (b) Equivalent circuitFigure 6. Inductor property editor and equivalent circuitThe default value of PAR_RES is 6.6kohm.(Note 5) These parameters can take any positive value or zero in simulation but it does not guarantee the operation of the IC in any condition. Refer to the datasheet to determine adequate value of parameters.6 Open Loop Transfer Function (OLTF) MonitorOLTF1 is the insert model to measure AC open loop transfer function and is inserted to acquire the gain and phase output. To monitor the gain and phase from OLTF1, select probe items ‘dbMag’for gain and ‘phase’for phase plot, respectively from ‘property’ of OLTF1.Figure 7. Probe Items of OLTF17 Link to the product information and tools7.1 Product webpage link:https:///products/power-management/switching-regulators/integrated-fet/buck-converters-synchronous/bd9e104fj-product7.2 Related documentsThe application notes are available from ‘Documents in Design Resources’ tab of the product page.7.3 Design assist tools are available from ‘Tools in Design Resources’ tab of the product page.The Circuit constant calculation sheet is useful for deciding the application circuit constants.NoticeROHM Customer Support Systemhttps:///contact/Thank you for your accessing to ROHM product informations.More detail product informations and catalogs are available, please contact us.N o t e sThe information contained herein is subject to change without notice.Before you use our Products, please contact our sales representative and verify the latest specifica-tions :Although ROHM is continuously working to improve product reliability and quality, semicon-ductors can break down and malfunction due to various factors.Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. ROHM shall have no responsibility for any damages arising out of the use of our Poducts beyond the rating specified by ROHM.Examples of application circuits, circuit constants and any other information contained herein areprovided only to illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.The technical information specified herein is intended only to show the typical functions of andexamples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM or any other parties. ROHM shall have no responsibility whatsoever for any dispute arising out of the use of such technical information.The Products specified in this document are not designed to be radiation tolerant.For use of our Products in applications requiring a high degree of reliability (as exemplifiedbelow), please contact and consult with a ROHM representative : transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems.Do not use our Products in applications requiring extremely high reliability, such as aerospaceequipment, nuclear power control systems, and submarine repeaters.ROHM shall have no responsibility for any damages or injury arising from non-compliance withthe recommended usage conditions and specifications contained herein.ROHM has used reasonable care to ensur e the accuracy of the information contained in thisdocument. However, ROHM does not warrants that such information is error-free, and ROHM shall have no responsibility for any damages arising from any inaccuracy or misprint of such information.Please use the Products in accordance with any applicable environmental laws and regulations,such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. ROHM shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.W hen providing our Products and technologies contained in this document to other countries,you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.This document, in part or in whole, may not be reprinted or reproduced without prior consent ofROHM.1) 2)3)4)5)6)7)8)9)10)11)12)13)。
高压直流详细仿真模型CIGRE HVDC Detailed modeling
Detailed Modeling of CIGRÉHVDC Benchmark System Using PSCAD/EMTDC and PSB/SIMULINK M.O.Faruque,Student Member,IEEE,Yuyan Zhang,and Venkata Dinavahi,Member,IEEEAbstract—This paper focuses on a comparative study of the mod-eling and simulation of thefirst CIGRÉHVDC benchmark system using two simulation tools PSCAD/EMTDC and PSB/SIMULINK; an interface between them(PSCAD-SIMULINK)has also been im-plemented and used as a simulator.The CIGRÉHVDC system and its controller has been carefully modeled in all three simulation environments so that the differences are parison of steady-state and transient situations have been carried out,and a high degree of agreement in most of the cases has been observed. Index Terms—HVDC transmission,modeling,simulation.I.I NTRODUCTIONT HE DESIGN,analysis,and operation of complex ac-dc systems require extensive simulation resources that are accurate and reliable.Analog simulators,long used for studying such systems,have reached their physical limits due to the increasing complexity of modern systems.Currently,there are several industrial grade digital time-domain simulation tools available for modeling ac-dc power systems.Among them,some have the added advantages of dealing with power electronics apparatus and controls with more accuracy and efficiency.PSCAD/EMTDC[1]and PSB/SIMULINK[2]are such two simulators that are being increasingly used in the industry as well as in the universities.Both programs allow the user to construct schematic diagram of electrical networks, run the simulation,and produce the results in a user-friendly graphical environment.Furthermore,several real-time digital simulators use models or the graphical front-end that are similar to PSCAD/EMTDC and PSB/SIMULINK.The objective of this paper is to report a detailed compar-ison between PSCAD/EMTDC and PSB/SIMULINK for the modeling and simulation of ac-dc power systems.In a digital simulator,the system model and the algorithm used to solve that model directly affect the accuracy and consistency of the sim-ulation results.Therefore,based on the objective of the study, careful attention should be given to the selection of the model, the numerical solver,and the algorithm.A comparative study among simulation tools will help in identifying the pros and cons that the programs inherit.For the last two decades,digital simulators have been widely used for the simulation of HVDCManuscript received September1,2004;revised December4,2004.This work was supported by the Natural Sciences and Engineering Research Council (NSERC)of Canada and the University of Alberta.Paper no.TPWRD-00406-2004.The authors are with the Electrical and Computer Engineering Depart-ment,University of Alberta,Edmonton,AB T6G2V4,Canada(e-mail: faruque@ece.ualberta.ca;yuyan@ece.ualberta.ca;dinavahi@ece.ualberta.ca). Digital Object Identifier10.1109/TPWRD.2005.852376and its control system.However,to compare the performance of any two simulators,similar circuit topology with control is a prerequisite.To achieve that goal,a benchmark system for HVDC,known as the CIGRÉBenchmark Model,was proposed in1985[3].It provided a common reference system for HVDC system ter in1991,a comparison of four digital models has been carried out by the CIGRÉWorking Group[4],[5],and a benchmark system for HVDC control study was also proposed.A detailed comparison between ATP and NETOMAC for the simulation of HVDC system wasfirst reported in[6],where the fundamental differences between the two software and their effects on simulation results have been discussed.The study found a good agreement between the two simulation results.More recently,custom power con-trollers such as DSTATCOM and DVR have been simulated [7]using PSCAD/EMTDC and SIMULINK to compare their performance.However,for a rigorous comparison between simulation tools and to gain insight into their capabilities and limitations,the modeled system should be able to offer the highest degree of difficulty.The main motivation for using the CIGRÉBenchmark HVDC System in this paper is that not only is it a widely used test system but also it is complex enough, with deliberate difficulties introduced for a comprehensive performance evaluation of the two simulation tools.Section II of this paper gives a brief introduction about the two simulation tools highlighting their solution techniques, and Section III introduces the CIGRÉHVDC benchmark system.Sections IV–VI present the detailed model of HVDC system and its controller in three simulation environments: PSCAD/EMTDC,PSB/SIMULINK,and PSCAD-SIMULINK interface.Results are presented in Section VII,followed by conclusions in Section VIII.II.PSCAD/EMTDC AND PSB/SIMULINK PSCAD/EMTDC is a powerful time-domain transient sim-ulator for simulating power systems and its controls.It uses graphical user interface to sketch virtually any electrical equip-ment and provide a fast andflexible solution.PSCAD/EMTDC represents and solves the differential equations of the entire power system and its control in the time domain(both elec-tromagnetic and electromechanical systems)[8].It employs the well-known nodal analysis technique together with trapezoidal integration rule withfixed integration time-step.It also uses in-terpolation technique with instantaneous switching to represent the structural changes of the system[9],[10].MATLAB/SIMULINK is a high-performance multifunc-tional software that uses functions for numerical computation,0885-8977/$20.00©2006IEEEFig.1.Single-line diagram of the CIGRÉbenchmark HVDC system.system simulation,and application development.Power System Blockset(PSB)is one of its design tools for modeling and simulating electric power systems within the SIMULINK environment[2],[11].It contains a block library with common components and devices found in electrical power networks that are based on electromagnetic and electromechanical equations.PSB/SIMULINK can be used for modeling and simulation of both power and control systems.PSB solves the system equations through state-variable analysis using either fixed or variable integration time-step.The linear dynamics of the system are expressed through continuous or discrete time-domain state-space equations.It also offers theflexibility of choosing from a variety of integration algorithms.III.F IRST CIGRÉHVDC B ENCHMARK S YSTEMThefirst CIGRÉHVDC benchmark system shown in Fig.1 was proposed in[3].The system is a mono-polar500-kV, 1000-MW HVDC link with12-pulse converters on both rec-tifier and inverter sides,connected to weak ac systems(short circuit ratio of2.5at a rated frequency of50Hz)that provide a considerable degree of difficulty for dc controls.Damped filters and capacitive reactive compensation are also provided on both sides.The power circuit of the converter consists of the following subcircuits.A.AC SideThe ac sides of the HVDC system consist of supply net-work,filters,and transformers on both sides of the converter. The ac supply network is represented by a Thévénin equivalent voltage source with an equivalent source impedance.ACfilters are added to absorb the harmonics generated by the converter as well as to supply reactive power to the converter.B.DC SideThe dc side of the converter consists of smoothing reactors for both rectifier and the inverter side.The dc transmission line is represented by an equivalent T network,which can be tuned to fundamental frequency to provide a difficult resonant condition for the modeled system.C.ConverterThe converter stations are represented by12-pulse configura-tion with two six-pulse valves in series.In the actual converter, each valve is constructed with many thyristors in series.Each valve hasa limiting inductor,and each thyristor has par-allel RC snubbers.IV.CIGRÉHVDC S YSTEM M ODEL IN PSCADThe full three-phase model of the CIGRÉHVDC benchmark system is available as an examplefile in PSCAD/EMTDC Ver-sion4.0.1.Data for the CIGRÉHVDC benchmark system[4],[5]is given in Table V.A.Power Circuit Modeling1)Converter Model:The converters(rectifier and inverter) are modeled using six-pulse Graetz bridge block,which in-cludes an internal Phase Locked Oscillator(PLO),firing and valve blocking controls,andfiringangle/extinctionangle measurements.It also includes built-in RC snubber circuits for each thyristor.Thyristor valves are modeled as ideal devices, and therefore,negative turn-off andfiring due tolargeor are not considered.2)Converter Transformer Model:Two transformers on the rectifier side are modeled by three-phase two winding trans-former,one with grounded Wye–Wye connection and the other with grounded Wye–Delta connection.The model uses satura-tion characteristic and tap setting arrangement.The inverter side transformers use a similar model.3)DC Line Model:The dc line is modeled using an equiva-lent-T network with smoothing reactors inserted on both sides.4)Supply Voltage Source:The supply voltages on both rec-tifier and inverter sides have been represented through three-phase ac voltage sources.5)Filters and Reactive Support:Tunedfilters and reactive support are provided at both the rectifier and the inverter ac sides,as shown in Fig.1.B.Control System ModelThe control model mainly consistsof measurements and generation offiring signals for both the rectifier and inverter. The PLO is used to build thefiring signals.The output signal of the PLO is a ramp,synchronized to the phase-A commutatingbus line-to-ground voltage,which is used to generate the firing signal for Valve 1.The ramps for other valves are generated by adding 60to the Valve 1ramp.As a result,an equidistant pulse is realized.The actual firing time is calculated by comparingthe order to the value of the ramp and using interpolation [10]technique.At the same time,if the valve is pulsed but its voltage is still less than the forward voltage drop,this model has a logic to delay firing until the voltage is exactly equal to the forward voltage drop.The firing pulse is maintained across each valve for 120.Theand measurement circuits use zero-crossing informa-tion from commutating bus voltages and valve switching times and then convert this time difference to an angle (using mea-sured PLO frequency).Firingangle (in seconds)is the time when valve turns on minus the zero crossing time for valve .Extinctionangle (in seconds)for valve is the time at which the commutation bus voltage for valve crosses zero (negative to positive)minus the time valve turns off.The control schemes for both recti fier and inverter of the CIGR ÉHVDC system are available in the example file in PSCAD/EMTDC Version 4.0.1.Following are the controllers used in the control schemes:•ExtinctionAngleController;•dc Current Controller;•V oltage Dependent Current Limiter (VDCOL).1)Rectifier Control:The recti fier control system uses Con-stant Current Control (CCC)technique.The reference for cur-rent limit is obtained from the inverter side.This is done to en-sure the protection of the converter in situations when inverter side does not have suf ficient dc voltage support (due to a fault)or does not have suf ficient load requirement (load rejection).The reference current used in recti fier control depends on the dc voltage available at the inverter side.Dc current on the recti fier side is measured using proper transducers and passed through necessary filters before they are compared to produce the error signal.The error signal is then passed through a PI controller,which produces the necessary firing angleorder .The firing circuit uses this information to generate the equidistant pulses for the valves using the technique described earlier.2)Inverter Control:The Extinction Angle Controlor con-trol and current control have been implemented on the inverter side.The CCC with V oltage Dependent Current Order Limiter (VDCOL)have been used here through PI controllers.The ref-erence limit for the current control is obtained through a com-parison of the external reference (selected by the operator or load requirement)and VDCOL (implemented through lookup table)output.The measured current is then subtracted from the reference limit to produce an error signal that is sent to the PI controller to produce the required angle order.The control uses another PI controller to produce gamma angle order for the inverter.The two angle orders are compared,and the minimum of the two is used to calculate the firing instant.V .CIGR ÉHVDC S YSTEM M ODEL IN PSBThe CIGR ÉHVDC system model developed using PSB/SIMULINK Version 6.5release 13is shown in Fig.9.To implement this model,a total of 106states,37inputs,112outputs,and 31switches were used.A.Power Circuit ModelingThe recti fier and the inverter are 12-pulse converters con-structed by two universal bridge blocks connected in series.The converter transformers are modeled by one three-phase two winding transformer with grounded Wye –Wye connection,the other by three-phase two winding transformer with grounded Wye –Delta connection.The converters are interconnected through a T-network.1)Universal Bridge Block:The universal bridge block im-plements a universal three-phase power converter that consists of six power switches connected as a bridge.The type of power switch and converter con figuration can be selected from the di-alog box.Series RC snubber circuits are connected in parallel with each switch device.The vector gating signals are six-pulse trains corresponding to the natural order of commutation.Theand measurements are not realized in this model.2)Three Phase Source:A three-phase ac voltage source in series with a R-L combination is used to model the source,and its parameters are set as in Table V .3)Converter Transformer Model:The three-phase two winding transformers models have been used where winding connection and winding parameters can be set through mask parameters.The tap position is at a fixed position determined by a multiplication factor applied on the primary nominal voltage of the converter transformers (1.01on recti fier side;0.989on inverter side).The saturation has been simulated.The saturation characteristic has been speci fied by a series of current/flux pairs (in p.u.)starting with the pair (0,0).The dc line,ac filters,and reactive support are similar to the ones used in the PSCAD/EMTDC model.B.Control System ModelThe control blocks available in SIMULINK have been used to emulate the control algorithm described in Section IV-B,and enough care has been taken to ensure that exact parameters as in PSCAD/EMTDC simulation are used.Some control param-eters required conversion to their proper values due to differ-ences in units.The recti fier side uses current control with a ref-erence obtained from the inverter VDCOL output (implemented through a lookup table),and the inverter control has both cur-rent controland control operating in parallel,and the lower output of the two is used to generate the firing pulses.Unlike PSCAD/EMTDC,theangle is not provided directly from the converter valve data.It needed to be implemented through mea-surements taken from valve data.The control block diagrams are shown in Fig.2.VI.PSCAD-SIMULINK I NTERFACEPSCAD Version 4.0.1has the capability of interfacing with MATLAB/SIMULINK commands and toolboxes through a special interface.MATLAB programs or block-sets that would be interfaced,with PSCAD needing to be designed and saved as a MATLAB program file or as a SIMULINK block file.Then,a user-de fined block must be provided in PSCAD,with the neces-sary inputs and outputs,to interface the MATLAB/SIMULINK file.In this paper,the power circuit of CIGR ÉHVDC system has been modeled in the PSCAD/EMTDC environment whileFig.2.CIGR ÉHVDC control system in SIMULINK.(a)Recti fier control.(b)Gamma measurement.(c)Inverter control.the control system has been modeled using block-sets from PSB and the SIMULINK Control Library.An interfacing block has been created in PSCAD/EMTDC that linked the SIMULINK files through FORTRAN scripts de fined within the block.A reverse scenario,where the power circuit is mod-eled in PSB/SIMULINK and the control system is modeled in PSCAD/EMTDC,is also feasible.Fig.3shows the block diagram of PSCAD-SIMULINK interface used to simulate CIGR ÉHVDC system.The time step used for the simulation is50;the two programs exchange information between them continuously at every time step.VII.S IMULATION R ESULTSWith the goal of performing a rigorous comparative study among the simulation tools,the CIGR ÉHVDC system has been simulated in three environments:1)using PSCAD/EMTDC only;2)using PSB/SIMULINK only;3)using the PSCAD-SIMULINK Interface.Steady-state and transient results (created through various faults)were recorded and then compared.The comparison reveals a high degree of similarity among the results obtained through the three simulation environments with minor discrep-ancies.A.Steady StateFor steady-state analysis,the system has been simulated for a duration of 2s in all three simulation environments.There were some initial transients that subsided within about 0.5s and the system reached steady state.1)DC Voltages and Currents:Fig.4shows the results where the first column is produced by PSCAD/EMTDC,the second from PSB/SIMULINK,and the third by the PSCAD-SIMULINK interface.Row-wise,the first row shows the recti fier dc voltage produced by the three simulation tools;the second and fourth row are the magni fied view of dc voltages on both the recti fier and inverter side;the third and fifthrowFig.3.PSCAD-SIMULINK interface.show the harmonic spectrum.The following observations can be made from Fig.4.•For both inverter and recti fier,the dc voltages show small oscillations around the reference value (1p.u);however,they are almost identical,except for minor differences at start-up.During initialization,PSCAD/EMTDC and PSCAD-SIMULINK interface do not show any negative dc voltage,whereas PSB/SIMULINK shows a negativetransientp.u .However,all three simulation tools have produced identical waveforms in terms of phase and magnitude in steady state,and there is hardly any discrep-ancy among them.The zoomed view of their steady-state waveforms re flects that fact.•The mean of output dc voltage produced by PSCAD/EMTDC and PSCAD-SIMULINK interface falls short of reference outputs by (1–2)%(0.99p.u.for PSCAD/EMTDC and 0.98p.u.for PSCAD-SIMULINK interface),whereas it is 1.0p.u.for PSB/SIMULINK.•The Fourier spectrum of the corresponding waveforms have very few differences.The dc component is close to 1.0for all environments,but in the plot,it is not shown in full magnitude,for the sake of highlighting the harmonicsFig.4.Steady-state results for dc voltage.TABLE IC OMPARISON OF THD(%),M EAN,AND MAD FOR DC V OLTAGES AND C URRENTS P RODUCED BY D IFFERENT S IMULATION TOOLSpresent in the signal.The THDs found in the three cases for different waveforms are also very close.•Table I shows further information about thefine differ-ences in terms of mean value,THD,and Mean Absolute Deviation(MAD).Close results have also been observed for dc currents on both the rectifier and inverter sides. 2)AC Voltages and Currents:All ac side waveforms on both the rectifier and inverter sides have also been compared. The results were found to be similar,and only the ac current waveforms and their harmonic spectrum are shown in Fig.5. Both rectifier and inverter ac currents are similar in terms of phase angle and their magnitude;their spectrum is identical, which reaffirms the accuracy of all three simulation techniques. The11th and13th harmonics are the dominant harmonics on both rectifier and inverter sides;their THDs have been found to be close for all simulation environments.Table II compares other control outputs(,inverter,and rectifier). PSCAD-SIMULINK shows the maximum rectifier(17.28), while PSB/SIMULINK shows the minimum(14.44).This result agrees with the mean value of the dc voltage produced on the rectifier side by the three simulation environments.Sim-ilarly,for,PSCAD-SIMULINK shows the highest(15.72), and PSB/SIMULINK shows the lowest(14.95).However, these differences are small,and the produced results are con-sistent.B.TransientsDc and ac faults have been simulated in the three simula-tion environments.The instant and duration of faults have beenFig.5.Steady-state results for ac currents on the recti fier and inverter side.TABLE IIC OMPARISON OF O UTPUTS P RODUCED BY C ONTROL SYSTEMSmaintained the same for all types of faults,i.e.,the fault is ap-plied at 1.0s and cleared after 0.15s.The fault resistance hasbeen chosen as0.1and1for fault-on and fault-off situa-tions,respectively.Clearing of the fault has been allowed,even when there is a fault current flowing.1)Dc Fault:This fault has been located at the midpoint of the dc line.Fig.6illustrates different output parameters of the system.The transient response in all three simulation environ-ments has been found almost similar.During the fault,the dc voltage has gone down to zero (the small oscillation is due to the energy stored in the capacitor),and a momentary transient dc current has been observed.However,control response forces recti fier andinverter to reach maximum andinverter to reach minimum,thereby reducing the current flow.VDCOL forces the current to stay minimum until the dc voltage situation is improved.Once the fault is cleared,the dc voltage is recov-ered,and the control system brings the system back to normal operation.The transient response for all three simulation envi-ronments has been compared in terms of Rise Time (RT),Set-tling Time (ST),and Overshoot (OS)in Table III.2)AC Faults:Two cases of ac faults have been simulated:One is a single line-to-ground fault (see Fig.7),and the other is a three-phase to ground fault (see Fig.8).Both are applied on the inverter side of the system.During fault,the dc voltage has gone down to zero (neglecting oscillation due to capacitor energy storage),the dc current faces a momentary overshoot,and then goes to minimum limit with some oscillation present (due to the oscillation of dc voltage).Recti fier ,inverter ,andinverter reach to maximum value,thereby blocking the system for the fault duration.Once the fault is cleared,the system comes back to its normal operation.During an ac fault,commutation failures happen,resulting in a momentary drop-down of dc voltage.This causes the VDCOL to limit the dc current to a minimum,and ac voltages also get disturbed (not shown in the figure).The voltage and current waveforms for the three environments are similar;however,the following minor discrepancies were observed.•In all three cases,the rise-time for inverter dc voltage for ac faults is shorter than that for the dc fault.Even though PSCAD/EMTDC and PSCAD-SIMULINK showFig.6.V oltages and currents under a short duration dc fault.a faster rise than PSB/SIMULINK case,PSB/SIMULINKreaches steady state before the other two cases.•The highest transient values of inverter dc currents during the phase-to-ground fault are 2.58p.u.for PSCAD/EMTDC, 2.4p.u.for PSB/SIMULINK,and2.39p.u.for PSCAD-SIMULINK.•The peak value of inverter ac current for the single phase-to-ground fault is13.2kA for PSCAD/EMTDC, 14kA for PSB/SIMULINK,and13kA for PSCAD-SIMULINK.•In case of the three-phase to ground fault,when the faultis clearedat,in all the three environments,thesystem is brought back to normal operation within0.05 s;however,PSCAD/EMTDC and PSCAD-SIMULINK could not stabilize the system,i.e.,after a small over-shoot,the system collapses again,though it regains the control very fast,and the system stability is restored.PSB/SIMULINK,however,does not show this behavior.C.Execution Time and MemoryAll three environments were run on a Pentium IV1.5–GHz processor running Windows2000operating system.The ex-ecution time was recorded from the Time Summary shown on the output window in PSCAD/EMTDC and by using the cputime function at the start and end of the simulation in PSB/rmation on memory usage was collected from the System Performance Monitor on Windows2000. Although resource requirements for both programs may not be the same,attempts have been made to allow no other programs except the systemfiles to run while the simulations were performed.Table IV shows the execution time and memory usage for the three environments.PSCAD/EMTDC was found to be the fastest environment,while PSCAD-SIMULINK Interface was the slowest.For a simulation duration of2s, PSCAD/EMTDC took30.5s with a memory usage of42 MB,whereas PSB/SIMULINK took72.2s with a memory usage of107MB.In comparison to these two environments, PSCAD-SIMULINK took a much longer execution time;using a50sampling period in both PSCAD and SIMULINK environments,the execution time was found to be12503.58s with a memory usage of63MB(24MB for PSCAD and39MB for SIMULINK).The reason for such a long simulation time is the necessity of data exchange between the two programs at every50;the memory usage for the interface was less than the other two environments due to the task partition(electrical system in PSCAD and control system in SIMULINK).A higher control sampling period reduced the execution time by a very small margin(2.5%for100);however,it also reduced the accuracy of the simulation.TABLE IIIC OMPARISON OF R ISE T IME (RT)(S ),S ETTLING T IME (ST)(S ),AND O VERSHOOT (OS)(P .U .)D URING R ECOVERY F ROM A DC FAULTFig.7.V oltages and currents under a short duration ac fault (phase-A to ground)on the inverter side.D.General RemarksBoth PSCAD/EMTDC and PSB/SIMULINK provides user-friendly graphics for modeling power and control systems through simple functional blocks.However,the following minor differences particular to this case study,are worth men-tioning.•PSCAD/EMTDC is a specialized software designed mainly for the analysis of ac/dc systems.Therefore,it has added advantages such as built-in PLO-based firingcontrol and the measurementofangles embedded inside the six-pulse Garetz bridge .On the other hand,PSB/SIMULINK requires these blocks and the measure-ment system to be developed by the user.•PSB/SIMULINK offers more flexibility in terms of choice of the solution techniques:fixed or variable time-step-based solutions.However,for this study,a fixed step-size trapezoidal rule has been used to be consistent with PSCAD/EMTDC.•The error debugging system in PSCAD/EMTDC is quite complex.In some cases,instead of locating the exact source of error,it returned general error messages.VIII.C ONCLUSIONSA detailed comparison of the performance of three simu-lation environments (PSCAD/EMTDC,PSB/SIMULINK,and PSCAD-SIMULINK Interface)has been demonstrated by mod-eling the CIGR ÉHVDC Benchmark System.All three environ-ments produced almost identical and consistent results during steady-state and transients situations,validating the accuracy of the modeling and solution algorithms.In terms of computationalFig.8.V oltages and currents under a short duration ac fault(three-phase to ground)on the inverter side.Fig.9.CIGRÉHVDC benchmark system model in PSB/SIMULINK.TABLE IVE XECUTION T IME (ET)(S )AND M EMORY U SAGE (MU)(MB)FORAS IMULATION D URATION OF 2S W ITH A T IME S TEP OF 50sTABLE VCIGR ÉHVDC B ENCHMARK S YSTEM DATAspeed and memory usage,PSCAD/EMTDC was found to be the most ef ficient environment.A PPENDIXTable V shows the CIGR ÉHVDC benchmark system data.R EFERENCES[1] D.A.Woodford,A.M.Gole,and R.W.Menzies,“Digital simulationof DC links and AC machines,”IEEE Trans.Power App.Syst.,vol.102,no.6,pp.1616–1623,Jun.1983.[2]L.-A.Dessaint,H.Le-Huy,G.Sybille,and P.Brunelle,“A power systemsimulation tool based on SIMULINK,”IEEE Trans.Ind.Electron.,vol.46,no.6,pp.1252–1254,Dec.1999.[3]J.D.Ainsworth,“Proposed benchmark model for study of HVDC con-trols by simulator or digital computer,”in Proc.CIGRE SC-14Colloq.HVDC With Weak AC Systems ,Maidstone,U.K.,Sep.1985.[4]M.Szechtman,T.Wess,and C.V .Thio,“First benchmark model forHVDC control studies,”Electra ,no.135,pp.54–67,Apr.1991.[5],“A benchmark model for HVDC system studies,”in Proc.Int.Conf.AC/DC Power Transmission ,Sep.17–20,1991,pp.374–378.[6]P.Lehn,J.Rittiger,and B.Kulicke,“Comparison of the ATP versionof the EMTP and the NETOMAC program for simulation of HVDC systems,”IEEE Trans.Power Del.,vol.10,no.4,pp.2048–2053,Oct.1995.[7]W.Freitas and A.Morelato,“Comparative study between power systemblockset and PSCAD/EMTDC for transient analysis of custom power devices based on voltage source converter,”in Proc.Int.Conf.Power Systems Transients ,New Orleans,LA,2003,pp.91–96.[8] F.Jurado,N.Acero,J.Carpio,and M.Castro,“Using various computertools in electrical transient studies,”in Proc.Int.Conf.30th ASEE/IEEE Frontiers in Education ,Kansas City,MO,Oct.18–21,2000,pp.F4E17–F4E22.[9]PSCAD/EMTDC User ’s Manual ,Manitoba HVDC Research Centre,2001.[10]G.D.Irwin,D.A.Woodford,and A.Gole,“Precision simulation ofPWM controller,”in Proc.Int.Conf.Power System Transients ,Rio de Janeiro,Brazil,2001,pp.301–306.[11]Power System Blockset User ’s Guide ,TEQSIM International,Inc.,2001.M.O.Faruque (S ’03)received the B.Sc.Engg degree in 1992from Chittagong University of Engineering and Technology (CUET),Chittagong,Bangladesh,and M.Eng.Sc.degree in 1999from the University of Malaya,Kuala Lumpur,Malaysia,in the area of power engineering.He is working toward the Ph.D.degree from the Department of Electrical and Computer Engineering,University of Alberta,Edmonton,AB,Canada.For the last ten years,he has been working in both academia and industry,and his research interests include FACTS,HVDC,and real-time digital simulation of power electronics and power systems.Yuyan Zhang received the Bachelor ’s degree in electrical engineering from South-East University,Nanjing,China,in 1990and the M.E.degree from the University of Alberta,Edmonton,AB,Canada in 2003.Since then,she has worked as an Electrical Engineer for a variety of indus-tries,including the Beijing Chemical Plant,Hongkong Well fine Ltd.,Motorola China Ltd.,and Siemens Ltd.,China,in the power generation group.Her re-search interests are in the area of power distribution systems,HVDC,and digital simulation.Venkata Dinavahi (M ’00)received the B.Eng.degree in electrical engineering from Nagpur University,Nagpur,India,in 1993,the M.Tech.degree from the Indian Institute of Technology,Kanpur,India,in 1996,and the Ph.D.degree in electrical and computer engineering from the University of Toronto,Toronto,ON,Canada,in 2000.Presently,he is an Assistant Professor at the University of Alberta,Edmonton,AB,Canada.His research interests include electromagnetic transient analysis,power electronics,and real-time simulation and control.Dr.Dinavah is a member of CIGR Éand a Professional Engineer in the Province of Alberta,Canada.。
BDS Start to End Simulation说明书
BDS, Start to End Simulation, BDS Start to End Simulation Simulation Codes Summary yD. SchulteD SchultePresentations•Deepa Angal-Kalinin: Beam dynamics issues in BDSg p •Peter Tenenbaum: Possible migration to Accelerator Makeup Language•Glen White: BDS tuning simulation•Andrea Latina:Static and Dynamic Alignment of the CLIC BDS Andrea Latina: Static and Dynamic Alignment of the CLIC BDS •Javier Resta Lopez: Start to End simulations with intra-train feedbackTony Hartin:Luminosity performance with multiple feedbacks •Tony Hartin: Luminosity performance with multiple feedbacks •Peter Tenenbaum: Lucretia status and plans•Andrea Latina: PLACET : New features and plans•Paul Lebrun: CHEF status and plan•Roger Barlow: Issues in Simulating the Effects of Wakefields •Steve Malton: Interfacing BDSIM with PLACET, wakefield Steve Malton:Interfacing BDSIM with PLACET wakefieldcalculations of collimator•Isabell Melzer-Pellmann: Lumi scans with wakefields in MerlinBDS tasks related to LET (1)()•BDS has the most different styles of magnets;BDS has the most different styles of magnets;standardize the magnets and reduce the styles •Magnets on strings–Additional correctors/PSs–How will it affect the tuning + beam basedalignment–How will it affect the performance after push-pull •Temperature requirements in the tunnel and its effect on beam stabilityb bili•Stability requirements for push-pull•Angle feedback and integration of other feedbacks?Angle feedback and integration of other feedbacks?•Effect of wakes from pumping ports, vacuum chamber misalignments, resistive wall, IR wakes, HOM heating, wake fields from crab, spoilers, other transitions….k fi ld f b il th t itiBDS tasks related to LET (2) Laser wire•Define requirements on emittance measurement (absolute/relative) of train (or bunch) every ? second? Æbeam tuning procedureof train(or bunch)every?second?beam tuning procedure •The present design of laser wire assumes 300 scans per train, which drives the requirements of the laserD d b t i di ti b t lli ti•Do we need any beam spotsize diagnostics between collimation region and IP (somewhere in the final focus?)yCrab system–To understand and verify requirements on the crab cavity mode damping from beam dynamics point of view. e.g.g,y 10E+4 for SOM is difficult from RF design, but may berelaxed with intra-train feedback?–The alignment of crab cavity and effects of the orbit offset in sextupoles may be perhaps fixed with some smallin sextupoles may be perhaps fixed with some smallvertical crab cavity nearby the main one.•Low energy parameters•Work plan is being developed•Lattices to be frozen in autumBDS AlignmentBDS Ali t100nm BPM resolution needed in sextupoles•100nm BPM resolution needed in sextupoles•Quad shunting+DFSy p–Is the systematic error important?•Multi-knobs, also high order needed•Studies using one beam and it’s mirror yield 90% at better than 110%l i it110% luminosity–Independent beams yield 90% at better than75%slower convergence–slower convergence•1e-3 magnet error significantly impacts convergence•Intra-pulse beam-beam offset feedback kick limited by sextupole •200nm stability requirement for quadrupoles•Main goal is to have a verification by another studyATF2•ATF2 is an important test•Can take advantage of flight simulators•Need to fully study alignment and tuning Need to fully study alignment and tuning –E.g. losses can be a problem•Simulation of ATF2Simulation of ATF2–Spot size measurement is slow (1 minute)–Convergence speed crucial–Spot size growth 1nm/hourCLIC BDS Alignment •Few-to-few and DFS used•DFS problematic since response to energy deviation not linear•Collimations system alignment works •FFS alone does not workFull optimisation (brute force) with simplex •Full optimisation(brute force)with simplex works on 50% of the casesy–No solution yet•Could still be starting point for ILC second BDS alignment studyg yCLIC BDS Dynamic Effects•Choice of orbit feedback gain–Ground motion requires yields gain>0.01 tocorrect orbit–BPM resolution requires gain<0.3BPM l ti i i03•Very tight quadrupole stability requirements –Fractions of nm for final doublet–Nanometer for other magnets–Need to use stabilisation•Should also run this for ILCI t t d F db k St di Integrated Feedback Studies Continuation of studies started by Glen •Continuation of studies started by Glen•From linac to IP–Including fast IP feedbackIncluding fast IP feedback–Bunch compressor should come soonMulti bunch tracking•Multi-bunch tracking–Realistic main linac, undulator not usedy g y •Ground motion C or K yield 85% of target luminosity •Smoother luminosity increase during feedback than before–Banana effect is less important•Crab cavities and collimator wakefields to be includedFeedback Optimisation •Basic idea is to exploit luminosityinformation to speed up beam-beam i f ti t d b boffset feedback convergence•Based on Javier’s integrated simulation •Luminosity based on pair signal Luminosity based on pair signal•Optimise gain for minimum luminosity loss•Looks an interesting approachBeam-Beam Scans •Translate emittance growth intoluminosity lossTry to optimise collision in presence of •Try to optimise collision in presence of imperfection along the machine •Banana effect is reduced compared to B ff t i d d d t TESLAWakefield Models •Linear wakefields seem OK for main studiest di•Need something better for loss studiesg•Uncertainties still exist–Comparison between formulaeComparison between formulae•Check proper implementationBenchmarking with experiments–Benchmarking with experiments•Experiments are not easyBDSIM-PLACET Interface•BDSIM is a vital code for BDS studies –Halo and background studies–But not aimed at alignment and tuning studies •Geometry information–Currently: Halo tracking in BDSIM, core inPLACET–General lattice information–ImperfectionsDeck Format•Current deck format is based on XSIF –Parser is available and can be added to programs P i il bl d b dd d t•Slow transition to AML is planned–Until 2010 both formats (XSIF+AML) will beU til2010b th f t(XSIF AML)ill bsupportedAML is similar to XML–AML is similar to XML–An AML parser is available and can be used •Can also read and write SIF•Has been tied to PLACET•Plans exist to tie it to SAD, LUCRETIA and MERLINLUCRETIA •MATLAB based toolkit–Performs tracking–Correction and tuning is user supplied •LIAR and DIMAD are no longer supported •Mass production runs using MATLAB compiler •Used for ATF2•To be included–UndulatorU d l t–IR solenoid–Better cavity wakesBetter cavity wakes•Reference documentation availableTutorial to come–Tutorial to come•Way cool with it’s own cultPLACET•tcl/tk and OCTAVE interfacey–Dynamic libraries•AML interface+some more available •Coherent/incoherent synchrotron radiation •Collimator wakes, also from GdfidL •Misalignment, correction and tuning routines are includedi l d d–Can use your own ones, if you like •Preliminary MPI version existsPreliminary MPI version exists•Halo and tail generation module•Some reference manual availableSome reference manual available–Tutorials on the webOnline help–Online help•Used for ATF2CHEF•A libraryA library–Contains tracking–Correction and tuning left to the userp •Wakefields are to be improved •Significant modifications•XSIF interface rewrittenSome concerns about status of AML •Some concerns about status of AMLConclusion•Integrated simulations move forward •Confirmation of BDS alignment is neededg p •Interesting ideas on feedback improvements •Several codes are being developed–Way cool, way hot...Way cool way hot•More work to be done。
动态电压恢复器(DVR)的PI和模糊调节器-推荐下载
动态电压补偿（DVR）的PI和模糊调节器设计K. Sandhyaa*, Dr. A. Jaya Laxmib, Dr. M.P. Soni0 1．介绍当今，现代工业应用大多是基于可编程序逻辑控制器等电子设备和电子驱动器。
电子器件特别容易受到干扰，并且越来越不能忍受比如电压降低，升高，谐波等电能质量问题。
对工业设备来说，电压骤降被认为是最严重的干扰之一。
通过在负载共同连接点注入无功功率，能够在负载处获得电压补偿。
解决这一问题的一种普通方法是在配电变压器一次侧末端安装并联电容器。
而这种方法的缺点是，高速瞬变不能被补偿。
另外一种解决电压调整的电力电子方法是使用用户电力装置。
DVRs是为提供可靠的分配电能质量的一种用户电力装置。
2．电能质量问题的解决办法有两种方法可以缓解电能质量问题。
这种解决电能质量问题的方法可以从用户侧或者公共侧实施。
第一种方法叫负载调整，它可以确保装置对电能干扰的灵敏度降低，甚至可以允许在严重的电压畸变下操作。
另外一种方法是安装线路调节系统，它可以抑制或者抵消电网的干扰。
当前，这些方法是基于PWM转换，并且与并联或者串联下的低压和中压分布系统有关。
一些有效经济的方法是使用避雷器，基于晶闸管的静态开关，储能系统。
尽管有许多不同的方法来缓解电压上升和下降的情况，但是最有效的方法还是使用用户用电装置。
用许多不同种类的用户用电装置。
包括用功功率滤波器（APF），电池储能系统（BESS），配电静止同步补偿器（DSTATCOM），分布系列电容器（DSC），动态电压恢复器（DVR），避雷器（SA），超导磁能源系统（SMES），静态电子释放器（SETC），固态转换开关（SSTS），固态故障电流限流器（SSFCL），静止无功补偿装置（SVC），晶闸管投切电容器（TSC）和不间断电源（LTPS）。
其中，DVR是基于VSC原理的一个有效的用户用电装置，它可以解决电压下降和上升问题。
3．动态电压恢复器（DVR）动态电压恢复器（DVR），是用在配电网络中的最有效率和最有效的现代用户用电装置。
动态电压恢复器的原理及控制综述
动态电压恢复器的原理及控制综述KONG Shuhong, YIN Zhongdong，SHANRenzhongNorth China Electric Power UniversityBeijing , Chinae-mail: kshsh043@SHANG WeidongKaifeng Power Supply CompanyHenan，China摘要随着自动化技术信息化的发展，动态电压问题日益凸显。
动态电压恢复器（DVR）是现代配电系统中重要的缓解电压暂降的电力设备。
DVR的工作原理、结构和控制方法在许多DVR相关的学术会议和期刊上被引用和比较。
同时对未来DVR在电力系统中的应用和一些问题提出了建议。
关键词：电压暂降;动态电压恢复器（DVR）；控制技术；电能质量；优化的补偿；储能I引言最近几年，社会对于高功率质量（PQ）和电压稳定性的要求显著增加。
PQ 特性包括频率变化，电压变化，电压波动，不平衡三相电压，电压突变和谐波失真。
对于敏感的设备的一个严重威胁是持续10至100毫秒的电压暂降（60％至90％的额定电压的下降）。
电压暂降是因为大功率电机并网或切换操作时由动物接触，暴风雨，设备故障，绝缘故障，短路冲击电流较大等因素引起的。
这将导致巨大的财产和经济损失。
众所周知的保护关键负载不受干扰的定制功率器件有：STA TCOM分布（静止同步补偿器DSTATCOM），动态电压恢复器（DVR）和统一电能质量调节器（UPQC）。
DVR主要用于解决电压暂降问题。
1996年8月，Westinghouse电气公司在加利福尼亚州南部的Anderson在12.47KV变电站安装了世界上第一台DVR。
它主要为自动生产的工厂提供保护。
随后，ABB，西门子等其他公司也开发了自己的的产品来保证敏感负载的电压质量。
所以，在DVR的结构，参数检测，闭锁，补偿和控制技术等方面进行了大量的电力系统的研究。
在这片论文里，将对DVR的控制技术和结构进行调查和比较。
含超级电容储能的直驱永磁风电机组高电压穿越控制策略
含超级电容储能的直驱永磁风电机组高电压穿越控制策略孙谊媊;南东亮;张公生【摘要】为提高直驱永磁风电机组的高电压穿越(HVRT)能力,在分析电网电压骤升对直驱风机影响的基础上,提出了一种含超级电容储能的HVRT控制策略.在高电压故障期间,一方面利用超级电容储能吸收直流侧不平衡能量,稳定直流侧电压;另一方面优化网侧变流器控制策略,使之优先输出感性无功功率对故障电网进行无功支撑.在Matlab/Simulink环境中搭建系统仿真模型,对电网电压骤升下传统直驱机组控制策略的动态响应及所提的控制策略进行仿真分析.结果表明,含超级电容储能的HVRT控制策略可以有效提高直驱机组的高电压穿越能力.【期刊名称】《电气传动》【年(卷),期】2018(048)010【总页数】6页(P48-52,84)【关键词】直驱永磁风电机组;超级电容储能;网侧控制策略;高电压穿越【作者】孙谊媊;南东亮;张公生【作者单位】国网新疆电力有限公司电力科学研究院,新疆乌鲁木齐 830011;国网新疆电力有限公司电力科学研究院,新疆乌鲁木齐 830011;新疆大学教育部可再生能源发电与并网控制工程技术研究中心,新疆乌鲁木齐 830047【正文语种】中文【中图分类】TM614随着大规模高集中度风电持续接入电力系统，电网对并网风电机组的运行要求将日趋严格。
除了要求风电机组具有低电压穿越能力外，在最新的国家电网企业标准中已明确要求风电机组也要具备HVRT能力[1-3]，即当电网电压在短时骤升或长时间轻微骤升时，风电机组能够连续不脱网运行。
在实际的风电系统中，单相经弧光接地故障，风电场负载的突然切除，低电压过后无功补偿设备切除不及时或配合不协调等都会引起电网电压骤升故障。
2012年，河北某风电场发生大规模脱网事故就是因为低电压过后，由于无功调节不及时，导致电网电压骤升，大量风电机组因不具备HVRT能力而脱网，严重影响电网稳定运行[4]。
当前，针对并网风电机组HVRT的要求，国外大多制定了具体的运行导则，其中澳大利亚要求当电网电压骤升到电网额定电压的130%时，要求风电机组能够持续运行60 ms，并在故障期间提供足够大的故障电流支撑[5]，而我国在最新并网规定中要求电网电压骤升至120%额定电压时，风电机组能够持续200 ms不脱网运行。
智能电网专业名词英文对照资料
Transformer terminal uint Universal interconnect technology Unified modeling language
Modern grid initiative Manufacturing messaging specification Multi-service transfer platform National Renewable Energy Laboratory Outage management system Optical fiber composite low-voltage Cable
UPFC UPQC UPS VOD VRB VSC WAMS WAN WAP WAS A WDM WARMAP
XML
Unified power flow controller Unified power quality controller Uninterruptible power supply Video on demand Vansourced converter Wide area measurement system Wide area network Wide-area protection Wide area situational awareness Wavelength division multiplexing Wide area monitoring analys is protection-control
SIMATIC Energy Manager PRO V7.2 - Operation Operat
2 Energy Manager PRO Client................................................................................................................. 19
2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.5.1 2.1.5.2 2.1.6
Basics ................................................................................................................................ 19 Start Energy Manager ........................................................................................................ 19 Client as navigation tool..................................................................................................... 23 Basic configuration ............................................................................................................ 25 Search for object................................................................................................................ 31 Quicklinks.......................................................................................................................... 33 Create Quicklinks ............................................................................................................... 33 Editing Quicklinks .............................................................................................................. 35 Help .................................................................................................................................. 38
电铲工作装置EDEM Adams Simulink联合动态仿真
电铲工作装置EDEM Adams Simulink联合动态仿真作者：邹伟程书培杨磊周航来源：《计算机辅助工程》2020年第01期摘要：针对电铲工作装置驱动力设计问题，使用EDEM计算挖掘阻力，计算结果与理论值一致。
在Adams中建立电铲工作装置动力学模型，利用Simulink生成接近实际的提升和推压位移曲线，并将EDEM输出的挖掘阻力转化为挖掘阻力曲线，实现AdamsSimulink联合仿真。
挖掘轨迹、驱动力仿真结果与理论计算结果一致。
该方法可克服传统计算只取个别位姿的不足，为后续设计提供依据。
关键词：电铲; 工作装置; 驱动力; 挖掘阻力; 联合仿真; 动态仿真中图分类号：TD422.21; TP391.99文献标志码：BEDEMAdamsSimulink dynamic cosimulation ofpower shovel manipulatorZOU Wei， CHENG Shupei， YANG Lei， ZHOU Hang（China Railway Engineering Machinery Research and Design Institute Co.， Ltd.， Wuhan 430066， China）Abstract：As to the driving force design for the power shovel manipulator， the digging resistance is calculated by EDEM， and the results agree well with the theoretical values. The dynamic model of the power shovel manipulator is built in Adams. The displacement curves of hoisting and crowding are obtained by Simulink， which is closed to the real process. The digging resistances outputted by EDEM are converted to a digging resistance curve. The cosimulation of AdamsSimulink is achieved. The simulation results of digging trace and driving force are consistent with the theoretical calculation values. This method can overcome the disadvantage of traditional calculation which only takes individual postures， and it can provide a basis for subsequent design.Key words：power shovel; manipulator; driving force; digging resistance; cosimulation; dynamic simulation 0引言電铲即电动机械挖掘机，是露天矿山开采系统中最关键的设备之一。
NVIDIA DOCA虚拟设备用户指南说明书
User GuideTable of Contents Chapter 1. Mediated Devices (1)1.1. Related Configuration (1)Chapter 2. VirtIO-net Emulated Devices (3)2.1. VirtIO-net Controller (3)2.1.1. SystemD Service (3)2.1.2. User Frontend (4)2.1.3. Controller Recovery (4)2.2. VirtIO-net PF Devices (5)2.2.1. VirtIO-net PF Device Configuration (5)2.2.2. Creating Hotplug VirtIO-net PF Device (6)2.3. VirtIO-net SR-IOV VF Devices (6)2.3.1. Virtio-net SR-IOV VF Device Configuration (7)2.3.2. Creating Virtio-net SR-IOV VF Devices (7)Chapter 1.Mediated DevicesNVIDIA mediated devices deliver flexibility in allowing to create accelerated devices without SR-IOV on the BlueField® system. These mediated devices support NIC and RDMA and offer the same level of ASAP2 offloads as SR-IOV VFs. Mediates devices are supported using mlx5 sub-function acceleration technology.Two sub-function devices are created on the BlueField device upon boot (one per port if the port is in switchdev mode) using commands from /etc/mellanox/mlnx-sf.conf:/sbin/mlnx-sf -a create -d 0000:03:00.0 -u 61a59715-aeec-42d5-be83-f8f42ba8b049 --mac 12:11:11:11:11:11/sbin/mlnx-sf -a create -d 0000:03:00.1 -u 5b198182-1901-4c29-97a0-6623f3d02065 --mac 12:11:11:11:11:12The help menu for mlnx-sf is presented below:Usage: mlnx-sf [ OPTIONS ]OPTIONS:-a, -action, --action <action> Perform actionaction: { enable | create | configure | remove | show | set_max_mdevs |query_mdevs_num }-d, -device, --device <device> PCI device<domain>:<bus>:<device>.<func> (E.g.: 0000:03:00.0)-m, -max_mdevs, --max_mdevs <max mdevs number> Set maximum number of MDEVs-u, -uuid, --uuid <uuid> UUID to create SF with-M, -mac, --mac <MAC> MAC to create SF with-p, -permanent, --permanent [<conf file>] Store configuration to be used after reboot and/or driver restart. Default (/etc/mellanox/mlnx-sf.conf).-V, -version, --version Display script version and exit-D, -dryrun, --dryrun Display commands only-v, -verbose, --verbose Run script in verbose mode (print out every step of execution)-h, -help, --help Display help"/etc/mellanox/mlnx-sf.conf" can be updated manually or using "mlnx-sf" tool with "-p" parameter.1.1. Related ConfigurationInterface names are configured using the UDEV rule under /etc/udev/rules.d/82-net-setup-link.rules.SUBSYSTEM=="net", ACTION=="add", ATTR{phys_switch_id}!="", ATTR{phys_port_name}!="", \IMPORT{program}="/etc/infiniband/vf-net-link-name.sh $attr{phys_switch_id} $attr{phys_port_name}" \NAME="$env{NAME}", RUN+="/sbin/ethtool -L $env{NAME} combined 4"# MDEV network interfacesMediated DevicesACTION=="add", SUBSYSTEM=="net", DEVPATH=="/devices/pci0000:00/0000:00:00.0/0000:01:00.0/0000:02:02.0/0000:03:00.0/61a59715-aeec-42d5-be83-f8f42ba8b049/net/eth[0-9]", NAME="p0m0"ACTION=="add", SUBSYSTEM=="net", DEVPATH=="/devices/pci0000:00/0000:00:00.0/0000:01:00.0/0000:02:02.0/0000:03:00.1/5b198182-1901-4c29-97a0-6623f3d02065 net/eth[0-9]", NAME="p1m0"NVMe SNAP uses p0m0 as its default interface. See /etc/nvme_snap/sf1.conf.Chapter 2.VirtIO-net Emulated DevicesThis feature enables users to create VirtIO-net emulated PCIe devices in the system where the NVIDIA® BlueField®-2 DPU is connected. This is done by the virtio-net-controller software module present in the DPU. Virtio-net emulated devices allow users to hot plug up to 31 virtio-net PCIe PF Ethernet NIC devices or 504 virtio-net PCI VF Ethernet NIC devices in the host system where the DPU is plugged in.DPU software also enables users to create virtio block PCI PF and SR-IOV PCI VF devices. This is covered in the NVIDIA BlueField SNAP and virtio-blk SNAP Documentation.2.1. VirtIO-net ControllerVirtio-net-controller is a systemd service running on the DPU, with a user interface frontend to communicate with the background service. An SF representor is created for each virtio-net device created on the host. Virtio-net controller only uses an SF number ≥1000.Note: It is important to note that since the controller provides hardware resources andACKs the request from the host's VirtIO driver, in order to reboot the DPU and host OS, it isnecessary to reboot the host OS first, and only then reboot the DPU.Note: SF representor name is determined by udev rules. The default name is in the format of<prefix><pf_num><sf_num>. For example: en3f0pf0sf1001.2.1.1. SystemD ServiceController systemd service is enabled by default and runs automatically ifVIRTIO_NET_EMULATION_ENABLE is true from mlxconfig.1.To check controller service status, run:systemctl status virtio-net-controller.service2.To reload the service, make sure to unload virtio-net/virtio-pcie drivers on host. Then run:systemctl restart virtio-net-controller.service3.To monitor log output of the controller service, run:journalctl -u virtio-net-controllerThe controller service has an optional configuration file which allows users to customize several parameters. The configuration file should be defined on the DPU at the following path /opt/mellanox/mlnx_virtnet/virtnet.conf.This file will be read every time the controller starts. Dynamic change of virtnet.conf is not supported. It is defined as a JSON format configuration file. The currently supported options are:‣ib_dev_for_static_pf – the RDMA device (e.g, mlx5_0) which the static VirtIO PF is created on‣is_lag - whether or not LAG is used. Note that if LAG is used, make sure to use the correct IB dev for static PF.For example, the definition below has all static PFs using mlx5_0 (port 0) as the data path device in a non-lag configuration.{"ib_dev_for_static_pf":"mlx5_0", 190"is_lag":0}2.1.2. User FrontendTo communicate with the service, a user frontend program, virtnet, is installed on the DPU. Run the following command to check its usage:# virtnet -husage: virtnet [-h] [-v] {hotplug,unplug,list,query,modify,log} ...Nvidia virtio-net-controller command line interface v1.0.9positional arguments:{hotplug,unplug,list,query,modify,log}** Use -h for sub-command usagehotplug hotplug virtnet deviceunplug unplug virtnet devicelist list all virtnet devicesquery query all or individual virtnet device(s)modify modify virtnet devicelog set log leveloptional arguments:-h, --help show this help message and exit-v, --version show program's version number and exitNote that each positional argument has its own help menu as well. For example:# virtnet log -husage: virtnet log [-h] -l {info,err,debug}optional arguments:-h, --help show this help message and exit-l {info,err,debug}, --level {info,err,debug}log level: info/err/debug2.1.3. Controller RecoveryIt is possible to recover the control and data planes if communications are interrupted so the original traffic can resume.Recovery depends on the JSON files stored in /opt/mellanox/mlnx_virtnet/recovery where there is a file that corresponds to each device (either PF or VF). The following is an example of the data stored in these files:{{"pf_id": 0,"function_type": "pf","device_type": "hotplug","mac": "7e:f5:1b:79:79:75","pf_num": 0,"sf_num": 1000"rx_mode": 0}}These files should not be modified under normal circumstances. However, if necessary, advanced users may tune settings to meet their requirements. Users are responsible for the validity of the recovery files and should only perform this when the controller is not running.Note: Controller recovery is enabled by default and does not need user configuration orintervention unless a system reset is needed or BlueField configuration is changed (i.e. any of the mlxconfig options PCI_SWITCH_EMULATION_NUM_PORT, VIRTIO_NET_EMULATION_NUM_VF, or VIRTIO_NET_EMULATION_NUM_PF). To this end, the files under /opt/mellanox/mlnx_virtnet/recovery must be deleted.2.2. VirtIO-net PF DevicesThis section covers managing virtio-net PCIe PF devices using virtio-net-controller.2.2.1. VirtIO-net PF Device Configuration1.Run the following command on the DPU:mlxconfig -d /dev/mst/mt41686_pciconf0 s INTERNAL_CPU_MODEL=12.Add the following kernel boot parameters to the Linux boot arguments:intel_iommu=on iommu=pt pci=realloc3.Cold reboot the host system.4.Apply the following configuration on the DPU:$ mst start$ mlxconfig -d /dev/mst/mt41686_pciconf0 s PF_BAR2_ENABLE=0 PER_PF_NUM_SF=1$ mlxconfig -d /dev/mst/mt41686_pciconf0 s \PCI_SWITCH_EMULATION_ENABLE=1 \PCI_SWITCH_EMULATION_NUM_PORT=16 \VIRTIO_NET_EMULATION_ENABLE=1 \VIRTIO_NET_EMULATION_NUM_VF=0 \VIRTIO_NET_EMULATION_NUM_PF=0 \VIRTIO_NET_EMULATION_NUM_MSIX=10 \VIRTIO_NET_EMULATION_VENDOR_ID=0x1af4 \VIRTIO_NET_EMULATION_DEVICE_ID=0x1041 \VIRTIO_NET_EMULATION_CLASS_CODE=0x028000 \ECPF_ESWITCH_MANAGER=1 \ECPF_PAGE_SUPPLIER=1 \SRIOV_EN=0 \PF_SF_BAR_SIZE=10 \PF_TOTAL_SF=64$ mlxconfig -d /dev/mst/mt41686_pciconf0.1 s \PF_SF_BAR_SIZE=10 \PF_TOTAL_SF=645.Cold reboot the host system a second time.2.2.2. Creating Hotplug VirtIO-net PF DeviceVirtIO emulated network PCIe devices are created and destroyed using virtio-net-controller application console. When this application is terminated, all created virtio-net emulated devices are hot unplugged.1.Create a hotplug virtio-net device. Run:virtnet hotplug -i mlx5_0 -f 0x0 -m 0C:C4:7A:FF:22:93 -t 1500 -n 3 -s 1024 Note: The maximum number of virtio-net queues is bound by the minimum of the followingnumbers:‣VIRTIO_NET_EMULATION_NUM_MSIX from the command mlxconfig -d <mst_dev> q‣max_virtq from the command virtnet list"This creates one hotplug virtio-net device with MAC address 0C:C4:7A:FF:22:93, MTU 1500, and 3 VirtIO queues with a depth of 1024 entries. This device is uniquely identified by its index. This index is used to query and update device attributes. If the device is created successfully, an output appears similar to the following:"bdf": "84:0.0","id": 1,"rep_name": "en3f0pf0sf1001","mac": "0C:C4:7A:FF:22:93"2.Bring up the representor port of the device. Run:ip link set dev en3f0pf0sf1001 upovs-vsctl add-port <bridge> en3f0pf0sf1001Once steps 1-3 are completed, virtio-net device should be available in the host system.3.To query all the device configurations of virtio-net device that you created, run:virtnet query –p 14.To list all the virtio-net devices, run:virtnet list5.To modify device attributes, for example, changing its MAC address, run:virtnet modify -p 0 device -m 0C:C4:7A:FF:22:986.Once usage is complete, to hot-unplug a VirtIO net device, run:virtnet unplug -p 12.3. VirtIO-net SR-IOV VF DevicesThis section covers managing virtio-net PCIe SR-IOV VF devices using virtio-net-controller.2.3.1. Virtio-net SR-IOV VF Device ConfigurationNote: Virtio-net SR-IOV VF is only supported with statically configured PF, hot-plugged PF isnot currently supported.1.On the DPU, make sure virtio-net-controller service is enabled so that it startsautomatically. Run:systemctl status virtio-net-controller.service2.On the x86 host, enable SR-IOV. Please refer to MLNX_OFED documentation underFeatures Overview and Configuration > Virtualization > Single Root IO Virtualization (SR-IOV) > Setting Up SR-IOV for instructions on how to do that. Make sure the parameters intel_iommu=on iommu=pt pci=realloc exist in grub.conf file.3.It is recommended to add pci=assign-busses to the boot command line when creatingmore than 127 VFs. Without this option, the following errors might appear from host and the virtio driver will not probe these devices.pci 0000:84:00.0: [1af4:1041] type 7f class 0xffffffpci 0000:84:00.0: unknown header type 7f, ignoring device4.Run the following command on the DPU:mst start && mlxconfig -d /dev/mst/mt41686_pciconf0 s INTERNAL_CPU_MODEL=15.Cold reboot the host system.6.Apply the following configuration on the DPU in three steps to support up to 125 VFs perPF (500 VFs in total).a).mst start && mlxconfig -d /dev/mst/mt41686_pciconf0 s PF_BAR2_ENABLE=0PER_PF_NUM_SF=1b).mlxconfig -d /dev/mst/mt41686_pciconf0 s \PCI_SWITCH_EMULATION_ENABLE=1 \PCI_SWITCH_EMULATION_NUM_PORT=16 \VIRTIO_NET_EMULATION_ENABLE=1 \VIRTIO_NET_EMULATION_NUM_VF=126 \VIRTIO_NET_EMULATION_NUM_PF=4 \VIRTIO_NET_EMULATION_NUM_MSIX=4 \VIRTIO_NET_EMULATION_VENDOR_ID=0x1af4 \VIRTIO_NET_EMULATION_DEVICE_ID=0x1041 \VIRTIO_NET_EMULATION_CLASS_CODE=0x028000 \ECPF_ESWITCH_MANAGER=1 \ECPF_PAGE_SUPPLIER=1 \SRIOV_EN=1 \PF_SF_BAR_SIZE=8 \PF_TOTAL_SF=508 \NUM_OF_VFS=0c).mlxconfig -d /dev/mst/mt41686_pciconf0.1 s PF_TOTAL_SF=1 PF_SF_BAR_SIZE=87.Cold reboot the host system.2.3.2. Creating Virtio-net SR-IOV VF DevicesThe virtio-net-controller application console must be kept alive to maintain the functionality of the static PF and its VFs.1.On the host, make sure the static virtio network device presents. Run:# lspci | grep -i virtio85:00.3 Network controller: Red Hat, Inc. Virtio network device2.On the host, make sure virtio_pci and virtio_net are loaded. Run:# lsmod | grep virtioThe net device should be created:# ethtool -i p7p3driver: virtio_netversion: 1.0.0firmware-version:expansion-rom-version:bus-info: 0000:85:00.3supports-statistics: nosupports-test: nosupports-eeprom-access: nosupports-register-dump: nosupports-priv-flags: no3.To create SR-IOV VF devices on the x86 host, run:# echo 2 > /sys/bus/pci/drivers/virtio-pci/0000\:85\:00.3/sriov_numvfs Note: When the number of VFs created is high, SR-IOV enablement may take severalminutes.2 VFs should be created from the x86 host:# lspci | grep -i virt85:00.3 Network controller: Red Hat, Inc. Virtio network device85:04.5 Network controller: Red Hat, Inc. Virtio network device85:04.6 Network controller: Red Hat, Inc. Virtio network device4.From the DPU virtio-net controller, run the following command to get VF information.# virnet list{"vf_id": 0,"parent_pf_id": 0,"function_type": "VF","bdf": "85:04.5","sf_parent_device": "mlx5_0","sf_rep_name": "pf0sf5","msix_config_vector": "0x0","num_msix": 4,"max_queues": 4,"queues_size": 256,"net_mac": "1A:38:A4:55:BD:B0","net_mtu": 1500},You may use the pci-bdf to match the PF/VF on the x86 host to the information showing on DPU.To query all the device configurations of the virtio-net device of that VF, run:$ virtnet query -p 0 -v 0Bring up the corresponding SF and add it to the OVS bridge:# ip link set dev pf0sf5 up# ovs-vsctl add-port <bridge> pf0sf5Now the VF should be functional.Note: When port MTU (p0/p1 of the DPU) is changed after the controller is started, youmust restart controller service. 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数字多功能测试仪 D03046 和 D03047 的安全说明书
DIGITAL MULTIMETER Model: D03046 and D03047IMPORTANT SAFETY INFORMATIONPlease read these instructions carefully before use and retain for future reference.• Check the test leads, probes and case insulation before using. If you find any breakage or abnormality, or you consider the device is broken, stop using the device immediately.• When using the test probes, keep your fingers behind the finger protection ring.• Do not use the meter with the back cover open.• Select appropriate test range for measurements.• Ensure all inputs are less than the range selected otherwise it may cause electrical shock or meter damage.• Do not change the range selector position during voltage or current measurements.• Do not apply a voltage exceeding the marked voltage between COM terminal and ground.• Take caution when working voltages are above 60V DC or 30V AC rms.• Do not connect the meter to voltage signals when the range selector is on current, resistance, diode or continuity range.• When measuring current, each single measurement should be shorter than 10 seconds.• When a measurement has been completed, disconnect the testing probes from the circuit under test.• Replace the batteries as soon as the low battery indicator appears on the display.• Remove dead batteries from the meter or if it is not going to be used for a long time.• Never mix old and new batteries together, or different types of batteries.• Never dispose of batteries in a fire, or attempt to recharge ordinary batteries.• Before replacing the battery, turn off the meter and disconnect all the test probes.• To prolong battery life turn off the meter after use.FUNCTIONSModel DCV ACV DCAΩhFED03046P P P P P PD03047P P P P P P P PDC VOLTAGE LCDRotary Range Selector5A JackVΩmA Jack COM JackhFE SocketRange Resolution Accuracy200mV100µV±(0.5% of rdg +3D)2000mV1mV±(0.8% of rdg +5D)20V10mV200V100mV500V1V±(1.0% of rdg +5D)• OVERLOAD PROTECTION: 220V rms AC for 200mV range and 500V DC or 500V rms for all ranges.AC VOLTAGECONTINUITYDC CURRENTRange Resolution Accuracy 200V 100mV ±(2.0% of rdg +10D)500V1VRangeDescriptionBuilt in buzzer sounds if resistance is lessthan 30±20Ω• RESPONSE: Average responding, calibrated in rms of a sine wave.• FREQUENCY RANGE: 45Hz ~ 450Hz.•OVERLOAD PROTECTION: 500V DC or 500V rms for all ranges.•OVERLOAD PROTECTION: 15 seconds maximum 220V RMS.• OVERLOAD PROTECTION: F0.5A/500V and F5A/250V fuse.•MEASURING VOLTAGE DROP: 200mV.Range Resolution Accuracy200µA 100nA ±(1.8% of rdg +2D)2000µA 1µA 20mA 10µA 200mA 100µA ±(2.0% of rdg +2D)5A10mA±(2.0% of rdg +10D)RESISTANCEOPERATION• MAXIMUM OPEN CIRCUIT VOLTAGE: 3V.•OVERLOAD PROTECTION: 15 seconds maxi- mum 220Vrms.Range ResolutionAccuracy 200Ω0.1Ω±(1.0% of rdg +10D)2000Ω1Ω±(1.0% of rdg +4D)20k Ω10k Ω200k Ω100k Ω2000k Ω1k ΩDC & AC VOLTAGE MEASUREMENT• Connect red test lead to “VΩmA” jack, Black lead to “COM” jack.• Set RANGE switch to desired VOLTAGE position, if the voltage to bemeasured is not known beforehand, set switch to the highest range and reduce it until satisfactory reading is obtained.• Connect test leads to device or circuit being measured.• Turn on power of the device or circuit being measured voltage value willappear on Digital Display along with the voltage polarity. DC CURRENT MEASUREMENT• Red lead to “VΩmA”. Black lead to “COM” (for measurements between 200mAand 5A connect red lead to “5A” jack with fully depressed).• Set RANGE switches to desired DCA position.• Open the circuit to be measured, and connect test leads IN SERIES with theload in with current is to measure.• Read current value on Digital Display.• Additionally, “5A” function is designed for intermittent use only. Maximumcontact time of the test leads with the circuit is 10 seconds, with a minimum intermission time of 15 minutes between tests.RESISTANCE MEASUREMENT• Red lead to “VΩmA”. Black lead to “COM”.• Set RANGE switch to desired Ω position.• If the resistance being measured is connected to a circuit, turn off power and discharge all capacitors before measurement.• Connect test leads to circuit being measured.• Read resistance value on the display.DIODE MEASUREMENT• Red lead to “VΩmA”, Black lead to “COM”.• Set RANGE switch to “” position.• Connect the red test lead to the anode of the diode to be measured and black test lead to cathode.• The forward voltage drop in mV will be displayed. If the diode is reversed, figure “1” will be shown.TRANSISTOR hFE MEASUREMENT• Set RANGE switch to the hFE position.• Determine whether the transistor is PNP of NPN type and locate the Emitter, Base and Collector leads. Insert the leads into the correct pins of the hFEsocket.• The meter will display the approximate hFE value at the condition of base current 10μA and VCE2.8V.AUDIBLE CONTINUITY TEST• Red lead to “VΩmA”, Black lead to “COM”.• RANGE switch to “ ” position.• Connect test leads to two points of circuit to be tested. If the resistance is lower than 30Ω ± 20Ω, the buzzer will sound.TEST SIGNAL• Set RANGE switch to “” position.• A test signal (50Hz) is produced between “VΩmA” and “COM” jack.• The output voltage is approx 5V p-p with 50KΩ impedance.NOTE: OVERLOAD PROTECTION: 15 seconds maximum 220Vrms.BATTERY REPLACEMENTCLEANINGSPECIFICATIONS• If “” appears in display, it indicates that the battery should be replaced.• To replace battery remove the meter from the protective surround, then remove the 2 screws in the rear of the case• Remove the rear case half and simply remove the old battery, and replace with a new one. (9-volt battery, NEDA 1604 6F22 type)• Be careful to observe correct polarity.•Fuses rarely need replacement and blow almost always as a result of operator error. (F500mA/500V for mA terminal and F5A/500V for 5A terminal).• Clean the meter with a clean, soft cloth.•Do not use any chemicals, abrasives or solvents that could damage the meter.Max display: LCD 3½ digits (1999 count) 0.5” high Polarity:Automatic, indicated minus, assumed plus.Measure method: Double integral A/D switch implement Sampling speed: 2 times per second Over-load indication: “1” is displayed Operating Environment: 0o ~40o , at <80%RH Storage Environment: -10o ~50o , at <85%RH Power:9V NEDA 1604 or 6F22Low battery indication:“”Static electricity: Approx 4mA Dimension: 126 x 70 x 26mm Weight:108g (including battery)INFORMATION ON WASTE DISPOSAL FOR CONSUMERS OF ELECTRICAL& ELECTRONIC EQUIPMENT.When this product has reached the end of its life it must be treated as Waste Electrical & Electronics Equipment (WEEE). Any WEEE marked products must not be mixed with general household waste, but kept separate for the treatment, recovery and recycling of the materialsused. Contact your local authority for details of recycling schemes in your area.Made in China. PR2 9PP。
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some cases for the utility. Since there is no standard solution which will work for every site, each mitigation action must be carefully planned and evaluated. There are different ways to mitigate voltage dips, swell and interruptions in transmission and distribution systems. At present, a wide range of very flexible controllers, which capitalize on newly available power electronics components, are emerging for custom power applications [3, 4]. Among these, the distribution static compensator and the dynamic voltage restorer are most effective devices, both of them based on the VSC principle. A new PWM-based control scheme has been implemented to control the electronic valves in the two-level VSC used in the D-STATCOM and DVR [5, 6]. 2. VOLTAGE SOURCE CONVERTERS (VSC) A voltage-source converter is a power electronic device, which can generate a sinusoidal voltage with any required magnitude, frequency and phase angle. Voltage source converters are widely used in adjustable-speed drives, but can also be used to mitigate voltage dips. The VSC is used to either completely replace the voltage or to inject the ‘missing voltage’. The ‘missing voltage’ is the difference between the nominal voltage and the actual. The converter is normally based on some kind of energy storage, which will supply the converter with a DC voltage. The solid-state electronics in the converter is then switched to get the desired output voltage. Normally the VSC is not only used for voltage dip mitigation, but also for other power quality issues, e.g. flicker and harmonics.
VOL. 2, NO. 3, JUNE 2007
ISSN 1819-6608
ARPN Journal of Engineering and Applied Sciences
©2006-2007 Asian Research Publishing Network (ARPN). All rights reserved.
Keywords: D-Statcom, DVR, voltage dips, swells, interruption, poTRODUCTION One of the most common power quality problems today is voltage dips. A voltage dip is a short time (10 ms to 1 minute) event during which a reduction in r.m.s voltage magnitude occurs. It is often set only by two parameters, depth/magnitude and duration. The voltage dip magnitude is ranged from 10% to 90% of nominal voltage (which corresponds to 90% to 10% remaining voltage) and with a duration from half a cycle to 1 min. In a three-phase system a voltage dip is by nature a threephase phenomenon, which affects both the phase-toground and phase-to-phase voltages. A voltage dip is caused by a fault in the utility system, a fault within the customer’s facility or a large increase of the load current, like starting a motor or transformer energizing. Typical faults are single-phase or multiple-phase short circuits, which leads to high currents. The high current results in a voltage drop over the network impedance. At the fault location the voltage in the faulted phases drops close to zero, whereas in the non-faulted phases it remains more or less unchanged [1, 2]. Voltage dips are one of the most occurring power quality problems. Off course, for an industry an outage is worse, than a voltage dip, but voltage dips occur more often and cause severe problems and economical losses. Utilities often focus on disturbances from end-user equipment as the main power quality problems. This is correct for many disturbances, flicker, harmonics, etc., but voltage dips mainly have their origin in the higher voltage levels. Faults due to lightning, is one of the most common causes to voltage dips on overhead lines. If the economical losses due to voltage dips are significant, mitigation actions can be profitable for the customer and even in
ABSTRACT A Power quality problem is an occurrence manifested as a nonstandard voltage, current or frequency that results in a failure or a mis-operation of end user equipments. Utility distribution networks, sensitive industrial loads and critical commercial operations suffer from various types of outages and service interruptions which can cost significant financial losses. With the restructuring of power systems and with shifting trend towards distributed and dispersed generation, the issue of power quality is going to take newer dimensions. In developing countries like India, where the variation of power frequency and many such other determinants of power quality are themselves a serious question, it is very vital to take positive steps in this direction .The present work is to identify the prominent concerns in this area and hence the measures that can enhance the quality of the power are recommended. This work describes the techniques of correcting the supply voltage sag, swell and interruption in a distributed system. At present, a wide range of very flexible controllers, which capitalize on newly available power electronics components, are emerging for custom power applications. Among these, the distribution static compensator and the dynamic voltage restorer are most effective devices, both of them based on the VSC principle. A DVR injects a voltage in series with the system voltage and a D-STATCOM injects a current into the system to correct the voltage sag, swell and interruption. Comprehensive results are presented to assess the performance of each device as a potential custom power solution.