MAX6381LT46D5+T中文资料

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MAX13085EESA-T中文资料

General DescriptionThe MAX13080E–MAX13089E +5.0V, ±15kV ESD-protect-ed, RS-485/RS-422 transceivers feature one driver and one receiver. These devices include fail-safe circuitry,guaranteeing a logic-high receiver output when receiver inputs are open or shorted. The receiver outputs a logic-high if all transmitters on a terminated bus are disabled (high impedance). The MAX13080E–MAX13089E include a hot-swap capability to eliminate false transitions on the bus during power-up or hot insertion.The MAX13080E/MAX13081E/MAX13082E feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 250kbps. The MAX13083E/MAX13084E/MAX13085E also feature slew-rate-limited drivers but allow transmit speeds up to 500kbps. The MAX13086E/MAX13087E/MAX13088E driver slew rates are not limited, making transmit speeds up to 16Mbps possible. The MAX13089E slew rate is pin selectable for 250kbps,500kbps, and 16Mbps.The MAX13082E/MAX13085E/MAX13088E are intended for half-duplex communications, and the MAX13080E/MAX13081E/MAX13083E/MAX13084E/MAX13086E/MAX13087E are intended for full-duplex communica-tions. The MAX13089E is selectable for half-duplex or full-duplex operation. It also features independently programmable receiver and transmitter output phase through separate pins.The MAX13080E–MAX13089E transceivers draw 1.2mA of supply current when unloaded or when fully loaded with the drivers disabled. All devices have a 1/8-unit load receiver input impedance, allowing up to 256transceivers on the bus.The MAX13080E/MAX13083E/MAX13086E/MAX13089E are available in 14-pin PDIP and 14-pin SO packages.The MAX13081E/MAX13082E/MAX13084E/MAX13085E/MAX13087E/MAX13088E are available in 8-pin PDIP and 8-pin SO packages. The devices operate over the com-mercial, extended, and automotive temperature ranges.ApplicationsUtility Meters Lighting Systems Industrial Control Telecom Security Systems Instrumentation ProfibusFeatures♦+5.0V Operation♦Extended ESD Protection for RS-485/RS-422 I/O Pins±15kV Human Body Model ♦True Fail-Safe Receiver While Maintaining EIA/TIA-485 Compatibility ♦Hot-Swap Input Structures on DE and RE ♦Enhanced Slew-Rate Limiting Facilitates Error-Free Data Transmission(MAX13080E–MAX13085E/MAX13089E)♦Low-Current Shutdown Mode (Except MAX13081E/MAX13084E/MAX13087E)♦Pin-Selectable Full-/Half-Duplex Operation (MAX13089E)♦Phase Controls to Correct for Twisted-Pair Reversal (MAX13089E)♦Allow Up to 256 Transceivers on the Bus ♦Available in Industry-Standard 8-Pin SO PackageMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers________________________________________________________________Maxim Integrated Products 1Ordering Information19-3590; Rev 1; 4/05For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .Selector Guide, Pin Configurations, and Typical Operating Circuits appear at end of data sheet.Ordering Information continued at end of data sheet.M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSDC ELECTRICAL CHARACTERISTICS(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.) (Note 1)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.(All Voltages Referenced to GND)Supply Voltage (V CC ).............................................................+6V Control Input Voltage (RE , DE, SLR,H/F , TXP, RXP)......................................................-0.3V to +6V Driver Input Voltage (DI)...........................................-0.3V to +6V Driver Output Voltage (Z, Y, A, B).............................-8V to +13V Receiver Input Voltage (A, B)....................................-8V to +13V Receiver Input VoltageFull Duplex (A, B)..................................................-8V to +13V Receiver Output Voltage (RO)....................-0.3V to (V CC + 0.3V)Driver Output Current.....................................................±250mAContinuous Power Dissipation (T A = +70°C)8-Pin SO (derate 5.88mW/°C above +70°C).................471mW 8-Pin Plastic DIP (derate 9.09mW/°C above +70°C).....727mW 14-Pin SO (derate 8.33mW/°C above +70°C)...............667mW 14-Pin Plastic DIP (derate 10.0mW/°C above +70°C)...800mW Operating Temperature RangesMAX1308_EC_ _.................................................0°C to +75°C MAX1308_EE_ _..............................................-40°C to +85°C MAX1308_EA_ _............................................-40°C to +125°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________3DC ELECTRICAL CHARACTERISTICS (continued)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.) (Note 1)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 4_______________________________________________________________________________________DRIVER SWITCHING CHARACTERISTICSMAX13080E/MAX13081E/MAX13082E/MAX13089E WITH SRL = UNCONNECTED (250kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)RECEIVER SWITCHING CHARACTERISTICSMAX13080E/MAX13081E/MAX13082E/MAX13089E WITH SRL = UNCONNECTED (250kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________5DRIVER SWITCHING CHARACTERISTICSMAX13083E/MAX13084E/MAX13085E/MAX13089E WITH SRL = V CC (500kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)RECEIVER SWITCHING CHARACTERISTICSMAX13083E/MAX13084E/MAX13085E/MAX13089E WITH SRL = V CC (500kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 6_______________________________________________________________________________________DRIVER SWITCHING CHARACTERISTICSMAX13086E/MAX13087E/MAX13088E/MAX13089E WITH SRL = GND (16Mbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)RECEIVER SWITCHING CHARACTERISTICSMAX13086E/MAX13087E/MAX13088E/MAX13089E WITH SRL = GND (16Mbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)Note 2:∆V OD and ∆V OC are the changes in V OD and V OC , respectively, when the DI input changes state.Note 3:The short-circuit output current applies to peak current just prior to foldback current limiting. The short-circuit foldback outputcurrent applies during current limiting to allow a recovery from bus contention.MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________70.800.901.501.101.001.201.301.401.60-40-10520-253550958011065125SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (m A )0201040305060021345OUTPUT CURRENTvs. RECEIVER OUTPUT-HIGH VOLTAGEM A X 13080E -89E t o c 02OUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )20104030605070021345OUTPUT CURRENTvs. RECEIVER OUTPUT-LOW VOLTAGEM A X 13080E -89E t o c 03OUTPUT LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )4.04.44.24.84.65.25.05.4RECEIVER OUTPUT-HIGH VOLTAGEvs. TEMPERATURETEMPERATURE (°C)O U T P U T H I G H V O L T A G E (V )-40-10520-2535509580110651250.10.70.30.20.40.50.60.8RECEIVER OUTPUT-LOW VOLTAGEvs. TEMPERATURETEMPERATURE (°C)O U T P U T L O W V O L T A G E (V )-40-10520-25355095801106512502040608010012014016012345DRIVER DIFFERENTIAL OUTPUT CURRENT vs. DIFFERENTIAL OUTPUT VOLTAGEDIFFERENTIAL OUTPUT VOLTAGE (V)D I F FE R E N T I A L O U T P U T C U R R E N T (m A )2.02.82.43.63.24.44.04.8DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURED I F FE R E N T I A L O U T P U T V O L T A G E (V )-40-10520-253550958011065125TEMPERATURE (°C)40201008060120140180160200-7-5-4-6-3-2-1012354OUTPUT CURRENT vs. TRANSMITTEROUTPUT-HIGH VOLTAGEOUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )60402080100120140160180200042681012OUTPUT CURRENT vs. TRANSMITTEROUTPUT-LOW VOLTAGEOUTPUT-LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )Typical Operating Characteristics(V CC = +5.0V, T A = +25°C, unless otherwise noted.)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 8_______________________________________________________________________________________21543679810SHUTDOWN CURRENT vs. TEMPERATUREM A X 13080E -89E t o c 10S H U T D O W N C U R R E N T (µA )-40-10520-253550958011065125TEMPERATURE (°C)600800700100090011001200DRIVER PROPAGATION DELAY vs. TEMPERATURE (250kbps)D R I VE R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)300400350500450550600DRIVER PROPAGATION DELAY vs. TEMPERATURE (500kbps)D R I VE R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)1070302040506080DRIVER PROPAGATION DELAY vs. TEMPERATURE (16Mbps)D R I VE R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)40201008060120140160180RECEIVER PROPAGATION DELAYvs. TEMPERATURE (250kpbs AND 500kbps)R E C E I V E R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)40201008060120140160180RECEIVER PROPAGATION DELAYvs. TEMPERATURE (16Mbps)R EC E I V E R P R O P A G AT I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)2µs/div DRIVER PROPAGATION DELAY (250kbps)DI 2V/divV Y - V Z 5V/divR L = 100Ω200ns/divRECEIVER PROPAGATION DELAY(250kbps AND 500kbps)V A - V B 5V/divRO 2V/divTypical Operating Characteristics (continued)(V CC = +5.0V, T A = +25°C, unless otherwise noted.)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________9Test Circuits and Waveforms400ns/divDRIVER PROPAGATION DELAY (500kbps)DI 2V/divR L = 100ΩV Y - V Z 5V/div10ns/div DRIVER PROPAGATION DELAY (16Mbps)DI 2V/divR L = 100ΩV Y 2V/divV Z 2V/div40ns/divRECEIVER PROPAGATION DELAY (16Mbps)V B 2V/divR L = 100ΩRO 2V/divV A 2V/divTypical Operating Characteristics (continued)(V CC = +5.0V, T A = +25°C, unless otherwise noted.)Figure 2. Driver Timing Test CircuitM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 10______________________________________________________________________________________Test Circuits and Waveforms (continued)Figure 4. Driver Enable and Disable Times (t DHZ , t DZH , t DZH(SHDN))DZL DLZ DLZ(SHDN)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversTest Circuits and Waveforms (continued)Figure 6. Receiver Propagation Delay Test CircuitM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversMAX13080E/MAX13083E/MAX13086EMAX13081E/MAX13084E/MAX13086E/MAX13087EFunction TablesM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers MAX13082E/MAX13085E/MAX13088EFunction Tables (continued)MAX13089EDetailed Description The MAX13080E–MAX13089E high-speed transceivers for RS-485/RS-422 communication contain one driver and one receiver. These devices feature fail-safe circuit-ry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted, or when they are connected to a terminated transmission line with all dri-vers disabled (see the Fail-Safe section). The MAX13080E/MAX13082E/MAX13083E/MAX13085E/ MAX13086E/MAX13088E/MAX13089E also feature a hot-swap capability allowing line insertion without erroneous data transfer (see the Hot Swap Capability section). The MAX13080E/MAX13081E/MAX13082E feature reduced slew-rate drivers that minimize EMI and reduce reflec-tions caused by improperly terminated cables, allowing error-free data transmission up to 250kbps. The MAX13083E/MAX13084E/MAX13085E also offer slew-rate limits allowing transmit speeds up to 500kbps. The MAX13086E/MAX13087E/MAX13088Es’ driver slew rates are not limited, making transmit speeds up to 16Mbps possible. The MAX13089E’s slew rate is selectable between 250kbps, 500kbps, and 16Mbps by driving a selector pin with a three-state driver.The MAX13082E/MAX13085E/MAX13088E are half-duplex transceivers, while the MAX13080E/MAX13081E/ MAX13083E/MAX13084E/MAX13086E/MAX13087E are full-duplex transceivers. The MAX13089E is selectable between half- and full-duplex communication by driving a selector pin (H/F) high or low, respectively.All devices operate from a single +5.0V supply. Drivers are output short-circuit current limited. Thermal-shutdown circuitry protects drivers against excessive power dissi-pation. When activated, the thermal-shutdown circuitry places the driver outputs into a high-impedance state.Receiver Input Filtering The receivers of the MAX13080E–MAX13085E, and the MAX13089E when operating in 250kbps or 500kbps mode, incorporate input filtering in addition to input hysteresis. This filtering enhances noise immunity with differential signals that have very slow rise and fall times. Receiver propagation delay increases by 25% due to this filtering.Fail-Safe The MAX13080E family guarantees a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver input threshold between -50mV and -200mV. If the differential receiver input voltage (A - B) is greater than or equal to -50mV, RO is logic-high. If (A - B) is less than or equal to -200mV, RO is logic-low. In the case of a terminated bus with all transmitters disabled, the receiv-er’s differential input voltage is pulled to 0V by the termi-nation. With the receiver thresholds of the MAX13080E family, this results in a logic-high with a 50mV minimumnoise margin. Unlike previous fail-safe devices, the-50mV to -200mV threshold complies with the ±200mVEIA/TIA-485 standard.Hot-Swap Capability (Except MAX13081E/MAX13084E/MAX13087E)Hot-Swap InputsWhen circuit boards are inserted into a hot or powered backplane, differential disturbances to the data buscan lead to data errors. Upon initial circuit board inser-tion, the data communication processor undergoes itsown power-up sequence. During this period, the processor’s logic-output drivers are high impedanceand are unable to drive the DE and RE inputs of these devices to a defined logic level. Leakage currents up to±10µA from the high-impedance state of the proces-sor’s logic drivers could cause standard CMOS enableinputs of a transceiver to drift to an incorrect logic level. Additionally, parasitic circuit board capacitance couldcause coupling of V CC or GND to the enable inputs. Without the hot-swap capability, these factors could improperly enable the transceiver’s driver or receiver.When V CC rises, an internal pulldown circuit holds DElow and RE high. After the initial power-up sequence,the pulldown circuit becomes transparent, resetting thehot-swap tolerable input.Hot-Swap Input CircuitryThe enable inputs feature hot-swap capability. At theinput there are two NMOS devices, M1 and M2 (Figure 9). When V CC ramps from zero, an internal 7µstimer turns on M2 and sets the SR latch, which alsoturns on M1. Transistors M2, a 1.5mA current sink, andM1, a 500µA current sink, pull DE to GND through a5kΩresistor. M2 is designed to pull DE to the disabledstate against an external parasitic capacitance up to100pF that can drive DE high. After 7µs, the timer deactivates M2 while M1 remains on, holding DE low against three-state leakages that can drive DE high. M1 remains on until an external source overcomes the required input current. At this time, the SR latch resetsand M1 turns off. When M1 turns off, DE reverts to a standard, high-impedance CMOS input. Whenever V CCdrops below 1V, the hot-swap input is reset.For RE there is a complementary circuit employing two PMOS devices pulling RE to V CC. MAX13080E–MAX13089E+5.0V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversM A X 13080E –M A X 13089EMAX13089E ProgrammingThe MAX13089E has several programmable operating modes. Transmitter rise and fall times are programma-ble, resulting in maximum data rates of 250kbps,500kbps, and 16Mbps. To select the desired data rate,drive SRL to one of three possible states by using a three-state driver: V CC , GND, or unconnected. F or 250kbps operation, set the three-state device in high-impedance mode or leave SRL unconnected. F or 500kbps operation, drive SRL high or connect it to V CC .F or 16Mbps operation, drive SRL low or connect it to GND. SRL can be changed during operation without interrupting data communications.Occasionally, twisted-pair lines are connected backward from normal orientation. The MAX13089E has two pins that invert the phase of the driver and the receiver to cor-rect this problem. F or normal operation, drive TXP and RXP low, connect them to ground, or leave them uncon-nected (internal pulldown). To invert the driver phase,drive TXP high or connect it to V CC . To invert the receiver phase, drive RXP high or connect it to V CC . Note that the receiver threshold is positive when RXP is high.The MAX13089E can operate in full- or half-duplex mode. Drive H/F low, leave it unconnected (internal pulldown), or connect it to GND for full-duplex opera-tion. Drive H/F high for half-duplex operation. In full-duplex mode, the pin configuration of the driver and receiver is the same as that of a MAX13080E. In half-duplex mode, the receiver inputs are internally connect-ed to the driver outputs through a resistor-divider. This effectively changes the function of the device’s outputs.Y becomes the noninverting driver output and receiver input, Z becomes the inverting driver output and receiver input. In half-duplex mode, A and B are still connected to ground through an internal resistor-divider but they are not internally connected to the receiver.±15kV ESD ProtectionAs with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electro-static discharges encountered during handling and assembly. The driver outputs and receiver inputs of the MAX13080E family of devices have extra protection against static electricity. Maxim’s engineers have devel-oped state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD struc-tures withstand high ESD in all states: normal operation,shutdown, and powered down. After an ESD event, the MAX13080E–MAX13089E keep working without latchup or damage.ESD protection can be tested in various ways. The transmitter outputs and receiver inputs of the MAX13080E–MAX13089E are characterized for protec-tion to the following limits:•±15kV using the Human Body Model•±6kV using the Contact Discharge method specified in IEC 61000-4-2ESD Test ConditionsESD performance depends on a variety of conditions.Contact Maxim for a reliability report that documents test setup, test methodology, and test results.Human Body ModelFigure 10a shows the Human Body Model, and Figure 10b shows the current waveform it generates when dis-charged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest,which is then discharged into the test device through a 1.5k Ωresistor.IEC 61000-4-2The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. However, it does not specifically refer to integrated circuits. The MAX13080E family of devices helps you design equip-ment to meet IEC 61000-4-2, without the need for addi-tional ESD-protection components.+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversThe major difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2 because series resistance is lower in the IEC 61000-4-2 model. Hence, the ESD with-stand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human Body Model. Figure 10c shows the IEC 61000-4-2 model, and Figure 10d shows the current waveform for IEC 61000-4-2 ESD Contact Discharge test.Machine Model The machine model for ESD tests all pins using a 200pF storage capacitor and zero discharge resis-tance. The objective is to emulate the stress caused when I/O pins are contacted by handling equipment during test and assembly. Of course, all pins require this protection, not just RS-485 inputs and outputs.Applications Information256 Transceivers on the BusThe standard RS-485 receiver input impedance is 12kΩ(1-unit load), and the standard driver can drive up to 32-unit loads. The MAX13080E family of transceivers has a1/8-unit load receiver input impedance (96kΩ), allowingup to 256 transceivers to be connected in parallel on one communication line. Any combination of these devices,as well as other RS-485 transceivers with a total of 32-unit loads or fewer, can be connected to the line.Reduced EMI and ReflectionsThe MAX13080E/MAX13081E/MAX13082E feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to250kbps. The MAX13083E/MAX13084E/MAX13085Eoffer higher driver output slew-rate limits, allowing transmit speeds up to 500kbps. The MAX13089E withSRL = V CC or unconnected are slew-rate limited. WithSRL unconnected, the MAX13089E error-free data transmission is up to 250kbps. With SRL connected toV CC,the data transmit speeds up to 500kbps. MAX13080E–MAX13089E+5.0V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversM A X 13080E –M A X 13089ELow-Power Shutdown Mode (Except MAX13081E/MAX13084E/MAX13087E)Low-power shutdown mode is initiated by bringing both RE high and DE low. In shutdown, the devices typically draw only 2.8µA of supply current.RE and DE can be driven simultaneously; the devices are guaranteed not to enter shutdown if RE is high and DE is low for less than 50ns. If the inputs are in this state for at least 700ns, the devices are guaranteed to enter shutdown.Enable times t ZH and t ZL (see the Switching Characteristics section) assume the devices were not in a low-power shutdown state. Enable times t ZH(SHDN)and t ZL(SHDN)assume the devices were in shutdown state. It takes drivers and receivers longer to become enabled from low-power shutdown mode (t ZH(SHDN), t ZL(SHDN))than from driver/receiver-disable mode (t ZH , t ZL ).Driver Output ProtectionTwo mechanisms prevent excessive output current and power dissipation caused by faults or by bus contention.The first, a foldback current limit on the output stage,provides immediate protection against short circuits over the whole common-mode voltage range (see the Typical Operating Characteristics ). The second, a thermal-shut-down circuit, forces the driver outputs into a high-imped-ance state if the die temperature exceeds +175°C (typ).Line LengthThe RS-485/RS-422 standard covers line lengths up to 4000ft. F or line lengths greater than 4000ft, use the repeater application shown in Figure 11.Typical ApplicationsThe MAX13082E/MAX13085E/MAX13088E/MAX13089E transceivers are designed for bidirectional data commu-nications on multipoint bus transmission lines. F igures 12 and 13 show typical network applications circuits. To minimize reflections, terminate the line at both ends in its characteristic impedance, and keep stub lengths off the main line as short as possible. The slew-rate-lim-ited MAX13082E/MAX13085E and the two modes of the MAX13089E are more tolerant of imperfect termination.Chip InformationTRANSISTOR COUNT: 1228PROCESS: BiCMOS+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversFigure 11. Line Repeater for MAX13080E/MAX13081E/MAX13083E/MAX13084E/MAX13086E/MAX13087E/MAX13089E in Full-Duplex Mode+5.0V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversMAX13080E–MAX13089EM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversPin Configurations and Typical Operating CircuitsMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers______________________________________________________________________________________21Pin Configurations and Typical Operating Circuits (continued)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 22______________________________________________________________________________________Ordering Information (continued)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers______________________________________________________________________________________23Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. 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MAX485CPA+中文资料

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .General DescriptionThe MAX481, MAX483, MAX485, MAX487–MAX491, and MAX1487 are low-power transceivers for RS-485 and RS-422 communication. Each part contains one driver and one receiver. The MAX483, MAX487, MAX488, and MAX489feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables,thus allowing error-free data transmission up to 250kbps.The driver slew rates of the MAX481, MAX485, MAX490,MAX491, and MAX1487 are not limited, allowing them to transmit up to 2.5Mbps.These transceivers draw between 120µA and 500µA of supply current when unloaded or fully loaded with disabled drivers. Additionally, the MAX481, MAX483, and MAX487have a low-current shutdown mode in which they consume only 0.1µA. All parts operate from a single 5V supply.Drivers are short-circuit current limited and are protected against excessive power dissipation by thermal shutdown circuitry that places the driver outputs into a high-imped-ance state. The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit.The MAX487 and MAX1487 feature quarter-unit-load receiver input impedance, allowing up to 128 MAX487/MAX1487 transceivers on the bus. Full-duplex communi-cations are obtained using the MAX488–MAX491, while the MAX481, MAX483, MAX485, MAX487, and MAX1487are designed for half-duplex applications.________________________ApplicationsLow-Power RS-485 Transceivers Low-Power RS-422 Transceivers Level TranslatorsTransceivers for EMI-Sensitive Applications Industrial-Control Local Area Networks__Next Generation Device Features♦For Fault-Tolerant ApplicationsMAX3430: ±80V Fault-Protected, Fail-Safe, 1/4Unit Load, +3.3V, RS-485 TransceiverMAX3440E–MAX3444E: ±15kV ESD-Protected,±60V Fault-Protected, 10Mbps, Fail-Safe, RS-485/J1708 Transceivers♦For Space-Constrained ApplicationsMAX3460–MAX3464: +5V, Fail-Safe, 20Mbps,Profibus RS-485/RS-422 TransceiversMAX3362: +3.3V, High-Speed, RS-485/RS-422Transceiver in a SOT23 PackageMAX3280E–MAX3284E: ±15kV ESD-Protected,52Mbps, +3V to +5.5V, SOT23, RS-485/RS-422,True Fail-Safe ReceiversMAX3293/MAX3294/MAX3295: 20Mbps, +3.3V,SOT23, RS-855/RS-422 Transmitters ♦For Multiple Transceiver ApplicationsMAX3030E–MAX3033E: ±15kV ESD-Protected,+3.3V, Quad RS-422 Transmitters ♦For Fail-Safe ApplicationsMAX3080–MAX3089: Fail-Safe, High-Speed (10Mbps), Slew-Rate-Limited RS-485/RS-422Transceivers♦For Low-Voltage ApplicationsMAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E: +3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited,True RS-485/RS-422 TransceiversMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers______________________________________________________________Selection Table19-0122; Rev 8; 10/03Ordering Information appears at end of data sheet.M A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSSupply Voltage (V CC ).............................................................12V Control Input Voltage (RE , DE)...................-0.5V to (V CC + 0.5V)Driver Input Voltage (DI).............................-0.5V to (V CC + 0.5V)Driver Output Voltage (A, B)...................................-8V to +12.5V Receiver Input Voltage (A, B).................................-8V to +12.5V Receiver Output Voltage (RO).....................-0.5V to (V CC +0.5V)Continuous Power Dissipation (T A = +70°C)8-Pin Plastic DIP (derate 9.09mW/°C above +70°C)....727mW 14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)..800mW 8-Pin SO (derate 5.88mW/°C above +70°C).................471mW14-Pin SO (derate 8.33mW/°C above +70°C)...............667mW 8-Pin µMAX (derate 4.1mW/°C above +70°C)..............830mW 8-Pin CERDIP (derate 8.00mW/°C above +70°C).........640mW 14-Pin CERDIP (derate 9.09mW/°C above +70°C).......727mW Operating Temperature RangesMAX4_ _C_ _/MAX1487C_ A...............................0°C to +70°C MAX4__E_ _/MAX1487E_ A.............................-40°C to +85°C MAX4__MJ_/MAX1487MJA...........................-55°C to +125°C Storage Temperature Range.............................-65°C to +160°C Lead Temperature (soldering, 10sec).............................+300°CDC ELECTRICAL CHARACTERISTICS(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.V V IN = -7VV IN = 12V V IN = -7V V IN = 12V Input Current (A, B)I IN2V TH k Ω48-7V ≤V CM ≤12V, MAX487/MAX1487R INReceiver Input Resistance -7V ≤V CM ≤12V, all devices except MAX487/MAX1487R = 27Ω(RS-485), Figure 40.4V ≤V O ≤2.4VR = 50Ω(RS-422)I O = 4mA, V ID = -200mV I O = -4mA, V ID = 200mV V CM = 0V-7V ≤V CM ≤12V DE, DI, RE DE, DI, RE MAX487/MAX1487,DE = 0V, V CC = 0V or 5.25VDE, DI, RE R = 27Ωor 50Ω, Figure 4R = 27Ωor 50Ω, Figure 4R = 27Ωor 50Ω, Figure 4DE = 0V;V CC = 0V or 5.25V,all devices except MAX487/MAX1487CONDITIONSk Ω12µA ±1I OZRThree-State (high impedance)Output Current at ReceiverV 0.4V OL Receiver Output Low Voltage 3.5V OH Receiver Output High Voltage mV 70∆V TH Receiver Input Hysteresis V -0.20.2Receiver Differential Threshold Voltage-0.2mA 0.25mA-0.81.01.55V OD2Differential Driver Output (with load)V 2V 5V OD1Differential Driver Output (no load)µA±2I IN1Input CurrentV 0.8V IL Input Low Voltage V 2.0V IH Input High Voltage V 0.2∆V OD Change in Magnitude of Driver Common-Mode Output Voltage for Complementary Output States V 0.2∆V OD Change in Magnitude of Driver Differential Output Voltage for Complementary Output States V 3V OC Driver Common-Mode Output VoltageUNITS MINTYPMAX SYMBOL PARAMETERMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers_______________________________________________________________________________________3SWITCHING CHARACTERISTICS—MAX481/MAX485, MAX490/MAX491, MAX1487(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)DC ELECTRICAL CHARACTERISTICS (continued)(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)ns 103060t PHLDriver Rise or Fall Time Figures 6 and 8, R DIFF = 54Ω, C L1= C L2= 100pF ns MAX490M, MAX491M MAX490C/E, MAX491C/E2090150MAX481, MAX485, MAX1487MAX490M, MAX491MMAX490C/E, MAX491C/E MAX481, MAX485, MAX1487Figures 6 and 8, R DIFF = 54Ω,C L1= C L2= 100pF MAX481 (Note 5)Figures 5 and 11, C RL = 15pF, S2 closedFigures 5 and 11, C RL = 15pF, S1 closed Figures 5 and 11, C RL = 15pF, S2 closed Figures 5 and 11, C RL = 15pF, S1 closed Figures 6 and 10, R DIFF = 54Ω,C L1= C L2= 100pFFigures 6 and 8,R DIFF = 54Ω,C L1= C L2= 100pF Figures 6 and 10,R DIFF = 54Ω,C L1= C L2= 100pF CONDITIONS ns 510t SKEW ns50200600t SHDNTime to ShutdownMbps 2.5f MAX Maximum Data Rate ns 2050t HZ Receiver Disable Time from High ns 103060t PLH 2050t LZ Receiver Disable Time from Low ns 2050t ZH Driver Input to Output Receiver Enable to Output High ns 2050t ZL Receiver Enable to Output Low 2090200ns ns 134070t HZ t SKD Driver Disable Time from High |t PLH - t PHL |DifferentialReceiver Skewns 4070t LZ Driver Disable Time from Low ns 4070t ZL Driver Enable to Output Low 31540ns51525ns 31540t R , t F 2090200Driver Output Skew to Output t PLH , t PHL Receiver Input to Output4070t ZH Driver Enable to Output High UNITS MIN TYP MAX SYMBOL PARAMETERFigures 7 and 9, C L = 100pF, S2 closed Figures 7 and 9, C L = 100pF, S1 closed Figures 7 and 9, C L = 15pF, S1 closed Figures 7 and 9, C L = 15pF, S2 closedM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 4_______________________________________________________________________________________SWITCHING CHARACTERISTICS—MAX483, MAX487/MAX488/MAX489(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)SWITCHING CHARACTERISTICS—MAX481/MAX485, MAX490/MAX491, MAX1487 (continued)(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)3001000Figures 7 and 9, C L = 100pF, S2 closed Figures 7 and 9, C L = 100pF, S1 closed Figures 5 and 11, C L = 15pF, S2 closed,A - B = 2VCONDITIONSns 40100t ZH(SHDN)Driver Enable from Shutdown toOutput High (MAX481)nsFigures 5 and 11, C L = 15pF, S1 closed,B - A = 2Vt ZL(SHDN)Receiver Enable from Shutdownto Output Low (MAX481)ns 40100t ZL(SHDN)Driver Enable from Shutdown toOutput Low (MAX481)ns 3001000t ZH(SHDN)Receiver Enable from Shutdownto Output High (MAX481)UNITS MINTYP MAX SYMBOLPARAMETERt PLH t SKEW Figures 6 and 8, R DIFF = 54Ω,C L1= C L2= 100pFt PHL Figures 6 and 8, R DIFF = 54Ω,C L1= C L2= 100pFDriver Input to Output Driver Output Skew to Output ns 100800ns ns 2000MAX483/MAX487, Figures 7 and 9,C L = 100pF, S2 closedt ZH(SHDN)Driver Enable from Shutdown to Output High2502000ns2500MAX483/MAX487, Figures 5 and 11,C L = 15pF, S1 closedt ZL(SHDN)Receiver Enable from Shutdown to Output Lowns 2500MAX483/MAX487, Figures 5 and 11,C L = 15pF, S2 closedt ZH(SHDN)Receiver Enable from Shutdown to Output Highns 2000MAX483/MAX487, Figures 7 and 9,C L = 100pF, S1 closedt ZL(SHDN)Driver Enable from Shutdown to Output Lowns 50200600MAX483/MAX487 (Note 5) t SHDN Time to Shutdownt PHL t PLH , t PHL < 50% of data period Figures 5 and 11, C RL = 15pF, S2 closed Figures 5 and 11, C RL = 15pF, S1 closed Figures 5 and 11, C RL = 15pF, S2 closed Figures 5 and 11, C RL = 15pF, S1 closed Figures 7 and 9, C L = 15pF, S2 closed Figures 6 and 10, R DIFF = 54Ω,C L1= C L2= 100pFFigures 7 and 9, C L = 15pF, S1 closed Figures 7 and 9, C L = 100pF, S1 closed Figures 7 and 9, C L = 100pF, S2 closed CONDITIONSkbps 250f MAX 2508002000Maximum Data Rate ns 2050t HZ Receiver Disable Time from High ns 25080020002050t LZ Receiver Disable Time from Low ns 2050t ZH Receiver Enable to Output High ns 2050t ZL Receiver Enable to Output Low ns ns 1003003000t HZ t SKD Driver Disable Time from High I t PLH - t PHL I DifferentialReceiver SkewFigures 6 and 10, R DIFF = 54Ω,C L1= C L2= 100pFns 3003000t LZ Driver Disable Time from Low ns 2502000t ZL Driver Enable to Output Low ns Figures 6 and 8, R DIFF = 54Ω,C L1= C L2= 100pFns 2502000t R , t F 2502000Driver Rise or Fall Time ns t PLH Receiver Input to Output2502000t ZH Driver Enable to Output High UNITS MIN TYP MAX SYMBOL PARAMETERMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers_______________________________________________________________________________________530002.5OUTPUT CURRENT vs.RECEIVER OUTPUT LOW VOLTAGE525M A X 481-01OUTPUT LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )1.515100.51.02.0203540450.90.1-50-252575RECEIVER OUTPUT LOW VOLTAGE vs.TEMPERATURE0.30.7TEMPERATURE (°C)O U T P U TL O W V O L T A G E (V )500.50.80.20.60.40100125-20-41.5 2.0 3.0 5.0OUTPUT CURRENT vs.RECEIVER OUTPUT HIGH VOLTAGE-8-16M A X 481-02OUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )2.5 4.0-12-18-6-14-10-203.54.5 4.83.2-50-252575RECEIVER OUTPUT HIGH VOLTAGE vs.TEMPERATURE3.64.4TEMPERATURE (°C)O U T P UT H I G H V O L T A G E (V )0504.04.63.44.23.83.01001259000 1.0 3.0 4.5DRIVER OUTPUT CURRENT vs.DIFFERENTIAL OUTPUT VOLTAGE1070M A X 481-05DIFFERENTIAL OUTPUT VOLTAGE (V)O U T P U T C U R R E N T (m A )2.0 4.05030806040200.5 1.5 2.53.5 2.31.5-50-2525125DRIVER DIFFERENTIAL OUTPUT VOLTAGEvs. TEMPERATURE1.72.1TEMPERATURE (°C)D I F FE R E N T I A L O U T P U T V O L T A G E (V )751.92.21.62.01.8100502.4__________________________________________Typical Operating Characteristics(V CC = 5V, T A = +25°C, unless otherwise noted.)NOTES FOR ELECTRICAL/SWITCHING CHARACTERISTICSNote 1:All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to deviceground unless otherwise specified.Note 2:All typical specifications are given for V CC = 5V and T A = +25°C.Note 3:Supply current specification is valid for loaded transmitters when DE = 0V.Note 4:Applies to peak current. See Typical Operating Characteristics.Note 5:The MAX481/MAX483/MAX487 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for lessthan 50ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See Low-Power Shutdown Mode section.M A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 6___________________________________________________________________________________________________________________Typical Operating Characteristics (continued)(V CC = 5V, T A = +25°C, unless otherwise noted.)120008OUTPUT CURRENT vs.DRIVER OUTPUT LOW VOLTAGE20100M A X 481-07OUTPUT LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )6604024801012140-1200-7-5-15OUTPUT CURRENT vs.DRIVER OUTPUT HIGH VOLTAGE-20-80M A X 481-08OUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )-31-603-6-4-2024-100-40100-40-60-2040100120MAX1487SUPPLY CURRENT vs. TEMPERATURE300TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )20608050020060040000140100-50-2550100MAX481/MAX485/MAX490/MAX491SUPPLY CURRENT vs. TEMPERATURE300TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )257550020060040000125100-50-2550100MAX483/MAX487–MAX489SUPPLY CURRENT vs. TEMPERATURE300TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )257550020060040000125MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers_______________________________________________________________________________________7______________________________________________________________Pin DescriptionFigure 1. MAX481/MAX483/MAX485/MAX487/MAX1487 Pin Configuration and Typical Operating CircuitM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487__________Applications InformationThe MAX481/MAX483/MAX485/MAX487–MAX491 and MAX1487 are low-power transceivers for RS-485 and RS-422 communications. The MAX481, MAX485, MAX490,MAX491, and MAX1487 can transmit and receive at data rates up to 2.5Mbps, while the MAX483, MAX487,MAX488, and MAX489 are specified for data rates up to 250kbps. The MAX488–MAX491 are full-duplex trans-ceivers while the MAX481, MAX483, MAX485, MAX487,and MAX1487 are half-duplex. In addition, Driver Enable (DE) and Receiver Enable (RE) pins are included on the MAX481, MAX483, MAX485, MAX487, MAX489,MAX491, and MAX1487. When disabled, the driver and receiver outputs are high impedance.MAX487/MAX1487:128 Transceivers on the BusThe 48k Ω, 1/4-unit-load receiver input impedance of the MAX487 and MAX1487 allows up to 128 transceivers on a bus, compared to the 1-unit load (12k Ωinput impedance) of standard RS-485 drivers (32 trans-ceivers maximum). Any combination of MAX487/MAX1487 and other RS-485 transceivers with a total of 32 unit loads or less can be put on the bus. The MAX481/MAX483/MAX485 and MAX488–MAX491 have standard 12k ΩReceiver Input impedance.Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 8_______________________________________________________________________________________Figure 2. MAX488/MAX490 Pin Configuration and Typical Operating CircuitFigure 3. MAX489/MAX491 Pin Configuration and Typical Operating CircuitMAX483/MAX487/MAX488/MAX489:Reduced EMI and ReflectionsThe MAX483 and MAX487–MAX489 are slew-rate limit-ed, minimizing EMI and reducing reflections caused by improperly terminated cables. Figure 12 shows the dri-ver output waveform and its Fourier analysis of a 150kHz signal transmitted by a MAX481, MAX485,MAX490, MAX491, or MAX1487. High-frequency har-monics with large amplitudes are evident. Figure 13shows the same information displayed for a MAX483,MAX487, MAX488, or MAX489 transmitting under the same conditions. Figure 13’s high-frequency harmonics have much lower amplitudes, and the potential for EMI is significantly reduced.MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers_______________________________________________________________________________________9_________________________________________________________________Test CircuitsFigure 4. Driver DC Test Load Figure 5. Receiver Timing Test LoadFigure 6. Driver/Receiver Timing Test Circuit Figure 7. Driver Timing Test LoadM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 10_______________________________________________________Switching Waveforms_________________Function Tables (MAX481/MAX483/MAX485/MAX487/MAX1487)Figure 8. Driver Propagation DelaysFigure 9. Driver Enable and Disable Times (except MAX488 and MAX490)Figure 10. Receiver Propagation DelaysFigure 11. Receiver Enable and Disable Times (except MAX488and MAX490)Table 1. TransmittingTable 2. ReceivingLow-Power Shutdown Mode (MAX481/MAX483/MAX487)A low-power shutdown mode is initiated by bringing both RE high and DE low. The devices will not shut down unless both the driver and receiver are disabled.In shutdown, the devices typically draw only 0.1µA of supply current.RE and DE may be driven simultaneously; the parts are guaranteed not to enter shutdown if RE is high and DE is low for less than 50ns. If the inputs are in this state for at least 600ns, the parts are guaranteed to enter shutdown.For the MAX481, MAX483, and MAX487, the t ZH and t ZL enable times assume the part was not in the low-power shutdown state (the MAX485/MAX488–MAX491and MAX1487 can not be shut down). The t ZH(SHDN)and t ZL(SHDN)enable times assume the parts were shut down (see Electrical Characteristics ).It takes the drivers and receivers longer to become enabled from the low-power shutdown state (t ZH(SHDN ), t ZL(SHDN)) than from the operating mode (t ZH , t ZL ). (The parts are in operating mode if the –R —E –,DE inputs equal a logical 0,1 or 1,1 or 0, 0.)Driver Output ProtectionExcessive output current and power dissipation caused by faults or by bus contention are prevented by two mechanisms. A foldback current limit on the output stage provides immediate protection against short cir-cuits over the whole common-mode voltage range (see Typical Operating Characteristics ). In addition, a ther-mal shutdown circuit forces the driver outputs into a high-impedance state if the die temperature rises excessively.Propagation DelayMany digital encoding schemes depend on the differ-ence between the driver and receiver propagation delay times. Typical propagation delays are shown in Figures 15–18 using Figure 14’s test circuit.The difference in receiver delay times, | t PLH - t PHL |, is typically under 13ns for the MAX481, MAX485,MAX490, MAX491, and MAX1487 and is typically less than 100ns for the MAX483 and MAX487–MAX489.The driver skew times are typically 5ns (10ns max) for the MAX481, MAX485, MAX490, MAX491, and MAX1487, and are typically 100ns (800ns max) for the MAX483 and MAX487–MAX489.MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers______________________________________________________________________________________1110dB/div0Hz5MHz500kHz/div10dB/div0Hz5MHz500kHz/divFigure 12. Driver Output Waveform and FFT Plot of MAX481/MAX485/MAX490/MAX491/MAX1487 Transmitting a 150kHz SignalFigure 13. Driver Output Waveform and FFT Plot of MAX483/MAX487–MAX489 Transmitting a 150kHz SignalM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 12______________________________________________________________________________________V CC = 5V T A = +25°CV CC = 5V T A = +25°CV CC = 5V T A = +25°CV CC = 5V T A = +25°CFigure 14. Receiver Propagation Delay Test CircuitFigure 15. MAX481/MAX485/MAX490/MAX491/MAX1487Receiver t PHLFigure 16. MAX481/MAX485/MAX490/MAX491/MAX1487Receiver t PLHPHL Figure 18. MAX483, MAX487–MAX489 Receiver t PLHLine Length vs. Data RateThe RS-485/RS-422 standard covers line lengths up to 4000 feet. For line lengths greater than 4000 feet, see Figure 23.Figures 19 and 20 show the system differential voltage for the parts driving 4000 feet of 26AWG twisted-pair wire at 110kHz into 120Ωloads.Typical ApplicationsThe MAX481, MAX483, MAX485, MAX487–MAX491, and MAX1487 transceivers are designed for bidirectional data communications on multipoint bus transmission lines.Figures 21 and 22 show typical network applications circuits. These parts can also be used as line repeaters, with cable lengths longer than 4000 feet, as shown in Figure 23.To minimize reflections, the line should be terminated at both ends in its characteristic impedance, and stub lengths off the main line should be kept as short as possi-ble. The slew-rate-limited MAX483 and MAX487–MAX489are more tolerant of imperfect termination.MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers______________________________________________________________________________________13DIV Y -V ZRO5V 0V1V0V -1V5V 0V2µs/divFigure 19. MAX481/MAX485/MAX490/MAX491/MAX1487 System Differential Voltage at 110kHz Driving 4000ft of Cable Figure 20. MAX483, MAX487–MAX489 System Differential Voltage at 110kHz Driving 4000ft of CableFigure 21. MAX481/MAX483/MAX485/MAX487/MAX1487 Typical Half-Duplex RS-485 NetworkM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 14______________________________________________________________________________________Figure 22. MAX488–MAX491 Full-Duplex RS-485 NetworkFigure 23. Line Repeater for MAX488–MAX491Isolated RS-485For isolated RS-485 applications, see the MAX253 and MAX1480 data sheets.MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers______________________________________________________________________________________15_______________Ordering Information_________________Chip TopographiesMAX481/MAX483/MAX485/MAX487/MAX1487N.C. RO 0.054"(1.372mm)0.080"(2.032mm)DE DIGND B N.C.V CCARE * Contact factory for dice specifications.__Ordering Information (continued)M A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 16______________________________________________________________________________________TRANSISTOR COUNT: 248SUBSTRATE CONNECTED TO GNDMAX488/MAX490B RO 0.054"(1.372mm)0.080"(2.032mm)N.C. DIGND Z A V CCYN.C._____________________________________________Chip Topographies (continued)MAX489/MAX491B RO 0.054"(1.372mm)0.080"(2.032mm)DE DIGND Z A V CCYREMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers______________________________________________________________________________________17Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)S O I C N .E P SM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 18______________________________________________________________________________________Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)MAX481/MAX483/MAX485/MAX487–MAX491Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________19©2003 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.M A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487P D I P N .E PSPackage Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)。

MAX6356UWUT中文资料

元器件交易网
19-1508; Rev 6; 12/05
Dual/Triple-Voltage µP Supervisory Circuits
General Description
The MAX6351–MAX6360 microprocessor (µP) supervisors with multiple reset voltages significantly improve system reliability and accuracy compared to separate ICs or discrete components. If any input supply voltage drops below its associated preset threshold, all reset outputs are asserted. In addition, the outputs are valid as long as either input supply voltage remains greater than +1.0V. All devices in this series have an active-low debounced manual reset input. In addition, the MAX6358/MAX6359/ MAX6360 offer a watchdog-timer input with a 46.4s startup timeout period and a 2.9s timeout period. The MAX6355/MAX6356/MAX6357 offer an additional voltage monitor input to monitor a third voltage. The MAX6351 features two active-low, push-pull reset outputs, one is referenced to VCC1 and the other is referenced to VCC2. The MAX6353/MAX6356/MAX6359 offer an active-low, push-pull reset output referenced to VCC1. The MAX6354/MAX6357/MAX6360 offer an active-low, push-pull reset output referenced to VCC2. All these devices are offered with a wide variety of voltage threshold levels, as shown in the Voltage Threshold Levels table. They are available in 5- and 6-pin SOT23 packages and operate over the extended (-40°C to +85°C) temperature range.

MAX465中文资料

Devices offered in this series are as follows:
PART
DESCRIPΒιβλιοθήκη IONMAX463 MAX464 MAX465 MAX466 MAX467 MAX468 MAX469 MAX470
Triple RGB Switch & Buffer Quad RGB Switch & Buffer Triple RGB Switch & Buffer Quad RGB Switch & Buffer Triple Video Buffer Quad Video Buffer Triple Video Buffer Quad Video Buffer
Continuous Power Dissipation (TA = +70°C) 16-Pin Plastic DIP (derate 22.22mW/°C above +70°C) ....1778mW 16-Pin Wide SO (derate 20.00mW/°C above +70°C) .......1600mW
The MAX463–MAX470 series of two-channel, triple/quad buffered video switches and video buffers combines high-accuracy, unity-gain-stable amplifiers with high-performance video switches. Fast switching time and low differential gain and phase error make this series of switches and buffers ideal for all video applications. The devices are all specified for ±5V supply operation with inputs and outputs as high as ±2.5V when driving 150Ω loads (75Ω back-terminated cable).

max485esa中文资料

General DescriptionThe MAX481, MAX483, MAX485, MAX487–MAX491, andMAX1487 are low-power transceivers for RS-485 and RS-422 communication. Each part contains one driver and onereceiver. The MAX483, MAX487, MAX488, and MAX489feature reduced slew-rate drivers that minimize E MI andreduce reflections caused by improperly terminated cables,thus allowing error-free data transmission up to 250kbps.The driver slew rates of the MAX481, MAX485, MAX490,MAX491, and MAX1487 are not limited, allowing them totransmit up to 2.5Mbps.These transceivers draw between 120µA and 500µA ofsupply current when unloaded or fully loaded with disableddrivers. Additionally, the MAX481, MAX483, and MAX487have a low-current shutdown mode in which they consumeonly 0.1µA. All parts operate from a single 5V supply.Drivers are short-circuit current limited and are protectedagainst excessive power dissipation by thermal shutdowncircuitry that places the driver outputs into a high-imped-ance state. The receiver input has a fail-safe feature thatguarantees a logic-high output if the input is open circuit.The MAX487 and MAX1487 feature quarter-unit-loadreceiver input impedance, allowing up to 128 MAX487/MAX1487 transceivers on the bus. Full-duplex communi-cations are obtained using the MAX488–MAX491, whilethe MAX481, MAX483, MAX485, MAX487, and MAX1487are designed for half-duplex applications.________________________Applications Low-Power RS-485 Transceivers Low-Power RS-422 Transceivers Level Translators Transceivers for EMI-Sensitive Applications Industrial-Control Local Area Networks__Next Generation Device Features o For Fault-Tolerant Applications MAX3430: ±80V Fault-Protected, Fail-Safe, 1/4Unit Load, +3.3V, RS-485 Transceiver MAX3440E–MAX3444E: ±15kV ESD-Protected,±60V Fault-Protected, 10Mbps, Fail-Safe, RS-485/J1708 Transceivers o For Space-Constrained Applications MAX3460–MAX3464: +5V, Fail-Safe, 20Mbps,Profibus RS-485/RS-422 Transceivers MAX3362: +3.3V, High-Speed, RS-485/RS-422Transceiver in a SOT23 Package MAX3280E–MAX3284E: ±15kV ESD-Protected,52Mbps, +3V to +5.5V, SOT23, RS-485/RS-422,True Fail-Safe Receivers MAX3293/MAX3294/MAX3295: 20Mbps, +3.3V,SOT23, RS-485/RS-422 Transmitters o For Multiple Transceiver Applications MAX3030E–MAX3033E: ±15kV ESD-Protected,+3.3V, Quad RS-422 Transmitters o For Fail-Safe Applications MAX3080–MAX3089: Fail-Safe, High-Speed (10Mbps), Slew-Rate-Limited RS-485/RS-422Transceiverso For Low-Voltage ApplicationsMAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E: +3.3V Powered, ±15kVESD-Protected, 12Mbps, Slew-Rate-Limited,True RS-485/RS-422 Transceivers For pricing, delivery, and ordering information, please contact Maxim Direct at1-888-629-4642, or visit Maxim Integrated’s website at .______________________________________________________________Selection Table19-0122; Rev 10; 9/14PARTNUMBERHALF/FULL DUPLEX DATA RATE (Mbps) SLEW-RATE LIMITED LOW-POWER SHUTDOWN RECEIVER/DRIVER ENABLE QUIESCENT CURRENT (μA) NUMBER OF RECEIVERS ON BUS PIN COUNT MAX481Half 2.5No Yes Yes 300328MAX483Half 0.25Yes Yes Yes 120328MAX485Half 2.5No No Yes 300328MAX487Half 0.25Yes Yes Yes 1201288MAX488Full 0.25Yes No No 120328MAX489Full 0.25Yes No Yes 1203214MAX490Full 2.5No No No 300328MAX491Full 2.5No No Yes 3003214MAX1487 Half 2.5No No Yes 2301288Ordering Information appears at end of data sheet.找电子元器件上宇航军工MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-LimitedRS-485/RS-422 TransceiversPackage Information For the latest package outline information and land patterns, go to . Note that a “+”, “#”, or “-”in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.16Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-100017©2014 Maxim Integrated Products, Inc.Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.。

MAX6425UK46-T中文资料

General DescriptionThe MAX6340/MAX6421–MAX6426 low-power micro-processor supervisor circuits monitor system voltages from 1.6V to 5V. These devices perform a single function:they assert a reset signal whenever the V CC supply volt-age falls below its reset threshold. The reset output remains asserted for the reset timeout period after V CC rises above the reset threshold. The reset timeout is exter-nally set by a capacitor to provide more flexibility.The MAX6421/MAX6424 have an active-low, push-pull reset output. The MAX6422 has an active-high,push-pull reset output and the MAX6340/MAX6423/MAX6425/MAX6426 have an active-low, open-drain reset output. The MAX6421/MAX6422/MAX6423 are offered in 4-pin SC70 or SOT143 packages. The MAX6340/MAX6424/MAX6425/MAX6426 are available in 5-pin SOT23-5 packages.ApplicationsPortable EquipmentBattery-Powered Computers/Controllers Automotive Medical Equipment Intelligent Instruments Embedded Controllers Critical µP Monitoring Set-Top Boxes ComputersFeatureso Monitor System Voltages from 1.6V to 5V o Capacitor-Adjustable Reset Timeout Period o Low Quiescent Current (1.6µA typ)o Three RESET Output OptionsPush-Pull RESET Push-Pull RESET Open-Drain RESET o Guaranteed Reset Valid to V CC = 1V o Immune to Short V CC Transientso Small 4-Pin SC70, 4-Pin SOT143, and 5-Pin SOT23Packages o MAX6340 Pin Compatible with LP3470o MAX6424/MAX6425 Pin Compatible with NCP300–NCP303, MC33464/MC33465,S807/S808/S809, and RN5VD o MAX6426 Pin Compatible with PST92XXMAX6340/MAX6421–MAX6426Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay________________________________________________________________Maxim Integrated Products1Ordering InformationPin Configurations19-2440; Rev 2; 10/02For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .Typical Operating Circuit appears at end of data sheet.Selector Guide appears at end of data sheet.Note: The MAX6340/MAX6421–MAX6426 are available with fac-tory-trimmed reset thresholds from 1.575V to 5.0V in approxi-mately 0.1V increments. Insert the desired nominal reset threshold suffix (from Table 1) into the blanks. There are 50 stan-dard versions with a required order increment of 2500 pieces.Sample stock is generally held on standard versions only (see Standard Versions Table). Required order increment is 10,000pieces for nonstandard versions. Contact factory for availability.All devices are available in tape-and-reel only.M A X 6340/M A X 6421–M A X 6426Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.All Voltages Referenced to GNDV CC ........................................................................-0.3V to +6.0V SRT, RESET , RESET (push-pull).................-0.3V to (V CC + 0.3V)RESET (open drain)...............................................-0.3V to +6.0V Input Current (all pins)......................................................±20mA Output Current (RESET , RESET)......................................±20mAContinuous Power Dissipation (T A = +70°C)4-Pin SC70 (derate 3.1mW/°C above +70°C)..............245mW 4-Pin SOT143 (derate 4mW/°C above +70°C).............320mW 5-Pin SOT23 (derate 7.1mW/°C above +70°C)............571mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range.............................-65°C to +150°C Junction Temperature......................................................+150°C Lead Temperature (soldering, 10s).................................+300°CMAX6340/MAX6421–MAX6426Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay_______________________________________________________________________________________300.51.01.52.02.53.03.54.00213456SUPPLY CURRENT vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (µA )0.1110010100010,0000.0010.10.011101001000RESET TIMEOUT PERIOD vs. C SRTM A X 6421/26 t o c 02C SRT (nF)R E S E T T I M E O U T P E R I O D(m s )4.104.204.154.254.30-50-25255075100125RESET TIMEOUT PERIOD vs. TEMPERATURETEMPERATURE (°C)R E S E T T I M E O U T P E R I O D (m s )RESET TIMEOUT PERIOD vs. TEMPERATURE200250350300500550450400600R E S E T T I M E O U T P E R I O D (µs )-5025-255075100125TEMPERATURE (°C)050251007515012517504002006008001000MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVERESET THRESHOLD OVERDRIVE (mV)T R A N S I E N T D U R A T I O N (µs )V CCTO RESET DELAYvs. TEMPERATURE (V CC FALLING)8090110100140150130120160V C C T O R E S E T D E L A Y (µs )-5025-255075100125TEMPERATURE (°C)POWER-UP/POWER-DOWNCHARACTERISTIC1V/div1V/div400µs/div0.9940.9980.9961.0021.0001.0041.006-502550-25075100125NORMALIZED RESET THRESHOLDvs. TEMPERATUREM A X 6421/26 t o c 08TEMPERATURE (°C)N O R M A L I Z E D R E S E T T H R E S H O L DTypical Operating Characteristics(V CC = 5V, C SRT = 1500pF, T A = +25°C, unless otherwise noted.)M A X 6340/M A X 6421–M A X 6426Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay4_______________________________________________________________________________________Detailed DescriptionReset OutputThe reset output is typically connected to the reset input of a µP. A µP ’s reset input starts or restarts the µP in a known state. The MAX6340/MAX6421–MAX6426 µP supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power-down,and brownout conditions (see Typical Operating Characteristics ).RESET changes from high to low whenever V CC drops below the threshold voltage. Once V CC exceeds the threshold voltage, RESET remains low for the capacitor-adjustable reset timeout period.The MAX6422 active-high RESET output is the inverse logic of the active-low RESET output. All device outputs are guaranteed valid for V CC > 1V.The MAX6340/MAX6423/MAX6425/MAX6426 are open-drain RESET outputs. Connect an external pullup resis-tor to any supply from 0 to 5.5V. Select a resistor value large enough to register a logic low when RESET is asserted and small enough to register a logic high while supplying all input current and leakage paths connected to the RESET line. A 10k Ωto 100k Ωpullup is sufficient in most applications.Selecting a Reset CapacitorThe reset timeout period is adjustable to accommodate a variety of µP applications. Adjust the reset timeout period (t RP ) by connecting a capacitor (C SRT ) between SRT and ground. Calculate the reset timeout capacitor as follows:RESET Output Allows Use with Multiple SuppliesMAX6340/MAX6421–MAX6426Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay_______________________________________________________________________________________5C SRT = (t RP - 275µs) / (2.73 ✕106)where t RP is in seconds and C SRT is in farads.The reset delay time is set by a current/capacitor-con-trolled ramp compared to an internal 0.65V reference.An internal 240nA ramp current source charges the external capacitor. The charge to the capacitor is cleared when a reset condition is detected. Once the reset condition is removed, the voltage on the capacitor ramps according to the formula: dV/dt = I/C. The C SRT capacitor must ramp to 0.65V to deassert the reset.C SRT must be a low-leakage (<10nA) type capacitor;ceramic is recommended.Operating as a Voltage DetectorThe MAX6340/MAX6421–MAX6426 can be operated in a voltage detector mode by floating the SRT pin. The reset delay times for V CC rising above or falling below the threshold are not significantly different. The reset output is deasserted smoothly without false pulses.Applications InformationInterfacing to Other Voltages for LogicCompatibilityThe open-drain outputs of the MAX6340/MAX6423/MAX6425/MAX6426 can be used to interface to µPs with other logic levels. As shown in Figure 1, the open-drain output can be connected to voltages from 0 to 5.5V. This allows for easy logic compatibility to various µPs.Wired-OR ResetTo allow auxiliary circuitry to hold the system in reset,an external open-drain logic signal can be connected to the open-drain RESET of the MAX6340/MAX6423/MAX6425/MAX6426, as shown in Figure 2. This config-uration can reset the µP, but does not provide the reset timeout when the external logic signal is released.Negative-Going V CC TransientsIn addition to issuing a reset to the µP during power-up,power-down, and brownout conditions, these supervisors are relatively immune to short-duration negative-going transients (glitches). The graph Maximum Transient Duration vs. Reset Threshold Overdrive in the Typical Operating Characteristics shows this relationship.The area below the curve of the graph is the region in which these devices typically do not generate a reset pulse. This graph was generated using a negative-going pulse applied to V CC , starting above the actual reset threshold (V TH ) and ending below it by the magni-tude indicated (reset-threshold overdrive). As the mag-nitude of the transient decreases (farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a V CC transient that goes 100mV below the reset threshold and lasts 50µs or less does not cause a reset pulse to be issued.Ensuring a Valid RESET or RESETDown to V CC = 0When V CC falls below 1V, RESET /RESET current-sink-ing (sourcing) capabilities decline drastically. In the case of the MAX6421/MAX6424, high-impedance CMOS-logic inputs connected to RESET can drift to undetermined voltages. This presents no problems in most applications, since most µPs and other circuitry do not operate with V CC below 1V.In those applications where RESET must be valid down to zero, adding a pulldown resistor between RESET and ground sinks any stray leakage currents, holding RESET low (Figure 3). The value of the pulldown resis-tor is not critical; 100k Ωis large enough not to load RESET and small enough to pull RESET to ground. For applications using the MAX6422, a 100k Ωpullup resis-M A X 6340/M A X 6421–M A X 6426Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay6_______________________________________________________________________________________tor between RESET and V CC holds RESET high when V CC falls below 1V (F igure 4). Open-drain RESET ver-sions are not recommended for applications requiring valid logic for V CC down to zero.Layout ConsiderationSRT is a precise current source. When developing the layout for the application, be careful to minimize board capacitance and leakage currents around this pin.Traces connected to SRT should be kept as short as possible. Traces carrying high-speed digital signals and traces with large voltage potentials should be rout-ed as far from SRT as possible. Leakage current and stray capacitance (e.g., a scope probe) at this pin could cause errors in the reset timeout period. When evaluating these parts, use clean prototype boards to ensure accurate reset periods.Figure 3. Ensuring RESET Valid to V CC= 0CCMAX6340/MAX6421–MAX6426Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay7factory for availability of nonstandard versions.Typical Operating CircuitM A X 6340/M A X 6421–M A X 6426Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay8_______________________________________________________________________________________Pin Configurations (continued)Chip InformationTRANSISTOR COUNT: 295PROCESS: BiCMOSMAX6340/MAX6421–MAX6426Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay_______________________________________________________________________________________9Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)M A X 6340/M A X 6421–M A X 6426Low-Power, SC70/SOT µP Reset Circuits with Capacitor-Adjustable Reset Timeout DelayMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.10____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2002 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)。

SDRAM EM638165TS-6G TSOP54

R/½s¸¹¡G E107012005/09/08EtronTech EM638165Etron Technology, Inc.No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-57786714Mega x 16 Synchronous DRAM (SDRAM)Preliminary (Rev 0.6, 2/2001)Features• Fast access time from clock: 5/6/6/6/7 ns • Fast clock rate: 166/143/133/125/100 MHz • Fully synchronous operation • Internal pipelined architecture • 1M word x 16-bit x 4-bank • Programmable Mode registers - CAS# Latency: 2, or 3- Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function• Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • CKE power down mode• Single +3.3V ± 0.3V power supply • Interface: LVTTL• 54-pin 400 mil plastic TSOP II packageOverviewThe EM638165 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.The EM638165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use.By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.Pin Assignment (Top View)Key SpecificationsEM638165- 6/7/7.5/8/10t CK3 Clock Cycle time(min.)6/7/7.5/8/10 ns t AC3 Access time from CLK(max.) 5/5.4/5.4/6/7 nst RAS Row Active time(max.) 42/45/45/48/50 ns t RC Row Cycle time(min.)60/63/68/70/80 nsOrdering InformationPart Number Frequency Package EM638165TS-6 166MHz TSOP II EM638165TS-7 143MHz TSOP II EM638165TS-7.5 133MHz TSOP II EM638165TS-8 125MHz TSOP II EM638165TS-10100MHzTSOP II7-155- 2/76 -REEtronTech EM638165Block DiagramR E COUNTERADDRESSBUFFER- 3/76 -7-155EtronTech EM638165Pin DescriptionsTable 1. Pin Details of EM638165Symbol Type DescriptionCLKInputClock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.CKE InputClock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power.Bank Select: BA0,BA1 input select the bank for operation.BA1 BA0 Select Bank 0 0 BANK #A 0 1 BANK #B1 0 BANK #C BA0,BA1 Input11BANK #DA0-A11 InputAddress Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location out of the 2M available in the respective bank. During a Precharge command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set command.CS# InputChip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code.RAS# InputRow Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation.CAS# InputColumn Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH."7-15- 4/76 -REEtronTech EM638165 WE# Input Write Enable: The WE# signal defines the operation commands in conjunctionwith the RAS# and CAS# signals and is latched at the positive edges of CLK.The WE# input is used to select the BankActivate or Precharge command andRead or Write command.LDQM, UDQM Input Data Input/Output Mask: Controls output buffers in read mode and masks Input data in write mode.DQ0-DQ15 Input /Output Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are maskable during Reads and Writes.NC/RFU - No Connect: These pins should be left unconnected.V DDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity.( 3.3V± 0.3V )V SSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.( 0 V )V DD Supply Power Supply: +3.3V ± 0.3VV SS Supply Ground7-15- 5/76 -R ERClock Suspend Mode Entry Active H L X X X X X X X XPower Down Mode Entry Any(5)H L X X X X H X X XL H H HClock Suspend Mode Exit Active L H X X X X X X X XPower Down Mode Exit Any L H X X X X H X X X(PowerDown)L H H HData Write/Output Enable Active H X L X X X X X X XData Mask/Output Disable Active H X H X X X X X X XNote: 1. V=Valid X=Don't Care L=Low level H=High level2. CKE n signal is input level when commands are provided.CKE n-1 signal is input level one clock cycle before the commands are provided.3. These are states of bank designated by BS signal.4. Device state is 1, 2, 4, 8, and full page burst operation.5. Power Down Mode can not enter in the burst operation.When this command is asserted in the burst cycle, device state is clock suspend mode.- 6/767-152 BankPrecharge command(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)The BankPrecharge command precharges the bank disignated by BA signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime aftert RAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time anybank can be active is specified by t RAS(max.). Therefore, the precharge function must be performedin any active bank within t RAS(max.). At the end of precharge, the precharged bank is still in the idlestate and is ready to be activated again.3 PrechargeAll command(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0-A9 and A11 = Don't care)The PrechargeAll command precharges all banks simultaneously and can be issued even if all banks are not in the active state. All banks are then switched to the idle state.4 Read command(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A7 = Column Address)The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least t RCD(min.) before the Read command isissued. During read bursts, the valid data-out element from the starting column address will beavailable following the CAS# latency after the issue of the Read command. Each subsequent data-out element will be valid by the next positive clock edge (refer to the following figure). The DQs gointo high-impedance at the end of the burst unless other command is initiated. The burst length,burst sequence, and CAS# latency are determined by the mode register, which is already- 7/76 programmed. A full-page burst will continue until terminated (at the end of the page it will wrap tocolumn 0 and continue). 7-15t CK3, DQ'sRead Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comesfrom a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures). If the data output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior tothe Write command to avoid internal bus contention.CLK DQMCOMM ANDDQ'sT0T 1T2T3T4T 5T6T 7T8Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 3)7-15- 8/76A read burst without the auto precharge function may be interrupted by a BankPrecharge/PrechargeAll command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll command is issued in different CAS# latency.CLKCOMMANDCAS# latency=2 t CK2, DQ'sCAS# latency=3t CK3, DQ'sADDRESSRead to Precharge (CAS# Latency = 2, 3)5 Read and AutoPrecharge command(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A7 = Column Address)The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within atime delay of {t RP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. 7-15- 9/76COMMANDDQ'sWrite Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)The Read command that interrupts a write burst without auto precharge function should beissued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). Once the Read command isregistered, the data inputs will be ignored and writes will not be executed.CLKCOMMAND T0T 1T2T3T4T5T6T7T8data contention.CAS# latency=2t CK2, DQ's CAS# latency=3t CK3, DQ'sWrite Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)7-15- 10/76the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + t WR + t RP (min.)}. At full-page burst, only the write operation isperformed in this command and the auto precharge function is ignored.CLK COMMANDT0T 1T2T3T4T5T6T7T8CAS# latency=2t CK2, DQ's CAS# latency=3t CK3, DQ'st DAL = t WR + t RP*Begin AutoPrechargeBank can be reactivated at completion of t DALBurst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3)8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)The mode register stores the data for controlling the various operating modes of SDRAM. TheMode Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode Register after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the mode register. One clock cycle is required to complete the write in the mode register (refer to the following figure). The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state.7-15- 11/76Set Command CommandMode Register Set Cycle (CAS# Latency = 2, 3)The mode register is divided into various fields depending on functionality.Address BS0,1 A11,10 A9A8A7A6A5A4A3 A2 A1 A0Function RFU* RFU* WBL Test ModeCAS Latency BT Burst Length*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.• Burst Length Field (A2~A0)This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8, or full page.A2 A1 A0 Burst Length0 0 0 10 0 1 2 0 1 0 4 0 1 1 81 0 0 Reserved1 0 1 Reserved 1 1 0 Reserved 111Full Page7-15- 12/76RRData 2 A7 A6 A5 A4 A3 A2 A1# A0Data 3 A7 A6 A5 A4 A3 A2 A1# A0# 8 wordsData 4 A7 A6 A5 A4 A3 A2# A1 A0Data 5 A7 A6 A5 A4 A3 A2# A1 A0#Data 6 A7 A6 A5 A4 A3 A2# A1# A0Data 7 A7 A6 A5 A4 A3 A2# A1# A0#•CAS# Latency Field (A6~A4)This field specifies the number of clock cycles from the assertion of the Read command to the firstread data. The minimum whole value of CAS# Latency depends on the frequency of CLK. Theminimum whole value satisfying the following formula must be programmed into this field.t CAC(min) ≤ CAS# Latency X t CKA6 A5 A4 CAS# Latency0 0 0 Reserved0 0 1 Reserved0 1 0 2 clocks0 1 1 3 clocks1 X X Reserved- 13/767-15CLKCOMMANDCAS # latency=2t CK2, DQ's CAS # latency=3t CK3, DQ'sTermination of a Burst Read Operation (Burst Length ¡Ö 4, CAS# Latency = 2, 3)CLKCOMMAND DQ'sTermination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3)7-15- 14/76This command is used to exit from the SelfRefresh mode. Once this command is registered,NOP or Device Deselect commands must be issued for t RC (min.) because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode.15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) fromthe subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms) since the command does not perform any refresh operations. 16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")When the internal CLK has been suspended, the operation of the internal CLK is reinitiatedfrom the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. t PDE (min.) is required when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command. 17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")During a write cycle, the DQM signal functions as a Data Mask and can control every word ofthe input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system.7-15- 15/76RR - 16/767-15EtronTech EM638165Recommended D.C. Operating Conditions (V DD = 3.3V ± 0.3V, Ta = 0~70°C)- 6/7/7.5/8/10Description/Test condition Symbol Max. Unit Note Operating Currentt RC ≥ t RC(min), Outputs Open I DD185 3 Precharge Standby Current in non-power down modet CK = 15ns, CS#≥ V IH(min), CKE≥ V IH I DD2N20 3 Precharge Standby Current in non-power down modet CK = ∞, CLK ≤ V IL(max), CKE≥ V IH I DD2NS15Precharge Standby Current in power down modet CK = 15ns, CKE ≤ V IL(max)I DD2P2 3 Precharge Standby Current in power down modet CK = ∞, CKE ≤ V IL(max)I DD2PS1Active Standby Current in non-power down modeCKE≥ V IH(min), CS#≥ V IH(min), t CK = 15ns I DD3N30Active Standby Current in non-power down modeCKE≥ V IH(min), CLK ≤ V IL(max), t CK = ∞I DD3NS25Operating Current (Burst mode)t CK =t CK(min), Outputs Open, Multi-bank interleave I DD4100 3, 4 Refresh Currentt RC ≥ t RC(min) I DD5130 3Self Refresh CurrentV IH≥ V DD - 0.2, 0V ≤ V IL≤ 0.2V I DD61mAParameter Description Min. Max. Unit NoteI IL Input Leakage Current( 0V ≤ V IN≤ V DD, All other pins not under test = 0V )- 1 1 µAI OL Output Leakage CurrentOutput disable, 0V ≤ V OUT≤ V DDQ)- 1 1 µAV OH LVTTL Output "H" Level Voltage( I OUT = -2mA )2.4 ¡ÐVV OL LVTTL Output "L" Level Voltage( I OUT = 2mA )¡Ð0.4 V7-15- 17/76 R ER5/5.4/5.4/6/7t OH Data output hold time 2.5/2.7/3/3/3 9t LZ Data output low impedance 1t HZ Data output high impedance 5/5.4/5.4/6/7 8t IS Data/Address/Control Input set-up time 1/1.5/1.3/2/2.5 10t IH Data/Address/Control Input hold time 1/0.8/0.8/0.8/0.8 10t PDE Power Down Exit set-up time 6/7/7.5/8/10* CL is CAS# Latency.Note:1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage tothe device.2. All voltages are referenced to V SS.3. These parameters depend on the cycle rate and these values are measured by the cycle rate under theminimum value of t CK and t RC. Input signals are changed one time during t CK.4. These parameters depend on the output loading. Specified values are obtained with the output open.5. Power-up sequence is described in Note 11.- 18/767-158. t HZ defines the time in which the outputs achieve the open circuit condition and are not at referencelevels.9. If clock rising time is longer than 1 ns, ( t R / 2 -0.5) ns should be added to the parameter.10. Assumed input rise and fall time t T ( t R & t F ) = 1 nsIf t R or t F is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] nsshould be added to the parameter.11. Power up SequencePower up must be performed in the following sequence.1) Power must be applied to V DD and V DDQ(simultaneously) when all input signals are held "NOP" stateand both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.2) After power-up, a pause of 200µseconds minimum is required. Then, it is recommended that DQMis held "HIGH" (V DD levels) to ensure DQ output is in high impedance.3) All banks must be precharged.4) Mode Register Set command must be asserted to initialize the Mode register.5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry ofthe device.- 19/767-15EtronTech EM638165 Timing WaveformsFigure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2) BA0,1T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22C om ma nd Bank A AutoPrechargeCom ma ndBank AC om ma ndBank BAutoPrechargeC om ma ndBank BCom ma ndBank AC om ma ndBank AC om ma ndBank AC om ma ndBank ACom ma ndBank BCLKCKECS#RAS#CAS#WE#A10A0-A9,A11DQMDQ7-15- 20/7 R- 21/7 7-15- 22/7 7-15- 23/7 7-15EtronTech EM638165Figure 5. Self Refresh Entry & Exit CycleCLKCKECS#RAS#CAS#BA0,1A0-A9,A11WE#DQMDQNote: To Enter SelfRefresh Mode1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.3. The device remains in SelfRefresh mode as long as CKE stays "low".Once the device enters SelfRefresh mode, minimum t RAS is required before exit from SelfRefresh. To Exit SelfRefresh Mode1. System clock restart and be stable before returning CKE high.2. Enable CKE and CKE should be set high for minimum time of t SRX .3. CS# starts from high.4. Minimum t RC is required after CKE going high to complete SelfRefresh exit.5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh.7-15- 24/76REEtronTech EM638165 R E Figure 6.1. Clock Suspension During Burst Read (Using CKE)(Burst Length=4, CAS# Latency=1)T8T9T10T 11T1T13T14T15T16T17T1T19T20T21T22T0T 1T2T3T4T5T6T7CLKCKECS#RAS#CAS#WE#BA0,1A10A0-A9,A11DQMDQCom ma ndBank ANote: CKE to CLK disable/enable = 1 clock7-15- 25/76- 26/7 7-15- 27/7 7-15- 28/7 7-15- 29/7 7-15- 30/7 7-15- 31/7 7-15- 32/7 7-15- 33/7 7-15- 34/7 7-15EtronTech EM638165Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=1)T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22CLKCKECS#RAS#CAS#WE#A10A0~A9,A11DQM DQBA0,1C Com ma nd Bank BHi-Z Com ma nd Bank BC omma nd Bank B7-15- 35/76RE- 36/7 7-15- 37/7 7-15- 38/7 7-15- 39/7 7-15EtronTech EM638165 Figure 11.3. Random Row Read (Interleaving Banks)(Burst Length=8, CAS# Latency=3)T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22 CLKCKECS#RAS#CAS#WE#A10A0~A9,A11DQMDQBA0,1Com ma nd Bank BCom mandBank AC omma ndBank BCom mandBank BCom mandBank BC omma ndBank AC omma ndBank BCom mandBank A7-15- 40/76 R E- 41/7 7-15- 42/7 7-15EtronTech EM638165Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=3)T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22CLKCKE CS#RAS#CAS#WE#A10A0~A9,A11DQMDQBA0,1t CK3Com ma nd Bank A Com mand Bank B Com mand Bank A Com ma nd Bank A Com ma nd Bank BC omma nd Bank ACom mand Bank B Com mand Bank A* t WR > t WR (min.)7-1- 43/7R- 44/7 7-15- 45/7 7-15- 46/7 7-15- 47/7 7-15- 48/7 7-15- 49/7 7-15- 50/7 7-15。

M63812P中文资料

mA
V
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, Ta = 25°C)
Symbol V (BR) CEO VCE(sat) VIN(on) VR IR h FE Parameter Collector-emitter breakdown voltage Test conditions Limits min 35 — — 13 — — 50 typ — — — 19 1.2 — — max — 0.2 0.8 23 2.0 10 — Unit V V V V µA —
GND
→COM COMMOM
Package type
16P4(P) 16P2N-A(FP) 16P2S-A(GP) 16P2Z-A(KP)
CIRCUIT DIAGRAM
COM OUTPUT
Vz=7V
APPLICATION Driving of digit drives of indication elements (LEDs and lamps) with small signals
•The collector current values represent the current per circuit. •Repeated frequency ≥ 10Hz •The value the circle represents the value of the simultaneously-operated circuit. •Ta = 85°C
Thermal Derating Factor Characteristics 2.0
Power dissipation Pd (W)
Input Characteristics 4

MAX6315US36D4-T中文资料

2
_______________________________________________________________________________________
元器件交易网
Open-Drain SOT µP Reset Circuit
__________________________________________Typical Operating Characteristics
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ordering and Marking Information appear at end of data sheet.
__________Typical Operating Circuit
VCC
__________________Pin Configuration
VCC LASERTRIMMED RESISTORS

MAXIM MAX4561 MAX4568 MAX4569 数据手册

General DescriptionThe MAX4561/MAX4568/MAX4569 are low-voltage,ESD-protected analog switches. The normally open (NO) and normally closed (NC) inputs are protected against ±15kV electrostatic discharge (ESD) without latchup or damage, and the COM input is protected against 2.5kV ESD.These switches operate from a single +1.8V to +12V supply. The 70Ωat 5V (120Ωat 3V) on-resistance is matched between channels to 2Ωmax, and is flat (4Ωmax) over the specified signal range. The switches can handle Rail-to-Rail ® analog signals. Off-leakage current is only 0.5nA at +25°C and 5nA at +85°C. The digital input has +0.8V to +2.4V logic thresholds, ensuring TTL/CMOS-logic compatibility when using a single +5V supply. The MAX4561 is a single-pole/double-throw (SPDT) switch. The MAX4568 NO and MAX4569 NC are single-pole/single-throw (SPST) switches.The MAX4561 is available in a 6-pin SOT23 package,and the MAX4568/MAX4569 are available in 5-pin SOT23 packages.________________________ApplicationsHigh-ESD Environments Battery-Powered Systems Audio and Video Signal Routing Low-Voltage Data-Acquisition Systems Sample-and-Hold Circuits Communications CircuitsFeatureso ESD-Protected NO, NC±15kV—Human Body Model±15kV—IEC 1000-4-2, Air-Gap Discharge ±8kV—IEC 1000-4-2, Contact Discharge o Guaranteed On-Resistance70Ω+5V Supply120Ωwith Single +3V Supplyo On-Resistance Match Between Channels (2Ωmax)o Low On-Resistance Flatness: 4Ωmax o Guaranteed Low Leakage Currents0.5nA Off-Leakage (at T A = +25°C)0.5nA On-Leakage (at T A = +25°C)o Guaranteed Break-Before-Make at 5ns(MAX4561 only)o Rail-to-Rail Signal Handling Capabilityo TTL/CMOS-Logic Compatible with +5V Supplies o Industry Standard Pin-OutsMAX4561 Pin Compatible with MAX4544MAX4568/MAX4569 Pin Compatible with MAX4514/MAX4515MAX4561/MAX4568/MAX4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches________________________________________________________________Maxim Integrated Products 1Pin Configurations/Functional Diagrams/Truth Tables19-1714; Rev 0; 4/00For free samples and the latest literature, visit or phone 1-800-998-8800.For small orders, phone 1-800-835-8769.Ordering InformationRail-to-Rail is a registered trademark of Nippon Motorola, Ltd.查询MAX4561EUT-T供应商M A X 4561/M A X 4568/M A X 4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS —Single +5V Supply(V+ = +4.5V to +5.5V, V IH = +2.4V, V IL = +0.8V, T A = T MIN to T MAX , unless otherwise specified. Typical values are at T A = +25°C.)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.V+ to GND................................................................-0.3 to +13V IN, COM, NO, NC to GND (Note 1)..............-0.3V to (V+ + 0.3V)Continuous Current (any terminal)....................................±10mA Peak Current(NO, NC, COM; pulsed at 1ms 10% duty cycle).........±30mA ESD Protection per Method IEC 1000-4-2 (NO, NC)Air-Gap Discharge........................................................±15kV Contact Discharge..........................................................±8kVESD Protection per Method 3015.7V+, GND, IN, COM.......................................................±2.5kV NO, NC..........................................................................±15kV Continuous Power Dissipation (T A = +70°C)SOT23 (derate 8.7mW/°C above +70°C)....................696mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CNote 1:Signals on NO, NC, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward current to maximumcurrent rating.MAX4561/MAX4568/MAX4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS —Single +5V Supply (continued)050150100200250ON-RESISTANCEvs. V COM AND SUPPLY VOLTAGEV COM (V)R O N (Ω)4812302010405060021345ON-RESISTANCE vs. TEMPERATUREV COM (V)R D S (O N ) (Ω)40020010008006001600140012001800-4020-20406080100LEAKAGE CURRENT vs. TEMPERATURETEMPERATURE (°C)L E A K A G E C U R R E N T (p A )Typical Operating Characteristics(T A = +25°C, unless otherwise noted.)M A X 4561/M A X 4568/M A X 4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches 4_______________________________________________________________________________________ELECTRICAL CHARACTERISTICS —Single +3V Supply(V+ = +2.7V to +3.6V, V IH = +2.0V, V IL = +0.6V, T A = T MIN to T MAX , unless otherwise specified. Typical values are at T A = +25°C.)Note 3:Parameters are 100% tested at +25°C and guaranteed by correlation at the full rated temperature.Note 4:∆R ON = R ON(MAX)- R ON(MIN).Note 5:Flatness is defined as the difference between the maximum and the minimum value of on-resistance as measured over thespecified analog signal ranges.Note 6:Off-Isolation = 20log 10(V COM /V NO ), V COM = output, V NO = input to off switch.MAX4561/MAX4568/MAX4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches________________________________________________________________________________________50201040305060-402040-206080100SUPPLY CURRENTvs. TEMPERATURE AND SUPPLY VOLTAGETEMPERATURE (°C)S U P P L Y C U R R E N T (n A)40208060100120-40020-20406080TURN-ON/TURN-OFF TIME vs. TEMPERATURETEMPERATURE (°C)t O N /t O F F (n s )40208060100120021345TURN-ON/TURN-OFF TIME vs. V COMV COM (V)t O N /t O F F (n s )TURN-ON/TURN-OFF TIME vs. V COM02040608010012014016001.00.51.52.02.53.0V COM (V)t O N /t O F F (n s )010050200150300250350TURN-ON/TURN-OFF TIME vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)t O N /t O F F (n s )12345Typical Operating Characteristics (continued)(T A = +25°C, unless otherwise noted.)40208060120100140180160200-60-20-4020406080100SCR HOLDING CURRENT vs. TEMPERATURETEMPERATURE (°C)H O L D I N G C U R R E N T (m A )-40-25-30-35-20-15-10-5051021345MAX4561CHARGE INJECTION vs. V COMV COM (V)Q (p C)-1050-5101520021345MAX4568/MAX4569CHARGE INJECTION vs. V COMV COM (V)Q (p C )M A X 4561/M A X 4568/M A X 4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches 6_______________________________________________________________________________________Do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause perma-nent damage to the device.Proper power-supply sequencing is recommended for all CMOS devices. Always sequence V+ on first, fol-lowed by the logic inputs, NO/NC, or COM.High-Voltage SupplyThe MAX4561/MAX4568/MAX4569 are capable of +12V single-supply operation with some precautions.The absolute maximum rating for V+ is +13V (refer-enced to GND). When operating near this region,bypass V+ with a 0.1µF min capacitor to ground as close to the device as possible.Typical Operating Characteristics (continued)(T A = +25°C, unless otherwise noted.)10100010010,000100,000TOTAL HARMONIC DISTORTIONvs. FREQUENCYFREQUENCY (Hz)T H D (%)10.0010.010.10.010.11001000FREQUENCY RESPONSEFREQUENCY (MHz)L O S S (d B )20-100-80-60-40-200110MAX4561/MAX4568/MAX4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches_______________________________________________________________________________________7±15kV ESD ProtectionThe MAX4561/MAX4568/MAX4569 are ±15kV ESD-pro-tected at the NC/NO terminals in accordance with IEC1000-4-2. To accomplish this, bidirectional SCRs are included on-chip between these terminals. When the voltages at these terminals go Beyond-the-Rails ™,the corresponding SCR turns on in a few nanoseconds and bypasses the surge safely to ground. This method is superior to using diode clamps to the supplies because unless the supplies are very carefully decou-pled through low-ESR capacitors, the ESD current through the diode clamp could cause a significant spike in the supplies. This may damage or compromise the reliability of any other chip powered by those same supplies.There are diodes from NC/NO to the supplies in addi-tion to the SCRs. A resistance in series with each of these diodes limits the current into the supplies during an ESD strike. The diodes protect these terminals from overvoltages that are not a result of ESD strikes. These diodes also protect the device from improper power-supply sequencing.Once the SCR turns on because of an ESD strike, it remains on until the current through it falls below its “holding current.” The holding current is typically 110mA in the positive direction (current flowing into the NC/NO terminal) at room temperature (see SCR Holding Current vs.Temperature in the Typical Operating Characteristics ). Design the system so that any sources connected to NC/NO are current-limited to a value below the holding current to ensure the SCR turns off when the ESD event is finished and normal operation resumes. Also, remember that the holding current varies significantly with temperature. The worst case is at +85°C when the holding currents drop to 70mA. Since this is a typical number to guarantee turn-off of the SCRs under all conditions, the sources con-nected to these terminals should be current-limited to no more than half this value. When the SCR is latched,the voltage across it is approximately 3V. The supply voltages do not affect the holding current appreciably.The sources connected to the COM side of the switches need not be current limited since the switches turn off internally when the corresponding SCR(s) latch.Even though most of the ESD current flows to GND through the SCRs, a small portion of it goes into V+.Therefore, it is a good idea to bypass the V+ with 0.1µF capacitors directly to the ground plane.ESD protection can be tested in various ways. Inputs are characterized for protection to the following:•±15kV using the Human Body Model•±8kV using the Contact Discharge method speci-fied in IEC 1000-4-2 (formerly IEC 801-2)•±15kV using the Air-Gap Discharge method speci-fied in IEC 1000-4-2 (formerly IEC 801-2)ESD Test ConditionsContact Maxim Integrated Products for a reliability report that documents test setup, methodology, and results.Human Body ModelFigure 6 shows the Human Body Model, and Figure 7shows the waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which can be dis-charged into the test device through a 1.5k Ωresistor.IEC 1000-4-2The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifi-cally refer to integrated circuits. The MAX4561 enables the design of equipment that meets Level 4 (the highest level) of IEC 1000-4-2, without additional ESD protec-tion components.The major difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak cur-rent in IEC 1000-4-2. Because series resistance is lower in the IEC 1000-4-2 ESD test model (Figure 8), the ESD withstand voltage measured to this standard is generally lower than that measured using the Human Body Model.Figure 9 shows the current waveform for the ±8kV IEC 1000-4-2 Level 4 ESD Contact Discharge test.The Air-Gap test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized.Chip InformationPROCESS: CMOSBeyond-the-Rails is a trademark of Maxim Integrated Products.TRANSISTOR COUNT: 69(MAX4561)39(MAX4568/MAX4569)M A X 4561/M A X 4568/M A X 4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches 8_______________________________________________________________________________________Figure 1. Switching TimeFigure 2. Break-Before-Make IntervalFigure 3. Charge Injection Test Circuits/Timing DiagramsMAX4561/MAX4568/MAX4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches_______________________________________________________________________________________9Figure 4. Channel On/Off-CapacitanceFigure 5. Off-Isolation/On-ChannelFigure 6. Human Body ESD Test ModelFigure 7. Human Body Model Current WaveformFigure 8. IEC 1000-4-2 ESD Test Model Figure 9. IED 1000-4-2 ESD Generator Current WaveformTest Circuits/Timing Diagrams (continued)M A X 4561/M A X 4568/M A X 4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches 10______________________________________________________________________________________Package InformationMAX4561/MAX4568/MAX4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog Switches______________________________________________________________________________________11Package Information (continued)M A X 4561/M A X 4568/M A X 4569±15kV ESD-Protected, Low-Voltage,SPDT/SPST, CMOS Analog SwitchesMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.12____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2000 Maxim Integrated Products Printed USAis a registered trademark of Maxim Integrated Products.NOTES。

MAX31865中文资料_数据手册_参数

VIL
CS, SDI, SCLK
Input Logic 1
Analog Voltages (FORCE+,FORCE2, FORCE-, RTDIN+, RTDIN-) Reference Resistor Cable Resistance
VIH
CS, SDI, SCLK
Normal conversion results
MAX31865 RTD-to-Digital Converter
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VDD Relative to GND1.............-0.3V to +4.0V Voltage Range on BIAS, REFIN+,
Applications
Industrial Equipment Medical Equipment Instrumentation
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part, refer to /MAX31865.related.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN Junction-to-Ambient Thermal Resistance (qJA)...........29°C/W Junction-to-Case Thermal Resistance (qJC)..................2°C/W
EVALUATION KIT AVAILABLE

MAX9635中文资料

16-BIT ADC
Байду номын сангаас
6-BIT RANGE DIGITAL
CDR, TIM
SIGNAL
CONTROL PROCESSING
16-BIT ADC
方框图
VCC
SDA SCL I2C AO INT
N
GND
________________________________________________________________ Maxim Integrated Products 1 本文是英文数据资料的译文，文中可能存在翻译上的不准确或错误。如需进一步确认，请在您的设计中参考英文资料。
平板PC/笔记本电脑 TV/投影仪/显示器
数字照明管理便携设备
蜂窝电话/智能电话
安全系统
应用
业内功耗最低的环境光传感器，内置ADC
特性
♦♦0.045流明至188,000流明宽检测范围 ♦♦小尺寸、2mm x 2mm x 0.6mm UTDFN-Opto封装 ♦♦VCC = 1.7V至3.6V ♦♦工作电流ICC = 0.65µA ♦♦-40°C至+85°C工作温度范围
由于能够检测极其微弱的光线，非常适合光线较暗的工作环境。
片上光电二极管的光谱响应针对人眼对环境光的响应进行优化，集成红外及紫外线屏蔽功能。自适应增益电路可自动选
择正确的流明范围优化测试(计数值 / 流明)。
IC设计工作在1.7V至3.6V供电范围，满负荷工作时仅消耗0.65µA电流。器件采用小尺寸2mm x 2mm x 0.6mm UTDFN-Opto封装。
有关价格、供货及订购信息，请联络Maxim亚洲销售中心：10800 852 1249 (北中国区)，10800 152 1249 (南中国区)，或访问Maxim的中文网站：。

MAX6381XR44D5资料

General Description The MAX6381–MAX6390 microprocessor (µP) supervisory circuits monitor power-supply voltages from +1.8V to +5.0V while consuming only 3µA of supply current at +1.8V. Whenever V CC falls below the factory-set reset thresholds, the reset output asserts and remains assert-ed for a minimum reset timeout period after V CC rises above the reset threshold. Reset thresholds are available from +1.58V to +4.63V, in approximately 100mV incre-ments. Seven minimum reset timeout delays ranging from 1ms to 1200ms are available.The MAX6381/MAX6384/MAX6387 have a push-pull active-low reset output. The MAX6382/MAX6385/ MAX6388 have a push-pull active-high reset output, and the MAX6383/MAX6386/MAX6389/MAX6390 have an open-drain active-low reset output. The MAX6384/MAX6385/MAX6386 also feature a debounced manual reset input (with internal pullup resistor). The MAX6387/MAX6388/MAX6389 have an auxiliary input for monitoring a second voltage. The MAX6390 offers a manual reset input with a longer V CC reset timeout period (1120ms or 1200ms) and a shorter manual reset timeout (140ms or 150ms).The MAX6381/MAX6382/MAX6383 are available in 3-pin SC70 and6-pinµDFN packages and the MAX6384–MAX6390 are available in 4-pin SC70 andFeatures♦Factory-Set Reset Threshold Voltages Rangingfrom +1.58V to +4.63V in Approximately 100mVIncrements♦±2.5% Reset Threshold Accuracy OverTemperature (-40°C to +125°C)♦Seven Reset Timeout Periods Available: 1ms,20ms, 140ms, 280ms, 560ms, 1120ms,1200ms (min)♦3 Reset Output OptionsActive-Low Push-PullActive-High Push-PullActive-Low Open-Drain♦Reset Output State Guaranteed ValidDown to V CC= 1V♦Manual Reset Input (MAX6384/MAX6385/MAX6386)♦Auxiliary RESET IN(MAX6387/MAX6388/MAX6389)♦V CC Reset Timeout (1120ms or 1200ms)/ManualReset Timeout (140ms or 150ms) (MAX6390)♦Negative-Going V CC Transient Immunity♦Low Power Consumption of 6µA at +3.6Vand 3µA at +1.8V♦Pin Compatible withMAX809/MAX810/MAX803/MAX6326/MAX6327/MAX6328/MAX6346/MAX6347/MAX6348,and MAX6711/MAX6712/MAX6713♦Tiny 3-Pin/4-Pin SC70 and 6-Pin µDFN PackagesMAX6381–MAX6390 SC70/µDFN, Single/Dual Low-Voltage,Low-Power µP Reset Circuits ________________________________________________________________Maxim Integrated Products1Pin Configurations19-1839; Rev 4; 4/07Ordering InformationOrdering Information continued at end of data sheet.Typi cal Operati ng Ci rcui t appears at end of data sheet.Selector Guide appears at end of data sheet.after "XR", "XS", or "LT." Insert reset timeout delay (see ResetTimeout Delay table) after "D" to complete the part number.Sample stock is generally held on standard versions only (seeStandard Versions table). Standard versions have an orderincrement requirement of 2500 pieces. Nonstandard versionshave an order increment requirement of 10,000 pieces.Contact factory for availability of nonstandard versions.+Denotes a lead-free package.For pricing, delivery, and ordering information,please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at .ComputersControllersIntelligent InstrumentsCritical µP and µCPower MonitoringPortable/Battery-Powered EquipmentDual Voltage SystemsM A X 6381–M A X 6390SC70/µDFN, Single/Dual Low-Voltage, Low-Power µP Reset CircuitsABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS(V CC = full range, T A = -40°C to +125°C, unless otherwise specified. Typical values are at T A = +25°C.) (Note 1)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.V CC to GND..........................................................-0.3V to +6.0V RESET Open-Drain Output....................................-0.3V to +6.0V RESET , RESET (push-pull output)..............-0.3V to (V CC + 0.3V)MR , RESET IN.............................................-0.3V to (V CC + 0.3V)Input Current (V CC ).............................................................20mA Output Current (all pins).....................................................20mAContinuous Power Dissipation (T A = +70°C)3-Pin SC70 (derate 2.9mW/°C above +70°C)..............235mW 4-Pin SC70 (derate 3.1mW/°C above +70°C)..............245mW 6-Pin µDFN (derate 2.1mW/°C above +70°C)..........167.7mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CMAX6381–MAX6390SC70/µDFN, Single/Dual Low-Voltage,Low-Power µP Reset Circuits_______________________________________________________________________________________3M A X 6381–M A X 6390SC70/µDFN, Single/Dual Low-Voltage, Low-Power µP Reset Circuits 4______________________________________________________________________________________Typical Operating Characteristics(T A = +25°C, unless otherwise noted.)215436789-40-105-25203550658095110125SUPPLY CURRENT vs. TEMPERATURE(NO LOAD)TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )25292735333137394143-40-105-25203550658095110125POWER-DOWN RESET DELAYvs. TEMPERATURETEMPERATURE (°C)P O W E R -D O W N R E S E T D E L A Y (µs )0.940.980.961.021.001.061.041.08-40-10520-253550658095110125NORMALIZED POWER-UP RESET TIMEOUTvs. TEMPERATUREM A X 6381/90 t o c 03TEMPERATURE (°C)N O R M A L I Z E D R E S E T T I M E O U T P E R I O D0.9900.9851.0150.9950.9901.0001.0051.0101.020-40-10520-253550958011065125M A X 6381/90 t o c 04TEMPERATURE (°C)N O R M A L I Z E D R E S E T TH R E S H O L D NORMALIZED RESET THRESHOLDvs. TEMPERATURE00.40.20.80.61.01.2063912OUTPUT-VOLTAGE LOW vs. SINK CURRENTI SINK (mA)V O L (V )01.00.52.01.52.53.00500750250100012501500OUTPUT-VOLTAGE HIGH vs. SOURCE CURRENTI SOURCE (µA)V O H (V )45001100010010MAXIMUM TRANSIENT DURATION vs. RESET COMPARATOR OVERDRIVE15050350250500200100400300RESET COMPARATOR OVERDRIVE, V TH - V CC (mV)M A X I M U M T R A N S I E N T D U R A T I O N (µs )3.53.93.74.54.34.14.74.95.35.15.5-40-105-25203550658095110125RESET IN TO RESET DELAYvs. TEMPERATUREM A X 6381/90 t o c 08TEMPERATURE (°C)R E S E T I N D E L A Y (µs )MAX6381–MAX6390SC70/µDFN, Single/Dual Low-Voltage,Low-Power µP Reset CircuitsPin DescriptionM A X 6381–M A X 6390SC70/µDFN, Single/Dual Low-Voltage, Low-Power µP Reset Circuits 6_______________________________________________________________________________________Detailed DescriptionRESET OutputA µP reset input starts the µP in a known state. These µP supervisory circuits assert reset to prevent code execution errors during power-up, power-down, or brownout conditions.Reset asserts when V CC is below the reset threshold;once V CC exceeds the reset threshold, an internal timer keeps the reset output asserted for the reset timeout period. After this interval, reset output deasserts. Reset output is guaranteed to be in the correct logic state for V CC ≥1V.Manual Reset Input (MAX6384/MAX6385/MAX6386/MAX6390)Many µP-based products require manual reset capabil-ity, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic low on MR asserts reset. Reset remains asserted while MR is low,and for the reset active timeout period (t RP ) after MR returns high. This input has an internal 63k Ωpullup resistor (1.56k Ωfor MAX6390), so it can be left uncon-nected if it is not used. MR can be driven with TTL or CMOS logic levels, or with open-drain/collector outputs.Connect a normally open momentary switch from MR to G ND to create a manual-reset function; external debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environ-ment, connecting a 0.1µF capacitor from MR to G ND provides additional noise immunity.RESET IN Comparator(MAX6387/MAX6388/MAX6389)RESET IN is compared to an internal +1.27V reference.If the voltage at RESET IN is less than 1.27V, reset asserts. Use the RESET IN comparator as a user-adjustable reset detector or as a secondary power-sup-ply monitor by implementing a resistor-divider at RESET IN (shown in Figure 1). Reset asserts when either V CC or RESET IN falls below its respective threshold volt-age. Use the following equation to set the threshold:V INTH = V THRST (R1/R2 + 1)where V THRST = +1.27V. To simplify the resistor selec-tion, choose a value of R2 and calculate R1:R1 = R2 [(V INTH /V THRST ) - 1]Since the input current at RESET IN is 50nA (max),large values can be used for R2 with no significant loss in accuracy.___________Applications InformationNegative-Going V CC TransientsIn addition to issuing a reset to the µP during power-up,power-down, and brownout conditions, the MAX6381–MAX6390 are relatively immune to short dura-tion negative-going V CC transients (glitches).The Typical Operating Characteristics section shows the Maximum Transient Durations vs. Reset Comparator Overdrive, for which the MAX6381–MAX6390 do not generate a reset pulse. This graph was generated usinga negative-going pulse applied to V CC , starting above the actual reset threshold and ending below it by the magnitude indicated (reset comparator overdrive). The graph indicates the typical maximum pulse width a neg-ative-going V CC transient may have without causing a reset pulse to be issued. As the magnitude of the tran-sient increases (goes farther below the reset threshold),the maximum allowable pulse width decreases. A 0.1µF capacitor mounted as close as possible to V CC provides additional transient immunity.Ensuring a Valid RESET Output Down to V CC = 0VThe MAX6381–MAX6390 are guaranteed to operate properly down to V CC = 1V. In applications that require valid reset levels down to V CC = 0V, a pulldown resistor to active-low outputs (push/pull only, Figure 2) and a pullup resistor to active-high outputs (push/pull only)will ensure that the reset line is valid while the reset out-put can no longer sink or source current. This schemedoes not work with the open-drain outputs of the MAX6383/MAX6386/MAX6389/MAX6390. The resistor value used is not critical, but it must be small enough not to load the reset output when V CC is above the reset threshold. For most applications, 100k Ωis ade-quate.MAX6381–MAX6390SC70/µDFN, Single/Dual Low-Voltage,Low-Power µP Reset Circuits_______________________________________________________________________________________7M A X 6381–M A X 6390SC70/µDFN, Single/Dual Low-Voltage, Low-Power µP Reset Circuits 8_______________________________________________________________________________________Selector GuideOrdering Information (continued)Note:Insert reset threshold suffix (see Reset Threshold table)after "XR", "XS", or "LT." Insert reset timeout delay (see Reset Timeout Delay table) after "D" to complete the part number.Sample stock is generally held on standard versions only (see Standard Versions table). Standard versions have an order increment requirement of 2500 pieces. Nonstandard versions have an order increment requirement of 10,000 pieces.Contact factory for availability of nonstandard versions.*MAX6390 is available with D4 or D7 timing only.+Denotes a lead-free package.MAX6381–MAX6390SC70/µDFN, Single/Dual Low-Voltage,Low-Power µP Reset Circuits_______________________________________________________________________________________9Chip InformationTRANSISTOR COUNT: 647PROCESS: BiCMOSPin Configurations (continued)M A X 6381–M A X 6390SC70/µDFN, Single/Dual Low-Voltage, Low-Power µP Reset Circuits 10______________________________________________________________________________________Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)MAX6381–MAX6390SC70/µDFN, Single/Dual Low-Voltage,Low-Power µP Reset Circuits______________________________________________________________________________________11Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)M A X 6381–M A X 6390SC70/µDFN, Single/Dual Low-Voltage, Low-Power µP Reset Circuits 12______________________________________________________________________________________Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)SC70/µDFN, Single/Dual Low-Voltage,Low-Power µP Reset CircuitsMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600____________________13©2007 Maxim Integrated Productsis a registered trademark of Maxim Integrated Products, Inc.MAX6381–MAX6390Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)Revision HistoryPages changed at Rev 4: Title on all pages, 1, 2, 5,7–13。

MAX6314US26D2-T中文资料

General DescriptionThe MAX6314 low-power CMOS microprocessor (µP)supervisory circuit is designed to monitor power supplies in µP and digital systems. The MAX6314’s RESET output is bidirectional, allowing it to be directly connected to µPs with bidirectional reset inputs, such as the 68HC11. It provides excellent circuit reliability and low cost by eliminating external components and adjustments. The MAX6314 also provides a debounced manual reset input.This device performs a single function: it asserts a reset signal whenever the V CC supply voltage falls below a preset threshold or whenever manual reset is asserted.Reset remains asserted for an internally programmed interval (reset timeout period) after V CC has risen above the reset threshold or manual reset is deasserted.The MAX6314 comes with factory-trimmed reset threshold voltages in 100mV increments from 2.5V to 5V. Preset timeout periods of 1ms, 20ms, 140ms,and 1120ms (minimum) are also available. The device comes in a SOT143 package.F or a µP supervisor with an open-drain reset pin, see the MAX6315 data sheet.________________________ApplicationsComputers ControllersIntelligent InstrumentsCritical µP and µC Power Monitoring Portable/Battery-Powered EquipmentFeatures♦Small SOT143 Package♦RESET Output Simplifies Interface to Bidirectional Reset I/Os♦Precision Factory-Set V CC Reset Thresholds:100mV Increments from 2.5V to 5V♦±1.8% Reset Threshold Accuracy at T A = +25°C ♦±2.5% Reset Threshold Accuracy Over Temp.♦Four Reset Timeout Periods Available: 1ms, 20ms, 140ms, or 1120ms (minimum) ♦Immune to Short V CC Transients ♦5µA Supply Current♦Pin-Compatible with MAX811MAX6314*68HC11/Bidirectional-CompatibleµP Reset Circuit________________________________________________________________Maxim Integrated Products1Pin ConfigurationTypical Operating Circuit19-1090; Rev 2; 12/05Ordering Information continued at end of data sheet.*Patents PendingFor pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .Ordering Information†The MAX6314 is available in a SOT143 package, -40°C to+85°C temperature range.††The first two letters in the package top mark identify the part,while the remaining two letters are the lot tracking code.Devices are available in both leaded and lead-free packaging.Specify lead-free by replacing “-T” with “+T” when ordering.M A X 631468HC11/Bidirectional-Compatible µP Reset Circuit 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS(V CC = +2.5V to +5.5V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at T A = +25°C.)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Note 1:The MAX6314 monitors V CC through an internal, factory-trimmed voltage divider that programs the nominal reset threshold.Factory-trimmed reset thresholds are available in 100mV increments from 2.5V to 5V (see Ordering and Marking Information ).Note 2:This is the minimum time RESET must be held low by an external pull-down source to set the active pull-up flip-flop.Note 3:Measured from RESET V OL to (0.8 x V CC ), R LOAD = ∞.V CC ........................................................................-0.3V to +6.0V All Other Pins..............................................-0.3V to (V CC + 0.3V)Input Current (V CC ).............................................................20mA Output Current (RESET )......................................................20mA Rate of Rise (V CC )...........................................................100V/µsContinuous Power Dissipation (T A = +70°C)SOT143 (derate 4mW/°C above +70°C).......................320mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range.............................-65°C to +160°C Lead Temperature (soldering, 10sec).............................+300°CMAX631468HC11/Bidirectional-CompatibleµP Reset Circuit_______________________________________________________________________________________3__________________________________________Typical Operating Characteristics(T A = +25°C, unless otherwise noted.)4.7k Ω PULL-UP 2V/divMAX6314 PULL-UP 2V/divINPUT 5V/div200ns/divPULLUP CHARACTERISTICS100pF4.7k Ω+5V74HC0574HC05V CCGNDMR 100pF+5VRESETMAX63146-50-303090SUPPLY CURRENT vs. TEMPERATURE215TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )-101050347060135SUPPLY CURRENT vs. SUPPLY VOLTAGE215SUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (µA )2344500-50-301090POWER-DOWN RESET DELAYvs. TEMPERATURE1040TEMPERATURE (°C)P O W E R -D O W N R E S E T D E L A Y (µs )-1020303050701.040.96-50-301090NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE (V CC RISING)0.970.981.021.001.03M A X 6314-05TEMPERATURE (°C)N O R M A L I Z E D R E S E T T I M E O U T P E R I O D -100.991.013050701.0060.994-50-301090NORMALIZED RESET THRESHOLD vs. TEMPERATURE (V CC FALLING)0.9960.9981.0041.000M A X 6314-06TEMPERATURE (°C)N O R M A L I Z E D R E S E T T H R E S H O L D-101.0023050701000101001000MAXIMUM TRANSIENT DURATION vs. RESET COMPARATOR OVERDRIVE20RESET COMP. OVERDRIVE, V TH - V CC (mV)M A X I M U M T R A N S I E N T D U R A T I O N (µs )4060806000-50-301090RESET PULLUP TIME vs. TEMPERATURE100200500300TEMPERATURE (°C)R E S E T P U L L -U P -T I M E (n s )-10400305070Figure 1. Functional Diagram M A X 631468HC11/Bidirectional-Compatible µP Reset Circuit 4_____________________________________________________________________________________________________________________________________________________Pin DescriptionSupply Voltage and Reset Threshold Monitor InputV CC4Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR is low, and for the reset timeout period (t RP ) after the reset conditions are terminated. Connect to V CC if not used.MR 3PIN Active-Low Complementary Output. In addition to the normal n-channel pulldown, RESET has a p-channel pullup transistor in parallel with a 4.7k Ωresistor to facilitate connection to µPs with bidirectional resets. See the Reset Output section.RESET2GroundGND 1FUNCTIONNAMEMAX631468HC11/Bidirectional-CompatibleµP Reset Circuit_______________________________________________________________________________________5Detailed DescriptionThe MAX6314 has a reset output consisting of a 4.7k Ωpull-up resistor in parallel with a P-channel transistor and an N-channel pull down (Figure 1), allowing this IC to directly interface with microprocessors (µPs) that have bidirectional reset pins (see the Reset Output section).Reset OutputA µP’s reset input starts the µP in a known state. The MAX6314 asserts reset to prevent code-execution errors during power-up, power-down, or brownout conditions. RESET is guaranteed to be a logic low for V CC > 1V (see the Electrical Characteristics table).Once V CC exceeds the reset threshold, the internal timer keeps reset asserted for the reset timeout period (t RP ); after this interval RESET goes high. If a brownout condition occurs (monitored voltage dips below its pro-grammed reset threshold), RESET goes low. Any time V CC dips below the reset threshold, the internal timer resets to zero and RESET goes low. The internal timer starts when V CC returns above the reset threshold, and RESET remains low for the reset timeout period.The MAX6314’s RESET output is designed to interface with µPs that have bidirectional reset pins, such as the Motorola 68HC11. Like an open-drain output, the MAX6314 allows the µP or other devices to pull RESET low and assert a reset condition. However, unlike a standard open-drain output, it includes the commonly specified 4.7k Ωpullup resistor with a P-channel active pullup in parallel.This configuration allows the MAX6314 to solve a prob-lem associated with µPs that have bidirectional reset pins in systems where several devices connect to RESET . These µPs can often determine if a reset was asserted by an external device (i.e., the supervisor IC)or by the µP itself (due to a watchdog fault, clock error,or other source), and then jump to a vector appropriate for the source of the reset. However, if the µP does assert reset, it does not retain the information, but must determine the cause after the reset has occurred.The following procedure describes how this is done with the Motorola 68HC11. In all cases of reset, the µP pulls RESET low for about four E-clock cycles. It then releases RESET , waits for two E-clock cycles, then checks RESET ’s state. If RESET is still low, the µP con-cludes that the source of the reset was external and,when RESET eventually reaches the high state, jumps to the normal reset vector. In this case, stored state information is erased and processing begins fromscratch. If, on the other hand, RESET is high after the two E-clock cycle delay, the processor knows that it caused the reset itself and can jump to a different vec-tor and use stored state information to determine what caused the reset.The problem occurs with faster µPs; two E-clock cycles is only 500ns at 4MHz. When there are several devices on the reset line, the input capacitance and stray capacitance can prevent RESET from reaching the logic-high state (0.8 x V CC ) in the allowed time if only a passive pullup resistor is used. In this case, all resets will be interpreted as external. The µP is guaranteed to sink only 1.6mA, so the rise time cannot be much reduced by decreasing the recommended 4.7k Ωpullup resistance.The MAX6314 solves this problem by including a pullup transistor in parallel with the recommended 4.7k Ωresis-tor (Figure 1). The pullup resistor holds the output high until RESET is forced low by the µP reset I/O, or by the MAX6314 itself. Once RESET goes below 0.5V, a com-parator sets the transition edge flip-flop, indicating that the next transition for RESET will be low to high. As soon as RESET is released, the 4.7k Ωresistor pulls RESET up toward V CC . When RESET rises above 0.5V,the active p-channel pullup turns on for the 2µs duration of the one-shot. The parallel combination of the 4.7k Ωpullup and the p-channel transistor on-resistance quickly charges stray capacitance on the reset line, allowing RESET to transition low to high with-in the required two E-clock period, even with several devices on the reset line (Figure 2). Once the one-shot times out, the p-channel transistor turns off. This process occurs regardless of whether the reset was caused by V CC dipping below the reset threshold, MR being asserted, or the µP or other device asserting RESET . Because the MAX6314 includes the standard 4.7k Ωpullup resistor, no external pullup resistor is required. To minimize current consumption, the internal pullup resistor is disconnected whenever the MAX6314asserts RESET .Manual Reset InputMany µP-based products require manual reset capabil-ity, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic low on MR asserts reset. Reset remains asserted while MR is low,and for the reset active timeout period after MR returns high. To minimize current consumption, the internal 4.7k Ωpullup resistor on RESET is disconnected whenever RESET is asserted.M A X 631468HC11/Bidirectional-Compatible µP Reset Circuit 6_______________________________________________________________________________________MR has an internal 63k Ωpullup resistor, so it can be left open if not used. Connect a normally open momen-tary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environment, connecting a 0.1µF capacitor from MR to ground provides additional noise immunity.__________Applications InformationNegative-Going V CC TransientsIn addition to issuing a reset to the µP during power-up,power-down, and brownout conditions, these devices are relatively immune to short-duration negative-going transients (glitches). The T ypical Operating Character-istics show the Maximum Transient Duration vs. Reset Threshold Overdrive, for which reset pulses are not generated. The graph was produced using negative-going pulses, starting at V RST max and ending below the programmed reset threshold by the magnitude indicated (reset threshold overdrive). The graph shows the maximum pulse width that a negative-going V CC transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold),the maximum allowable pulse width decreases. A 0.1µF bypass capacitor mounted close to V CC provides addi-tional transient immunity.Ensuring a Valid RESET OutputDown to V CC = 0VWhen V CC falls below 1V, RESET no longer sinks current—it becomes an open circuit. Therefore, high-impedance CMOS-logic inputs connected to RESET can drift to undetermined voltages. This presents no problem in most applications, since most µP and other circuitry is inoperative with V CC below 1V. However, in applications where RESET must be valid down to V CC = 0V, adding a pull-down resistor to RESET will cause any stray leakage currents to flow to ground,holding RESET low (Figure 3). R1’s value is not critical;100k Ωis large enough not to load RESET and small enough to pull RESET to ground.Figure 2. MAX6314 Supports Additional Devices on the Reset BusFigure 3. RESET Valid to V CC = Ground CircuitMAX631468HC11/Bidirectional-CompatibleµP Reset Circuit_______________________________________________________________________________________7Figure 4. RESET Timing Diagram†The MAX6314 is available in a SOT143 package, -40°C to +85°C temperature range.††The first two letters in the package top mark identify the part, while the remaining two letters are the lot tracking code.†††Sample stocks generally held on the bolded products; also, the bolded products have 2,500 piece minimum-order quantities.Non-bolded products have 10,000 piece minimum-order quantities. Contact factory for details.Devices are available in both leaded and lead-free packaging. Specify lead-free by replacing “-T” with “+T” when ordering.Note:All devices available in tape-and-reel only. Contact factory for availability.___________________________________________Ordering Information (continued)M A X 631468HC11/Bidirectional-Compatible µP Reset Circuit Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.8_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2005 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products, Inc._____________________________Ordering and Marking Information (continued)†The MAX6314 is available in a SOT143 package, -40°C to +85°C temperature range.††The first two letters in the package top mark identify the part, while the remaining two letters are the lot tracking code.†††Sample stocks generally held on the bolded products; also, the bolded products have 2,500 piece minimum-order quantities.Non-bolded products have 10,000 piece minimum-order quantities. Contact factory for details.Devices are available in both leaded and lead-free packaging. Specify lead-free by replacing “-T” with “+T” when ordering.Note:All devices available in tape-and-reel only. Contact factory for availability.Chip InformationTRANSISTOR COUNT: 519Package InformationFor the latest package outline information, go to /packages .。

max3485中文资料

MAX3483，MAX3485，MAX3486，MAX3488，MAX3490以及MAX3491是用于RS-485与RS-422通信的3.3V，低功耗收发器，每个器件中都具有一个驱动器和一个接收器。

MAX3483和MAX3488具有限摆率驱动器，可以减小EMI，并降低由不恰当的终端匹配电缆引起的反射，实现最高250kbps的无差错数据传输。

MAX3486的驱动器摆率部分受限，可以实现最高2.5Mbps的传输速率。

MAX3485，MAX3490和MAX3491则可以实现最高10Mbps 的传输速率。

驱动器具有短路电流限制，并可以通过热关断电路将驱动器输出置为高阻状态，防止过度的功率损耗。

接收器输入具有失效保护特性，当输入开路时，可以确保逻辑高电平输出。

特性●半双工●速率：10Mbps●限摆率：NO●接收允许控制：YES●关断电流：2nA●引脚数：8参数暂无MAX3485的参数信息引脚图与功能MAX3485ESA品牌厂家：Maxim Integrated（美信），MAX3485ESA 渠道分销商：2家，现货库存数量：1542 PCS，MAX3485ESA价格参考：¥8.121元。

Maxim Integrated（美信）MAX3485ESA参数（SOIC 8Pin 3V 10Mbps，封装：SOIC），MAX3485ESA中文资料和引脚图及功能表说明书PDF下载（17页，409KB），您可以在MAX3485ESA接口芯片规格书Datesheet数据手册中，查到MAX3485ESA引脚图及功能的应用电路图电压和使用方法，MAX3485ESA典型电路教程。

MAX3485ESA可以用什么代替？代换型号如：MAX3485CSA+T、MAX3485CSA替代换，MAX3485ESA芯片系列中文手册中包含MAX3485ESA各引脚定义说明介绍及MAX3485ESA引脚功能图解，用户中文手册MAX3485ESA芯片手册PDF下载（17页，409KB）。

MAX34561T+;中文规格书,Datasheet资料

_________________________________________________________________Maxim Integrated Products__1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, MAX3456112V/5V Hot-Plug Switch 19-5621; Rev 1; 1/12General Description The MAX34561 is a dual, self-contained, hot-plug switch intended to be used on +12V and +5V power rails to limit through current and to control the power-up output-volt-age ramp. The device contains two on-board n-channel power MOSFETs that are actively closed-loop controlled to ensure that an adjustable current limit is not exceed-ed. The maximum allowable current through the device is adjusted by external resistors connected between the LOAD and ILIM pins.The device can control the power-up output-voltage ramp. Capacitors connected to the VRAMP pins set the desired voltage-ramp rate. The output voltages are unconditionally clamped to keep input overvoltage stresses from harming the load. The device also contains adjustable power-up timers. Capacitors connected to the TIMER pins determine how long after power-on reset (POR) the device should wait before starting to apply power to the loads. The TIMER pins can be driven with a digital logic output to create a device-enable function. The device contains an on-board temperature sensor with hysteresis. If operating conditions cause the device to exceed an internal thermal limit, the device either unconditionally shuts down and latches off awaiting a POR, or waits until the device has cooled by the hyster-esis amount and then restarts.Applications RAID/Hard DrivesServers/RoutersPCI/PCI Express MInfiniBand TM/SMBase StationsFeatures S Completely_Integrated_Hot-Plug_Functionality_for_ +12V_and_+5V_Power_RailsS Dual_Version_of_the_DS4560S On-Board_Power_MOSFETs_(68m I_and_43m I)S No_High-Power_R SENSE_Resistors_NeededS Adjustable_Current_LimitsS Adjustable_Output-Voltage_Slew_RatesS Adjustable_Power-Up_Enable_TimingS Output_Overvoltage_LimitingS On-Board_Thermal_ProtectionS On-Board_Charge_PumpS User-Selectable_Latchoff_or_Automatic_Retry_ OperationOrdering Information+Denotes a lead(Pb)-free/RoHS compliant package.T = Tape and reel.*EP = Exposed pad.PCI Express is a registered trademark of PCI-SIG Corp. InfiniBand is a trademark and service mark of InfiniBand TradeAssociation.PART TEMP_RANGE PIN-PACKAGE MAX34561T+-40N C to +85N C24 TQFN-EP* MAX34561T+T-40N C to +85N C24 TQFN-EP*M A X 3456112V/5V Hot-Plug Switch 2Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Voltage Range on V CC5 Relative to GND ............-0.3V to +6.5V Voltage Range on V CC12 Relative to GND ...........-0.3V to +18V Voltage Range on ILIM5, VRAMP5,TIMER5, ARD5 Relative to GND .........-0.3V to (V CC5 + 0.3V),not to exceed +6.5VVoltage Range on ILIM12, VRAMP12Relative to GND ................................-0.3V to (V CC12 + 0.3V),not to exceed +18VVoltage Range on TIMER12, ARD12Relative to GND .......................................-0.3V to +5V (V REG )5V Drain CurrentContinuous ............................................................................2A Peak ......................................................................................4A12V Drain CurrentContinuous ............................................................................3A Peak ......................................................................................4A Continuous Power Dissipation (T A = +70N C)TQFN (derate 20.8mW/N C above +70N C) ...............1666.7mW Operating Junction Temperature Range .........-40N C to +135N C Operating Temperature Range ..........................-40N C to +85N C Storage Temperature Range ..........................-55N C to +135N C Lead Temperature (soldering, 10s) ................................+300N C Soldering Temperature (reflow) ......................................+260N CRECOMMENDED_OPERATING_CONDITIONS(T J = -40N C to +135N C)ELECTRICAL_CHARACTERISTICS(V CC5 = +5V, V CC12 = +12V, T J = +25N C, unless otherwise noted.)ABSOLUTE_MAXIMUM_RATINGSPARAMETERSYMBOL CONDITIONSMIN TYP MAX UNITS V CC5 Voltage V CC5(Notes 1, 2) 4.0 5.0 5.5V V CC12 Voltage V CC12(Notes 1, 2)91213.2V R ILIM_ Value R ILIM_20400I C VRAMP_ Value C VRAMP_0.045F F C TIMER_ ValueC TIMER_0.045F F TIMER_ Turn-On Voltage V ON TIMER5 2.1V CC5 + 0.3V TIMER12 2.6 5.0TIMER_ Turn-Off VoltageV OFF-0.3+1.5VPARAMETERSYMBOL CONDITIONSMINTYP MAX UNITS V CC5 Supply Current I CC5(Note 3) 1.52mA V CC12 Supply Current I CC12(Note 3)1.52.25mA 5V UVLO: Rising V UR53.7 3.95V 5V UVLO: Falling V UF5 2.73.2V 5V UVLO: Hysteresis V UH50.5V 12V UVLO: Rising V UR1288.5V 12V UVLO: Falling V UF12 6.57V 12V UVLO: Hysteresis V UH121V 5V On-Resistance R ON54356m I 12V On-ResistanceR ON126888m I 5V Internal Voltage Reference V REF5 1.80V 12V Internal Voltage ReferenceV REF122.35VMAX3456112V/5V Hot-Plug Switch3ELECTRICAL_CHARACTERISTICS_(continued)(V CC5 = +5V, V CC12 = +12V, T J = +25N C, unless otherwise noted.)Note_1: All voltages are referenced to ground. Currents entering the device are specified positive, and currents exiting the deviceare negative.Note_2: This supply range guarantees that the LOAD voltage is not clamped by the overvoltage limit.Note_3: Supply current specified with no load on the LOAD pin.Note_4: Guaranteed by design; not production tested.PARAMETERSYMBOL CONDITIONSMINTYP MAXUNITS 5V MOSFET Output Capacitance C OUT (Note 4)400pF 12V MOSFET Output CapacitanceC OUT(Note 4)400pF5V and 12V Delay Time from Enable to Beginning of Conductiont POND C VRAMP_ = 1F F 8ms5V and 12V Gate-Charging Time from Conduction to 90% of V OUT t GCT C VRAMP_ = 1F F, C LOAD_ = 1000F F 486480ms Shutdown Junction Temperature T SHDN (Note 4)120135150N C Thermal Hysteresis T HYS (Note 4)40N C TIMER_ Charging Current I TIMER 648096F A VRAMP_ Charging Current I VRAMP 648096F A 5V Overvoltage Clamp V OVC5 5.5 6.0 6.5V 12V Overvoltage Clamp V OVC1213.21516.5V 5V Power-On Short-Circuit Current LimitI SCL5R ILIM5 = 47I (Note 5)0.6 1.0 1.5A 12V Power-On Short-Circuit Current LimitI SCL12R ILIM12 = 47I (Note 5)0.6 1.0 1.5A 5V Operating Overload Current LimitI OVL5R ILIM5 = 47I (Notes 4, 6) 1.5 2.5 3.7A 12V Operating Overload Current LimitI OVL12R ILIM12 = 47I (Notes 4, 6) 1.00 1.8 2.6A 5V VRAMP5 Slew Rate SR VRAMP C VRAMP5 = 1F F 0.160.190.23V/ms 12V VRAMP12 Slew Rate SR VRAMP C VRAMP12 = 1F F0.130.150.18V/ms ARD5 Pullup Resistor R PU5100k I ARD12 Pullup ResistorR PU12k IM A X 3456112V/5V Hot-Plug Switch 4Typical Operating Characteristics(T A = +25°C, unless otherwise noted.)ON-RESISTANCE vs. TEMPERATURETEMPERATURE (°C)R O N (m Ω)10012080604020-20102030405060700-40OVERVOLTAGE CLAMP vs. TEMPERATURETEMPERATURE (°C)O V E R V O L T A G E C L A M P (V )10012080604020-2015.015.215.415.615.816.016.214.8-40OVERVOLTAGE CLAMP vs. TEMPERATURETEMPERATURE (°C)O V E R V O L T A G E C L A M P (V )120100608002040-206.106.156.206.256.306.356.406.456.506.556.05-40CURRENT LIMIT vs. TEMPERATURETEMPERATURE (°C)C U R R E N T L I M I T (A )10012080604020-200.51.01.52.02.50-40CURRENT LIMIT vs. TEMPERATURETEMPERATURE (°C)C U R R E N T L I M I T (A )10012080604020-200.51.01.52.02.53.03.50-4012V CURRENT LIMIT vs. ILIM RESISTANCER ILIM (Ω)12V C U R R E N T L I M I T (A )100500.51.01.52.02.501505V CURRENT LIMIT vs. ILIM RESISTANCER ILIM (Ω)5V C U R R E N T L I M I T (A )501000.20.40.60.81.01.21.41.61.82.02.22.42.60150SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)I C C (m A )120100608002040-200.20.40.60.81.01.21.41.61.80-40MAX3456112V/5V Hot-Plug Switch5Typical Operating Characteristics (continued)(T A = +25°C, unless otherwise noted.)THERMAL SHUTDOWN WITH AUTORETRY ENABLEDV CC = 12V, 2Ω RESISTIVE LOADMAX34561 toc16500ms/divV CC12LOAD125V/divLOAD CURRENT500mA/divTHERMAL SHUTDOWN WITH AUTORETRY ENABLEDV CC = 5V, 2Ω RESISTIVE LOADMAX34561 toc151s/div V CC5LOAD52V/divLOAD CURRENT500mA/divTURN-ON WAVEFORMSV CC = 12V, 3300µF CAPACITIVE LOAD10ms/divV CC12LOAD12LOAD CURRENT500mA/div5V/divTURN-ON WAVEFORMSV CC = 5V, 3300µF CAPACITIVE LOAD5ms/div V CC5LOAD5LOAD CURRENT500mA/div2V/divTURN-ON WAVEFORMSV CC = 12V, 20Ω RESISTIVE LOAD5ms/div V CC12LOAD12LOAD CURRENT500mA/div5V/divTURN-ON WAVEFORMS V CC = 5V, 20Ω RESISTIVE LOAD5ms/divTYPICAL MAX34561 TURN-ON WAVEFORMSV CC = 12V, 20Ω RESISTIVE LOAD5ms/div 2V /d i vTYPICAL MAX34561 TURN-ON WAVEFORMSV CC = 5V, 20Ω RESISTIVE LOAD2ms/div 1V /d i vM A X 3456112V/5V Hot-Plug SwitchPin ConfigurationPin DescriptionMAX3456112V/5V Hot-Plug Switch7Detailed DescriptionThe MAX34561 has hot-plug controls for both +12V and +5V power rails. The circuitry for the +12V and +5V con-trols are independent of each other and can be treated as two separate hot-plug switches, even though the GND pin is common between the two switches. The sections that follow are written from the +12V circuit perspective, but also apply for the +5V switch control.The device begins to operate when the supply voltage V CC12 (or V CC5) exceeds its undervoltage lockout level, V UR12 (or V UR5). At this level, the corresponding enable circuit and TIMER12 (TIMER5) become active. Once the device has been enabled, a gate voltage is applied to the corresponding power MOSFET, allowing current to begin flowing from V CC12 (V CC5) to LOAD12 (LOAD5). The speed of the output-voltage ramp is controlled by the capacitance placed at the VRAMP12 (VRAMP5) pin. The load current is continuously monitored during the initial conduction (I SCL12 or I SCL5) and after the cor-responding MOSFET is fully on (I OVL12 or I OVL5). If the current exceeds the current limit that is set by the exter-nal resistance at ILIM12 (ILIM5), the gate voltage of the corresponding power MOSFET is decreased, reducing the output current to the set current limit.Current is limited by the device comparing the volt-age difference between LOAD12 (LOAD5) and ILIM12 (ILIM5) to an internal reference voltage. If the output cur-rent exceeds the limit that is set by the R ILIM12 (R ILIM5) resistor, the gate voltage of the corresponding power MOSFET is decreased, which reduces the output current to the load.When the output power is initially ramping up, the current limit is I SCL12 (I SCL5). Once the corresponding MOSFET is fully on, the current limit is I OVL12 (I OVL5). The I SCL12 (I SCL5) current limit protects the source if there is a dead short on initial power-up.The device acts as a fuse and automatically disables the current flowing to the load when the temperature of the power corresponding MOSFET has exceeded the shut-down junction temperature, T SHDN .Enable/TimerThe voltage level of TIMER12 (TIMER5) is compared to an internal source (see the Functional Diagram ). When the level on the pin exceeds V ON , the comparator out-puts a low level. This then turns on the voltage ramp circuit, enabling the device’s output. TIMER12 (TIMER5) can be configured into one of four different modes of operation as listed in Table 1. TIMER12 (TIMER5) pin was designed to work with most logic families. TIMER12 (TIMER5) has at least 250mV of hysteresis between V ON and V OFF . It is recommended that any logic gate used to drive TIMER12 (TIMER5) be tested to ensure proper operation.Pin Description (continued)Table_1._TIMER__Pin_ModesPINNAMEFUNCTION22ARD55V Autoretry Disable. Connect this pin to GND to disable automatic retry functionality; the device latches off during an overtemperature fault. Leave this pin open to enable automatic retry function. This pin contains a pullup (R PU5) to V CC5. This pin is only sampled on device power-on. If the 5V side is not used, connect this pin to GND.23VRAMP55V Voltage Ramp Control. A capacitor connected to this pin determines the voltage ramp of the LOAD5 output during turn-on according to the equation: dV LOAD5 = 2.3332 x (I VRAMP /C VRAMP5).24TIMER55V Enable Delay Control. A capacitor connected to this pin determines the enable delay according to the equation: Enable Delay = C TIMER5 x (V REF5/I TIMER ).—EPExposed Pad. Connect to ground. The EP must be soldered to ground for proper thermal and elec-trical operation.OPERATION_MODE TIMER_PIN_SETUP Automatic Enable No connection to TIMER12 (TIMER5)Delayed Automatic EnableCapacitor C TIMER_ connected to TIMER12 (TIMER5)Enable/Disable Open-collector device Enable with Delay/DisableOpen-collector device and C TIMER _M A X 3456112V/5V Hot-Plug SwitchFunctional DiagramMAX3456112V/5V Hot-Plug Switch9Once the device has been enabled, there is a delay (t POND ) until conduction begins from V CC12 (V CC5) to LOAD12 (LOAD5). This delay is the time required for the charge pump to bring the gate voltage of the cor-responding power MOSFET above its threshold level. Once the gate is above the threshold level, conduction begins and the output voltage begins ramping.Automatic-Enable ModeWhen V CC12 (V CC5) exceeds V UR12 (V UR5), the gate holding the TIMER12 (TIMER5) node low is released. The internal current source brings the node to a level greater than V ON , enabling the device.Delayed Automatic-Enable ModeWhen V CC12 (V CC5) exceeds V UR12 (V UR5), the gate holding the TIMER12 (TIMER5) node low is released. The internal current source (I TIMER ) then begins charging C TIMER_. When C TIMER_ is charged to a level greater than V REF12 (V REF5), the device turns on. The equation for the delay time is:t DELAY = (C TIMER12 x V REF12)/I TIMER t DELAY = (C TIMER5 x V REF5)/I TIMEREnable/Disable ModeA logic gate or open-collector device can be connected to TIMER12 (TIMER5) to enable or disable the device. When TIMER12 (TIMER5) is held low, the device is dis-abled. When an open-collector device is used to drive TIMER12 (TIMER5), the device is enabled when the open collector is in its high-impedance state by the internal current source bringing the TIMER12 (TIMER5) node high. TIMER12 (TIMER5) is also compatible with most logic families if the output high voltage level of the gate exceeds the V ON level, and the gate can sink the I TIMER current.Enable with Delay/Disable ModeAn open-collector device is connected in parallel with C TIMER_. When the pin is held low, the device is dis-abled. When the open-collector driver is high imped-ance, the internal current source begins to charge C TIMER_ as in the delayed mode.Output-Voltage RampThe voltage ramp circuit uses an operational ampli-fier to control the gate bias of the corresponding n-channel power MOSFET. When the timer/enable circuit is disabled, a FET is used to keep C VRAMP_ discharged, which forces the output voltage to GND. Once the enable/timer circuit has been enabled, aninternal current source, I VRAMP , begins to charge the external capacitor, C VRAMP_, connected to VRAMP12 (VRAMP5). The amplifier controls the gate of the corre-sponding power MOSFET so that the LOAD12 (LOAD5) output voltage divided by two tracks the rising voltage level of C VRAMP_. The output voltage continues to ramp until it reaches either the input V CC12 (V CC5) level or the overvoltage clamp limits. The equation for the output-voltage ramp function is:dV LOAD /dt = 2 x (I VRAMP /C VRAMP12) for +12V circuit dV LOAD /dt = 2.3332 x (I VRAMP /C VRAMP5) for +5V circuitThermal ShutdownThe device enters a thermal shutdown state when the temperature of the corresponding power MOSFET reaches or exceeds T SHDN , approximately +135N C. When T SHDN is exceeded, the thermal-limiting cir-cuitry disables the device using the enable circuitry. Depending on the state of ARD12 (ARD5), the device attempts to autoretry once the device has cooled, or it latches off.AutoretryIf ARD12 (ARD5) is unconnected or connected high, the device continually monitors the temperature once it has entered thermal shutdown. If the junction temperature falls below approximately +95N C (T SHDN - T HYS ), the corresponding power MOSFET is re-enabled. See the Thermal Shutdown with Autoretry Enabled typical operat-ing curves for details.LatchoffIf ARD12 (ARD5) is pulled low and the device has entered thermal shutdown, it does not attempt to turn back on. The only way to turn the device back on is to cycle the power to the device. When power is reapplied to V CC12 (V CC5), the junction temperature needs to be less than T SHDN for the device to be enabled.Overvoltage LimitThe overvoltage-limiting clamp monitors the VRAMP12 (VRAMP5) level compared to an internal voltage ref-erence. When the voltage on VRAMP12 (VRAMP5) exceeds V OVC12/2 (or V OVC5/2.3332), the gate volt-age of the corresponding n-channel power MOSFET is reduced, limiting the voltage on LOAD12 (LOAD5) to V OVC12 (V OVC5) even as V CC12 (V CC5) increases. If the device is in overvoltage for an extended period of time, the device could overheat and enter thermal shutdown. This is caused by the power created by the voltageM A X 3456112V/5V Hot-Plug Switch 10drop across the corresponding power MOSFET and the load current. See the Thermal Shutdown with Autoretry Enabled typical operating curves for details.Applications InformationExposed PadThe exposed pad is also a heatsink for the device. The exposed pad should be connected to a large trace or plane capable of dissipating heat from the device.Decoupling CapacitorsIt is of utmost importance to properly bypass the device's supply pins. A decoupling capacitor absorbs the energy stored in the supply and board parasitic inductance when the FET is turned off, thereby reducing the magni-tude of overshoot at V CC . This can be accomplished by using a high-quality (low ESR, low ESL) ceramic capaci-tor connected directly between the V CC and GND pins. Any series resistance with this bypass capacitor lowers its effectiveness and is not recommended. A minimum 0.5µF ceramic capacitor is required. However, depend-ing on the parasitic inductances present in the end appli-cation, a larger capacitor could be necessary.Unused PinsIf only one side (5V or 12V) of the device is being used, it is required that the unused V CC , AR, CTIMER, and VRAMP pins be connected to GND. Leaving these input pins unconnected can result in interference of the proper operation of the active portion of the device.LOAD and ILIM ConnectionsSmall parasitic resistances in the bond wires of the LOAD pins and in the traces connected to the LOAD pins can result in a voltage offset while current is flowing. Since the voltage drop across RILIM is used to set the I SCL and I OVL limits, this induced offset can increase the value of I SCL and I OVL from the specified values for any given R ILIM . To greatly reduce this offset, it is recommended that one of the LOAD pins have a dedicated connection to ILIM though R ILIM , and not be used to pass the LOAD current (Figure 1). This would leave three LOAD pins to pass I LOAD , which should be sufficient. Because there is only a small amount of current passed from this lone LOAD pin to ILIM, there is a negligible voltage offset applied to the internal comparator. This method is the best way to attain an accurate current limit for I LOAD .Package InformationFor the latest package outline information and land patterns, go to /packages . Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.Figure 1. LOAD and ILIM ConnectionsPACKAGE_TYPE PACKAGE_CODE OUTLINE_ND_PATTERN_NO.24 TQFN-EPT2444+421-013990-0022分销商库存信息: MAXIMMAX34561T+。

XC61CN替换MAX6377和MAX6380及MAX6808

XC61CN替换MAX6377和MAX6380及MAX6808例：XC61CN 替换MAX6377XC61CN 替换MAX6380XC61CN 替换MAX6808系列名称：【XC61CN/XC61CC】特点：低功耗(0.8V)输入电压(V)：最小--0.8V；最大--6V输出电压(V)：最小--0.7V；最大--10V最大输出电流(mA)：400mA消耗电流(μA)：0.7A封装：SOT-23，SOT-89，SSOT-24，TO-92【TOREX-XC61CN系列】描述：1.XC61CN系列是一款高精度,低功耗的电压检测器芯片,并采用了CMOS生产工艺和激光微调技术。

2.XC61CN系列受温度漂移特性的影响很小,电压检测精度很高。

3.XC61CN系列有CMOS和N沟道开漏两种输出模式供选择。

【TOREX-XC61CN系列】特点：●高精度：±2%, ±1% (VDF=2.6V~5.1V)●低消耗电流：0.7μA(TYP.)[VIN=1.5V]●检测电压范围：能够在0.8V～6.0V范围内以0.1V间隔设定●工作电压范围：0.7V～6.0V(低检测电压0.8V～1.5V), 0.7V～10.0V(一般检测电压1.6V～6.0V)●检测电压温度特性：±100ppm/℃(TYP.)●輸出形式：N沟道开漏/CMOS輸出●封装：SSOT-24, SOT-23, SOT-89, TO-92TOREX日本IC均可完全替代下列型号:XC6221Bxx2MR 替代MIC5253 XC6115xxxxMR 替代LTC699CN8 XC6221BXX2MR 替代MIC5255-xxBM5 XC6116x0xxMR 替代LTC2915xxS8 XC6221BXX2MR 替代MIC5259 XC6121 替代MAX6320XC6204Bxx2DR 替代MIC5305-xxYML XC6122 替代MAX6320XC6419 替代MIC5371 XC6123 替代MAX6320XB1086 替代MIC39100-xxBS XC6124 替代MAX6320XC6205 替代MIC5203 XC6113 替代MAX823XC6411 替代MIC5371 XC6103 替代MAX823XC6412 替代MIC5371 XC6112 替代MAX823XC6415 替代MIC5371 XC6102 替代MAX823XCM406 替代MIC5264 XC6115 替代MAX824XC8101 替代MIC94060 XC6105 替代MAX824XC6601 替代MCP1727 XC6114xxxxMR 替代DS1819BRXC6213 替代TC1014-xxVCT713 XC6104xxxxMR 替代DS1819BRXC6212 替代TC1014-xxVCT713 XC61H 替代MAX809/803XC62KNxx02PR 替代TC59xx02EMBTR XC6101xxxxMR 替代DS1819ARXC62KNxx02MR 替代TC59xx02ECB XC6106xxxxER 替代MAX6335XC62EPxxxxMR 替代TC57xx02ECT XC6106xxxxER 替代MAX6402XC6206Pxx2TB替代TC55RPxx02EZB XC6107 替代MAX825XC6206Pxx2PR 替代TC55RPxx02EMB XC6116xxxxER 替代MAX6402XC6206Pxx2MR 替代TC55RPxx01ECB XC612 替代MAX6779XC6203Pxx2FR 替代TC1264-xxVDB XC61CNxx02NR 替代MAX6377XRxx XC6207 替代TC1014-xxVCT713 XC61CNxx02NR 替代MAX6380XRxx XC6217 替代TC1014-xxVCT XC61CNxx02MR 替代MAX6808URxx XC6206Pxx2PR 替代MCP1700T-xx02E/TT XC61FC 替代MAX809XC6209Bxx2MR 替代TC1014-xxVCT713 XC61FC2912MR 替代MAX809SEUR XC6209Bxx2MR 替代TC1015xxVCT XC61CCxx02NR 替代MAX6375XRxx XC6209Bxx2MR 替代TC1185xxVCT XC61CCxx02NR 替代MAX6378XRxx XC6203Pxx2FR 替代TC1262-xxVDB XC61CCxx02MR 替代MAX6806URxx XC6204Bxx2MR 替代LX8211-xxISE XC6111xxxxMR 替代DS1819ARXC6215Pxx2NR 替代MC78LC00 XC6101 替代MAX823XC6210Bxx2 替代MC78M00 XC6111 替代MAX823XC6401CHxxMR 替代LP3988IMX-xx XC6104 替代MAX824XC6403DHxxMR 替代LP3988IMF-xx XC6114 替代MAX824XC6210B122DR 替代LP3990TL-xx XC6106 替代MAX825XC6210B122DR 替代LP3990MF-xx XC6116 替代MAX825XC6221A182MR 替代LP3990MF-xx XC6107xxxxMR 替代MAX6337USxxD3 XC6202Pxx2TH 替代LM2931AZxx XC6117xxxxMR 替代MAX6337USxxD3 XC6214 替代LM1117MPX-xx XC6107xxxxMR 替代MAX6841/2XC6419 替代LP5996 XC6117xxxxMR 替代MAX6841/2XC6411 替代LP5996 XC61FNxxx2MR 替代MAX803XC6412 替代LP5996 XC61CNxx02MR 替代MAX6380URXC6415 替代LP5996 XC61CCxx02MR 替代MAX6375URXB1086Pxx1JR 替代LM1086CS XC6117 替代MAX825XB1117K12BFR 替代LM1117S XC6106 替代MIC2775XB1117PxxxFR 替代LM1117MPX-xx XC6116 替代MIC2775XC6203Pxx2FR 替代LM1117MPX-xx XC612 替代MIC2777XC6202Pxx2TH 替代LM2936Z-xx XCM410 替代MIC2774XB1117Pxx1FR 替代LM340S XC61CCxx02PR 替代TC54VCxx02EMB XC6202Pxx2TH 替代LM340LAZ-xx XC61CCxx02TB 替代TC54VCxx02EZB XC6202Pxx2MR 替代LM3480IM3-xx XC61H 替代TCM809XC6203P332FR 替代LM3940IMP-3.3 XCM410 替代TC52XC6202Pxx2TH 替代LM78LxxACZ XC6120 替代TC54XC6404DHxxMR 替代LMS5258MF-xx XC612 替代TC52XC6202Pxx2MR 替代LP2950 XC61CNxx02MR 替代TC53Nxx02ECTTR XC6204Bxx2MR 替代LP2978 XC61CNxx02NR 替代TC53Nxx02EVCTR XC6204Bxx2MR 替代LP2980AIM5-xx XC61CN 替代TC54VNXC6204Bxx2MR 替代LP2980IM5-xx XC6202Pxx2TH 替代L4931ABZxxXC6204Axx2MR 替代LP2980IM5X-xx XC6202Pxx2TH 替代L4931CZxxXC6204Bxx2MR 替代LP2981AIM5-xx XC6202Pxx2PR 替代L78LxxABUTRXC6204Bxx2MR 替代LP2981IM5-xx XC6202Pxx2TH 替代L78LxxABZXC6204Bxx2MR 替代LP2982AIM5-xx XC6202Pxx2PR 替代L78LxxACUXC6204Bxx2MR 替代LP2982IM5-xx XC6202Pxx2TH 替代L78LxxACZXC6204Bxx2MR 替代LP2985AIM5-xx XC6202Pxx2TH 替代L78LxxCZXC6204Bxx2MR 替代LP2985IM5-xx XC6203Pxx2FR 替代LD1117SXC6204Bxx2MR 替代LP3984IBP-xx XC6204Bxx2MR 替代LD2979MxxXC6403 替代LP3982 XC6202Pxx2TH 替代LD2979ZxxXC6204Bxx2DR 替代LP3985IBL-xx XC6204Bxx2MR 替代LD2980ABMxxXC6204Bxx2MR 替代LP3985IM5-x.x XC6201Pxx2PR 替代LD2980ABUxxTR XC62H 替代NCP584HSNxxT1G XC6204Bxx2MR 替代LD2980ACMxxXC62E 替代NCP584HSNxxT1G XC6201Pxx2PR 替代LD2980ACUxxXC6404 替代NCP400FCT2G XC6204Bxx2MR 替代LD2981ABMxxXB1086 替代LM317MBDTRK XC6201Pxx2PR 替代LD2981ABUxxXC6202 series 替代LM2931CD XC6204Bxx2MR 替代LD2981ACMxxXC6202Pxx2TH 替代LM2931Z-xx XC6201Pxx2PR 替代LD2981ACUxxXC6202Pxx2MR 替代LP2950 XC6202Pxx2TH 替代LExxABZ/CZXC6202Pxx2TH 替代LP2950CZ-xx XC6401 替代NCP583XVxxT2G XB1086 替代MC33269DTRK XC6214 替代MC78LCxxHT1XC6203Pxx2FR 替代MC33275ST-xxT3 XC6219 替代NCP584HSNxxT1G XC6204Bxx2MR 替代MC33761 XC6219Bxx2MR 替代BAxxxLBSGXC6206Pxx2PR 替代MC78FCxxHT1 XC6219 替代BA0xxLBSGXC6203xxx2PR 替代MC78LCxxHT1 XC6206Pxx2TB 替代RE5RExxACXC6202Pxx2TH 替代MC78LxxACP/BCP XC6206Pxx2PR 替代RH5RLxxAAXC6204Bxx2MR 替代MC78PCxxNTR XC6206Pxx2TH 替代RE5RLxxAAXC6206Pxx2PR 替代MC78RCxxHT1 XC6206Pxx2TB 替代RE5RLxxACXC6217Axx2MR 替代NCP584HSNxxT1G XC62EPxx02MR 替代RN5RGxxAATR XC6203Pxx2FR 替代SC5201-1GSTR3 XC62H 替代RN5RGxxAATR XC6402 替代NCP400FCT2G XC6419 替代R5325XC6403/04 替代NCP400FCT2G XB1086 替代RN5RGxxAATR XC6405 替代NCP400FCT2G XC6411 替代R5325XC6204Bxx2MR 替代R1111Nxx1A/B XC6412 替代R5325XC6204Bxx2MR 替代R1112Nxx1A/B XC6415 替代R5325XC6204Bxx2MR 替代R1112Nxx1B-TR XC8101 替代R5520HXC6206Pxx2PR 替代RH5RExxAA XC6204Bxx2MR 替代R1110Nxx1A/BXC6206Pxx2TH 替代RE5RExxAA。

MAX4851ETE-T中文资料

General DescriptionThe MAX4851/MAX4851H /MAX4853/MAX4853H family of quad single-pole/single-throw (SPST) switches oper-ates from a single +2V to +5.5V supply and can handle signals greater than the supply rail. These switches fea-ture low 3.5Ωon-resistance with 40pF on-capacitance or 7Ωon-resistance with 30pF on-capacitance, making them ideal for switching audio and data signals.The MAX4851/MAX4851H are configured with four SPST switches and feature a comparator for head-phone detection or mute/send key functions. The MAX4853/MAX4853H have four SPST switches but do not include a comparator.For over-rail applications, these devices offer either the pass-through or high-impedance option. For the MAX4851/ MAX4853, signals greater than the positive supply (up to 5.5V) pass through the switch without dis-tortion. For the MAX4851H/MAX4853H, the switch input becomes high impedance when the input signal exceeds the supply rail.The MAX4851/MAX4851H /MAX4853/MAX4853H are available in the space-saving, 16-pin, 3mm x 3mm thin QFN package and operate over the -40°C to +85°C extended temperature range.ApplicationsUSB Switching Audio Signal Routing Cellular Phones Notebook ComputersPDAs and Other Handheld DevicesFeatures♦USB 2.0 Full Speed (12Mbps) and USB 1.1 Signal Switching ♦Switch Signals Greater than V CC ♦+2V to +5.5V Supply Range ♦3.5Ω/7ΩOn-Resistance♦30pF On-Capacitance (7ΩSwitch)♦150MHz -3dB Bandwidth ♦1.8V Logic Compatibility ♦Low Supply Current0.01µA (MAX4853)5µA (MAX4851)10µA (MAX4851H/MAX4853H)♦Low 0.01nA Leakage Current♦Available in a Space-Saving 3mm x 3mm, 16-Pin TQFN PackageMAX4851/MAX4851H/MAX4853/MAX4853H3.5Ω/7ΩQuad SPST Switches with Over-RailSignal Handling________________________________________________________________Maxim Integrated Products 1Ordering InformationBlock Diagram/Truth Table19-3471; Rev 0; 10/04For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .*EP = Exposed paddle.Pin Configurations and Typical Operating Circuit appear at end of data sheetM A X 4851/M A X 4851H /M A X 4853/M A X 4853H3.5Ω/7ΩQuad SPST Switches with Over-Rail Signal Handling 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.V CC , IN_, CIN, COM_, NO_ to GND (Note 1)........-0.3V to +6.0V COUT..........................................................-0.3V to (V CC + 0.3V)COUT Continuous Current................................................±20mA Closed-Switch Continuous Current COM_, NO_, NC_3.5ΩSwitch ................................................................±100mA 7ΩSwitch .....................................................................±50mA Peak Current COM_, NO_ (pulsed at 1ms, 50% duty cycle)3.5ΩSwitch ................................................................±200mA 7ΩSwitch ...................................................................±100mAPeak Current COM_, NO_ (pulsed at 1ms, 10% duty cycle)3.5ΩSwitch ................................................................±240mA 7ΩSwitch ...................................................................±120mA Continuous Power Dissipation (T A = +70°C)16-Pin Thin QFN (derate 20.8mW/°C above +70°C)...1667mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CELECTRICAL CHARACTERISTICS(V= +2.7V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +3.0V, T = +25°C, unless other-Note 1:Signals on IN_, NO_, or COM_ below GND are clamped by internal diodes. Limit forward-diode current to maximum currentrating.MAX4851/MAX4851H/MAX4853/MAX4853H3.5Ω/7Ω Quad SPST Switches with Over-RailSignal Handling_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS (continued)M A X 4851/M A X 4851H /M A X 4853/M A X 4853H3.5Ω/7ΩQuad SPST Switches with Over-Rail Signal Handling 4_______________________________________________________________________________________ELECTRICAL CHARACTERISTICS (continued)perature range.Note 3:Guaranteed by design and characterization; not production tested.Note 4:∆R ON = R ON(MAX)- R ON(MIN).Note 5:Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over thespecified analog signal ranges.Note 6:Off-isolation = 20log 10(V COM_/ V NO_), V COM_= output, V NO_= input to off switch.MAX4851/MAX4851H/MAX4853/MAX4853H3.5Ω/7Ω Quad SPST Switches with Over-RailSignal Handling_______________________________________________________________________________________5MAX4851/MAX4853ON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)4212345678910006MAX4851/MAX4853ON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)421.01.52.02.53.03.54.04.50.506MAX4851/MAX4853ON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)421.01.52.02.53.03.50.506MAX4851H/MAX4853HON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)4212345678910006MAX4851H/MAX4853HON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)2.52.00.51.01.51.52.02.53.03.54.04.55.01.03.0MAX4851H/MAX4853HON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)43211.01.52.02.53.03.50.505MAX4853ON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)4251015202530354045006MAX4853ON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)42345678206MAX4853ON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)541232.02.53.03.54.04.55.05.51.56Typical Operating Characteristics(V CC = 3.0V, T A = +25°C, unless otherwise noted.)M A X 4851/M A X 4851H /M A X 4853/M A X 4853H3.5Ω/7ΩQuad SPST Switches with Over-Rail Signal Handling 6_______________________________________________________________________________________MAX4853HON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)4251015202530354045006MAX4853HON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)2.52.01.51.00.5345678203.0MAX4853HON-RESISTANCE vs. COM VOLTAGECOM VOLTAGE (V)O N -R E S I S T A N C E (Ω)43122.02.53.03.54.04.55.05.51.55MAX4851SUPPLY CURRENT vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (µA )5.04.54.03.53.02.52.02.53.03.54.04.55.05.52.01.55.5MAX4851HSUPPLY CURRENT vs. SUPPLY VOLTAGE3456782SUPPLY VOLTAGE (V)S U P P L Y C U R R E N T(µA )5.04.54.03.53.02.52.01.55.50.20.40.60.81.0MAX4853SUPPLY CURRENT vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (n A)5.04.54.03.53.02.52.01.55.55.05.56.06.57.07.58.04.5MAX4853HSUPPLY CURRENT vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)S U P P L YC U R R E N T (µA )5.04.54.03.53.02.52.01.55.5TURN-ON/TURN-OFF TIME vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)T U R N -O N /T U R N -O F F T I M E (n s)4.53.52.510203040506001.5 5.5TURN-ON/TURN-OFF TIME vs. TEMPERATURETEMPERATURE (°C)T U R N -O N /T U R N -O F F T I M E (n s )603510-152224262830323420-4085Typical Operating Characteristics (continued)(V CC = 3.0V, T A = +25°C, unless otherwise noted.)MAX4851/MAX4851H/MAX4853/MAX4853H3.5Ω/7Ω Quad SPST Switches with Over-RailSignal Handling_______________________________________________________________________________________7TURN-ON/TURN-OFF TIME vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)T U R N -O N /T U R N -O F F T I M E (n s )4.53.52.510203040506001.55.5TURN-ON/TURN-OFF TIME vs. TEMPERATURETEMPERATURE (°C)T U R N -O N /T U R N -O F F T I M E (n s )603510-152224262830323420-4085LOGIC THRESHOLD vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)L O G I C T H R E S H O L D (V )4.53.52.50.81.01.21.41.60.61.55.5CHARGE INJECTION vs. COM VOLTAGECOM VOLTAGE (V)C H A R G E I N J E C T I O N (p C )4321102030005CHARGE INJECTION vs. COM VOLTAGECOM VOLTAGE (V)C H A R G E I N J E C T I O N (p C )43211020305LEAKAGE CURRENT vs. TEMPERATURETEMPERATURE (°C)L E A K A G E C U R R E N T (n A )603510-150.20.40.60.81.01.21.40-4085LEAKAGE CURRENT vs. TEMPERATURETEMPERATURE (°C)L E A K A G E C U R R E N T (n A )6035-15100.20.40.60.81.01.21.41.60-4085FREQUENCY RESPONSEFREQUENCY (MHz)F R E Q U E N C Y R E S P O N S E (d B )100101-80-60-40-20020-1000.11000FREQUENCY RESPONSEFREQUENCY (MHz)F R E Q U E N C Y R E S P O N S E (d B )100101-80-60-40-20020-1000.11000Typical Operating Characteristics (continued)(V CC = 3.0V, T A = +25°C, unless otherwise noted.)M A X 4851/M A X 4851H /M A X 4853/M A X 4853H3.5Ω/7ΩQuad SPST Switches with Over-Rail Signal Handling 8_______________________________________________________________________________________TOTAL HARMONIC DISTORTIONvs. FREQUENCYFREQUENCY (Hz)T H D (%)10k1k 1000.110100k10.01TOTAL HARMONIC DISTORTIONvs. FREQUENCYFREQUENCY (Hz)T H D (%)10k1k 1000.110100k10.01(MAX4851/MAX4851H) COMPARATOR THRESHOLD vs. TEMPERATURETEMPERATURE (°C)C O M P A R A T O R T H R E S H O LD (V )603510-151.021.041.061.081.101.00-4085COMPARATOR THRESHOLDvs. TEMPERATURETEMPERATURE (°C)C O M P A R A T O R T H R E S H O L D (V )603510-151.6251.6501.6751.7001.7251.7501.600-4085MAX4851/MAX4853SWITCH PASSING SIGNALS ABOVE SUPPLY VOLTAGEV NC 2V/div 0VV COM 0V200µs/divV CC = 3.0VMAX4851H/MAX4853H SWITCH ENTERING HIGH-IMPEDANCE STATE200µs/divV NC 2V/div 0VV COM 0VV CC = 3.0VHI-Z STATE HI-Z STATETypical Operating Characteristics (continued)(V CC = 3.0V, T A = +25°C, unless otherwise noted.)Detailed Description The MAX4851/MAX4851H/MAX4853/MAX4853H are low on-resistance, low-voltage, analog switches that operate from a +2V to +5.5V single supply and are fully specified for nominal 3.0V applications. The MAX4851/MAX4853 devices feature over-rail signal capability that allows sig-nals up to 5.5V with supply voltages down to 2.0V to pass through without distortion. The MAX4851H/ MAX4853H enter high-impedance mode when the signal voltage exceeds V CC and return to normal operation when the signal voltage drops below V CC.tance, which allows switching of the data signals for USB 2.0/1.1 applications (12Mbps). They are designed to switch D+ and D- USB signals with a guaranteed skew of less than 1ns (see Figure 2), as measured from 50% of the input signal to 50% of the output signal.The MAX4851_ features a comparator that can be used for headphone or mute detection. The comparator threshold is internally generated to be approximately 1/3 of V CC.3.5Ω/7ΩQuad SPST Switches with Over-RailSignal Handling_______________________________________________________________________________________9MAX4851/MAX4851H/MAX4853/MAX4853H Pin DescriptionM A X 4851/M A X 4851H /M A X 4853/M A X 4853H3.5Ω/7ΩQuad SPST Switches with Over-Rail Signal Handling 10______________________________________________________________________________________Test Circuits/Timing DiagramsFigure 1. Switching TimeFigure 2. Input/Output Skew Timing DiagramMAX4851/MAX4851H/MAX4853/MAX4853H3.5Ω/7Ω Quad SPST Switches with Over-RailSignal Handling______________________________________________________________________________________11Figure 3. Charge InjectionTest Circuits/Timing Diagrams (continued)M A X 4851/M A X 4851H /M A X 4853/M A X 4853HApplications InformationDigital Control InputsThe logic inputs (IN_) accept up to +5.5V even if the supply voltages are below this level. For example, with a +3.3V V CC supply, IN_ can be driven low to GND and high to +5.5V, allowing for mixing of logic levels in a sys-tem. Driving IN_ rail-to-rail minimizes power consump-tion. For a +2V supply voltage, the logic thresholds are 0.5V (low) and 1.4V (high). For a +5V supply voltage, the logic thresholds are 0.8V (low) and 1.8V (high).Analog Signal LevelsThe on-resistance of these switches changes very little for analog input signals across the entire supply volt-age range (see Typical Operating Characteristics ). The switches are bidirectional; therefore, NO_ and COM_can be either inputs or outputs.ComparatorThe positive terminal of the comparator is internally set to V CC / 3. When the negative comparator terminal (CIN) is below the threshold (V CC / 3), the comparator output (COUT) goes high. When CIN rises above V CC / 3, COUT goes low.The comparator threshold allows for detection of head-phones since headphone audio signals are typically biased to V CC / 2.Power-Supply SequencingCaution: Do not exceed the absolute maximum rat-ings because stresses beyond the listed ratings may cause permanent damage to the device.Proper power-supply sequencing is recommended for all CMOS devices. Always apply V CC before applying analog signals, especially if the analog signal is not current limited.3.5Ω/7ΩQuad SPST Switches with Over-Rail Signal HandlingFigure 5. Channel Off-/On-CapacitanceFigure 6. Comparator Switching TimeSelector GuideMAX4851/MAX4851H/MAX4853/MAX4853H3.5Ω/7Ω Quad SPST Switches with Over-RailSignal Handling______________________________________________________________________________________13Pin ConfigurationsTypical Operating CircuitChip InformationTRANSISTOR COUNT: 735PROCESS: CMOSM A X 4851/M A X 4851H /M A X 4853/M A X 4853H3.5Ω/7ΩQuad SPST Switches with Over-Rail Signal Handling Maxim cannot assume responsib ility for use of any circuitry other than circuitry entirely emb odied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.14____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2004 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)。

MAXIM MAX3841 说明书

General DescriptionThe MAX3841 is a low-power, 12.5Gbps 2 ×2 cross-point switch I C for high-speed serial data loopback,redundancy, and switching applications. The MAX3841current-mode logic (CML) inputs and outputs have iso-lated V CC connections to enable DC-coupled interfaces to 1.8V, 2.5V, or 3.3V CML ICs. Fully differential signal paths and Maxim’s second-generation SiGe technology provide optimum signal integrity, minimizing jitter,crosstalk, and signal skew. The MAX3841 is ideal for serial OC-192 and 10GbE optical module, line card,switch fabric, and similar applications.The MAX3841 has 150mV P-P minimum differential input sensitivity, and 500mV P-P nominal differential output swing. Unused outputs can be powered down individu-ally to conserve power. In addition to functioning as a 2×2 switch, the MAX3841 can be configured as a 2:1multiplexer, 1:2 buffer, or dual 1:1 buffer. The MAX3841is available in a 4mm ×4mm 24-pin thin QFN package,and consumes only 215mW with both outputs enabled.ApplicationsOC-192, 10GbE Switch/Line Cards OC-192, 10GbE Optical Modules System Redundancy/Self Test Clock FanoutFeatures♦Up to 12.5Gbps Operation♦Less Than 10ps P-P Deterministic Jitter ♦Less Than 0.7ps RMS Random Jitter ♦1.8V, 2.5V, and 3.3V DC-Coupled CML I/O ♦Independent Output Power-Down ♦4mm ×4mm Thin QFN Package ♦-40°C to +85°C Operation ♦+3.3V Core Supply♦215mW Power Consumption (Excluding Termination Currents)MAX3841×2 Crosspoint Switch________________________________________________________________Maxim Integrated Products1Ordering InformationTypical Application Circuit19-2905; Rev 1; 3/09Pin Configuration appears at end of data sheet.+Denotes a lead(Pb)-free/RoHS-compliant package.*EP = Exposed pad.For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,or visit Maxim's website at .M A X 384112.5Gbps CML 2 ×2 Crosspoint Switch 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.IN OUT Note 3:Measured using a 0000011111 pattern at 12.5Gbps, and V IN = 400mV P-P differential.Note 4:Measured at 9.953Gbps using a pattern of 100 ones, 27 - 1 PRBS, 100 zeros, 27 - 1 PRBS, and at 12.5Gbps using a ±K28.5 pattern. VCC_IN = VCC_OUT = 1.8V, and V IN = 400mV P-P differential.Note 5:Refer to Application Note 1181:HFAN-04.5.1: Measuring Random Jitter on a Digital Sampling Oscilloscope .Supply Voltage, V CC ..............................................-0.5V to +4.0V CML Supply Voltage (VCC_IN, VCC_OUT)...........-0.5V to +4.0V Continuous Output Current (OUT1±, OUT2±)...................±25mA CML Input Voltage (IN1±, IN2±)...........-0.5V to (VCC_IN + 0.5V)LVCMOS Input Voltage (SEL1, SEL2,ENO1, ENO2).........................................-0.5V to (V CC + 0.5V)Continuous Power Dissipation (T A = +85°C)24-Pin Thin QFN (derate 20.8mW/°Cabove +85°C).............................................................1352mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range.............................-55°C to +150°C Lead Temperature (soldering, 10s).................................+300°CMAX384112.5Gbps CML 2 ×2 Crosspoint Switch_______________________________________________________________________________________3Typical Operating Characteristics(V CC = 3.3V, VCC_IN, VCC_OUT = 1.8V, V IN = 500mV P-P , T A = +25°C, unless otherwise noted.)CORE SUPPLY CURRENT vs. TEMPERATURE(EXCLUDES CML I/O CURRENTS)TEMPERATURE (°C)S U P P L Y C U R R E N T (m A )603510-15506070809010011012013014040-4085SUPPLY CURRENT vs. TEMPERATURE (CORE PLUS CML I/O CURRENTS)TEMPERATURE (°C)S U P P L Y C U R R E NT (m A )603510-15506070809010011012013014040-4085OUTPUT EYE DIAGRAM (12.5Gbps, 223 - 1 PRBS)MAX3841 toc0314ps/div60mV/divOUTPUT EYE DIAGRAM (10.7Gbps, 223 - 1 PRBS)MAX3841 toc0416ps/div 60mV/div OUTPUT EYE DIAGRAM (6.25Gbps, 223 - 1 PRBS)MAX3841 toc0528ps/div 60mV/div OUTPUT EYE DIAGRAM (622Mbps, 223 - 1 PRBS)MAX3841 toc06270ps/div60mV/divDETERMINISTIC JITTER vs. TEMPERATURETEMPERATURE (°C)D E T E R M I N I S T I C J I T T E R (p s )6035-15102468101214160-4085DIFFERENTIAL OUTPUT SWINGvs. TEMPERATUREM A X 3841 t o c 08TEMPERATURE (°C)D I F FE R E N T I A L O U T P U T (m V P -P )603510-15460470480490500510520530540550450-4085PROPAGATION DELAYMAX3841 toc09100ps/divOUT1IN1M A X 384112.5Gbps CML 2 ×2 Crosspoint Switch 4_______________________________________________________________________________________Detailed DescriptionThe MAX3841 contains a pair of CML inputs that drive two 2:1 multiplexers, with separate select inputs SEL1and SEL2, providing a 2 ×2 crosspoint data path. The outputs of the multiplexers each drive a high-perfor-mance CML output that can be disabled (powered down) using the ENO1/ENO2 inputs. All of the data paths are fully differential to minimize jitter, crosstalk,and signal skew. See Figure 1 for the functional diagram.CML Input and Output BuffersThe MAX3841 input and output buffers are terminated with 50Ωto independent supply lines, and are also com-patible with 100Ωdifferential terminations. (See Figures 3and 4.) Separate power-supply connections are provided for the core, input buffers, and output buffers to allow DC-coupling to 1.8V, 2.5V, or 3.3V CML ICs. If desired, the CML inputs and outputs can be AC-coupled.The CML inputs accept serial NRZ data with differential amplitude from 150mV P-P to 1200mV P-P (see Figure 2).The CML outputs provide 500mV P-P nominal differential swing, resulting in low power consumption.Figure 1. Functional DiagramApplications InformationSelect and Enable ControlsThe MAX3841 provides two LVCMOS-compatible select inputs, SEL1 and SEL2. Either data input can be connected to either or both data outputs. The MAX3841provides two LVCMOS-compatible enable inputs,ENO1 and ENO2, so each output can be disabled independently. The MAX3841 can also be used as a 1:2 driver, 2:1 multiplexer, or a dual 1:1 buffer by using the LVCMOS control inputs accordingly (see Table 1).Power-Supply ConnectionsEach of the input and output power-supply connections (VCC1I N, VCC2I N, VCC1OUT, VCC2OUT) is indepen-dent and need not be connected to the same voltage.The input and output supplies can be connected to 1.8V, 2.5V, or 3.3V, but the core supply (V CC ) must be connected to 3.3V for proper operation.Input and Output InterfacesThe MAX3841 inputs and outputs can be AC-coupled or DC-coupled according to the application. If an input or output is not used it should be terminated with 50Ωto the correct input or output supply voltage. For more information about interfacing with logic families, refer to Application Note 291:HFAN-01.0: I ntroduction to LVDS, PECL, and CML .Package and Layout ConsiderationsThe MAX3841 is packaged in a 4mm ×4mm 24-pin thin QFN with exposed pad. The exposed pad provides thermal and electrical connectivity to the I C and must be soldered to a high-frequency ground plane. Use multiple vias to connect the exposed pad underneath the package to the PC board ground plane.Use good layout techniques for the 10Gbps PC board transmission lines, and configure the layout near the IC to minimize impedance discontinuities. Power-supply decoupling capacitors should be located as close as possible to the IC.MAX384112.5Gbps CML 2 ×2 Crosspoint Switch_______________________________________________________________________________________5Figure 2. Definition of Differential Voltage SwingFigure 4. Equivalent CML Output CircuitM A X 384112.5Gbps CML 2 ×2 Crosspoint Switch 6_______________________________________________________________________________________Chip InformationTRANSISTOR COUNT: 950PROCESS: SiGe BiCMOSPin ConfigurationPackage InformationFor the latest package outline information and land patterns, go to /packages .12.5Gbps CML 2 ×2 Crosspoint SwitchMAX3841 ArrayMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________7©2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.。

fp6381as5ctr参数

fp6381as5ctr参数
FP6381AS5CTR参数解析
FP6381AS5CTR是一款高度集成的直流与直流转换器，采用了先进的CMOS工艺和控制算法，能够有效地将高压直流电压转换成较低的输出电压，并且保证了高效、高准确度和稳定性。

此款电源管理芯片广泛应用于汽车电子、遥感设备及工业控制设备等领域。

那么，让我们看看它有哪些重要的参数吧。

1. 输入电压范围：FP6381AS5CTR的输入电压范围广泛，最大可以达到60V，所以可以支持大多数工业应用中的各种直流高压输出。

而且通过内部开关电源的控制，能够减少开关噪音和EMC干扰。

2. 输出电压范围：FP6381AS5CTR的输出电压通常在2V至50V之间，可以通过外界电阻调节电压幅值。

因此，可根据不同负载和应用来调整输出电压。

3. 输出电流范围：此款芯片的最大输出电流为2A，可以满足许多电子设备的需求。

4. 精度和稳定性：FP6381AS5CTR采用高精度反馈控制技术，输出精度不会受到输入电压、温度等外界因素的影响。

同时，该芯片支持超过90%的高效转换效率，减少了能量的浪费和散热成本。

5. 温度范围：FP6381AS5CTR可以在-40℃至+125℃的工作温度范围内正常工作，能适应各种苛刻的工作环境。

6. 保护特性：除了具有过流、欠压、过热和过载保护等常见的保护特性，FP6381AS5CTR还具有输出短路保护，以确保设备安全。

综上所述，FP6381AS5CTR是一个高性能、多功能的直流与直流转换器，适用于各种应用场合。

在使用之前，用户应当详细了解其参数要求，并遵循相应的电路设计和散热措施。

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