FPGA可编程逻辑器件芯片EP2S60F672C5N中文规格书

合集下载

FPGA可编程逻辑器件芯片EP2S60F672I5N中文规格书

FPGA可编程逻辑器件芯片EP2S60F672I5N中文规格书

Stratix II GX Device Handbook, Volume 1Operating ConditionsTable 4–20 provides information on recommended input clock jitter foreach mode.Notes to Table 4–19:(1)Dedicated REFCLK pins were used to drive the input reference clocks.(2)Jitter numbers specified are valid for the stated conditions only.(3)Refer to the protocol characterization documents for detailed information.(4)HiGig configuration is available in a -3 speed grade only. For more information, refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook .(5)Stratix II GX transceivers meet CEI jitter generation specification of 0.3 UI for a V OD range of 400mV to 1000 mV . (6)The Sinusoidal Jitter Tolerance Mask is defined only for low voltage (LV) variant of CPRI.(7)The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.(8)The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.(9)The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.(10)The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.(11)The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.(12)The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.(13)The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.(14)The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.(15)The jitter numbers for CPRI are compliant to the CPRI Specification V2.1.(16)The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.(17)The Fibre Channel transmitter jitter generation numbers are compliant to the specification at βT interoperability point.(18)The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at βR interoperability point.Table 4–19.Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3)(Part 19 of 19)Symbol/Description Conditions -3 SpeedCommercial SpeedGrade-4 Speed Commercial and Industrial Speed Grade -5 Speed Commercial Speed Grade Unit MinTyp MaxMin Typ Max Min Typ Max Table 4–20.Recommended Input Clock Jitter (Part 1 of 2)ModeReference Clock (MHz)Vectron LVPECL XO Type/Model Frequency Range (MHz)RMS Jitter (12 kHz to 20 MHz) (ps)Period Jitter (Peak to Peak) (ps)Phase Noise at 1 MHz (dB c/Hz)PCI-E100VCC6-Q/R 10 to 2700.323-149.9957(OIF) CEIPHY156.25VCC6-Q/R 10 to 2700.323-146.2169622.08VCC6-Q 270 to 800230Not available GIGE62.5VCC6-Q/R 10 to 2700.323-149.9957125VCC6-Q/R 10 to 2700.323-146.9957XAUI 156.25VCC6-Q/R 10 to 2700.323-146.2169Stratix II GX Device Handbook, Volume 1DC and Switching CharacteristicsI/O Standard SpecificationsTables 4–24 through 4–47 show the Stratix II GX device family I/Ostandard specifications.R CONF(4)Value of I/O pin pull-up resistor before and during configuration Vi = 0, V CCIO = 3.3V 102550KOhmVi = 0, V CCIO = 2.5V 153570KOhmVi = 0, V CCIO = 1.8V 3050100KOhmVi = 0, V CCIO = 1.5V 4075150KOhmVi = 0, V CCIO = 1.2V 5090170KOhmRecommended value ofI/O pin externalpull-down resistor before and duringconfiguration12KOhm Notes to Table 4–23:(1)Typical values are for T A = 25 °C, V CCINT = 1.2 V , and V CCIO = 1.5 V , 1.8 V , 2.5 V , and 3.3 V .(2)This value is specified for normal device operation. The value may vary during power-up. This applies for all V CCIO settings (3.3, 2.5, 1.8, and 1.5 V).(3)Maximum values depend on the actual TJ and design utilization. See PowerPlay Early Power Estimator (EPE) and Power Analyzer or the Quartus II PowerPlay Power Analyzer and Optimization Technology (available at ) for maximum values. See the section “Power Consumption” on page 4–59 for more information.(4)Pin pull-up resistance values will lower if an external source drives the pin higher than V CCIO .Table 4–23.Stratix II GX Device DC Operating Conditions (Part 2 of 2)Note (1)SymbolParameter Conditions Device Minimum Typical Maximum Unit Table 4–24.LVTTL Specifications (Part 1 of 2)SymbolParameter Conditions Minimum Maximum Unit V CCIO (1)Output supply voltage 3.135 3.465V V IHHigh-level input voltage 1.7 4.0V V ILLow-level input voltage –0.30.8V V OH High-level output voltage I OH = –4mA (2) 2.4VOperating ConditionsTable4–35.SSTL-18 Class I SpecificationsSymbol Parameter Conditions Minimum Typical Maximum Unit V CCIO Output supply voltage 1.71 1.8 1.89V V REF Reference voltage0.8550.90.945V V TT Termination voltage V REF – 0.04V REF V REF + 0.04V V IH (DC)High-level DC input voltage V REF + 0.125V V IL (DC)Low-level DC input voltage V REF – 0.125V V IH (AC)High-level AC input voltage V REF + 0.25V V IL (AC)Low-level AC input voltage V REF – 0.25V V OH High-level output voltage I OH = –6.7mA (1)V TT + 0.475V V OL Low-level output voltage I OL = 6.7mA (1)V TT – 0.475V Note to Table4–35:(1)This specification is supported across all the programmable drive settings available for this I/O standard as shownin the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.Table4–36.SSTL-18 Class II SpecificationsSymbol Parameter Conditions Minimum Typical Maximum Unit V CCIO Output supply voltage 1.71 1.8 1.89V V REF Reference voltage0.8550.90.945V V TT Termination voltage V REF – 0.04V REF V REF + 0.04V V IH (DC)High-level DC input voltage V REF + 0.125V V IL (DC)Low-level DC input voltage V REF – 0.125V V IH (AC)High-level AC input voltage V REF + 0.25V V IL (AC)Low-level AC input voltage V REF – 0.25V V OH High-level output voltage I OH = –13.4mA (1)V CCIO – 0.28V V OL Low-level output voltage I OL = 13.4mA (1)0.28V Note to Table4–36:(1)This specification is supported across all the programmable drive settings available for this I/O standard as shownin the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.Stratix II GX Device Handbook, Volume 1Document Revision HistoryStratix II GX Device Handbook, Volume 1。

FPGA可编程逻辑器件芯片EP20K600EFI672中文规格书

FPGA可编程逻辑器件芯片EP20K600EFI672中文规格书
n/a
Port Connect
0, 1, 2 0, 1, 2 0 0 0 0 0 1 0, 1 0 0 n/a n/a
n/a
ADSP-BF60X BLACKFIN PROCESSOR HARDWARE REFERENCE
PIPELINED VISION PROCESSOR (PVP) PVP FUNCTIONAL DESCRIPTION
ቤተ መጻሕፍቲ ባይዱ
56$7,-,QS,-,QS,-56$7,- 56$7,- 56$7,-
All values outside of the region are defined as zero—InpI,-1 = RSATI,-1 = RSATI,-2 = 0, as shown in the Illustration of RSAT Mode figure.
ADSP-BF60X BLACKFIN PROCESSOR HARDWARE REFERENCE
PIPELINED VISION PROCESSOR (PVP) OPERATING MODES
the signal processing blocks (PVP blocks). You have full flexibility to assign each of the PVP blocks to any pipe. The one exception is the up/down-scaler block (UDS), which can only operate in memory pipe mode. Each PVP block may be assigned only to one pipe at a time. But, there is support for dynamic re-configuration of the pipe assignments. For a graphical overview of all PVP block interconnections, see Configuring Pipe Structure. The PVP blocks are: • Two input formatters (IPFn, x=0, 1) supporting selection of input streams, gating pipeline processing

FPGA可编程逻辑器件芯片EP20K600CF672C8中文规格书

FPGA可编程逻辑器件芯片EP20K600CF672C8中文规格书

28Link Port (LP)Link ports allow the processor to connect to other processors or peripheral link ports using a simplecommunication protocol for high-speed parallel data transfer. This peripheral allows a variety of I/Operipheral interconnection schemes to I/O peripheral devices as well as co-processing and multiprocessing schemes.The processor’s link ports support 8-bit wide data transfers. The link port pins are multiplexed in the GPIO ports. For information on processor multiplexing, see the processor specific data sheet.Link ports can operate independently and simultaneously, allowing glueless high-speed connectivity of up to four external processors.LP FeaturesAll link ports are identical in their design and have the following common features.•Bidirectional ports with eight data signals (LP_D0 – LP_D7, an acknowledge signal (LP_ACK), and a clock signal (LP_CLK).•Provide high-speed, point-to-point data transfers to other processors, allowing different types of inter-connections between multiple processors.•Pack data into 32-bit words. This data can be directly read by the processor or transferred via DMA to or from on-chip memory.•Support for data buffering through a 2-deep FIFO for transmit and a 4-deep FIFO for receive.•Programmable clock and acknowledge based handshake mechanism for efficient communication.• A dedicated DMA channel.LP Functional DescriptionThis section provides a description of the link port, including a list of its registers and a functional block diagram.ADSP-BF60x LP Register ListThe LP are 8-bit wide ports, which can connect to another processor or peripheral LP. These ports allow a variety of interconnection schemes to I/O peripheral devices as well as co-processing and multiprocessingMissed Event Interrupt Mask RegisterThe ACM_MEVMSK register enables interrupts corresponding to status bits in the ACM_MEVSTAT register. When an ACM_MEVMSK bit is set (=1), an interrupt is generated when the corresponding event missed bit is set (bit in ACM_MEVSTAT is set).3(R/W1C)EV3Event 3 Missed.The ACM_MEVSTAT.EV3 bit indicates when an instance of event 3 hasbeen missed since the last trigger. If set and the corresponding bit inACM_MEVMSK is set (interrupt enabled), the condition generates aninterrupt. This bit is W1C.No Event 3 Missed Status 1Event 3 Missed2(R/W1C)EV2Event 2 Missed.The ACM_MEVSTAT.EV2 bit indicates when an instance of event 2 hasbeen missed since the last trigger. If set and the corresponding bit inACM_MEVMSK is set (interrupt enabled), the condition generates aninterrupt. This bit is W1C.No Event 2 Missed Status 1Event 2 Missed1(R/W1C)EV1Event 1 Missed.The ACM_MEVSTAT.EV1 bit indicates when an instance of event 1 hasbeen missed since the last trigger. If set and the corresponding bit inACM_MEVMSK is set (interrupt enabled), the condition generates aninterrupt. This bit is W1C.No Event 1 Missed Status 1Event 1 Missed(R/W1C)EV0Event 0 Missed.The ACM_MEVSTAT.EV0 bit indicates when an instance of event 0 hasbeen missed since the last trigger. If set and the corresponding bit inACM_MEVMSK is set (interrupt enabled), the condition generates aninterrupt. This bit is W1C.No Event 0 Missed Status 1Event 0 MissedTable 27-12:ACM_MEVSTAT Register Fields (Continued)Bit No.(Access)Bit Name Description/EnumerationEvent N Time RegisterThe ACM_EVTIMEn registers each hold a 32-bit event time value. There are 16 event time registers: 8 are assigned to each ACM timer, if both timers are enabled. If only one timer is enabled, all 16 of the ACM_EVTIMEn registers are assigned to the enabled timer.Note that the ACM_EVTIMEn register should not be programmed when an event is active. The register might give incorrect results. The user should program this register before giving trigger and should re-program the register after all the events are complete (ACM_STAT.ECOM1 or ACM_STAT.ECOM0 bit is set). Also note that even if none of the events are enabled in the ACM_EVTIMEn register (for example, all ACM_EVCTLn.ENAEV =0), the ACM_STAT.ECOM0 or ACM_STAT.ECOM1 bit is set and an interrupt is raised (if unmasked) if a trigger is applied with the Timer enabled.Table 27-14:ACM_EVCTLn Register Fields Bit No.(Access)Bit Name Description/Enumeration5:1(R/W)EPF Event Parameter Field.The ACM_EVCTLn.EPF bits select values for the ADC control pins(ACM_A0, ACM_A1, ACM_A2, and ACM_A3), which are output when theenabled event occurs. Selection of ACM_EVCTLn.EPF values are basedon the type of ADC, usage mode, and other items. For moreinformation, see the operating modes section. Note that all ACM_EVCTLn.EPF bits have the same external pin timing.0(R/W)ENAEVEnable Event.The ACM_EVCTLn.ENAEV bit causes a sampling event to occur to theADC with the ADC controls selected by the ACM_EVCTLn.EPF fieldwhen an event (time comparison match or other external trigger)occurs. If disabled, the corresponding event has no significance, andthe control values is not used.Disable Event 1Enable Event。

FPGA可编程逻辑器件芯片EP2S60F672I4中文规格书

FPGA可编程逻辑器件芯片EP2S60F672I4中文规格书

Software Stratix®II devices are supported by the Altera® Quartus®II designsoftware, which provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includesHDL and schematic design entry, compilation and logic synthesis, fullsimulation and advanced timing analysis, SignalTap®II logic analyzer,and device configuration. See the Quartus II Handbook for moreinformation on the Quartus II software features.The Quartus II software supports the Windows XP/2000/NT/98, SunSolaris, Linux Red Hat v7.1 and HP-UX operating systems. It alsosupports seamless integration with industry-leading EDA tools throughthe NativeLink® interface.Duty Cycle DistortionHere is an example for calculating the DCD in percentage for a DDIO output on a row I/O on a -3 device:If the input I/O standard is SSTL-2 and the DDIO output I/O standard is SSTL-2 Class II, the maximum DCD is 60ps (see Table 5–82). If the clock frequency is 267MHz, the clock period T is:T = 1/ f = 1 / 267MHz = 3.745ns = 3745ps Calculate the DCD as a percentage:(T/2 – DCD) / T = (3745ps/2 – 60ps) / 3745ps = 48.4% (for low boundary)(T/2 + DCD) / T = (3745ps/2 + 60ps) / 3745ps = 51.6% (for high boundary)Table 5–82.Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3 Devices Notes (1), (2)Row DDIO Output I/OStandardMaximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port(No PLL in Clock Path)UnitTTL/CMOSSSTL-2SSTL/HSTL LVDS/ HyperTransport Technology3.3 & 2.5 V1.8 & 1.5 V2.5 V1.8 & 1.5 V3.3 V3.3-V LVTTL 260380145145110ps 3.3-V LVCMOS 21033010010065ps 2.5 V 195315858575ps 1.8 V1502658585120ps 1.5-V LVCMOS 255370140140105ps SSTL-2 Class I 175295656570ps SSTL-2 Class II 170290606075ps SSTL-18 Class I 155275555090ps 1.8-V HSTL Class I 150270606095ps 1.5-V HSTL Class I 150270555590ps LVDS/ HyperTransport technology 180180180180180psNotes to Table 5–82:(1)The information in Table 5–82 assumes the input clock has zero DCD.(2)The DCD specification is based on a no logic array noise condition.Table5–84.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 1 of 2)Notes (1), (2)DDIO Column Output I/OStandardMaximum DCD Based on I/O Standard of Input Feeding the DDIOClock Port (No PLL in the Clock Path)UnitTTL/CMOS SSTL-2SSTL/HSTL 1.2-V HSTL 3.3/2.5 V1.8/1.5 V2.5 V1.8/1.5 V1.2 V3.3-V LVTTL 260380145145145ps 3.3-V LVCMOS 210330100100100ps 2.5 V195315858585psPLL Timing Specifications Tables5–92 and 5–93 describe the Stratix II PLL specifications when operating in both the commercial junction temperature range (0 to 85°C) and the industrial junction temperature range (–40 to 100 °C).Table5–92.Enhanced PLL Specifications(Part 1 of2)Name Description Min Typ Max Unit f I N Input clock frequency2500MHz f I N P F D Input frequency to thePFD2420MHz f I N D U T Y Input clock duty cycle4060%f E I N D U T Y External feedbackinput clock duty cycle4060%t I N J I T T E R Input or externalfeedback clock inputjitter tolerance interms of period jitter.Bandwidth ≤0.85MHz0.5ns (p-p)Input or externalfeedback clock inputjitter tolerance interms of period jitter.Bandwidth >0.85MHz1.0ns (p-p)t O U T J I T T E R Dedicated clockoutput period jitter 250ps for ≥ 100 MHz outclk25mUI for < 100 MHz outclkps or mUI(p-p)t F C O M P External feedbackcompensation time10nsf O U T Output frequency forinternal global orregional clock 1.5(2)550.0MHzt O U T D U T Y Duty cycle for externalclock output (when setto 50%).455055%f S C A N C L K Scanclk frequency100MHz t C O N F I G P L L Time required toreconfigure scanchains for enhancedPLLs174/f S C A N C L K nsf O U T_E X T PLL external clockoutput frequency 1.5(2)550.0 (1)MHz5Stratix II Device Handbook, Volume PLL Timing Specificationst L O C KTime required for the PLL to lock from the time it is enabled or the end of device configuration 0.031mst D L O C KTime required for the PLL to lockdynamically after automatic clock switchover between two identical clock frequencies 1msf S W I T C H OV E RFrequency range where the clock switchover performs properly 4500MHzf C L B W PLL closed-loop bandwidth0.13 1.2016.90MHz f V C OPLL VCO operating range for –3 and –4 speed grade devices 3001,040MHzPLL VCO operating range for –5 speed grade devices300840MHzf S SSpread-spectrum modulation frequency 30150kHz % spreadPercent down spread for a given clock frequency 0.40.50.6%t P L L _P S E R R Accuracy of PLL phase shift±15ps t A R E S E TMinimum pulse width on areset signal. 10ns t A R E S E T _R E C O N F I GMinimum pulse width on the areset signal when using PLLreconfiguration. Reset the PLL after scandone goes high.500nsNotes to Table 5–92:(1)Limited by I/O f M A X . See Table 5–78 on page 5–69 for the maximum. Cannot exceed f O U T specification.(2)If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.Table 5–92.Enhanced PLL Specifications (Part 2 of 2)NameDescriptionMin TypMaxUnit。

FPGA可编程逻辑器件芯片EP2S15F672C6中文规格书

FPGA可编程逻辑器件芯片EP2S15F672C6中文规格书

PLLs & Clock NetworksPLLs & Clock Networks Stratix II devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution. Global & Hierarchical ClockingStratix II devices provide 16 dedicated global clock networks and32regional clock networks (eight per device quadrant). These clocks are organized into a hierarchical clock structure that allows for up to24clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains in Stratix II devices.There are 16 dedicated clock pins (CLK[15..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device, as shown in Figures2–31 and 2–32. Internal logic and enhanced and fast PLL outputs can also drive the global and regional clock networks. Each global and regional clock has a clock control block, which controls the selection of the clock source and dynamically enables/disables the clock to reduce power consumption. Table2–8 shows global and regional clock features.Global Clock NetworkThese clocks drive throughout the entire device, feeding all device quadrants. The global clock networks can be used as clock sources for all resources in the device-IOEs, ALMs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The Table2–8.Global & Regional Clock FeaturesFeature Global Clocks Regional Clocks Number per device1632Number available perquadrant168Sources CLK pins, PLL outputs,or internal logicCLK pins, PLL outputs,or internal logic Dynamic clock sourceselectionv (1)Dynamic enable/disable v vNote to Table2–8:(1)Dynamic source clock selection is supported for selecting between CLKp pins andPLL outputs only.Figure2–55.Output TIming Diagram in DDR ModeThe Stratix II IOE operates in bidirectional DDR mode by combining theDDR input and DDR output configurations. The negative-edge-clockedOE register holds the OE signal inactive until the falling edge of the clock.This is done to meet DDR SDRAM timing requirements.External RAM InterfacingIn addition to the six I/O registers in each IOE, Stratix II devices also havededicated phase-shift circuitry for interfacing with external memoryinterfaces. Stratix II devices support DDR and DDR2 SDRAM, QDR IISRAM, RLDRAM II, and SDR SDRAM memory interfaces. In everyStratix II device, the I/O banks at the top (banks 3 and 4) and bottom(banks 7 and 8) of the device support DQ and DQS signals with DQ busmodes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table2–14 shows the numberof DQ and DQS buses that are supported per device.Table2–14.DQS & DQ Bus Mode Support(Part 1 of2)Note(1)Device Package Number of×4GroupsNumber of×8/×9 GroupsNumber of×16/×18 GroupsNumber of×32/×36 GroupsEP2S15484-pin FineLine BGA8400 672-pin FineLine BGA18840 EP2S30484-pin FineLine BGA8400 672-pin FineLine BGA18840 EP2S60484-pin FineLine BGA8400 672-pin FineLine BGA188401,020-pin FineLine BGA361884I/O StructureA compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of theircorresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal.The Stratix II device has two phase-shifting reference circuits, one on the top and one on the bottom of the device. The circuit on the top controls the compensated delay elements for all DQS pins on the top. The circuit on the bottom controls the compensated delay elements for all DQS pins on the bottom.Each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequency as the DQS signal. Clock pins CLK[15..12]p feed the phase circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device. In addition, PLL clock outputs can also feed the phase-shifting reference circuits.Figure 2–56 illustrates the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device.EP2S90484-pin Hybrid FineLine BGA 8400780-pin FineLine BGA 188401,020-pin FineLine BGA 3618841,508-pin FineLine BGA361884EP2S130780-pin FineLine BGA188401,020-pin FineLine BGA 3618841,508-pin FineLine BGA361884EP2S1801,020-pin FineLine BGA3618841,508-pin FineLine BGA361884Notes to Table 2–14:(1)Check the pin table for each DQS/DQ group in the different modes.Table 2–14.DQS & DQ Bus Mode Support (Part 2 of 2)Note (1)DevicePackageNumber of ×4GroupsNumber of ×8/×9 GroupsNumber of ×16/×18 Groups Number of ×32/×36 Groups。

FPGA可编程逻辑器件芯片EP1S25F672C6中文规格书

FPGA可编程逻辑器件芯片EP1S25F672C6中文规格书

2.Stratix ArchitectureFunctional Description Stratix® devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks.The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device.M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318MHz. M512 blocks are grouped into columns across the device in between certain LABs.M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 291MHz. These blocks are grouped into columns across the device in between certain LABs.M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to 269MHz. Several M-RAM blocks are located individually or in pairs within the device’s logic array.Digital signal processing (DSP) blocks can implement up to either eight full-precision 9×9-bit multipliers, four full-precision 18 × 18-bit multipliers, or one full-precision 36×36-bit multiplier with add or subtract features. These blocks also contain 18-bit input shift registers for digital signal processing applications, including FIR and infinite impulse response (IIR) filters. DSP blocks are grouped into two columns in each device.Each Stratix device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for registering input, output, and output-enable signals. When used withStratix Device Handbook, Volume 1Stratix ArchitectureFigure 2–7.LE in Dynamic Arithmetic ModeStratix Device Handbook, Volume 1MultiTrack InterconnectTable 2–2 shows the Stratix device’s routing scheme.Table 2–2.Stratix Device Routing SchemeSourceDestinationL U T C h a i nR e g i s t e r C h a i nL o c a l I n t e r c o n n e c tD i r e c t L i n k I n t e r c o n n e c tR 4 I n t e r c o n n e c tR 8 I n t e r c o n n e c tR 24 I n t e r c o n n e c tC 4 I n t e r c o n n e c tC 8 I n t e r c o n n e c tC 16 I n t e r c o n n e c tL EM 512 R A M B l o c kM 4K R A M B l o c kM -R A M B l o c kD S P B l o c k sC o l u m n I O E R o w I O ELUT Chain v Register Chain v LocalInterconnect vvvvvvvDirect Link Interconnect v R4 Interconnect v vvvvR8 Interconnect vvvR24Interconnect vvv v C4 Interconnect v vvC8 Interconnect vvvC16Interconnect vvv vLEvvv v v v v v M512 RAM Blockv v v v v v M4K RAM Block v v v v v v M-RAM Block v v DSP Blocks vv vv v v Column IOE v v v v Row IOEvvvvvvStratix Device Handbook, Volume 1Stratix ArchitectureTriMatrix MemoryTriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM blocks. Although these memory blocks are different, they can all implement various types of memory with or without parity,including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table 2–3 shows the size and features of the different RAM blocks.Table 2–3.TriMatrix Memory Features (Part 1 of 2)Memory FeatureM512 RAM Block (32×18Bits)M4K RAM Block (128×36Bits)M-RAM Block (4K ×144Bits)Maximum performance (1)(1)(1)T rue dual-port memory vv Simple dual-port memoryv v v Single-port memoryvvvStratix Device Handbook, Volume 1TriMatrix MemoryConfigurations512×1256×2128×464×864×932×1632×184K ×12K ×21K ×4512×8512×9256×16256×18128×32128×3664K ×864K ×932K ×1632K ×1816K ×3216K ×368K ×648K ×724K ×1284K ×144Table 2–3.TriMatrix Memory Features (Part 2 of 2)Memory FeatureM512 RAM Block (32×18Bits)M4K RAM Block (128×36Bits)M-RAM Block (4K ×144Bits)。

FPGA可编程逻辑器件芯片EP2S30F672C5中文规格书

FPGA可编程逻辑器件芯片EP2S30F672C5中文规格书

Table 6–5 shows the summary of input register modes for the DSP block.Multiplier StageThe multiplier stage supports 9 × 9, 18 × 18, or 36 × 36 multipliers as well as other smaller multipliers in between these configurations. See“Operational Modes” on page 6–21 for details. Depending on the data width of the multiplier, a single DSP block can perform many multiplications in parallel.Each multiplier operand can be a unique signed or unsigned number. Two signals, signa and signb , control the representation of eachoperand respectively. A logic 1 value on the signa signal indicates that data A is a signed number while a logic 0 value indicates an unsigned number. Table 6–6 shows the sign of the multiplication result for the various operand sign representations. The result of the multiplication is signed if any one of the operands is a signed value.There is only one signa and one signb signal for each DSP block.Therefore, all of the data A inputs feeding the same DSP block must have the same sign representation. Similarly, all of the data B inputs feeding the same DSP block must have the same sign representation. The multiplier offers full precision regardless of the sign representation.1When the signa and signb signals are unused, the Quartus ® IIsoftware sets the multiplier to perform unsigned multiplication by default.Table 6–5.Input Register ModesRegister InputMode9 × 918 × 1836 × 36Parallel inputv v vShift register input v v Table 6–6.Multiplier Sign RepresentationData A (signa Value)Data B (signb Value)Result Unsigned (logic 0)Unsigned (logic 0)Unsigned Unsigned (logic 0)Signed (logic 1)Signed Signed (logic 1)Unsigned (logic 0)Signed Signed (logic 1)Signed (logic 1)SignedAccumulatorWhen the adder/subtractor/accumulator is configured as an accumulator, the output of the adder/output block feeds back to the accumulator as shown in Figure6–7. The accumulator can be set up to perform addition only, subtraction only or the addnsub signal can be used to dynamically control the accumulation direction. A logic 1 value on the addnsub signal indicates that the accumulator is performing addition while a logic 0 value indicates subtraction.Each accumulator can be cleared by either clearing the DSP block output register or by using the accum_sload signal. The accumulator clear using the accum_sload signal is independent from the resetting of the output registers so the accumulation can be cleared and a new one can begin without losing any clock cycles. The accum_sload signal controls a feedback multiplexer that specifies that the output of the multiplier should be summed with a zero instead of the accumulator feedback path. The accumulator can also be initialized/preloaded with a non-zero value using the accum_sload signal and the accum_sload_upper_data bus with one clock cycle latency. Preloading the accumulator is done by adding the result of the multiplier with the value specified on the accum_sload_upper_data bus. As in the case of the accumulator clearing, the accum_sload signal specifies to the feedback multiplexer that the accum_sload_upper_data signal should feed the accumulator instead of the accumulator feedback signal. Theaccum_sload_upper_data signal only loads the upper 36-bits of the accumulator. To load the entire accumulator, the value for the lower16-bits must be sent through the multiplier feeding that accumulator with the multiplier set to perform a multiplication by one.The overflow signal will go high on the positive edge of the clock when the accumulator detects an overflow or underflow. The overflow signal will stay high for only one clock cycle after an overflow or underflow is detected even if the overflow or underflow condition is still present. A latch external to the DSP block has to be used to preserve the overflow signal indefinitely or until the latch is cleared.The DSP blocks support Q1.15 input format saturation and rounding in each accumulator. The following signals are available that can control if saturation or rounding or both is performed to the output of the accumulator:■accum_round■accum_saturation■accum_is_saturated outputDSP Blocks in Stratix II and Stratix II GX Devices Each DSP block has two sets of accum_round and accum_saturation signals which control if rounding or saturation is performed on the accumulator output respectively (one set of signals for each accumulator). Rounding and saturation of the accumulator output is only available when implementing an 16 × 16 multiplier-accumulator to conform to the bit widths required for Q1.15 input format computation.A logic 1 value on the accum_round and accum_saturation signal indicates that rounding or saturation is performed while a logic 0 indicates that no rounding or saturation is performed. A logic 1 value on the accum_is_saturated output signal tells you that saturation has occurred to the result of the accumulator.Figure6–10 shows the DSP block configured to perform multiplier-accumulator operations.Adder/SubtractorThe addnsub1 or addnsub3 signals specify whether you are performing addition or subtraction. A logic 1 value on the addnsub1 or addnsub3 signals indicates that the adder/subtractor is performing addition while a logic 0 value indicates subtraction. These signals can be dynamically controlled using logic external to the DSP block. If the first stage is configured as a subtractor, the output is A – B and C – D.The adder/subtractor block share the same signa and signb signals as the multiplier block. The signa and signb signals can be pipelined with a latency of one or two clock cycles or not.The DSP blocks support Q1.15 input format rounding (not saturation) after each adder/subtractor. The addnsub1_round andaddnsub3_round signals determine if rounding is performed to the output of the adder/subtractor.The addnsub1_round signal controls the rounding of the topadder/subtractor and the addnsub3_round signal controls the rounding of the bottom adder/subtractor. Rounding of the adder output is only available when implementing an 16 × 16 multiplier-adder to conform to the bit widths required for Q1.15 input format computation.A logic 1 value on the addnsub_round signal indicates that rounding is performed while a logic 0 indicates that no rounding is performed. Summation BlockThe output of the adder/subtractor block feeds an optional summation block, which is an adder block that sums the outputs of bothadder/subtractor blocks. The summation block is used when more than two multiplier results are summed. This is useful in applications such as FIR filtering.。

FPGA可编程逻辑器件芯片XC2VP7-5FFG672I中文规格书

FPGA可编程逻辑器件芯片XC2VP7-5FFG672I中文规格书

BurstMin RequirementsBurstMin must be less than or equal to half BurstMax and a multiple of the LBUS width. Channel ChangesChannel changes are only permitted after a burst has been fully written to the LBUS.Status/Control InterfaceThe Status/Control interface allows you to set up the Interlaken IP core configuration and monitor the Interlaken IP core status. The following sections describe the various Status and Control signals.Note:Most of the following status signal descriptions assume a good understanding of the Interlaken Protocol. See the Interlaken Protocol Definition Revision 1.2 document for more details.RX Meta Frame StatusThe Interlaken protocol requires that each lane align or synchronize to incoming words using the procedure described in the Interlaken specification. The Interlaken IP core provides status bits to indicate the state of word boundary synchronization and lane alignment. All signals are synchronous with the rising-edge of LBUS_CLK and a detailed description of each signal is included in this section.STAT_RX_SYNCED[11:0]When a bit of this bus is 0, it indicates that word boundary synchronization of the corresponding lane is not complete or that an error has occurred as identified by another status bit.When a bit of this bus is 1, it indicates that the corresponding lane is word boundary synchronized and is receiving Meta Frame Synchronization Words and Scrambler State Control Words as expected.STAT_RX_SYNCED_ERR[11:0]When a bit of this bus is 1, it indicates one of several possible failures on the corresponding lane:•Word boundary synchronization in the lane was not possible using Framing bits [65:64].•After word boundary synchronization in the lane was achieved, errors were detected on Framing bits [65:64].•After word boundary synchronization in the lane was achieved, a valid Meta Frame Synchronization Word was never received.The bits of the bus remain asserted until word boundary synchronization occurs or until some other error or failure is signaled for the corresponding lane.STAT_RX_MF_LEN_ERR[11:0]When a bit of this bus is 1, it indicates that Meta Frame Synchronization Words are being received but not at the expected rate in the corresponding lane. The transmitter and receiver must be re-configured with the same Meta Frame length.The bits of the bus remain asserted until word boundary synchronization occurs or until some other error or failure is signaled for the corresponding lane.STAT_RX_MF_REPEAT_ERR[11:0]After word boundary synchronization is achieved in a lane, if a bit of this bus is a 1, it indicates one of the following:•Four consecutive invalid Meta Frame Synchronization Words were detected in the corresponding lane.•Three consecutive invalid Scrambler State Control Words were detected in the corresponding lane.The bits of the bus remain asserted until word boundary synchronization occurs or until some other error or failure is signaled for the corresponding lane.STAT_RX_DESCRAM_ERR[11:0]When a bit of this bus is 1, it indicates that a Scrambler State Control Word with an unexpected value was received on the corresponding lane. This bit is only asserted after word boundary synchronization is achieved. This output is asserted for one clock period each time a descrambler error is detected.STAT_RX_MF_ERR[11:0]When a bit of this bus is 1, it indicates that an invalid Meta Frame Synchronization Word was received on the corresponding lane. This bit is only asserted after word boundary synchronization is achieved. This output is asserted for one clock period each time an invalid Meta Frame Synchronization Word is detected.STAT_RX_ALIGNEDWhen STAT_RX_ALIGNED is a value of 1, all of the lanes are aligned or de-skewed as explained in the Interlaken specification and the receiver is ready to receive packet data.STAT_RX_ALIGNED_ERRWhen STAT_RX_ALIGNED_ERR is a value of 1, one of the following occurs:•Lane alignment fails after several attempts•Lane alignment is lost (STAT_RX_ALIGNED is asserted and then it is negated)STAT_RX_FRAMING_ERR[11:0]When a bit of this bus is 1, an illegal framing pattern is detected on the corresponding lane after word boundary synchronization. If this error is detected after lane alignment, the error is treated like a CRC24 error.This output is asserted for one clock period each time an illegal framing pattern is detected.RX Error StatusThe Interlaken IP core provides status signals to identify Interlaken data transmission protocol violations in sequences of Control and Data words. These are errors independent of the status of the Meta Frame. Generally, these signals do not indicate a failure on the part of the sending transmitter but some type of corruption during the transmission.All signals are synchronous with the rising-edge of LBUS_CLK and a detailed description of each signal follows.STAT_RX_CRC24_ERRWhen this signal is a value of 1, it indicates that the error detection logic has identified a mismatch between the expected and received value of CRC24 in a Control Word.Every time a CRC24 error is detected, all open packets are marked as containing errors as specified by the Interlaken Protocol specification. By definition, there is no mechanism provided by Interlaken to associate a CRC24 error with individual packets.This signal is asserted for one clock period each time a CRC24 error is detected.。

FPGA可编程逻辑器件芯片EP2S15F672I3N中文规格书

FPGA可编程逻辑器件芯片EP2S15F672I3N中文规格书

Symbol
Parameter
Conditions
Minimum Maximum Unit
VOL
Low-level output voltage
IOL = 4 mA (2)
0.45
V
Notes to Tables 5–5: (1) Stratix II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
Figure 2–58. Stratix II Transmitter Channel
Data from R4, R24, C4, or direct link interconnect
10
10
+
Up to 1 Gbps

refclk
Local Interconnect
diffioclk
Fast PLL
For more information on multi-volt support, including information on using TDO and nCEO in multi-volt systems, refer to the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
JESD8-B. (2) This specification is supported across all the programmable drive strength available for this I/O standard as

FPGA可编程逻辑器件芯片EP2AGX260FF35C5N中文规格书

FPGA可编程逻辑器件芯片EP2AGX260FF35C5N中文规格书

U NIVERSAL A SYNCHRONOUS R ECEIVER /T RANSMITTER (UART)UART O PERATING M ODESADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCENOTE :The UART’s status interrupt goes directly to the system event controller (SEC), bypassing theDMA unit completely.For transmit DMA, programs should set the DMA_CFG.SYNC bit. With this bit set, interrupt generation is delayed until the entire DMA FIFO is drained to the UART module. The UART transmit DMA interrupt service routine is allowed to disable the DMA or to clear the UART_IMSK.ETBEI control bit only when the DMA_CFG.SYNC bit is set, otherwise up to four data bytes might be lost.When the UART_IMSK.ETBEI bit is set, an initial transmit DMA request is issued immediately. The program should then clear the UART_IMSK.ETBEI bit through the DMA service routine.In DMA transmit mode, the UART_IMSK.ETBEI bit enables the peripheral request to the DMA FIFO. The strobe on the memory side is still enabled by the DMA_CFG.EN bit. If the DMA count is less than the DMA FIFO depth, which is 4, then the DMA interrupt might be requested before the UART_IMSK.ETBEI bit is set. If this is behavior not wanted, set the DMA_CFG.SYNC bit.Regardless of the DMA_CFG.SYNC setting, the DMA stream has not left the UART transmitter completely at the time the interrupt is generated. Transmission may abort in the middle of the stream, causing data loss, if the UART clock was disabled without additional synchronization with the UART_STAT.TEMT bit.The UART provides functionality to avoid resource consuming polling of the UART_STAT.TEMT bit. The UART_IMSK_SET.EDTPTI bit enables the UART_STAT.TEMT bit to trigger a DMA interrupt. To delay the DMA completion interrupt until the last data word of a STOP DMA has left the UART, keep the DMA_CFG.DI_EN bit cleared and set the UART_IMSK_SET.EDTPTI bit instead. Then, the normal DMA completion interrupt is suppressed. Later, the UART_STAT.TEMT event triggers a DMA interrupt after the DMA’s last word has left the UART transmit buffers. If DI_EN and UART_IMSK.EDTPTI are set, when finishing STOP mode, the DMA requests two interrupts.The UART’s DMA supports 8-bit and 16-bit operation, but not 32-bit operation. Sign extension is also not supported.Mixing DMA and Core ModesSwitching from DMA mode to core operation on the fly requires some consideration, especially fortransmit operations. By default, the interrupt timing of the DMA is synchronized with the memory side of the DMA FIFOs. Normally, the transmit DMA completion interrupt is generated after the last byte is copied from the memory into the DMA FIFO. The transmit DMA interrupt service routine is not yet permitted to disable the DMA_CFG.EN bit. The interrupt is requested by the time the DMA_STAT.IRQDONE bit is set. The DMA_STAT.RUN bit, however, remains set until the data has completely left the transmit DMA FIFO.Therefore, when planning to switch from a DMA to the core mode, always set the DMA_CFG.SYNC bit in the word of the last descriptor or work unit before handing over control to core mode. Then, after the interrupt occurs, software can write new data into the UART_THR register as soon as the UART_STAT.THRE bit permits. If the DMA_CFG.SYNC bit cannot be set, software can poll the DMA_STAT.RUN bit instead. Alternatively, using the UART_IMSK.EDTPTI bit can avoid expensive status bit polling.U NIVERSAL A SYNCHRONOUS R ECEIVER/T RANSMITTER (UART)UART O PERATING M ODESThe two force error bits, UART_CTL.FPE and UART_CTL.FFE, are intended for test purposes. They areuseful for debugging software, especially in loop back mode.The UART can be set to internal loop back mode (UART_CTL.LOOP_EN=1). Loop back mode disconnects the receiver’s input from the receive pin and internally redirects the transmit output to the receiver. The transmit pin remains active and continues to transmit data externally as well. Loop back mode also forces the UART_RTS pin to de-assert, disconnects the UART_STAT.CTS bit from the UART_CTS input pin, and connects the internal version of UART_RTS to the UART_STAT.CTS bit.Additionally, the UART_TX pin can be forced to zero asynchronously using the UART_CTL.SB bit. UART Operating ModesThe UART’s main operating modes are described in the following sections.•UART Mode•IrDA SIR Mode•Multi-Drop Bus ModeUART ModeThe UART Mode follows an asynchronous serial communication protocol with these options:• 1 start bit•5-8 data bits•Address bit (available in MDB mode only)•None, even, odd or sticky parity•1, 1½, or 2 stop bits (1½ stop bits valid only in 5-bit word length)The format of received and transmitted character frames is controlled by the UART_CTL register. Data is always transmitted and received with the least significant bit (LSB) first.The following figure shows a typical physical bit stream measured on a UART_TX pin.ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCEU NIVERSAL A SYNCHRONOUS R ECEIVER /T RANSMITTER (UART)UART O PERATING M ODESADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCE The transmission of break command/inter-frame gap is followed by transmission of the number of stop bits as set in the UART_CTL.STB and UART_CTL.STBH bit fields.The UART receiver can detect break commands through the break indicator (UART_STAT.BI ) flag. This flag reports that an entire UART frame has been received in low state. It does not report whether the dura-tion of the received low pulse was exact or at least 13 bit times as LIN masters transmit. Typically, the break indicator meets LIN requirements. If however the pulse width needs to be determined more precisely, the GP timers can be used.On ADSP-BF60x processors each UART_RX pin is also routed to any of the GP timers through their alter-nate capture input (TACI). This is not only useful for bit rate detection (autobaud ) but also helps to precisely measure the pulse widths on the UART_RX input. Additionally, the new windowed watchdog width mode of the GP timers can issue an interrupt or a fault condition if the received pulse width is shorter than a bit time or longer than the worst case break condition.UART Mode Receive Operation (Core)The receive operation uses the same data format as the transmit configuration, except that one valid stop bit is always sufficient; that is, the UART_CTL.STB and UART_CTL.STBH bits have no impact to the receiver.The UART receiver senses the falling edges of the receive input. When an edge is detected, the receiver starts sampling the input according to settings in the UART_CLK register. The start bit is sampled (majority sampling) close to its midpoint. If sampled low, a valid start condition is assumed. Otherwise, the detected falling edge is discarded.After detection of the start bit, the received word is shifted into the UART_RSR register.After the corresponding stop bit is received, the content of the UART_RSR register is transferred to the 8-deep receive FIFO and is accessible by reading the UART_RBR register.The receive FIFOs and the UART_RBR register can be seen as a 9-stage receive buffer. If the stop bit of the 9th word is received before software reads the UART_RBR register, an overrun error is reported. Overruns protect data in the UART_RBR register and the receive FIFO from being overwritten by further data until the UART_STAT.OE bit is cleared by software. However, the data in the UART_RSR register is immediately destroyed as soon as the overrun occurs.The sampling clock is 16 times faster than the bit clock. The receiver over samples every bit 16 times and makes a majority decision based on the middle three samples. This improves immunity against noise and hazards on the line. Spurious pulses of less than two times the sampling clock period are disregarded.Normally, every incoming bit is sampled at exactly the 7th, 8th and 9th sample clock. If, however, the UART_CLK.EDBO bit is set to 1 to achieve better bit rate granularity and accuracy as required at high oper-ation speeds, the bits are one roughly sampled at 7/16th, 8/16th and 9/16th of their period. Hardware design should ensure that the incoming signal is stable between 6/16th and 10/16th of the nominal bit period.Reception starts when a falling edge is detected on the UART_RX input pin. The receiver attempts to see a start bit. The data is shifted into the UART_RSR register. After the 9th sample of the first stop bit is。

FPGA可编程逻辑器件芯片EP20K300EFI672-2N中文规格书

FPGA可编程逻辑器件芯片EP20K300EFI672-2N中文规格书

UART O PERATING M ODESMDB Transmit OperationIn MDB mode, receive and transmit paths operate completely independently from each other, except for sharing bit rate and frame formats for both transfer directions.Transmit operation is initiated by writing the UART_THR or UART_TAIP registers. A write to the UART_THR register transmits the written word with the appending address bit set low, a write to the UART_TAIPregister transmits the written word with the appended address bit set high. The data is moved into the UART_TSR register, where it is shifted out at the bit rate programmed by the UART_CLK register, with start, stop, address, and parity bits appended as required.If DMA is enabled, the DMA engine always writes the data into the UART_THR register, and the written word is transmitted with the appending address bit set low.The polarity of transmit data is selectable, using the UART_CTL.TPOLC bit.MDB Receive OperationReceive operations use the same data format as the transmit configuration, except that the number of stop bits is always assumed to be 1. After detection of the start bit, the received word is shifted into the UART_ RSR register at the programmed bit.Normally, every incoming bit is sampled at exactly the 7th, 8th and 9th sample clock. If, however, the UART_CLK.EDBO bit is set to achieve better bit rate granularity and accuracy as required at high operation speeds, the bits are roughly sampled at 7/16th, 8/16th and 9/16th of their period. Hardware design should ensure that the incoming signal is stable between 6/16th and 10/16th of the nominal bit period.After the appropriate number of bits (including address, parity, and stop bits) is received, the UART_RSR register is transferred to the receive FIFO and accessible through the UART_RBR register.The polarity of receive data is selectable, using the UART_CTL.RPOLC bit.DMA ModeIn DMA mode, separate receive and transmit DMA channels move data between the UART and memory.The software does not have to move data; it just has to set up the appropriate transfers either through the descriptor mechanism or through autobuffer mode.DMA channels provide a 4-deep FIFO, resulting in total buffer capabilities of 6 words at the transmit side and 9 words at the receive side. In DMA mode, the latency is determined by the bus activity and arbitration mechanism and not by the processor loading and interrupt priorities.To enable UART DMA, first set up the system DMA control registers and then enable the UART_IMSK.ERBFI and/or UART_IMSK.ETBEI interrupts. This is necessary because these interrupt request lines double as DMA request lines. With DMA enabled, once these requests are received, the DMA control unit gener-ates a direct memory access. If DMA is not enabled, the UART interrupt is passed on to the system inter-rupt handling unit.ADSP-BF60X UART R EGISTER D ESCRIPTIONSUsing Core TransfersA core transmit operation is accomplished by writing data into the UART_THR register, when the UART_STAT.THRE bit is set. If the UART_STAT.DR bit is set, received data can be read from the UART_RBR register.Using DMA Transfers1.Make sure that the UART_IMSK.ETBEI or the UART_IMSK.ERBFI bits are cleared before configuring theDMA.2.Configure the dedicated DMA channel.3.Set the UART_IMSK.ETBEI or UART_IMSK.ERBFI bits to start the transfer.Using InterruptsEach UART features three interrupt signal outputs.1.Enable individual interrupts in the system event controller (SEC).2.Register IRQ handlers.e the interrupts mask registers to enable specific IRQ events.Setting Up Hardware Flow Control1.Configure automatic or manual hardware flow control for the receiver through the UART_CTL.ARTS bit,and/or the transmitter through the UART_CTL.ACTS bit.2.Configure UART_CTS and UART_RTS polarity through the UART_CTL.FCPOL bit.ADSP-BF60x UART Register DescriptionsUART (UART) contains the following registers.Table 19-9:ADSP-BF60x UART Register ListName DescriptionUART_CTL Control RegisterUART_STAT Status RegisterUART_SCR Scratch RegisterU NIVERSAL A SYNCHRONOUS R ECEIVER/T RANSMITTER (UART)UART E VENT C ONTROL register in the normal manner. Accordingly, the UART_IMSK.ETBEI bit can be cleared through the UART_IMSK_CLR register if the string transmission has completed.The UART_STAT.THRE bit is cleared by hardware when new data is written to the UART_THR register. These writes also clear the transmit interrupt request. However, they also initiate further transmission. Ifcontinued transmission is not desired, the transmit request can alternatively be cleared through the UART_ IMSK_CLR.ETBEI bit register. Transfers of data from the UART_THR register to the UART_TSR register re-set this status flag in the UART_STAT register.The UART_STAT.TEMT bit can be interrogated to discover any ongoing transmission. The UART_STAT.TEMT bit’s sticky counterpart, UART_STAT.TFI, indicates if the transmit buffer has drained and can trigger a status interrupt, if required. When data is pending in either one of these registers, the UART_STAT.TEMT flag is low. As soon as all data has left the UART_TSR register, the UART_STAT.TEMT bit goes high again and indicates that all pending transmit operations (including stop bits) have finished. At that time it is safe to disable the UART_CTL.EN bit or to three-state off-chip line drivers. By this time an interrupt can be gener-ated either through the status interrupt channel when the UART_IMSK.ETFI bit is set, or through the DMA controller when enabled by the UART_IMSK.EDTPTI bit.When enabled by the UART_IMSK.ETBEI bit, the UART_STAT.THRE flag requests data along the peripheral command lines to the DMA controller (hereafter referred to as TXREQ). This signal is routed through the DMA controller. If the associated DMA channel is enabled, the TXREQ signal functions as a DMA request, otherwise the DMA controller simply forwards it to the SEC. Alternatively the UART_IMSK.ETXS bit can redirect the transmit interrupts to the UART status interrupt.With interrupts disabled, these status flags can be polled to determine when data is ready to move. Note that because polling is processor intensive, it is not typically used in real-time signal processing environ-ments. Since read operations from UART_STAT registers have no side effects, different software threads can interrogate these registers without mutual impacts. Polling the SEC_SSTATn register without enabling the interrupts by the SEC_CCTLn register is an alternate method of operation to consider. Software can write up to two words into the UART_THR register before enabling the UART clock. As soon as the UART_CTL.EN bit is set, those two words are sent.Receive InterruptsReceive interrupts are enabled by the UART_IMSK_SET.ERBFI bit. If set, the UART_STAT.DR flag requests an interrupt on the dedicated RXREQ output, indicating that new data is available in the UART_RBR register.This signal is routed through the DMA controller. If the associated DMA channel is enabled, the RXREQ signal functions as a DMA request; otherwise the DMA controller simply forwards it to the SEC. Alterna-tively, if no DMA channel is assigned to the UART, the UART_IMSK.ERXS bit can redirect the receive inter-rupts to the UART status interrupt. When software reads the UART_RBR register, hardware clears the UART_ STAT.DR bit again, which, in turn, clears the receive interrupt request.。

FPGA可编程逻辑器件芯片EP1S25F672I6N中文规格书

FPGA可编程逻辑器件芯片EP1S25F672I6N中文规格书

If the Auto-restart configuration after error option is turned on, the devices release their nSTATUS pins after a reset time-out period (maximum of 100μs). After all nSTATUS pins are released and pulled high, the MAX II device can attempt toreconfigure the chain without needing to pulse nCONFIG low. If this option is turned off, the MAX II device must generate a low-to-high transition (with a low pulse of at least 2μs) on nCONFIG to restart the configuration process.1If you have enabled the Auto-restart configuration after error option, the nSTATUS pin transitions from high to low and back again to high when a configuration error is detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width of 10μs to a maximum pulse width of 500μs, as defined in the t STATUS specification.In your system, you can have multiple devices that contain the same configuration data. To support this configuration scheme, all device nCE inputs are tied to GND, while nCEO pins are left floating. All other configuration pins (nCONFIG , nSTATUS , DCLK , DATA0, and CONF _DONE ) are connected to every device in the chain.Configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for every fourth device. Devices must be the same density and package. All devices will start and complete configuration at the same time. Figure 11–15 shows multi-device PS configuration when both Stratix III devices are receiving the same configuration data.You can use a single configuration chain to configure Stratix III devices with other Altera devices. To ensure that all devices in the chain complete configuration at the same time, or that an error flagged by one device initiates reconfiguration in all devices, all of the device CONF _DONE and nSTATUS pins must be tied together.fFor more information about configuring multiple Altera devices in the sameconfiguration chain, refer to the Configuring Mixed Altera FPGA Chains chapter in the Configuration Handbook .Figure 11–15.Multiple-Device PS Configuration When Both Devices Receive the Same DataNotes to Figure 11–15:(1)Connect the resistor to a supply that provides an acceptable input signal for all Stratix III devices on the chain. V CCPGM must be high enough tomeet the V IH specification of the I/O on the external host. It is recommended to power up all configuration systems’ I/O with V CCPGM .(2)The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple devices.Chapter 11:Configuring Stratix III DevicesPassive Serial ConfigurationPS Configuration TimingFigure 11–16 shows the timing waveform for PS configuration when using a MAX II device as an external host.Table 11–10 defines the timing parameters for Stratix III devices for PS configuration.Figure 11–16.PS Configuration Timing Waveform (Note 1)Notes to Figure 11–16:(1)The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG , nSTATUS , and CONF_DONE a re at logic high levels.When nCONFIG is pulled low, a reconfiguration cycle begins.(2)Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay.(3)Upon power-up, before and during configuration, CONF_DONE is low .(4)Do not leave DCLK floating after configuration. You should drive it high or low, whichever is more convenient. DATA[0] is available as a userI/O pin after configuration. The state of this pin depends on the dual-purpose pin settings.(5)Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.nCO N FIGnSTATUS (2)CO N F_DO N E (3)DCLK DATAUser I/OI N IT_DO NEt Table 11–10.PS Timing Parameters for Stratix III Devices (Part 1 of 2)Chapter 11:Configuring Stratix III DevicesPassive Serial ConfigurationTable11–10.PS Timing Parameters for Stratix III Devices (Part 2 of 2)Notes to Table11–10:(1)This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.(2)The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device.f Device configuration options and how to create configuration files are discussedfurther in the Device Configuration Options and Configuration File Format s chapters involume 2 of the Configuration Handbook.PS Configuration Using a MicroprocessorIn this PS configuration scheme, a microprocessor can control the transfer ofconfiguration data from a storage device, such as flash memory, to the target Stratix IIIdevice.f You can do a PS configuration using MicroBlaster™ Passive Serial Software Driver.For more information, refer to AN423: Configuring the MicroBlaster Passive SerialSoftware Driver.1For all configuration and timing information, refer to “PS Configuration Using a MAX II Device as an External Host” on page11–27. This section is also applicablewhen using a microprocessor as an external host.PS Configuration Using a Download CableIn this section, the generic term download cable includes the Altera USB-Blaster USBport download cable, MasterBlaster™ serial/USB communications cable,ByteBlaster II parallel port download cable, ByteBlasterMV™ parallel port downloadcable, and the EthernetBlaster download cable.In PS configuration with a download cable, an intelligent host (such as a PC) transfersdata from a storage device to the device by using the USB-Blaster, MasterBlaster,ByteBlaster II, EthernetBlaster, or ByteBlasterMV cable.Chapter 11:Configuring Stratix III DevicesPassive Serial ConfigurationChapter 11:Configuring Stratix III DevicesJTAG ConfigurationJTAG ConfigurationThe JTAG has developed a specification for boundary-scan testing. Thisboundary-scan test (BST) architecture offers the capability to efficiently testcomponents on PCBs with tight lead spacing. The BST architecture can test pinconnections without using physical test probes and capture functional data while adevice is operating normally. You can also use the JTAG circuitry to shiftconfiguration data into the device. The Quartus II software automatically generatesSOFs that can be used for JTAG configuration with a download cable in the Quartus IIsoftware programmer.f For more information about JTAG boundary-scan testing and commands availableusing Stratix III devices, refer to the following documents:■IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Device chapter of theStratix III Device Handbook■AN 425: Using the Command-Line Jam STAPL Solution for Device ProgrammingStratix III devices are designed such that JTAG instructions have precedence over anydevice configuration modes. Therefore, JTAG configuration can take place withoutwaiting for other configuration modes to complete. For example, if you attempt JTAGconfiguration of Stratix III devices during PS configuration, PS configuration isterminated and JTAG configuration begins.1You cannot use the Stratix III decompression or design security features if you are configuring your Stratix III device when using JTAG-based configuration.1 A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK,and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor,while the TDI, TMS, and TRST pins have weak internal pull-up resistors (typically25kΩ). JTAG output pin TDO and all JTAG input pins are powered by thepower supply of I/O bank 1A. All the JTAG pins support2.5V/3.0V/3.3V VCCPDonly LVTTL I/O standard.All user I/O pins are tri-stated during JTAG configuration. Table11–11 explains eachJTAG pin's function.f The TDO output is powered by the Vpower supply of I/O bank 1A. ForCCPDrecommendations on how to connect a JTAG chain with multiple voltages across thedevices in the chain, refer to the IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix IIIDevices chapter of the Stratix III Device Handbook.。

FPGA可编程逻辑器件芯片EP2S60F672C3N中文规格书

FPGA可编程逻辑器件芯片EP2S60F672C3N中文规格书

DC & Switching Characteristics
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 3 of 5) Note (1)
I/O Standard
Drive Strength
Column I/O Pins (MHz)
-
-
- 550 500 500
-
-
- 550 550 550
350
300 300 350 300 300
500
500 450 500 500 450
700
650 600 700 650 600
-
-
- 700 700 650
-
-
- 700 700 700
-
-
- 600 600 550
-
-
- 650 600 600
4 mA 6 mA 8 mA 10 mA 12 mA 8 mA 16 mA 18 mA 20 mA 4 mA 6 mA 8 mA 10 mA 12 mA 16 mA 18 mA 20 mA 4 mA 6 mA 8 mA 10 mA 12 mA 16 mA 18 mA 20 mA 8 mA 12 mA 16 mA 20 mA 24 mA
Column I/O Pins (MHz) Row I/O Pins (MHz)
-3 -4
-5
-3 -4
-5
500 500 450 500 500 450 500 500 450 500 500 450 500 500 450 500 500 450 500 500 450 500 500 450 500 500 450 500 500 450 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500

FPGA可编程逻辑器件芯片EP1S10F672C中文规格书

FPGA可编程逻辑器件芯片EP1S10F672C中文规格书

Data Transfer ModesThe memory transfer modes involve memory write or memory read-and-write operations allowing for memory to be initialized or transferred from one region of memory to another. There are two forms of memory transfer mode:•CRC compute-and-compare performs a full data transfer from one memory region to another memory region.The CRC generates a signature on the data presented and compares it with a pre-determined and pre-loaded result. An error is generated when the results differ.•Data fill initializes a region of memory with a pre-loaded 32-bit constant value.The CRC compute-and-compare mode of operation requires both incoming and outgoing data channels. The oper-ation occurs either using DMA channels, using core-driven write or read operations to and from the FIFO or using a combination of both. The data fill mode of operation requires only a memory write DMA destination channel—this mode does not support core driven operations.Memory Scan Compute-and-Compare ModeIn this mode of operation, the CRC engine of the peripheral is enabled. The mode is configured through theCRC_CTL.OPMODE field and the CRC engine performs a 32-bit CRC operation on the incoming data stream.The length of the data stream is configured through the CRC_DCNT register. The accumulated result of the CRC operation is contained in the CRC_RESULT_CUR register. As the CRC engine processes each 32-bit word, theCRC_DCNT register is decremented and CRC_RESULT_CUR is updated.Once CRC_DCNT decrements to zero, the contents of the CRC_RESULT_CUR register are copied toCRC_RESULT_FIN and CRC_STAT.DCNTEXP is updated accordingly. The CRC uses the CRC_COMP register to store the expected result of the operation. After the CRC calculation, CRC_COMP is compared withCRC_RESULT_FIN and CRC_STAT.CMPERR is updated to reflect the status of the compare operation.CRC_STAT.CMPERR must be cleared before the next CRC operation is performed.The CRC peripheral also contains CRC_DCNTRLD register. The CRC uses this register to reload CRC_DCNT upon completion of the CRC operation in preparation for the next transfer.The initial seed of the CRC computation can be configured through CRC_CTL.AUTOCLRZ andCRC_CTL.AUTOCLRF. This configuration provides a way to reset CRC_RESULT_CUR to 0x00000000,0xFFFFFFFF or to leave the current register contents untouched for the next operation.The peripheral can be configured to allow for the compare error and data expiration events to generate an interrupt. Memory Scan Data VerifyIn this mode of operation, the CRC engine of the peripheral is not required. The mode is enabled through the CRC_CTL.OPMODE field. Each 32-bit word of the data stream is compared with a constant value that is stored in the CRC_COMP register. The CRC_DCNT register contains the number of words for comparison. The CRC_DCNT register is decremented upon receiving a new 32-bit word from the data stream. If the compare operation fails, theCRC_STAT.CMPERR bit is updated and the contents of CRC_DCNT are captured in the CRC_DCNTCAP register. This information can be used to identify the location in the data stream where the error occurred. Clear theCRC_STAT.CMPERR field to reenable capturing of further errors.ADSP-BF70x Blackfin+ Processor Hardware ReferenceCRC Mode ConfigurationADDITIONAL INFORMATION: This register contains the pre-calculated final CRC signature result for the memory region that the software uses in the final compare operation.5.Initialize the CRC_INEN register.ADDITIONAL INFORMATION: The CRC uses this register to enable the generation of the CRC interrupts for notification of compare errors and block completion. Configure these interrupts. If enabled, ensure that the corresponding interrupt handlers are also configured.6.Initialize CRC_CTL register with the CRC_CTL.OPMODE bit set to memory scan compute-and-compare modeand the CRC_CTL.BLKEN bit configured to enable the CRC peripheral.•Disable the CRC_CTL.OBRSTALL and CRC_CTL.IRRSTALL bit options for this task example.•Configure all mirroring and bit reversal options.•Configure CRC auto clear options.The CRC peripheral is now enabled and ready for the core or DMA channel to write data.7.Write memory region data to the CRC peripheral.a.While CRC_STAT.IBR bit indicates that the input buffer is ready, write the CRC_DFIFO register with 32-bit data.ADDITIONAL INFORMATION: Repeat this step until all data has been written.8.Poll the CRC_STAT.DCNTEXP bit if the interrupt was disabled.ADDITIONAL INFORMATION: Perform this step only if counter expired interrupt is disabled. Polling en-sures that all the data has been processed.9.Poll the CRC_STAT.CMPERR bit if the interrupt was disabled to check for a compare error.ADDITIONAL INFORMATION: Perform this step only if the compare error interrupt is not enabled.10.Write the CRC_STAT register to clear both CRC_STAT.DCNTEXP and CRC_STAT.CMPERR bits.ADDITIONAL INFORMATION: If interrupts were enabled, then clear of these status bits within the interrupt handlers for the respective interrupts.The CRC compute-and-compare operation is now complete. The CRC peripheral is ready to be configured for the next CRC operation.The integrity check of the memory through the expected CRC signature has completed. The final result is indicated through the CRC_STAT.CMPERR bit and the corresponding interrupt when enabled.Clear any W1C CRC status bits before performing more CRC operations.ADSP-BF70x Blackfin+ Processor Hardware ReferenceCRC Mode ConfigurationDMA Driven Memory Scan Data Verify ModeReads a region of memory using DMA transactions and performs a compare operation on each 32-bit word against a single pre-loaded 32-bit constant. The compare error interrupt is enabled to capture and log the location of any compare errors.The task assumes the following:•The polynomial has been loaded and the look-up table is fully initialized•All CRC interrupts have been serviced (none pending)•The CRC block is disabled per the CRC_CTL.BLKEN bitThe interrupt service routine for the compare error interrupt reads and stores the contents of the CRC_DCNTCAP register to a buffer before clearing the compare error interrupt.1.Initialize the CRC_DCNT register.ADDITIONAL INFORMATION: The value loaded must represent the number of 32-bit words in the memory region for which the software calculates and verifies the signature.2.Initialize the CRC_DCNTRLD register.ADDITIONAL INFORMATION: The CRC module uses this register to reload the CRC_DCNT register upon completion of current CRC operation. If no further operation is needed, then this register can be initialized to zero.3.Initialize the CRC_COMP register.ADDITIONAL INFORMATION: This register contains the 32-bit constant that the memory region is expec-ted to be filled with. Each 32 bit of data presented to the peripheral is compared with this value.4.Initialize the CRC_INEN register.ADDITIONAL INFORMATION: The CRC module uses this register to enable the generation of the CRC interrupts for notification of compare errors and block completion. Configure these interrupts, as needed. If enabled, ensure that the corresponding interrupt handlers are also configured.5.Initialize the CRC_CTL register with the CRC_CTL.OPMODE bit set to memory scan data verify mode andCRC_CTL.BLKEN configured to enable the CRC peripheral.The CRC peripheral is now enabled and ready for the core or DMA channel to write the data.6.Configure and enable the memory-to-memory source DMA channel for memory read STOP mode.ADDITIONAL INFORMATION: This step starts the data transfer from the memory region and writes the da-ta to the CRC peripheral.7.Poll the CRC_STAT.DCNTEXP bit if the interrupt was disabled.ADSP-BF70x Blackfin+ Processor Hardware Reference。

FPGA可编程逻辑器件芯片EP2S60F672C5中文规格书

FPGA可编程逻辑器件芯片EP2S60F672C5中文规格书

Operating ConditionsStratix ®II devices are offered in both commercial and industrial grades. Industrial devices are offered in -4 speed grades and commercial devices are offered in -3 (fastest), -4, -5 speed grades.Tables 5–1 through 5–32 provide information about absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for Stratix II devices.Absolute Maximum RatingsTable 5–1 contains the absolute maximum ratings for the Stratix II device family.Table 5–1.StratixII Device Absolute Maximum Ratings Notes (1), (2), (3)SymbolParameterConditionsMinimumMaximumUnitV CCINT Supply voltage With respect to ground –0.5 1.8V V CCIO Supply voltage With respect to ground –0.5 4.6V V CCPD Supply voltageWith respect to ground –0.5 4.6V V CCA Analog power supply for PLLsWith respect to ground–0.5 1.8V V CCD Digital power supply for PLLs With respect to ground –0.5 1.8V V I DC input voltage (4)–0.5 4.6V I OUT DC output current, per pin –2540mA T STG Storage temperature No bias–65150°C T J Junction temperatureBGA packages under bias–55125°CNotes to Tables 5–1(1)See the Operating Requirements for Altera Devices Data Sheet .(2)Conditions beyond those listed in Table 5–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.(3)Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.(4)During transitions, the inputs may overshoot to the voltage shown in Table 5–2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100mA and periods shorter than 20ns.SII51005-4.5Stratix II Device Handbook, Volume 1DC & Switching Characteristics1.8-V HSTL Class II 1.6600.830 1.6600.831.5-V HSTL Class I1.3750.688 1.3750.68751.5-V HSTL Class II 1.3750.688 1.3750.68751.2-V HSTL with OCT 1.1400.570 1.1400.570Differential SSTL-2 Class I2.3251.1632.3251.1625Table 5–35.Timing Measurement Methodology for Input Pins (Part 2 of 2)Notes (1)–(4)I/O StandardMeasurement Conditions Measurement PointV CCIO (V)V REF (V)Edge Rate (ns)V M E A S (V)Timing Model1The performance numbers in Table5–36 are extracted from theQuartus II software version 5.1 SP1.Table5–36.Stratix II Performance Notes(Part 1 of6)Note(1)ApplicationsResources Used PerformanceALUTsTriMatrixMemoryBlocksDSPBlocks-3SpeedGrade(2)-3SpeedGrade(3)-4SpeedGrade-5SpeedGradeUnitLE16-to-1multiplexer(4)2100654.87625.0523.83460.4MHz32-to-1 multiplexer (4)3800519.21473.26464.25384.17MHz16-bit counter1600566.57538.79489.23421.05MHz64-bit counter6400244.31232.07209.11181.38MHzT riMatrix Memory M512 block Simple dual-port RAM32 × 18 bit010500.00476.19434.02373.13MHz FIFO 32 x 18 bit 2210500.00476.19434.78373.13MHzT riMatrix Memory M4K block Simple dual-port RAM128 x 36 bit (8)010540.54515.46469.48401.60MHzT rue dual-port RAM128 × 18 bit (8)010540.54515.46469.48401.60MHzFIFO128 × 36 bit2210530.22499.00469.48401.60MHzSimple dual-port RAM128 × 36 bit (9)010475.28453.30413.22354.10MHzT rue dual-port RAM128 × 18 bit (9)010475.28453.30413.22354.10MHzStratix II Device Handbook, Volume 1DC & Switching CharacteristicsT riMatrix Memory M-RAM block Single portRAM 4K × 144 bit010349.65333.33303.95261.09MHzSimple dual-portRAM 4K × 144 bit010420.16400.00364.96313.47MHzT rue dual-portRAM 4K × 144 bit010349.65333.33303.95261.09MHzSingle portRAM 8K × 72 bit010354.60337.83307.69263.85MHzSimple dual-portRAM 8K × 72 bit010420.16400.00364.96313.47MHzT rue dual-portRAM 8K × 72 bit010349.65333.33303.95261.09MHzSingle portRAM 16K × 36 bit010364.96347.22317.46271.73MHzSimple dual-portRAM 16K × 36 bit010420.16400.00364.96313.47MHzT rue dual-portRAM 16K × 36 bit010359.71342.46313.47268.09MHzSingle portRAM 32K × 18 bit010364.96347.22317.46271.73MHzSimple dual-portRAM 32K × 18 bit010420.16400.0364.96313.47MHzT rue dual-portRAM 32K × 18 bit010359.71342.46313.47268.09MHzSingle portRAM 64K × 9 bit010364.96347.22317.46271.73MHzSimple dual-portRAM 64K × 9 bit010420.16400.0364.96313.47MHzT rue dual-portRAM 64K × 9 bit010359.71342.46313.47268.09MHzTable5–36.Stratix II Performance Notes(Part 2 of6)Note(1)ApplicationsResources Used PerformanceALUTsTriMatrixMemoryBlocksDSPBlocks-3SpeedGrade(2)-3SpeedGrade(3)-4SpeedGrade-5SpeedGradeUnitStratix II Device Handbook, Volume 1Timing ModelDSP block 9 × 9-bit multiplier(5) 001430.29409.16373.13320.10MHz 18 × 18-bitmultiplier(5)001410.17390.01356.12305.06MHz18 × 18-bitmultiplier(7)001450.04428.08391.23335.12MHz36 × 36-bitmultiplier(5)001250.00238.15217.48186.60MHz36 × 36-bit multiplier(6)001410.17390.01356.12305.06MHz18-bit, four-tap FIRfilter001410.17390.01356.12305.06MHzLarger designs 8-bit,16-tap parallelFIR filter5804259.06240.61217.15185.01MHz8-bit, 1024-point,streaming, threemultipliers and fiveadders FFT function2976229398.72364.03355.23306.37MHz8-bit, 1024-point,streaming, fourmultipliers and twoadders FFT function27812212398.56409.16347.22311.13MHz8-bit, 1024-point,single output, oneparallel FFT engine,burst, three multipliersand five adders FFTfunction98453425.17365.76346.98292.39MHz8-bit, 1024-point,single output, oneparallel FFT engine,burst, four multipliersand two adders FFTfunction91954427.53378.78357.14307.59MHzTable5–36.Stratix II Performance Notes(Part 3 of6)Note(1)ApplicationsResources Used PerformanceALUTsTriMatrixMemoryBlocksDSPBlocks-3SpeedGrade(2)-3SpeedGrade(3)-4SpeedGrade-5SpeedGradeUnitStratix II Device Handbook, Volume 1。

FPGA可编程逻辑器件芯片EP2S60F1020C5中文规格书

FPGA可编程逻辑器件芯片EP2S60F1020C5中文规格书

Table 1–2. Stratix II GX Package Options (Pin Counts and Transceiver Channels)
Device
Transceiver Channels
Source-Synchronous Channels
Receive (1) Transmit
31 31
42Biblioteka Source-synchronous
29
transmit channels
29 29
42
M512 RAM blocks
202
329
(32 × 18 bits)
M4K RAM blocks
144
255
(128 × 36 bits)
M-RAM blocks
1
2
(4K × 144 bits)
Two reference clocks, REFCLK0 and REFCLK1, are available per transceiver block. The inter-transceiver block bus allows multiple transceivers to use the same reference clocks. Each transceiver block has one outgoing reference clock which connects to one inter-transceiver block line. The incoming reference clock can be selected from five inter-transceiver block lines IQ[4..0] or from the global clock line that is driven by an input pin.

FPGA可编程逻辑器件芯片EP2AGX260FF35I6N中文规格书

FPGA可编程逻辑器件芯片EP2AGX260FF35I6N中文规格书

P ULSE-W IDTH M ODULATOR (PWM)F UNCTIONAL D ESCRIPTIONSwitching Dead Time (PWM_DT) RegisterThe second important parameter that must be set up in the initial configuration of the PWM Controller is the switching dead time. This is a short delay introduced between turning off one PWM signal (forexample, AH) and turning on the complementary signal (for example, AL). This short time delay permits the power switch being turned off (AH in this case) to completely recover its blocking capability before the complementary switch is turned on. This time delay prevents a potentially destructive short-circuit condi-tion from developing across the dc link capacitor of a typical voltage source inverter.The 10-bit, read/write PWM_DT register controls the dead time. This register controls the dead time inserted into the three pairs of PWM output signals. Dead time (T d) is related to the value in the PWM_DT register by: T d = PWM_DT × 2 × t SCLKTherefore, a PWM_DT value of 0x00A introduces a 200 ns delay (for a SCLK of 100 MHz) between turning off any PWM signal (for example, AH) and then turning on its complementary signal (for example, AL).The length of the dead time can therefore be programmed in increments of 2 × t SCLK (or 20 ns for an SCLK of 100 MHz). The PWM_DT register is a 10-bit register whose maximum value of 0x3FF (1023 decimal) corresponds to a maximum programmed dead time of:T d(max) = 1023 × 2 × t SCLK = 1023 × 2 × 10 × 10-9 = 20.5 μsfor an f SCLK rate of 100 MHz. The dead time can be programmed to be zero by writing 0 to the PWM_DT register.Duty Cycle with Dead-Time Control: Calculations for PULSEMODE 00The duty cycle registers are scaled such that a value of 0 represents a 50% PWM duty, cycle. The switching signals produced are also adjusted to incorporate the programmed dead time value in the PWM_DT register.The unit in this case produces active low signals so that a low level corresponds to a command to turn on the associated power device.A typical pair of PWM outputs, PWM_AH and PWM_AL, is shown in the following figure. The time values inthe figure indicate the integer value in the associated register and can be converted to time by multiplying by the fundamental time increment, t CK. In the example channel A is working off of PWMTMR0.Because PULSEMODE is set to 00, the switching patterns are perfectly symmetrical about the mid-point of the switching period. The dead time is incorporated by moving the switching instants of both PWM signals away from the instant set by the PWM_AH0 register. Both switching edges are moved by an equal amount (PWMDT × t CK) to preserve the symmetrical output patterns. Also shown is the PWM_SYNC_OUT pulse whose rising edge denotes the beginning of the switching period, and the PWM_STAT.TMR0PHASE bit.ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCEP ULSE -W IDTH M ODULATOR (PWM)E VENT C ONTROLADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCEeven in the event of a loss of the processor clock. In addition to the hardware shutdown features, the PWM system may be shutdown in software by means of the PWM_CTL.SWTRIP bit.Status information about the PWM is available to the user in the PWM_STAT register, which stores all status bits, including raw interrupt status bits. In particular, the period boundary of each timer is available, as well as status bits that indicate whether the operation is in the first half or the second half of the timer. Addi-tionally the TRIP status is also available.The PWM_IMSK and PWM_ILAT registers allow masking and show masked interrupt status bits respectively. The interrupt bits are latched and held on the interrupt event and the software must write a 1 to clear the interrupt bit, usually during the Interrupt Service routine.Trip Control UnitThe PWM Trip unit processes hardware or software fault conditions and shuts down the PWM channel outputs immediately on the occurrence of these conditions. This shut down mechanism can be enabled separately for each channel. The design also allows for a self-restart mechanism to be enabled on a channel. Self-restart re-enables the channel outputs following the fault condition (allowed only on hardware trips) when the PWMTMR-y that the channel is using reaches its period boundary.There are 2 external hardware sources that can indicate a hardware fault condition:1.PWMTRIP0 input pin2.PWMTRIP1 input pinThese are active low inputs where a falling edge on either of these pins indicates a fault condition.To enable the trip unit to shut down a particular channel's output in response to the fault event on either of these PWM_TRIPn pins, program the PWM_TRIPCFG.EN0A bit corresponding to that channel.The PWM_TRIPCFG.MODE0A bits must be programmed to specify the restart mechanism for a channel that has been tripped.1.If PWM_TRIPCFG.MODE0A = 0, once tripped, a trip condition is registered on this channel in the PWM_STAT.FLTTRIPA bit and the outputs of that channel are immediately shut down. This is called a FAULT TRIP condition. To resume channel output when a FAULT TRIP occurs, clear the PWM_STAT.FLTTRIPA bit by writing a 1 to it. Note that the bit cannot be cleared by a processor write if the trip condition is still active. The RAW trip status is available for both the pins in the PWM_STAT.RAWTRIP0register bits.2.If PWM_TRIPCFG.MODE0A = 1, once tripped, a trip condition is registered on this channel in the PWM_STAT.SRTRIPA bit and the outputs of that channel are immediately shut down. This is called a self-restart trip condition. At the next period boundary of the PWMTMR-y that the channel is using, if the tripping condition is not active, the design clears the status register bit and restores the outputs.The trip input pins should have an external pull-down resistor on the chip pin, so that if the pin becomes unconnected the PWM will be disabled.P ULSE-W IDTH M ODULATOR (PWM)F UNCTIONAL D ESCRIPTIONFigure 18-15:XOVR and DISHI/DISLO FunctionalityBrushless DC Motor (Electronically Commutated Motor) ControlIn the control of an electronically commutated motor (ECM), only two inverter legs are switched at any time. Often, the high-side device in one leg must be switched on at the same time as the low-side driver ina second leg. Therefore, by programming identical duty cycles values for two PWM channels (for example,PWM_CHA = PWM_CHB) and setting the PWM_BCTL.XOVR bit to crossover the BH/BL pair if PWM signals, it is possible to turn on the high-side switch of phase A and the low-side switch of phase B at the same time.To control ECM, normally the third inverter leg (phase C in this example) is disabled for a number of PWM cycles. To implement this function, both the PWM_CH and PWM_CL outputs are disabled by setting the PWM_CCTL.DISHI and PWM_CCTL.DISLO bits.In normal ECM operation, each inverter leg is disabled for certain time periods so that the PWM channel registers change based on the position of the rotor shaft (motor commutation).ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCE。

FPGA可编程逻辑器件芯片EPXA1F672C2ES中文规格书

FPGA可编程逻辑器件芯片EPXA1F672C2ES中文规格书

Figure 15-11: PKTE_CONT Register Diagram
Table 15-33: PKTE_CONT Register Fields
Bit No. (Access)
Bit Name
31:0 VALUE (RX/W)
Description/Enumeration
Continue Operating. The PKTE_CONT.VALUE bit field releases the packet engine from a halt state when written with any value in halt mode.
ADSP-BF70x PKTE Register Descriptions
PKTE Continue Register
A write to the PKTE_CONT register (with any value) releases the packet engine from a halt state when in halt mode.
ADSP-BF70x Blackfin+ Processor Hardware Reference
0 Do Not Clear Ownership Bits. The packet engine does not clear the ownership bits in the command descriptor when it completes an operation. The host application must clear the ownership bits in "old descriptors" before the packet engine is allowed to wrap around the CDR to re-encounter these "old descriptors". This setting has the advantage of eliminating a separate DMA write to the CDR.

FPGA可编程逻辑器件芯片EP2S90F1020C5中文规格书

FPGA可编程逻辑器件芯片EP2S90F1020C5中文规格书

The Stratix II clock networks can be disabled (powered down) by both static and dynamic approaches. When a clock net is powered down, all the logic fed by the clock net is in an off-state thereby reducing the overall power consumption of the device.The global and regional clock networks can be powered down statically through a setting in the configuration (.sof or .pof) file. Clock networks that are not used are automatically powered down through configuration bit settings in the configuration file generated by the Quartus II software. The dynamic clock enable/disable feature allows the internal logic to control power up/down synchronously on GCLK and RCLK nets and PLL_OUT pins. This function is independent of the PLL and is applied directly on the clock network or PLL_OUT pin, as shown in Figures2–37 through2–39.1The following restrictions for the input clock pins apply:•CLK0 pin -> inclk[0] of CLKCTRL•CLK1 pin -> inclk[1] of CLKCTRL•CLK2 pin -> inclk[0] of CLKCTRL•CLK3 pin -> inclk[1] of CLKCTRLIn general, even CLK numbers connect to the inclk[0] port ofCLKCTRL, and odd CLK numbers connect to the inclk[1] portof CLKCTRL.Failure to comply with these restrictions will result in a no-fiterror.Enhanced & Fast PLLsStratix II devices provide robust clock management and synthesis using up to four enhanced PLLs and eight fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clock-frequency synthesis. With features such as clock switchover,spread-spectrum clocking, reconfigurable bandwidth, phase control, and reconfigurable phase shifting, the Stratix II device’s enhanced PLLs provide you with complete control of clocks and system timing. The fast PLLs provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support. Enhanced and fast PLLs work together with the Stratix IIhigh-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth.Document Revision HistoryConfigurationf See the Configuring Stratix II & Stratix II GX Devices chapter in volume 2of the Stratix II Device Handbook or the Stratix II GX Device Handbook formore information about configuration schemes in Stratix II andStratix II GX devices.Device Security Using Configuration Bitstream EncryptionStratix II FPGAs are the industry’s first FPGAs with the ability to decrypta configuration bitstream using the Advanced Encryption Standard(AES) algorithm. When using the design security feature, a 128-bitsecurity key is stored in the Stratix II FPGA. To successfully configure aStratix II FPGA that has the design security feature enabled, it must beconfigured with a configuration file that was encrypted using the same128-bit security key. The security key can be stored in non-volatilememory inside the Stratix II device. This non-volatile memory does notrequire any external devices, such as a battery back-up, for storage.PPAMAX II device or microprocessor and flash device vJTAG Download cable (4)MAX II device or microprocessor andflash device Notes for Table 3–5:(1)In these modes, the host system must send a DCLK that is 4× the data rate.(2)The enhanced configuration device decompression feature is available, while the Stratix II decompression feature is not available.(3)Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported.(4)The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable,MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and theByteBlasterMV parallel port download cable.Table 3–5.Stratix II Configuration Features (Part 2 of 2)ConfigurationSchemeConfiguration Method Design Security Decompression Remote System UpgradeConfiguration & Testing 1An encryption configuration file is the same size as a non-encryption configuration file. When using a serial configurationscheme such as passive serial (PS) or active serial (AS),configuration time is the same whether or not the designsecurity feature is enabled. If the fast passive parallel (FPP)scheme us used with the design security or decompressionfeature, a 4× DCLK is required. This results in a slowerconfiguration time when compared to the configuration time ofan FPGA that has neither the design security, nordecompression feature enabled. For more information aboutthis feature, refer to AN 341: Using the Design Security Feature inStratix II Devices. Contact your local Altera sales representativeto request this document.Device Configuration Data DecompressionStratix II FPGAs support decompression of configuration data, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory, and transmit this compressed bit stream to Stratix II FPGAs. During configuration, the Stratix II FPGA decompresses the bit stream in real time and programs its SRAM cells.Stratix II FPGAs support decompression in the FPP (when using a MAX II device/microprocessor and flash memory), AS and PS configuration schemes. Decompression is not supported in the PPA configuration scheme nor in JTAG-based configuration.Remote System UpgradesShortened design cycles, evolving standards, and system deployments in remote locations are difficult challenges faced by modern system designers. Stratix II devices can help effectively deal with these challenges with their inherent re-programmability and dedicated circuitry to perform remote system updates. Remote system updates help deliver feature enhancements and bug fixes without costly recalls, reduce time to market, and extend product life.Stratix II FPGAs feature dedicated remote system upgrade circuitry to facilitate remote system updates. Soft logic (Nios® processor or user logic) implemented in the Stratix II device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides。

FPGA可编程逻辑器件芯片EP2S30F672C3N中文规格书

FPGA可编程逻辑器件芯片EP2S30F672C3N中文规格书

1.IntroductionThe Stratix® II GX family of devices is Altera’s third generation of FPGAsto combine high-speed serial transceivers with a scalable,high-performance logic array. Stratix II GX devices include 4 to 20high-speed transceiver channels, each incorporating clock and datarecovery unit (CRU) technology and embedded SERDES capability atdata rates of up to 6.375gigabits per second (Gbps). The transceivers aregrouped into four-channel transceiver blocks and are designed for lowpower consumption and small die size. The Stratix II GX FPGAtechnology is built upon the Stratix II architecture and offers a 1.2-V logicarray with unmatched performance, flexibility, and time-to-marketcapabilities. This scalable, high-performance architecture makesStratix II GX devices ideal for high-speed backplane interface,chip-to-chip, and communications protocol-bridging applications.Features This section lists the Stratix II GX device features.■Main device features:●TriMatrix memory consisting of three RAM block sizes toimplement true dual-port memory and first-in first-out (FIFO)buffers with performance up to 550 MHz●Up to 16 global clock networks with up to 32 regional clocknetworks per device region●High-speed DSP blocks provide dedicated implementation ofmultipliers (at up to 450 MHz), multiply-accumulate functions,and finite impulse response (FIR) filters●Up to four enhanced PLLs per device provide spread spectrum,programmable bandwidth, clock switch-over, real-time PLLreconfiguration, and advanced multiplication and phaseshifting●Support for numerous single-ended and differential I/Ostandards●High-speed source-synchronous differential I/O support on upto 71 channels●Support for source-synchronous bus standards, including SPI-4Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI,and CSIX-L1●Support for high-speed external memory, including quad datarate (QDR and QDRII) SRAM, double data rate (DDR andDDR2) SDRAM, and single data rate (SDR) SDRAMFeatures●Support for multiple intellectual property megafunctions fromAltera® MegaCore® functions and Altera Megafunction PartnersProgram (AMPP SM) megafunctions●Support for design security using configuration bitstreamencryption●Support for remote configuration updates■Transceiver block features:●High-speed serial transceiver channels with clock data recovery(CDR) provide 600-megabits per second (Mbps) to 6.375-Gbpsfull-duplex transceiver operation per channel●Devices available with 4, 8, 12, 16, or 20 high-speed serialtransceiver channels providing up to 255 Gbps of serialbandwidth (full duplex)●Dynamically programmable voltage output differential (V OD)and pre-emphasis settings for improved signal integrity●Support for CDR-based serial protocols, including PCI Express,Gigabit Ethernet, SDI, Altera’s SerialLite II, XAUI, CEI-6G,CPRI, Serial RapidIO, SONET/SDH●Dynamic reconfiguration of transceiver channels to switchbetween multiple protocols and data rates●Individual transmitter and receiver channel power-downcapability for reduced power consumption duringnon-operation●Adaptive equalization (AEQ) capability at the receiver tocompensate for changing link characteristics●Selectable on-chip termination resistors (100, 120, or 150 Ω) forimproved signal integrity on a variety of transmission media●Programmable transceiver-to-FPGA interface with support for8-, 10-, 16-, 20-, 32-, and 40-bit wide data transfer● 1.2- and 1.5-V pseudo current mode logic (PCML) for 600Mbpsto 6.375Gbps (AC coupling)●Receiver indicator for loss of signal (available only in PIPEmode)●Built-in self test (BIST)●Hot socketing for hot plug-in or hot swap and powersequencing support without the use of external devices●Rate matcher, byte-reordering, bit-reordering, pattern detector,and word aligner support programmable patterns●Dedicated circuitry that is compliant with PIPE, XAUI, andGIGE●Built-in byte ordering so that a frame or packet always starts ina known byte lane●Transmitters with two PLL inputs for each transceiver blockwith independent clock dividers to provide varying clock rateson each of its transmittersTransceiversasserted. All 8B/10B control signals, such as disparity error or controldetect, are pipelined with the data in the Stratix II GX receiver block andare edge aligned with the data.Figure2–23 shows how the 20-bit code is decoded to the 16-bit data +2-bit control indicator.Figure2–23.20-Bit to 16-Bit Decoding ProcessThere are two optional error status ports available in the 8B/10B decoder,rx_errdetect and rx_disperr. These status signals are aligned withthe code group in which the error occurred.Receiver State MachineThe receiver state machine operates in Basic, GIGE, PCI Express, andXAUI modes. In GIGE mode, the receiver state machine replaces invalidcode groups with K30.7. In XAUI mode, the receiver state machinetranslates the XAUI PCS code group to the XAUI XGMII code group.Byte DeserializerThe byte deserializer widens the transceiver data path before the FPGAinterface. This reduces the rate at which the received data needs to beclocked at in the FPGA logic. The byte deserializer block is available inboth single- and double-width modes.The byte deserializer converts the one- or two-byte interface into atwo-or four-byte-wide data path from the transceiver to the FPGA logic(see Table2–9). The FPGA interface has a limit of 250 MHz, so the bytedeserializer is needed to widen the bus width at the FPGA interface and。

相关主题
  1. 1、下载文档前请自行甄别文档内容的完整性,平台不提供额外的编辑、内容补充、找答案等附加服务。
  2. 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
  3. 3、如文档侵犯您的权益,请联系客服反馈,我们会尽快为您处理(人工客服工作时间:9:00-18:30)。

you need to support configuration input voltages of 1.8 V/1.5 V, youshould set the VCCSEL to a logic high and the V CCIO of the bank thatcontains the configuration inputs to 1.8 V/1.5 V.f For more information on multi-volt support, including information onusing TDO and nCEO in multi-volt systems, refer to the Stratix IIArchitecture chapter in volume 1 of the Stratix II Device Handbook.Configuration SchemesYou can load the configuration data for a Stratix II device with one of fiveconfiguration schemes (see Table3–5), chosen on the basis of the targetapplication. You can use a configuration device, intelligent controller, orthe JTAG port to configure a Stratix II device. A configuration device canautomatically configure a Stratix II device at system power-up.You can configure multiple Stratix II devices in any of the fiveconfiguration schemes by connecting the configuration enable (nCE) andconfiguration enable output (nCEO) pins on each device.Stratix II FPGAs offer the following:■Configuration data decompression to reduce configuration filestorage■Design security using configuration data encryption to protect yourdesigns■Remote system upgrades for remotely updating your Stratix IIdesignsTable3–5summarizes which configuration features can be used in eachconfiguration scheme.Table3–5.Stratix II Configuration Features(Part 1 of2)Configuration Scheme Configuration Method Design Security DecompressionRemote SystemUpgradeFPP MAX II device or microprocessor andflash devicev(1)v(1)v Enhanced configuration device v(2)v AS Serial configuration device v v v(3) PS MAX II device or microprocessor andflash devicev v v Enhanced configuration device v v vDownload cable (4)v vConfiguration PPAMAX II device or microprocessor and flash device vJTAG Download cable (4)MAX II device or microprocessor andflash device Notes for Table 3–5:(1)In these modes, the host system must send a DCLK that is 4× the data rate.(2)The enhanced configuration device decompression feature is available, while the Stratix II decompression feature is not available.(3)Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported.(4)The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable,MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and theByteBlasterMV parallel port download cable.Table 3–5.Stratix II Configuration Features (Part 2 of 2)ConfigurationSchemeConfiguration Method Design Security Decompression Remote System UpgradeConfiguration & Testing 1An encryption configuration file is the same size as a non-encryption configuration file. When using a serial configurationscheme such as passive serial (PS) or active serial (AS),configuration time is the same whether or not the designsecurity feature is enabled. If the fast passive parallel (FPP)scheme us used with the design security or decompressionfeature, a 4× DCLK is required. This results in a slowerconfiguration time when compared to the configuration time ofan FPGA that has neither the design security, nordecompression feature enabled. For more information aboutthis feature, refer to AN 341: Using the Design Security Feature inStratix II Devices. Contact your local Altera sales representativeto request this document.Device Configuration Data DecompressionStratix II FPGAs support decompression of configuration data, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory, and transmit this compressed bit stream to Stratix II FPGAs. During configuration, the Stratix II FPGA decompresses the bit stream in real time and programs its SRAM cells.Stratix II FPGAs support decompression in the FPP (when using a MAX II device/microprocessor and flash memory), AS and PS configuration schemes. Decompression is not supported in the PPA configuration scheme nor in JTAG-based configuration.Remote System UpgradesShortened design cycles, evolving standards, and system deployments in remote locations are difficult challenges faced by modern system designers. Stratix II devices can help effectively deal with these challenges with their inherent re-programmability and dedicated circuitry to perform remote system updates. Remote system updates help deliver feature enhancements and bug fixes without costly recalls, reduce time to market, and extend product life.Stratix II FPGAs feature dedicated remote system upgrade circuitry to facilitate remote system updates. Soft logic (Nios® processor or user logic) implemented in the Stratix II device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and providesConfigurationf error status information. This dedicated remote system upgrade circuitry avoids system downtime and is the critical component for successful remote system upgrades.RSC is supported in the following Stratix II configuration schemes: FPP, AS, PS, and PPA. RSC can also be implemented in conjunction with advanced Stratix II features such as real-time decompression of configuration data and design security using AES for secure and efficient field upgrades.See the Remote System Upgrades With Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook for more information about remote configuration in StratixII devices.Configuration & Testing。

相关文档
最新文档