2003ESSCRIC_Lee

Phase Frequency Detectors for Fast Frequency Acquisition in Zero-dead-zone CPPLLs for Mobile Communication Systems Kun-Seok Lee*, Byeong-Ha Park, Han-il Lee, and Min Jong YohRF P/J, SYSTEM-LSI DIVISION, SAMSUNG ELECTRONICS, YONGIN, KYOUNGGI-DO, 449-711, KOREA* leeks01@samsung.co.krABSTRACTThis paper introduces a new-type phase-frequency-detector(PFD) for charge-pump phase-looked-loops(CPPLLs). As the PFD is configured to separate the reset part and the delay part independently, the input signal edge data, which arrive during an added delay to remove dead-zone, are not lost and do not output the wrong information, resulting in faster locking property. The experimental results of the proposed PFD show the reduced frequency acquisition time by about 30% compared with the conventional PFD in the case of 70MHz voltage-controlled-oscillator(VCO) frequency hopping for PCS mobile applications. The PFD is designed and simulated by SPECTRE and the prototype, together with a frequency synthesizer, has been fabricated in a 0.5um BiCMOS technology.I. I NTRODUCTIONPLLs are widely used in microprocessors and digital signal processors for clock generation circuits, and as a reference signal for wireless communication systems[1]. In all of these applications, this work concentrates on the PFD used in the CPPLLs for personal mobile communication systems. The PFD, one of the critical building blocks, monitors the input reference signal and the divided VCO output signal, and produces an output signal proportional to the phase and frequency difference between them[3]. There are several design issues related to the PFD, such as faster operating frequency, dead-zone problems, and locking time of the PLLs. The PFD used in the CPPLLs for personal mobile communication systems has following characteristics.1.Even though the output frequency of the VCO is 900MHz ~2.1GHz, the operating frequency of the PFD is just 10MHz ~ 20MHz with a large frequency multiplication. The proportion of the reset time to the period of the reference signal is less than 1%, and the PFD reset time is not a bottleneck, determining the maximum operating frequency, as is in the case with the high speed PFD[1][2].2.As the dead-zone phenomenon seriously degrades the phase noise property, which is one of the key specifications in PLLs, it is very important to remove the dead-zone. Adding an additional delay is enough to resolve the dead-zone problem but the loading charge to activate the charge-pump switches is considerable. Therefore, the proportion of the added delay time to the period of the reference signal is 5%~10% or so.The fast locking time, along with the fine channel spacing, causes a fractional-N PLL to be a popular architecture, but the demands for faster locking time are still increasing. As the settling time is almost constant and the acquisition time is in proportion to the frequency hopping range, it is essential to minimize the acquisition time for faster locking in case the frequency hops from the first channel to the last channel at the worst case[3]. We describe a faster frequency acquisition PFD, which is configured to separate the reset part and the delay part independently and corrects the clock transition overrides occurring during an added delay to prevent the dead-zone in conventional PFD. The PFD doesn’t generate wrong information and reduces the acquisition time drastically without fast locking skill.This paper is organized as follows. In Section II, we describe the conventional PFD architecture and its incorrect output generations. The proposed PFD is introduced in Section III. In Section IV, we report simulation and measurement results base on the posed PFD compared with the conventional PFD. A brief summary of this paper is included in Section V.LoopFilter C K RC K VFig. 1. Conventional PFD and charge-pump.II. C ONVENTIONAL PFD C IRCUITSA schematic circuit diagram of a conventional PFD and a charge-pump is shown in Fig. 1. The PFD circuit includes two D-type flip-flops, a delay element, and an AND gate. The D inputs of the flip-flops are tied to logic high. One flip-flop is clocked by a reference clock CKREF and the other is clocked by a voltage-controlled-oscillator clock CKVCO, divided down from the VCO output signal. The outputs of the flip-flops, UP and DN, are ANDed, and the results are delayed in the delay element, then used to reset both flip-flops. The UP and DN signals are simultaneously logic high for durationgiven by the delay element. The UP and DN signals are reset to logic low by a reset signal RST . The delay element whose duration is τ seconds is used to prevent dead zone. The charge-pump provides a positive or negative currents to the low pass filter(LPF) to correct an instantaneous phase and frequency mismatch between two input clock signals. If the phase of the CKREF leads the phase of the CKVCO , net charge is added to the output, and if the phase of the CKREF lags the phase of the CKVCO , net charge is subtracted from theoutput[1][3].CKREF CKVCO UP DNRST(a)CKREF CKVCOUP DNRST (b)Fig. 2. (a) Incorrect output generation due to delay. (b) Incorrect output generation due to the resetsignal RST . Fig. 2 is a timing diagram illustrating operation of the PFD circuit of Fig. 1. The circuit operates as follows.Initially, the flip-flops are in the reset condition, and the UP and DN signals are logic low. A first leading rising-edge of the CKREF causes the UP signal to go logic high and this state is held until the rising-edge of the CKVCO arrives. When the both the UP and DN signals are logic high, the output of the AND gate is activated.However, the activated output of the AND gate is delayed by τ seconds, maintaining the UP and DN signals logic high. If the next leading rising-edge of the CKREF arrives within this duration τ(Fig. 2(a)), the new rising-edge of the CKREF has no effect on the UP signal resulting in a missing edge, because the UP signal already has been activated. After the duration τ, both the UP and DN signals are reset. If the next leading rising-edge of the CKREF arrives when the RST signal is logic high(Fig. 2(b)), the new rising-edge is also not reflected in the UP signal because the reset overrides the new rising-edge. In both cases, the subsequent rising-edge of the CKVCO causes the DN signal to lead the UP signal.The effect appears as a negative output increasing thephase and frequency difference between the CKREF and the CKVCO for phase differences higher than 2π – 2∆,where ∆ = 2π·τ / T CKREF , which depends on the added delay τ and the reference clock period TCKREF [1]. These kinds of malfunctions seriously degrade the locking property in PLLs. For instance, if the PFD frequency is 20MHz and a 5 nano-seconds delay is used, the on time fraction of the charge-pump in the range of incorrect behavior is 20%. The frequency acquisition slows by how often the wrong information occurs, which depends on the ratio of the delay time to the reference clock period. Recently, as the tendency is toward increasing the PFD operating frequency of the fractional-N frequency synthesizers, the error occurring range is on the increase.(a) (b)Fig. 3. (a) Characteristic of the ideal PFD. (b) Characteristic of the nonideal PFD.Fig. 3 shows the ideal and real characteristic of the conventional PFD. The ideal PFD's characteristic is linear for the entire range of input phase differences (Fig.3(a)). In real PFD, on the other hands, there is an offset around the zero phase difference, and a gain inversion region takes place for phase differences higher than 2π –2∆ (Fig. 3(b)). In this gain inversion region, the PFD outputs the wrong control signals increasing the phase and frequency differences between the inputs, and the lock time takes a sudden turn for the worse.III. P ROPOSED PFD C IRCUITSThe proposed PFD consists of four main parts; flip-flop part, reset part, delay part, and output part(Fig. 4).The flip-flop part is the same as in the case with conventional PFD. In the reset part, a NOR gate combines the inverted flip-flop output signals Q1B and Q2B to produce a reset signal RST , activating the delay part. As there is no delay element in feedback path, if we ignore the reset time of the flip-flop, the both UP and DN signals are not allowed to be logic high simultaneously. The delay part includes a delay element operating to delay the RST signal by a predetermined amount τ seconds to remove dead-zone, an inverter M1producing a reset information signal RIS , another inverter M2 inverting the RIS signal after τ seconds from the point of time activating the RST signal, and a back-to-back latch maintaining the RIS signal logic low for τseconds. The output part consists of two two-input NAND gates. Each NAND gate receives the invertedsignal from the flip-flop and the RIS signal, and logically combines to form the UP or DN signal. The UP and DN signals are selectively chosen depending on the RIS signal. While the RIS signal is logic low, the UP and DN signals are unconditionally logic high, otherwise follow the outputs of the flip-flops.CKREF CKVCOUP DNRISQ1Q2RST high rangehigh rangeFig. 5. Error correction effect of the proposed PFD.Fig. 5 is a timing diagram illustrating operation of the proposed PFD circuit of Fig. 4. When both Q1 and Q2signals are logic high, the two flip-flops are reset simultaneously with zero delay, and the pulse widths of the Q2 and RST signals, negatively activating the RIS signal, are very narrow and equal to the reset time of the PFD. The RIS signal with a low logic level cause the UP and DN signals to go logic high, which remain until the RIS signal return to logic high by M2. During this unconditionally high range, initialized flip-flips can accept the new incoming rising-edge data. As can be seen in Fig. 5, the second leading rising-edge of the CKREF is reflected in the Q1 signal and propagates to the UP signal. At the end of this range, the DN signal becomes logic low, and the UP signal remains logic high because the Q1 signal is logic high. In this manner, asthe new PFD is configured to separate the reset part and the delay part independently, the PFD no longer loses the rising-edge data of the inputs, which arrives during an added delay to remove dead-zone, and does not output the wrong information. The rising-edgeoverriding phenomenon(Fig. 2(b)) due to RST signal in the conventional PFD also has been disappeared because of the reduced active range of the RST signal. Since the corrected edge information propagates to PFD output at the end of the unconditionally high range, there would be a flat region in the characteristic, of which value is 2πbecause the leading input signal does not return to logic low, for phase differences grater than 2π – ∆.Fig. 6. Characteristic of the proposed PFD.Fig. 6 shows the characteristic of the proposed PFD.There is no gain inversion region for the entire range of input phase differences, and the flat region for the phase differences higher than 2π – ∆ is observed.IV. S IMULATION AND M EASUREMENT R ESULTSFig. 7 shows simulated characteristics of the conventional and the proposed PFDs. If we compare these results with those of the Fig. 3 and Fig. 6, the results are about the same. The gain inversion region in Fig. 7(a) and the flat gain region in Fig. 7(b) are observed as is expected. Fig. 8 illustrates the charge variation in the charge-pump output during the frequency acquisition. The output node of the charge pump is coupled to a capacitor instead of low pass filter(LPF). The upper line indicating the output voltage of the proposed PFD shows faster locking property.Charge reduction ranges shown in lower line are due to the gain inversion region. Simulated frequency acquisition time is depicted in Fig. 9. The output of the charge pump is coupled to the LPF, and a 40-kHz bandwidth PLL loop, 40-MHz PFD comparison frequency, 2GHz VCO frequency, and 14.5MHz VCO frequency hopping were used. The frequency acquisitionC K R CK V C Loop FilterFig. 4. Proposed PFD and charge-pump.time of the upper line has been reduced by more than 50% compared with the lower line. To verify the performance of the proposed PFD, a FNPLL[4] with both the proposed PFD and the conventional PFD has been implemented in a 0.5-µm BiCMOS technology. The microphotograph is shown in Fig. 10. Fig. 11 shows the measurement results of the proposed and the conventional PFDs. To demonstrate the performance of the new PFD, a 15-kHz bandwidth PLL loop, 19.2-MHz PFD comparison frequency, 2.1GHz VCO frequency,and 70MHz VCO frequency hopping were used.Measured locking time was 520-µs in new PFD and 730-µs in conventional PFD respectively. The slop of the proposed PFD is more sharply rising, implying faster locking time. The results show that the frequency acquisition time of the new PFD has been reduced by about 30% compared with the conventional PFD.V. C ONCLUSIONIn this paper, we demonstrated the incorrect output generation in the conventional PFD due to the delay element in the feedback path and introduced a new-type PFD, which corrected the wrong information and reduced the locking time. The PFD consists of the reset part generating reset signal and the delay part providing an additional delay to remove dead-zone problem independently. The simulation results from the proposed PFD design and the measurement results from prototype fabrication were presented.R EFERENCES[1] M. Mansuri, D. Liu, and C. K. Yang, "Fast Frequency Acquisition Phase-Frequency Detectors for Gsamples/s Phase-Locked Loops", IEEE Journal of Solid-State Circuits , vol. 37, pp. 1331-4, Oct. 2002.[2] S. Joen, T. Cheung, and W. Choi, "Phase/frequency detector for high-speed PLL applications", IEEE Electronics Letters , vol. 34, pp. 2120-1, Oct. 1998.[3] B. Razavi, ed., Monolithic Phase-Locked Loops and Clock Recover Circuits, NJ: IEEE Press, 1996.[4] K. Lee, J. Lee, M. J. Yoh, and B. Park, "A Fractional-N Frequency Synthesizer with a 3-bit 4th order Σ-∆ Modulator", IEEE ESSCIRC Digest, 2002,pp. 803- 806.(a) (b)Fig. 7. Simulated characteristics ofthe conventional (a) and the proposed PFDs (b).Fig. 8. Charge variation in the charge-pump outputduring the frequency acquisition.Fig. 9. Simulated frequency acquisition.Fig. 10. Chip photograph of the proposed andconventional PFDs.Fig. 11. Measured locking time.。