AD8131ARZ-REEL7中文资料
MEMORY存储芯片ADM3202ARUZ-REEL7中文规格书
READ OperationREAD bursts are initiated with a READ command. The starting column and bank ad-dresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled,the row will be left open after the completion of the burst.During READ bursts, the valid data-out element from the starting column address is available READ latency (RL) clocks later. RL is defined as the sum of posted CAS additive latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programma-ble in the mode register via the MRS command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (that is, at the next crossing of CK and CK#). Figure 69 shows an example of RL based on a CL setting of 8 and an AL setting of 0.Figure 69: READ LatencyCKCK#CommandAddressDQDQS, DQS#Don’t CareTransitioning Data Indicates break in time scaleNotes:1.DO n = data-out from column n .2.Subsequent elements of data-out appear in the programmed order following DO n .DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state on DQS and HIGH state on DQS# is known as the READ preamble (t RPRE). The LOW state on DQS and the HIGH state on DQS#, coincident with the last data-out element, isknown as the READ postamble (t RPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ goes High-Z. A detailed explanation of t DQSQ (valid data-out skew), t QH (data-out window hold), and the valid data window are de-picted in Figure 80 (page 171). A detailed explanation of t DQSCK (DQS transition skew to CK) is also depicted in Figure 80 (page 171).Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued t CCD cycles after the first READ command. This is shown for BL8 in Figure 70(page 165). If BC4 is enabled, t CCD must still be met, which will cause a gap in the data output, as shown in Figure 71 (page 165). Nonconsecutive READ data is reflected in Figure 72 (page 166). DDR3 SDRAM does not allow interrupting or truncating any READ burst.Figure 100: Precharge Power-Down (Slow-Exit Mode) Entry and ExitCKCK#CommandCKEEnter power-downmode Exit power-downmodeDon’t CareIndicates break in time scaleNotes:1.Any valid command not requiring a locked DLL.2.Any valid command requiring a locked DLL.Figure 101: Power-Down Entry After READ or READ with Auto Precharge (RDAP)Don’t CareTransitioning Data CKCK#Command DQ BL8DQ BC4DQS, DQS#Address CKEPower-down or self refresh entryIndicates break in time scaleFigure 102: Power-Down Entry After WRITECKCK#Command DQ BL8DQ BC4DQS, DQS#AddressCKEself refresh entry1Don’t CareTransitioning Data Indicates break in time scaleNote:1.CKE can go LOW 2t CK earlier if BC4MRS.Figure 103: Power-Down Entry After WRITE with Auto Precharge (WRAP)Don’t CareTransitioning Data CKCK#CommandDQ BL8DQ BC4DQS, DQS#Address A10CKEPower-down or self refresh entry 2Start internal precharge Indicates break in time scaleNotes:1.t WR is programmed through MR0[11:9] and represents t WRmin (ns)/t CK rounded up tothe next integer t CK.2.CKE can go LOW 2t CK earlier if BC4MRS.Figure 104: REFRESH to Power-Down EntryCKCK#CommandCKET0T1T2T3Ta0Ta1Ta2Tb0Don’t CareIndicates break in time scaleNote:1.After CKE goes HIGH during t RFC, CKE must remain HIGH until t RFC is satisfied.Figure 105: ACTIVATE to Power-Down EntryCKCK#Command Address CKET0T1T2T3T4T5T6T7Figure 108: Power-Down Exit to Refresh to Power-Down EntryCKCK#CKET0T1T2T3T4Ta0Ta1Tb0Command。
FPGA可编程逻辑器件芯片AD8130ARZ-REEL7中文规格书
MAXIMUM POWER DISSIPATION (W)
02464-005
AD8129/AD8130
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. The power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations.
+VS PD
3
1
VIN
7
8
6
4 2
5
VOUT
RG
RF
–VS VOUT = VIN [1+(RF/RG)]
Figure 3. Typical Connection Configuration
ABSOLUTE MAXIMUM RATINGS
Table 4. Parameter Supply Voltage Power Dissipation Input Voltage (Any Input) Differential Input Voltage (AD8129)
FPGA可编程逻辑器件芯片AD8628ARZ-REEL7中文规格书
M ax UnitTypConditions M in Parameter SymbolINPUT CHARACTERISTICSOffset Voltage V OS1 5 μV−40°C ≤ T A ≤ +125°C 10 μVInput Bias Current I BAD8628/AD862930 100 pA AD8630 100 300 pA−40°C ≤ T A ≤ +125°C 1.5 nAInput Offset Current I OS50 200 pA−40°C ≤ T A ≤ +125°C 250 pAInput Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 5 V 120 140 dB−40°C ≤ T A ≤ +125°C 115 130 dBLarge Signal Voltage Gain A VO R L = 10 kΩ, V O = 0.3 V to 4.7 V 125 145 dB−40°C ≤ T A ≤ +125°C 120 135 dBOffset Voltage Drift ∆V OS/∆T −40°C ≤ T A ≤ +125°C 0.002 0.02 μV/°C OUTPUT CHARACTERISTICSOutput Voltage High V OH R L = 100 kΩ to ground 4.99 4.996 V−40°C ≤ T A ≤ +125°C 4.99 4.995 VR L = 10 kΩ to ground 4.95 4.98 V−40°C ≤ T A ≤ +125°C 4.95 4.97 VOutput Voltage Low V OL R L = 100 kΩ to V+ 1 5 mV−40°C ≤ T A ≤ +125°C2 5 mVR L = 10 kΩ to V+ 10 20 mV−40°C ≤ T A ≤ +125°C15 20 mV Short-Circuit Limit I SC±25 ±50 mA−40°C ≤ T A ≤ +125°C±40 mAOutput Current I O±30 mA−40°C ≤ T A ≤ +125°C±15 mAPOWER SUPPLYPower Supply Rejection Ratio PSRR V S = 2.7 V to 5.5 V, −40°C ≤ T A ≤ +125°C 115 130 dBSupply Current per Amplifier I SY V O = V S/2 0.85 1.1 mA−40°C ≤ T A ≤ +125°C 1.0 1.2 mA INPUT CAPACITANCE C INDifferential 1.5 pFCommon Mode 8.0 pFDYNAMIC PERFORMANCESlew Rate SR R L = 10 kΩ 1.0 V/μsOverload Recovery Time 0.05 msGain Bandwidth Product GBP 2.5 MHzNOISE PERFORMANCEVoltage Noise e n p-p 0.1 Hz to 10 Hz 0.5 μV p-p0.1 Hz to 1.0 Hz 0.16 μV p-pVoltage Noise Density e n f = 1 kHz 22 nV/√Hz Current Noise Density i n f = 10 Hz 5 fA/√HzTYPICAL PERFORMANCE CHARACTERISTICSINPUT OFFSET VOLTAGE (µV)N U M B E R O F A M P L I F I E R S180160140120*********20002735-003Figure 5. Input Offset Voltage DistributionINPUT COMMON-MODE VOLTAGE (V)I N P U T B I A S C U R R E N T (p A )604050301020002735-004Figure 6. AD8628 Input Bias Current vs. Input Common-Mode VoltageINPUT COMMON-MODE VOLTAGE (V)I N P U T B I A S C U R R E N T (p A )150050010000–1000–500–150002735-005Figure 7. AD8628Input Bias Current vs. Input Common-Mode Voltage INPUT OFFSET VOLTAGE (µV)N U M B E R O F A M P L I F I E R S100809060704050102030002735-006Figure 8. Input Offset Voltage DistributionTCVOS (nV/°C)N U M B E R O F A M P L I F I E R S765432102735-007Figure 9. Input Offset Voltage DriftLOAD CURRENT (mA)O U T P U T V O L T A G E (m V )1k1001010.10.0102735-008Figure 10. Output Voltage to Supply Rail vs. Load CurrentFUNCTIONAL DESCRIPTIONThe AD8628/AD8629/AD8630 are single-supply, ultrahigh precision rail-to-rail input and output operational amplifiers. The typical offset voltage of less than 1 μV allows these amplifiers to be easily configured for high gains without risk of excessive output voltage errors. The extremely small temperature driftof 2 nV/°C ensures a minimum offset voltage error over their entire temperature range of −40°C to +125°C, making these amplifiers ideal for a variety of sensitive measurement applica-tions in harsh operating environments.The AD8628/AD8629/AD8630 achieve a high degree of precision through a patented combination of auto-zeroing and chopping. This unique topology allows the AD8628/AD8629/AD8630 to maintain their low offset voltage over a wide temperature range and over their operating lifetime. The AD8628/AD8629/AD8630 also optimize the noise and bandwidth over previous generations of auto-zero amplifiers, offering the lowest voltage noise of any auto-zero amplifier by more than 50%.Previous designs used either auto-zeroing or chopping to add precision to the specifications of an amplifier. Auto-zeroing results in low noise energy at the auto-zeroing frequency, at the expense of higher low frequency noise due to aliasing of wideband noise into the auto-zeroed frequency band. Chopping results in lower low frequency noise at the expense of larger noise energy at the chopping frequency. The AD8628/AD8629/AD8630 family uses both auto-zeroing and chopping in a patented ping-pong arrangement to obtain lower low frequency noise together with lower energy at the chopping and auto-zeroing frequencies, maximizing the signal-to-noise ratio for the majority of applications without the need for additional filtering. The relatively high clock frequency of 15 kHz simplifies filter requirements for a wide, useful noise-free bandwidth.The AD8628 is among the few auto-zero amplifiers offered in the 5-lead TSOT package. This provides a significant improvement over the ac parameters of the previous auto-zero amplifiers. The AD8628/AD8629/AD8630 have low noise over a relatively wide bandwidth (0 Hz to 10 kHz) and can be used where the highest dc precision is required. In systems with signal bandwidths of from 5 kHz to 10 kHz, the AD8628/AD8629/AD8630 provide true 16-bit accuracy, making them the best choice for very high resolution systems. 1/f NOISE1/f noise, also known as pink noise, is a major contributor to errors in dc-coupled measurements. This 1/f noise error term can be in the range of several μV or more, and, when amplified with the closed-loop gain of the circuit, can show up as a large output offset. For example, when an amplifier with a 5 μV p-p 1/f noise is configured for a gain of 1000, its output has 5 mV of error due to the 1/f noise. However, the AD8628/AD8629/AD8630 eliminate 1/f noise internally, thereby greatly reducing output errors.The internal elimination of 1/f noise is accomplished as follows. 1/f noise appears as a slowly varying offset to theAD8628/AD8629/ AD8630 inputs. Auto-zeroing corrects any dc or low frequency offset. Therefore, the 1/f noise component is essentially removed, leaving the AD8628/AD8629/AD8630 free of 1/f noise.One advantage that the AD8628/AD8629/AD8630 bring to system applications over competitive auto-zero amplifiers is their very low noise. The comparison shown in Figure 49 indicates an input-referred noise density of 19.4 nV/√Hz at 1 kHz for the AD8628, which is much better than the Competitor Aand Competitor B. The noise is flat from dc to 1.5 kHz, slowly increasing up to 20 kHz. The lower noise at low frequency is desirable where auto-zero amplifiers are widely used.2735-46FREQUENCY (kHz)VOLTAGENOISEDENSITY(nV/√Hz)120105907560453015Figure 49. Noise Spectral Density of AD8628 vs. CompetitionAD8628/AD8629/AD8630Data SheetPEAK-TO-PEAK NOISEBecause of the ping-pong action between auto-zeroing and chopping, the peak-to-peak noise of the AD8628/AD8629/ AD8630 is much lower than the competition. Figure 50 and Figure 51 show this comparison.TIME (1s/DIV)V O L T A G E (0.5µV /D I V )02735-047Figure 50. AD8628 Peak-to-Peak NoiseTIME (1s/DIV)V O L T A G E (0.5µV /D I V )02735-048Figure 51. Competitor A Peak-to-Peak NoiseNOISE BEHAVIOR WITH FIRST-ORDER, LOW-PASS FILTERThe AD8628 was simulated as a low-pass filter (see Figure 53) and then configured as shown in Figure 52. The behavior of the AD8628 matches the simulated data. It was verified that noise is rolled off by first-order filtering. Figure 53 and Figure 54 show the difference between the simulated and actual transferfunctions of the circuit shown in Figure 52.IN02735-049Figure 52. First-Order Low-Pass Filter Test Circuit,×101 Gain and 3 kHz Corner FrequencyFREQUENCY (kHz)N O I S E (d B )5045403530251510520030601009080705040201002735-050Figure 53. Simulation Transfer Function of the Test Circuit in Figure 52FREQUENCY (kHz)N O I S E (d B )5045403530251510520030601009080705040201002735-051Figure 54. Actual Transfer Function of the Test Circuit in Figure 52The measured noise spectrum of the test circuit charted in Figure 54 shows that noise between 5 kHz and 45 kHz is successfully rolled off by the first-order filter.TOTAL INTEGRATED INPUT-REFERRED NOISE FOR FIRST-ORDER FILTERFor a first-order filter, the total integrated noise from the AD8628 is lower than the noise of Competitor A.3dB FILTER BANDWIDTH (Hz)RM S N O I S E (µV )1010.102735-052Figure 55. RMS Noise vs. 3 dB Filter Bandwidth in HzData Sheet AD8628/AD8629/AD8630。
FPGA可编程逻辑器件芯片AD8608ARZ-REEL7中文规格书
Known Good Die AD8608-KGDFEATURESLow offset voltage: 65 µV maximumLow input bias currents: 1 pA maximumLow noise: 8 nV/√HzWide bandwidth: 10 MHzHigh open-loop gain: 1000 V/mVUnity gain stableSingle-supply operation: 2.7 V to 5.5 VKnown good die (KGD): these die are fully guaranteed to data sheet specificationsAPPLICATIONSPhotodiode amplificationBattery-powered instrumentationMultipole filtersSensorsBarcode scannersAudio GENERAL DESCRIPTIONThe AD8608-KGD1 is a single, rail-to-rail input and output, single-supply amplifier that features very low offset voltage, low input voltage and current noise, and wide signal bandwidth. The AD8608-KGD uses the Analog Devices, Inc. patented DigiTrim® trimming technique, which achieves superior precision without laser trimming.The combination of low offsets, low noise, very low input bias currents, and high speed makes this amplifier useful in a wide variety of applications. Filters, integrators, photodiode amplifiers, and high impedance sensors all benefit from the combination of performance features. Audio and other ac applications benefit from the wide bandwidth and low distortion. Applications for this amplifier include optical control loops, portable and loop-powered instrumentation, and audio amplification for portable devices.The AD8608-KGD is specified over the extended industrial temperature range (−40°C to +125°C).Additional application and technical information can be found in the AD8605/AD8606/AD8608 data sheet.2.7 V ELECTRICAL SPECIFICATIONSV S = 2.7 V, V CM = V S/2, T A = 25°C, unless otherwise noted.Table 2.Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICSOffset Voltage V OS V S = 3.5 V, V CM = 2.7 V 20 75V S = 2.7 V, V CM = 0 V to 2.7 V 80 300 µV−40°C < T A < +125°C 750 µV Input Bias Current I B0.2 1 pA−40°C < T A < +125°C 300 pA Input Offset Current I OS0.1 0.5 pA−40°C < T A < +125°C 75 pA Input Voltage Range 0 2.7 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 2.7 V 80 95 dB−40°C < T A < +125°C 70 85 dB Large Signal Voltage Gain A VO R L = 2 kΩ, V O = 0.5 V to 2.2 V 110 350 V/mV Offset Voltage Drift ΔV OS/ΔT −40°C < T A < +125°C 1.5 6.0 µV/°C INPUT CAPACITANCECommon-Mode Input Capacitance C COM8.8 pF Differential Input Capacitance C DIFF 2.6 pF OUTPUT CHARACTERISTICSOutput Voltage High V OH I L = 1 mA 2.6 2.66 V−40°C < T A < +125°C 2.6 V Output Voltage Low V OL I L = 1 mA 25 40 mV−40°C < T A < +125°C 50 mV Output Current I OUT±30 mA Closed-Loop Output Impedance Z OUT f = 1 MHz, A V = 1 1.2 Ω POWER SUPPLYPower Supply Rejection Ratio PSRR V S = 2.7 V to 5.5 V 77 92 dB−40°C < T A < +125°C 70 90 dB Supply Current/Amplifier I SY I OUT = 0 mA 1.15 1.4 mA−40°C < T A < +125°C 1.5 mA DYNAMIC PERFORMANCESlew Rate SR R L = 2 kΩ, C L = 16 pF 5 V/µs Settling Time t S To 0.01%, 0 V to 1 V step, A V = 1 <0.5 µs Unity Gain Bandwidth Product GBP 9 MHz Phase Margin ΦM 50 Degrees NOISE PERFORMANCEPeak-to-Peak Noise e n p-p f = 0.1 Hz to 10 Hz 2.3 3.5 µV p-p Voltage Noise Density e n f = 1 kHz 8 12 nV/√Hze nf = 10 kHz 6.5 nV/√Hz Current Noise Density i n f = 1 kHz 0.01 pA/√HzKnown Good Die AD8608-KGD ABSOLUTE MAXIMUM RATINGSESD CAUTIONTable 3.Parameter RatingSupply Voltage 6 VInput Voltage GND to V SDifferential Input Voltage 6 VOutput Short-Circuit Duration to GND Observe Derating CurvesStorage Temperature Range −65°C to +150°COperating Temperature Range −40°C to +125°CJunction Temperature Range −65°C to +150°CStresses at or above those listed under Absolute MaximumRatings may cause permanent damage to the product. This is astress rating only; functional operation of the product at theseor any other conditions above those indicated in the operationalsection of this specification is not implied. Operation beyondthe maximum operating conditions for extended periods mayaffect product reliability.AD8608-KGDKnown Good DiePIN CONFIGURATION AND FUNCTION DESCRIPTIONS123567NCNC 891011A11B 1213144A 4B13166-001Figure 1. Pad ConfigurationTable 4. Pad Function DescriptionsPad X-Axis (µm) Y-Axis (µm) Mnemonic Pad Type Description1 −490 +1239OUT A Single Output Channel A2 −749 +1153− IN A Single Inverting Input Channel A3 −749 +853+ IN A Single Noninverting Input Channel A 4A −703 +85 V+ Supply Double Positive Supply Voltage4B −703 −84 V+ Supply Double Positive Supply Voltage, Double Bond Pad 5 −749 −659 + IN B Single Noninverting Input Channel B 6 −749 −944 − IN B Single Inverting Input Channel B 7 −683 −1189OUTB Single Output Channel B 8 +688−1189OUTC Single Output Channel C9 +749−916 − IN C Single Inverting Input Channel C 10 +749−631 + IN C Single Noninverting Input Channel C 11A +749−122 V− Supply Double Negative Supply Voltage11B +749+47V− Supply Double Negative Supply Voltage, Double Bond Pad 12 +749+813+ IN D Single Noninverting Input Channel D 13 +749+1113− IN D Single Inverting Input Channel D 14+597+1239OUT DSingleOutput Channel D。
AD8131AR中文资料
Low-Cost, High-Speed Differential Driver AD8131
FUNCTIONAL BLOCK DIAGRAM
1 750⍀ 2 750⍀ 8 +DIN 7 NC 6 V– 1.5k⍀ +OUT 4 1.5k⍀ 5 –OUT VOCM
V+ 3
AD8131
NC = NO CONNECT
The AD8131 is a differential or single-ended input to differential output driver requiring no external components for a fixed gain of 2. The AD8131 is a major advancement over op amps for driving signals over long lines or for driving differential input ADCs. The AD8131 has a unique internal feedback feature that provides output gain and phase matching that are balanced to –60 dB at 10 MHz, reducing radiated EMI and suppressing harmonics. Manufactured on ADI’s next generation XFCB bipolar process, the AD8131 has a –3 dB bandwidth of 400 MHz and delivers a differential signal with very low harmonic distortion. The AD8131 is a differential driver for the transmission of high-speed signals over low-cost twisted pair or coax cables. The AD8131 can be used for either analog or digital video signals or for other high-speed data transmission. The AD8131 driver is capable of driving either Cat3 or Cat5 twisted pair or coax with minimal line attenuation. The AD8131 has considerable cost and performance improvements over discrete line driver solutions.
AD8138ARZ中文资料
FPGA可编程逻辑器件芯片ADM202EARNZ-REEL中文规格书
ADM202E/ADM1181AFEATURESComplies with 89/336/EEC EMC directive ESD protection to IEC1000-4-2 (801.2) ±8 kV: contact discharge ±15 kV: air-gap discharge ±15 kV: human body modelEFT fast transient/burst immunity (IEC1000-4-4) Low EMI emissions (EN55022) 230 kbits/s data rate guaranteed TSSOP package optionUpgrade for MAX202E, 232E, LT1181AAPPLICATIONSGeneral-purpose RS-232 data link Portable instruments PDAsGENERAL DESCRIPTIONThe ADM202E and ADM1181A are robust, high speed, 2-channel RS-232/V .28 interface devices that operate from a single 5 V power supply. Both products are suitable for operation in harsh electrical environments and are compliant with the EU directive on EMC (89/336/EEC). Both the level of electromagnetic emissions and immunity are in compliance. EM immunity includes ESD protection in excess of ±15 kV on all I/O lines, fast transient/burst protection (1000-4-4), and radiated immunity (1000-4-3). EM emissions include radiated and conducted emissions as required by Information Technology Equipment EN55022, CISPR22.The ADM202E and ADM1181A conform to the EIA-232E and CCITT V .28 specifications and operate at data rates up to 230 kbps.Four external 0.1 µF charge-pump capacitors are used for the voltage doubler/inverter, permitting operation from a single 5 V supply.FUNCTIONAL BLOCK DIAGRAMS*INTERNAL 5k ΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT10V T1T2R1R2*0.1µF 0.1µµF00066-001Figure 1.0.1µ 10V 10VT1µF T2R1R2*0.1µF 00066-002*INTERNAL 5k Ω PULL-DOWN RESISTOR ON EACH RS-232 INPUTFigure 2.The ADM202E provides a robust pin-compatible upgrade for existing ADM202, ADM232L, or MAX202E/MAX232E sockets. It is available in a 16-lead PDIP , a wide SOIC, a narrow SOIC, and a space-saving TSSOP package that is 44% smaller than the SOIC package.The ADM1181A provides a robust pin-compatible upgrade for the LTC1181A, and it is available in a 16-lead PDIP package and a wide 16-lead SOIC package.ADM202E/ADM1181A Rev. C | Page 6 of 16GENERAL DESCRIPTIONThe ADM202E/ADM1181E are rugged RS-232 linedrivers/receivers. Step-up voltage converters coupled with level-shifting transmitters and receivers allow RS-232 levels to be developed while operating from a single 5 V supply.Features include low power consumption, high transmission rates, and compliance with the EU directive on electromagnetic compatibility. EM compatibility includes protection against radiated and conducted interference, including high levels of electrostatic discharge.All inputs and outputs contain protection against electrostatic discharges of up to ±15 kV and electrical fast transients of up to ±2 kV . This ensures compliance to IEC1000-4-2 and IEC1000-4-4 requirements.The devices are ideally suited for operation in electrically harsh environments or where RS-232 cables are frequently being plugged/unplugged. They are also immune to high RF field strengths without special shielding precautions.CMOS technology is used to minimize the power dissipation, allowing maximum battery life in portable applications. The ADM202E/ADM1181A serve as a modification,enhancement, and improvement to the ADM230–ADM241 family and its derivatives. It is essentially plug-in compatible and do not have materially different applications.CIRCUIT DESCRIPTIONThe internal circuitry consists of four main sections: • A charge-pump voltage converter • 5 V logic to EIA-232 transmitters •EIA-232 to 5 V logic receivers.•Transient protection circuit on all I/O linesCharge-Pump DC-to-DC Voltage ConverterThe charge-pump voltage converter consists of a 200 kHz oscillator and a switching matrix. The converter generates a ±10 V supply from the input 5 V level. This is done in two stages, using a switched capacitor technique, as illustrated in Figure 6 and Figure 7. First, the 5 V input supply is doubled to 10 V , using Capacitor C1 as the charge storage element. The 10 V level is then inverted to generate −10 V , using C2 as the storage element. Capacitor C3 and Capacitor C4 are used to reduce the output ripple. Their values are not critical and can be increased if desired. On the ADM202E, Capacitor C3 is shown connected between V+ and V CC , whereas it is connected between V+ and GND on the ADM1181A. It is acceptable to use eitherconfiguration with both the ADM202E and ADM1181A. Ifdesired, larger capacitors (up to 47 µF) can be used forCapacitor C1 to Capacitor C4. This facilitates direct substitution with older generation charge-pump RS-232 transceivers.CCCCNOTE: C3 CONNECTS BETWEEN V+ AND GND ON THE ADM1181A00066-006Figure 6. Charge-Pump Voltage DoublerFigure 7. Charge-Pump Voltage InverterTransmitter (Driver) SectionThe drivers convert 5 V logic input levels into RS-232 output levels. When driving an RS-232 load with V CC = 5 V , the output voltage swing is typically ±9 V .Receiver SectionThe receivers are inverting level shifters that accept RS-232 input levels and translate them into 5 V logic output levels. The inputs have internal 5 kΩ pull-down resistors to ground and are also protected against overvoltages of up to ±30 V . Unconnected inputs are pulled to 0 V by the internal 5 kΩ pull-down resistor. Therefore, unconnected inputs and those connected to GND have a Logic 1 output level.The receivers have Schmitt-trigger inputs with a hysteresis level of 0.65 V . This ensures error-free reception for both noisy inputs and inputs with slow transition times.HIGH BAUD RATEThe ADM202E/ADM1181A feature high slew rates, permitting data transmission at rates well in excess of the EIA/RS-232-E specifications. RS-232 voltage levels are maintained at data rates of up to 230 kbps, even under worst case loading conditions. This allows for high speed data links between two terminals and is also suitable for the new generation ISDN modem standards, which require data rates of 230 kbps. The slew rate is internally controlled to less than 30 V/µs to minimize EMI interference.ADM202E/ADM1181ARev. C | Page 7 of 16ADM202E/ADM1181ARev. C | Page 10 of 16ESD TESTING (IEC1000-4-2)IEC1000-4-2 (previously 801-2) specifies compliance testing using two coupling methods, contact discharge and air-gap discharge. Contact discharge calls for a direct connection to the unit being tested. Air-gap discharge uses a higher test voltage, but does not make direct contact with the unit being tested. With air-gap discharge, the discharge gun is moved toward the unit being tested, developing an arc across the air gap. This method is influenced by humidity, temperature, barometric pressure, distance, and rate of closure of the discharge gun. Although less realistic, the contact-discharge method is more repeatable and is gaining preference to the air-gap method. Although very little energy is contained within an ESD pulse, the extremely fast rise time coupled with high voltages can cause failures in unprotected semiconductors. Catastrophic destruction can occur immediately as a result of arcing orheating. Even if catastrophic failure does not occur immediately, the device might suffer from parametric degradation, which can result in degraded performance. The cumulative effects of continuous exposure can eventually lead to complete failure. I/O lines are particularly vulnerable to ESD damage. Simply touching or plugging in an I/O cable can result in a static discharge, which can damage or completely destroy theinterface product connected to the I/O port. Traditional ESD test methods, such as the MIL-STD-883B method 3015.7, do not fully test a product’s susceptibility to this type of discharge. This test was intended to test a product’s susceptibility to ESD damage during handling. Each pin is tested with respect to all other pins. There are some important differences between the traditional test and the IEC test: •The IEC test is much more stringent in terms of discharge energy. The injected peak current is over four times greater. •The current rise time is significantly faster in the IEC test.•The IEC test is carried out while power is applied to the device.It is possible that the ESD discharge could induce latch-up in the device being tested. Therefore, this test is more representative of a real-world I/O discharge where the equipment is operating normally with power applied. For peace of mind, however, both tests should be performed to ensure maximum protection during both handling and field service.ESD TEST METHOD R2C1H.BODY MIL-STD883B 1.5k Ω100pF IEC1000-4-2330Ω150pF00066-018Figure 18. ESD Test StandardsI P E A K (%)00066-019Figure 19. Human Body Model ESD Current WaveformFigure 20. IEC1000-4-2 ESD Current WaveformThe ADM202E/ADM1181E products are tested using both of the previously mentioned test methods. Pins are tested with respect to all other pins as per the MIL-STD-883B specification. In addition, I/O pins are tested as per the IEC test specification. The products were tested under the following conditions: •Power-On •Power-OffThere are four levels of compliance defined by IEC1000-4-2. The ADM202E/ADM1181A products meet the most stringent level of compliance both for contact and for air-gap discharge. This means that the products are able to withstand contact discharges in excess of 8 kV and air-gap discharges in excess of 15 kV .ADM202E/ADM1181ARev. C | Page 11 of 16Table 4. IEC1000-4-2 Compliance LevelsLevel Contact Discharge Air Discharge 1 2 kV 2 kV 2 4 kV 4 kV 3 6 kV 8 kV 48 kV15 kVTable 5. ADM202E/ADM1181A ESD Test ResultsESD Test Method I/O Pins MIL-STD-883B ±15 kV IEC1000-4-2 Contact ±8 kV Air±15 kVFAST TRANSIENT/BURST TESTING (IEC1000-4-4)IEC1000-4-4 (previously 801-4) covers electrical fast transient (EFT)/burst immunity. Electrical fast transients occur as a result of arcing contacts in switches and relays. The tests simulate the interference generated when, for example, a power relaydisconnects an inductive load. A spark is generated due to the well-known back EMF effect. In fact, the spark consists of a burst of sparks as the relay contacts separate. The voltageappearing on the line, therefore, consists of a burst of extremely fast transient impulses. A similar effect occurs when switching on fluorescent lights.The fast transient/burst test defined in IEC1000-4-4 simulates this arcing, and its waveform is illustrated in Figure 17. It consists of a burst of 2.5 kHz to 5 kHz transients repeating at300 ms intervals. It is specified for both power and data lines.00066-021Figure 21. IEC1000-4-4 Fast Transient WaveformA simplified circuit diagram of the actual EFT generator is illustrated in Figure 22.The transients are coupled onto the signal lines using an EFT coupling clamp. The clamp, which is 1 m long, completelysurrounds the cable, providing maximum coupling capacitance (50 pF to 200 pF typ) between the clamp and the cable. High energy transients are capacitively coupled to the signal lines. Fast rise times (5 ns), as specified by the standard, result in very effective coupling. This test is very strenuous because high voltages are coupled onto the signal lines. The repetitive transients often cause problems where single pulses do not. Destructive latch-up can be induced due to the high energy content of the transients. Note that this stress is applied while the interface products are powered up and transmitting data. The EFT test applieshundreds of pulses with higher energy than ESD. Worst-case transient current on an I/O line can be as high as 40 A.00066-022Figure 22. IEC1000-4-4 Fast Transient GeneratorTest results are classified according to the following: •Classification 1: Normal performance within specifi- cation limits•Classification 2: Temporary degradation or loss of performance that is self-recoverable•Classification 3: Temporary degradation or loss of function or performance that requires operator intervention or system reset•Classification 4: Degradation or loss of function that is not recoverable due to damageThe ADM202E/ADM1181A meet Classification 2 and have been tested under worst-case conditions using unshielded cables. Data transmission during the transient condition iscorrupted, but can resume immediately following the EFT event without user intervention.。
AD8310ARM-REEL7资料
Fast, Voltage-Out DC–440 MHz,95 dB Logarithmic AmplifierAD8310 Rev.EInformation furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.461.3113© 2005 Analog Devices, Inc. All rights reserved.FEATURESMultistage demodulating logarithmic amplifierVoltage output, rise time <15 nsHigh current capacity: 25 mA into grounded R L95 dB dynamic range: −91 dBV to +4 dBVSingle supply of 2.7 V min at 8 mA typDC–440 MHz operation, ±0.4 dB linearitySlope of +24 mV/dB, intercept of −108 dBVHighly stable scaling over temperatureFully differential dc-coupled signal path100 ns power-up time, 1 mA sleep current APPLICATIONSConversion of signal level to decibel formTransmitter antenna power measurementReceiver signal strength indication (RSSI)Low cost radar and sonar signal processingNetwork and spectrum analyzersSignal-level determination down to 20 HzTrue-decibel ac mode for multimetersGENERAL DESCRIPTIONThe AD8310 is a complete, dc−440 MHz demodulating logarithmic amplifier (log amp) with a very fast voltage mode output, capable of driving up to 25 mA into a grounded load in under 15 ns. It uses the progressive compression (successive detection) technique to provide a dynamic range of up to 95 dB to ±3 dB law conformance or 90 dB to a ±1 dB error bound up to 100 MHz. It is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of 2.7 V to 5.5 V at 8 mA is needed, corresponding to a power consumption of only 24 mW at 3 V. A fast-acting CMOS-compatible enable pin is provided.Each of the six cascaded amplifier/limiter cells has a small-signal gain of 14.3 dB, with a −3 dB bandwidth of 900 MHz.A total of nine detector cells are used to provide a dynamic range that extends from −91 dBV (where 0 dBV is defined as the amplitude of a 1 V rms sine wave), an amplitude of about ±40 μV, up to +4 dBV (or ±2.2 V). The demodulated outputis accurately scaled, with a log slope of 24 mV/dB and an intercept of −108 dBV. The scaling parameters are supply-and temperature-independent.FUNCTIONAL BLOCK DIAGRAMSUPPLY+INPUT–INPUTCOMMON184-1Figure 1.The fully differential input offers a moderately high impedance (1 kΩ in parallel with about 1 pF). A simple network can match the input to 50 Ω and provide a power sensitivity of −78 dBm to+17 dBm. The logarithmic linearity is typically within ±0.4 dBup to 100 MHz over the central portion of the range, but it is somewhat greater at 440 MHz. There is no minimum frequency limit; the AD8310 can be used down to low audio frequencies. Special filtering features are provided to support this wide range.The output voltage runs from a noise-limited lower boundary of 400 mV to an upper limit within 200 mV of the supply voltagefor light loads. The slope and intercept can be readily altered using external resistors. The output is tolerant of a wide varietyof load conditions and is stable with capacitive loads of 100 pF. The AD8310 provides a unique combination of low cost, small size, low power consumption, high accuracy and stability, high dynamic range, a frequency range encompassing audio to UHF, fast response time, and good load-driving capabilities, making this product useful in numerous applications that require the reduction of a signal to its decibel equivalent.The AD8310 is available in the industrial temperature range of−40°C to +85°C in an 8-lead MSOP package.AD8310Rev. E | Page 2 of 24TABLE OF CONTENTSSpecifications.....................................................................................3 Absolute Maximum Ratings............................................................4 ESD Caution..................................................................................4 Pin Configuration and Function Descriptions.............................5 Typical Performance Characteristics.............................................6 Theory of Operation........................................................................9 Progressive Compression............................................................9 Slope and Intercept Calibration................................................10 Offset Control.............................................................................10 Product Overview...........................................................................11 Enable Interface..........................................................................11 Input Interface............................................................................11 Offset Interface...........................................................................12 Output Interface.........................................................................12 Using the AD8310..........................................................................14 Basic Connections......................................................................14 Transfer Function in Terms of Slope and Intercept...............15 dBV vs. dBm...............................................................................15 Input Matching...........................................................................15 Narrow-Band Matching............................................................16 General Matching Procedure....................................................16 Slope and Intercept Adjustments.............................................17 Increasing the Slope to a Fixed Value......................................17 Output Filtering..........................................................................18 Lowering the High-Pass Corner Frequency of the OffsetCompensation Loop..................................................................18 Applications.....................................................................................19 Cable-Driving.............................................................................19 DC-Coupled Input.....................................................................19 Evaluation Board............................................................................20 Outline Dimensions.......................................................................22 Ordering Guide.. (22)REVISION HISTORY6/05—Rev. D to Rev. EChanges to Figure 6..........................................................................6 Change to Basic Connections Section.........................................14 Changes to Equation 10.................................................................17 Changes to Ordering Guide..........................................................22 10/04—Rev. C to Rev. DFormat Updated..................................................................Universal Typical Performance Characteristics Reordered..........................6 Changes to Figures 41 and 42.......................................................20 7/03—Rev. B to Rev. CReplaced TPC 12...............................................................................5 Change to DC-Coupled Input Section........................................14 Replaced Figure 20.........................................................................15 Updated Outline Dimensions.......................................................16 2/03—Rev. A to Rev. BChange to Evaluation Board Section...........................................15 Change to Table III.........................................................................16 Updated Outline Dimensions.......................................................16 1/00—Rev. 0 to Rev. A10/99—Revision 0: Initial VersionAD8310SPECIFICATIONST A = 25°C, V S = 5 V, unless otherwise noted.Table 1.Parameter Conditions Min Typ Max Unit INPUT STAGE Inputs INHI, INLOMaximum Input1Single-ended, p-p ±2.0 ±2.2 V4 dBV Equivalent Power in 50 Ω Termination resistor of 52.3 Ω 17 dBmDifferential drive, p-p 20 dBmNoise Floor Terminated 50 Ω source 1.28 nV/√Hz Equivalent Power in 50 Ω 440 MHz bandwidth −78 dBm Input Resistance From INHI to INLO 800 1000 1200 ΩInput Capacitance From INHI to INLO 1.4 pFDC Bias Voltage Either input 3.2 V LOGARITHMIC AMPLIFIER Output VOUT±3 dB Error Dynamic Range From noise floor to maximum input 95 dB Transfer Slope 10 MHz ≤ f ≤ 200 MHz 22 24 26 mV/dBOvertemperature, –40°C < T A < +85°C 20 26 mV/dB Intercept (Log Offset)210 MHz ≤ f ≤ 200 MHz −115 −108 −99 dBVEquivalent dBm (re 50 Ω) −102 −95 −86 dBmOvertemperature, −40°C ≤ T A ≤ +85°C −120 −96 dBVEquivalent dBm (re 50 Ω) −107 −83 dBmTemperature sensitivity −0.04 dB/°C Linearity Error (Ripple) Input from –88 dBV (–75 dBm) to +2 dBV (+15 dBm) ±0.4 dBOutput Voltage Input = –91 dBV (–78 dBm) 0.4 VInput = 9 dBV (22 dBm) 2.6 V Minimum Load Resistance, R L100 Ω Maximum Sink Current 0.5 mAOutput Resistance 0.05 ΩVideo Bandwidth 25 MHzRise Time (10% to 90%) Input Level = −43 dBV (−30 dBm), R L ≥ 402 Ω, C L ≤ 68 pF 15 nsInput Level = −3 dBV (+10 dBm), R L ≥ 402 Ω, C L ≤ 68 pF 20 nsFall Time (90% to 10%) Input Level = −43 dBV (−30 dBm), R L ≥ 402 Ω, C L ≤ 68 pF 30 nsInput Level = −3 dBV (+10 dBm), R L ≥ 402 Ω, C L ≤ 68 pF 40 nsOutput Settling Time to 1% Input Level = −13 dBV (0 dBm), R L ≥ 402 Ω, C L ≤ 68 pF 40 ns POWER INTERFACESSupply Voltage, VPOS 2.7 5.5 V Quiescent Current Zero-signal 6.5 8.0 9.5 mA Overtemperature −40°C < T A < +85°C 5.5 8.5 10 mA Disable Current 0.05 μALogic Level to Enable Power High condition, −40°C < T A < +85°C 2.3 VInput Current when High 3 V at ENBL 35 μALogic Level to Disable Power Low condition, −40°C < T A < +85°C 0.8 V1 The input level is specified in dBV, because logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of1 V rms. A power level of 0 dBm (1 mW) in a 50 Ω termination corresponds to an input of 0.2236 V rms. Therefore, the relationship between dBV and dBm is a fixedoffset of 13 dBm in the special case of a 50 Ω termination.2 Guaranteed but not tested; limits are specified at six sigma levels.Rev. E | Page 3 of 24AD8310Rev. E | Page 4 of 24ABSOLUTE MAXIMUM RATINGSTable 2.Parameter Value Supply Voltage, V S 7.5 V Input Power (re 50 Ω), Single-Ended 18 dBm Differential Drive 22 dBm Internal Power Dissipation 200 mW θJA 200°C/W Maximum Junction Temperature 125°COperating Temperature Range −40°C to +85°C Storage Temperature Range−65°C to +150°C Lead Temperature (Soldering 60 sec)300°CStresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performancedegradation or loss of functionality.AD8310Rev. E | Page 5 of 24PIN CONFIGURATION AND FUNCTION DESCRIPTIONS01084-002INLOCOMM OFLT VOUTFigure 2. Pin ConfigurationTable 3. Pin Function DescriptionsPin No. Mnemonic Function1 INLO One of Two Balanced Inputs. Biased roughly to VPOS/2.2 COMM Common Pin. Usually grounded.3 OFLT Offset Filter Access. Nominally at about 1.75 V.4 VOUT Low Impedance Output Voltage. Carries a 25 mA maximum load. 5 VPOS Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current.6 BFIN Buffer Input. Used to lower post-detection bandwidth.7 ENBL CMOS Compatible Chip Enable. Active when high. 8INHISecond of Two Balanced Inputs.AD8310Rev. E | Page 6 of 24TYPICAL PERFORMANCE CHARACTERISTICSINPUT LEVEL (dBV)3.00–12020–100(–87dBm)R S S I O U T P U T (V )–80–60–40–200(+13dBm)2.52.01.51.00.501084-011Figure 3. RSSI Output vs. Input Level, 100 MHz Sine Input at T A = −40°C,+25°C, and +85°C, Single-Ended InputINPUT LEVEL (dBV)3.0–120–100(–87dBm)R S S I O U T P U T (V )–80–60–40–20(+13dBm)202.52.01.51.00.5001084-012Figure 4. RSSI Output vs. Input Level at T A = 25°C for Frequencies of 10 MHz, 50 MHz, and 100 MHzINPUT LEVEL (dBV)3.00–12020–100(–87dBm)R S S I O U T P U T (V )–80–60–40–200(+13dBm)2.52.01.51.00.501084-013Figure 5. RSSI Output vs. Input Level at T A = 25°C for Frequencies of 200 MHz, 300 MHz, and 440 MHz01084-043P IN (dBm)R S S I O U T P U T (V )E R R O R (d B )Figure 6. Log Linearity of RSSI Output vs. Input Level, 100 MHz Sine Input at T A = −40°C, +25°C, and +85°CINPUT LEVEL (dBV)–12020–100(–87dBm)E R R O R (d B )–80–60–40–20(+13dBm)01084-015Figure 7. Log Linearity of RSSI Output vs. Input Level, at T A = 25°C, for Frequencies of 10 MHz, 50 MHz, and 100 MHzINPUT LEVEL (dBV)–12020–100(–87dBm)E R R O R (d B )–80–60–40–20(+13dBm)01084-016Figure 8. Log Linearity of RSSI Output vs. Input Level at T A = 25°Cfor Frequencies of 200 MHz, 300 MHz, and 440 MHzAD8310Rev. E | Page 7 of 2401084-009Figure 9. Small-Signal AC Response of RSSI Output with External BFINCapacitance of 100 pF, 3300 pF, and 0.01 μFFigure 10. Large-Signal RSSI Pulse Response with C L = 100 pFand RL = 100 Ω, 154 Ω, and 200 Ω01084-006Figure 11. RSSI Pulse Response with R L = 402 Ω and C L = 68 pF,for Inputs Stepped from 0 dBV to −33 dBV, −23 dBV, −13 dBV, and −3 dBV 01084-010Figure 12. Small-Signal RSSI Pulse Responsewith R L = 402 Ω and C L = 68 pF01084-007Figure 13. Large-Signal RSSI Pulse Response with R L = 100 Ωand C L = 33 pF, 68 pF, and 100 pF01084-008Figure 14. Small-Signal RSSI Pulse Response with R L = 50 Ω and Back Termination of 50 Ω (Total Load = 100 Ω)AD8310Rev. E | Page 8 of 24ENABLE VOLTAGE (V)1000.000010.52.50.7S U P P L Y C U R R E N T (m A )0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.31010.10.010.0010.000101084-003Figure 15. Supply Current vs. Enable Voltage at T A = −40°C, +25°C, and +85°CFREQUENCY (MHz)3029201100010R S S I S L O P E(m V /d B )100242322212625282701084-017Figure 16. RSSI Slope vs. FrequencySLOPE (mV/dB)21.522.0C O U N T22.523.023.524.024.501084-019Figure 17. Transfer Slope Distribution, V S= 5 V, Frequency = 100 MHz, 25°C01084-004Figure 18. Power-On/Off Response Time with RF Input of −83 dBV to −3 dBVFREQUENCY (MHz)–99–101–1191100010R S S I I N T E R C E P T (d B V )100–111–113–115–117–107–109–103–10501084-018Figure 19. RSSI Intercept vs. FrequencyINTERCEPT (dBV)1240–115–113C O U N T210861416–111–109–107–105–103–101–99–971820222401084-020Figure 20. Intercept Distribution V S = 5 V, Frequency = 100 MHz, 25°CAD8310Rev. E | Page 9 of 24THEORY OF OPERATIONLogarithmic amplifiers perform a more complex operation than classical linear amplifiers, and their circuitry is significantlydifferent. A good grasp of what log amps do and how they do itcan help users avoid many pitfalls in their applications. For a complete discussion of the theory, see the AD8307 data sheet. The essential purpose of a log amp is not to amplify (though amplification is needed internally), but to compress a signal of wide dynamic range to its decibel equivalent. It is, therefore, a measurement device. An even better term might be logarithmic converter, because the function is to convert a signal from one domain of representation to another via a precise nonlinear transformation:⎟⎟⎠⎞⎜⎜⎝⎛=X IN Y OUT V V V V log (1) where:V OUT is the output voltage. V Y is the slope voltage. The logarithm is usually taken to base ten, in which case V Y is also the volts-per-decade. V IN is the input voltage. V X is the intercept voltage. Log amps implicitly require two references (here V X and V Y )that determine the scaling of the circuit. The accuracy of a log amp cannot be any better than the accuracy of its scaling reference s . In the AD8310, these are provided by a band gapreference.VFigure 21. General Form of the Logarithmic FunctionWhile Equation 1, plotted in Figure 21, is fundamentally correct, a different formula is appropriate for specifying the calibration attributes or demodulating log amps like theAD8310, operating in RF applications with a sine wave input.()O IN SLOPE OUT P P V V −= (2)where:V OUT is the demodulated and filtered baseband (video or RSSI) output.V SLOPE is the logarithmic slope, now expressed in V/dB (25 mV/dB for the AD8310).P IN is the input power, expressed in dB relative to some reference power level.P O is the logarithmic intercept, expressed in dB relative to the same reference level.A widely used reference in RF systems is dB above 1 mW in 50 Ω, a level of 0 dBm. Note that the quantity (P IN – P O ) is dB. The logarithmic function disappears from the formula, because the conversion has already been implicitly performed in stating the input in decibels. This is strictly a concession to popular convention. Log amps manifestly do not respond to power(tacitly, power absorbed at the input), but rather to input voltage. The input is specified in dBV (decibels with respect to 1 V rms) throughout this data sheet. This is more precise, although still incomplete, because the signal waveform is also involved. Many users specify RF signals in terms of power(usually in dBm/50 Ω), and this convention is used in this datasheet when specifying the performance of the AD8310.PROGRESSIVE COMPRESSION High speed, high dynamic-range log amps use a cascade ofnonlinear amplifier cells to generate the logarithmic functionas a series of contiguous segments, a type of piecewise linear technique. The AD8310 employs six cells in its main signal path, each having a small-signal gain of 14.3 dB (×5.2) and a −3 dB bandwidth of about 900 MHz. The overall gain is about 20,000 (86 dB), and the overall bandwidth of the chain is approximately 500 MHz, resulting in a gain-bandwidth product(GBW) of 10,000 GHz, about a million times that of a typical op amp. This very high GBW is essential to accurate operationunder small-signal conditions and at high frequencies. The AD8310 exhibits a logarithmic response down to inputs as small as 40 μV at 440 MHz.Progressive compression log amps either provide a baseband video response or accept an RF input and demodulate thissignal to develop an output that is essentially the envelope of the input represented on a logarithmic or decibel scale. TheAD8310 is the latter kind. Demodulation is performed in a total of nine detector cells. Six are associated with the amplifier stages, and three are passive detectors that receive a progres-sively attenuated fraction of the full input. The maximum signal frequency can be 440 MHz, but, because all the gain stages are dc-coupled, operation at very low frequencies is possible.AD8310Rev. E | Page 10 of 24SLOPE AND INTERCEPT CALIBRATIONAll monolithic log amps from Analog Devices use precision design techniques to control the logarithmic slope and intercept. The primary source of this calibration is a pair of accurate voltage references that provide supply- andtemperature-independent scaling. The slope is set to 24 mV/dB by the bias chosen for the detector cells and the subsequent gain of the postdetector output interface. With this slope, the full 95 dB dynamic range can be easily accommodated within the output swing capacity, when operating from a 2.7 V supply. Intercept positioning at −108 dBV (−95 dBm re 50 Ω) has likewise been chosen to provide an output centered in the available voltage range.Precise control of the slope and intercept results in a log amp with stable scaling parameters, making it a true measurement device as, for example, a calibrated received signal strength indicator (RSSI). In this application, the input waveform is invariably sinusoidal. The input level is correctly specified in dBV . It can alternatively be stated as an equivalent power, in dBm, but in this case, it is necessary to specify the impedance in which this power is presumed to be measured. In RF practice, it is common to assume a reference impedance of 50 Ω, in which 0 dBm (1 mW) corresponds to a sinusoidal amplitude of 316.2 mV (223.6 mV rms). However, the power metric is correct only when the input impedance is lowered to 50 Ω, either by a termination resistor added across INHI and INLO, or by the use of a narrow-band matching network.Note that log amps do not inherently respond to power, but to the voltage applied to their input. The AD8310 presents a nominal input impedance much higher than 50 Ω (typically 1 kΩ at low frequencies). A simple input matching network can considerably improve the power sensitivity of this type of log amp. This increases the voltage applied to the input and, therefore, alters the intercept. For a 50 Ω reactive match, the voltage gain is about 4.8, and the whole dynamic range moves down by 13.6 dB. The effective intercept is a function of wave-form. For example, a square-wave input reads 6 dB higher than a sine wave of the same amplitude, and a Gaussian noise input reads 0.5 dB higher than a sine wave of the same rms value. OFFSET CONTROLIn a monolithic log amp, direct coupling is used between the stages for several reasons. First, it avoids the need for coupling capacitors, which typically have a chip area at least as large as that of a basic gain cell, considerably increasing die size. Second, the capacitor values predetermine the lowest frequency at which the log amp can operate. For moderate values, this can be as high as 30 MHz, limiting the application range. Third, the parasitic back-plate capacitance lowers the bandwidth of the cell, further limiting the scope of applications.However, the very high dc gain of a direct-coupled amplifier raises a practical issue. An offset voltage in the early stages of the chain is indistinguishable from a real signal. If it were as high as 400 μV , it would be 18 dB larger than the smallest ac signal (50 μV), potentially reducing the dynamic range by this amount. This problem can be averted by using a global feedback path from the last stage to the first, which corrects this offset in a similar fashion to the dc negative feedback applied around an op amp. The high frequency components of the feedback signal must, of course, be removed to prevent a reduction of the HF gain in the forward path.An on-chip filter capacitor of 33 pF provides sufficient suppres-sion of HF feedback to allow operation above 1 MHz. The −3 dB point in the high-pass response is at 2 MHz, but theusable range extends well below this frequency. To further lower the frequency range, an external capacitor can be added at OFLT (Pin 3). For example, 300 pF lowers it by a factor of 10. Operation at low audio frequencies requires a capacitor of about 1 μF. Note that this filter has no effect for input levels well above the offset voltage, where the frequency range would extend down to dc (for a signal applied directly to the input pins). The dc offset can optionally be nulled by adjusting the voltage on the OFLT pin (see the Applications section).PRODUCT OVERVIEWThe AD8310 has six main amplifier/limiter stages. These six cells and their and associated g m styled full-wave detectors handle the lower two-thirds of the dynamic range. Three top-end detectors, placed at 14.3 dB taps on a passive attenuator, handle the upper third of the 95 dB range. The first amplifier stage provides a low noise spectral density (1.28 nV/√Hz). Biasing for these cells is provided by two references: onedetermines their gain, and the other is a band gap circuit that determines the logarithmic slope and stabilizes it against supply and temperature variations. The AD8310 can be enabled or disabled by a CMOS-compatible level at ENBL (Pin 7). The differential current-mode outputs of the nine detectors are summed and then converted to single-sided form, nominally scaled 2 μA/dB. The output voltage is developed by applying this current to a 3 kΩ load resistor followed by a high speed gain-of-four buffer amplifier, resulting in a logarithmic slope of 24 mV/dB (480 mV/decade) at VOUT (Pin 4). The unbuffered voltage can be accessed at BFIN (Pin 6), allowing certain functional modifications such as the addition of an external postdemodulation filter capacitor and the alteration or adjustment of slope and intercept.–INPUT01084-022Figure 22. Main Features of the AD8310The last gain stage also includes an offset-sensing cell. This generates a bipolarity output current, if the main signal path exhibits an imbalance due to accumulated dc offsets. This current is integrated by an on-chip capacitor that can beincreased in value by an off-chip component at OFLT (Pin 3). The resulting voltage is used to null the offset at the output of the first stage. Because it does not involve the signal inputconnections, whose ac-coupling capacitors otherwise introduce a second pole into the feedback path, the stability of the offset correction loop is assured.The AD8310 is built on an advanced, dielectrically isolated, complementary bipolar process. In the following interface diagrams shown in Figure 23 to Figure 26, resistors labeled as R are thin-film resistors that have a low temperature coefficient of resistance (TCR) and high linearity under large-signal conditions. Their absolute tolerance is typically within ±20%.Similarly, capacitors labeled as C have a typical tolerance of ±15% and essentially zero temperature or voltage sensitivity. Most interfaces have additional small junction capacitances associated with them, due to active devices or ESD protection, which might not be accurate or stable. Component numbering in these interface diagrams is local.ENABLE INTERFACEThe chip-enable interface is shown in Figure 23. The currents in the diode-connected transistors control the turn-on and turn-off states of the band gap reference and the bias generator. They are a maximum of 100 μA when ENBL is taken to 5 V under worst-case conditions. For voltages below 1 V , the AD8310 is disabled and consumes a sleep current of less than 1 μA. When tied to the supply or a voltage above 2 V , it is fully enabled. The internal bias circuitry is very fast (typically <100 ns for either off or on). In practice, however, the latency period before the log amp exhibits its full dynamic range is more likely to be limited by factors relating to the use of ac-coupling at the input or the settling of the offset-control loop (see the following sections).01084-023Figure 23. Enable InterfaceINPUT INTERFACEFigure 24 shows the essentials of the input interface. C P and C M are parasitic capacitances, and C D is the differential input capacitance, largely due to Q1 and Q2. In most applications, both input pins are ac-coupled. The S switches close whenenable is asserted. When disabled, bias current I E is shut off and the inputs float; therefore, the coupling capacitors remain charged. If the log amp is disabled for long periods, small leakage currents discharge these capacitors. Then, if they are poorly matched, charging currents at power-up can generate a transient input voltage that can block the lower reaches of the dynamic range until it becomes much less than the signal. A single-sided signal can be applied via a blocking capacitor to either Pin 1 or Pin 8, with the other pin ac-coupled to ground. Under these conditions, the largest input signal that can be handled is 0 dBV (a sine amplitude of 1.4 V) when using a 3 V supply; a 5 dBV input (2.5 V amplitude) can be handled with a 5 V supply. When using a fully balanced drive, this maximum input level is permissible for supply voltages as low as 2.7 V . Above 10 MHz, this is easily achieved using an LC matching network. Such a network, having an inductor at the input, usefully eliminates the input transient noted above.。
AD847ARZ中文资料
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FEATURES Superior Performance
High Unity Gain BW: 50 MHz Low Supply Current: 5.3 mA High Slew Rate: 300 V/s Excellent Video Specifications
AD847 Driving Capacitive Loads
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QUIESCENT CURRENT – mA
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Quiescent Current vs. Supply Voltage
REV. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
MEMORY存储芯片ADM485ARZ-REEL中文规格书
ADM485FUNCTIONAL BLOCK DIAGRAMCC 00078-001FEATURESMeets EIA RS-485 standard 5 Mbps data rateSingle 5 V supply–7 V to +12 V bus common-mode range High speed, low power BiCMOS Thermal shutdown protection Short-circuit protectionDriver propagation delay: 10 ns typical Receiver propagation delay: 15 ns typical High-Z outputs with power off Superior upgrade for LTC485APPLICATIONSLow power RS-485 systems DTE/DCE interface Packet switchingLocal area networks (LNAs) Data concentration Data multiplexersIntegrated services digital network (ISDN)GENERAL DESCRIPTIONThe ADM485 is a differential line transceiver suitable for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced data transmission and complies with EIA standards RS-485 and RS-422. The part contains a differential line driver and a differential line receiver. Both the driver and the receiver can be enabled independently. When disabled, the outputs are three-stated.The ADM485 operates from a single 5 V power supply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. If during fault conditions, a significant temperature increase is detected in the internal driver circuitry, this feature forces the driver output into a high impedance state.Up to 32 transceivers can be connected simultaneously on a bus, but only one driver should be enabled at any time. It is important, therefore, that the remaining disabled drivers do not load the bus. To ensure this, the ADM485 driver features high output impedance when disabled and when powered down, which minimizes the loading effect when the transceiver is not being used. The high impedance driver output is maintained over the common-mode voltage range of −7 V to +12 V .Figure 1.The receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). The ADM485 is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS with fast switching bipolar technology. All inputs and outputs contain protection against ESD; all driver outputs feature high source and sink current capability. An epitaxial layer is used to guard against latch-up.The ADM485 features extremely fast switching speeds. Minimal driver propagation delays permit transmission at data rates up to 5 Mbps while low skew minimizes EMI interference. The part is fully specified over the commercial and industrial temperature range and is available in 8-lead PDIP , 8-lead SOIC, and small footprint, 8-lead MSOP packages.ADM485Rev. F | Page 2 of 16ADM485SPECIFICATIONSV CC = 5 V ± 5%, all specifications T MIN to T MAX, unless otherwise noted.Rev. F | Page 3 of 16ADM485TIMING SPECIFICATIONSV CC = 5 V ± 5%, all specifications T MIN to T MAX, unless otherwise noted.1 Guaranteed by characterization.Rev. F | Page 4 of 16ADM485Rev. F | Page 5 of 16ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Table 4. TransmittingInputsOutputsDE DIB A 1 1 0 1 1 0 1 0 0X 1Z 2Z 21 X = don’t care.2Z = high impedance.1 X = don’t care.2Z = high impedance.ESD CAUTION。
ADUM1201ARZ-RL7中文资料
3 ns maximum channel-to-channel matching High common-mode transient immunity: > 25 kV/µs Safety and regulatory approvals
UL recognition 2500 V rms for 1 minute per UL 1577
APPLICATIONS
The ADuM120x isolators provide two independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). Both parts operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM120x provide low pulse-width distortion (< 3 ns for CR grade) and tight channel-to-channel matching (< 3 ns for CR grade). Unlike other optocoupler alternatives, the ADuM120x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions
半导体芯片ADM3202ARNZ-REEL中文规格书
ADG3304Data Sheet Rev. E | Page 16 of 21TERMINOLOGYV IHALogic input high voltage at Pin A1 to Pin A4. V ILALogic input low voltage at Pin A1 to Pin A4. V OHA Logic output high voltage at Pin A1 to Pin A4. V OLA Logic output low voltage at Pin A1 to Pin A4. C A Capacitance measured at Pin A1 to Pin A4 (EN = 0). I LA, Hi-ZLeakage current at Pin A1 to Pin A4 when EN = 0 (high impedance state at Pin A1 to Pin A4).V IHYLogic input high voltage at Pin Y1 to Pin Y4. V ILYLogic input low voltage at Pin Y1 to Pin Y4. V OHY Logic output high voltage at Pin Y1 to Pin Y4. V OLY Logic output low voltage at Pin Y1 to Pin Y4. C Y Capacitance measured at Pin Y1 to Pin Y4 (EN = 0). I LY , Hi-ZLeakage current at Pin Y1 to Pin Y4 when EN = 0 (high impedance state at Pin Y1 to Pin Y4).V IHENLogic input high voltage at the EN pin.V ILENLogic input low voltage at the EN pin.C ENCapacitance measured at EN pin.I LENEnable (EN) pin leakage current.t ENThree-state enable time for Pin A1 to Pin A4 and Pin Y1 to Pin Y4.t P , A→YPropagation delay when translating logic levels in the A→Y direction.t R, A→YRise time when translating logic levels in the A→Y direction. T F, A→Y Fall time when translating logic levels in the A→Y direction. D MAX, A→Y Guaranteed data rate when translating logic levels in the A→Y direction under the driving and loading conditions specified in Table 1. T S KEW , A→Y Difference between propagation delays on any two channels when translating logic levels in the A→Y direction. t PPSKEW , A→Y Difference in propagation delay between any one channel and the same channel on a different part (under same driving/ loading conditions) when translating in the A→Y direction. t P , Y→A Propagation delay when translating logic levels in the Y→A direction. t R, Y→A Rise time when translating logic levels in the Y→A direction. t F, Y→A Fall time when translating logic levels in the Y→A direction. D MAX, Y→A Guaranteed data rate when translating logic levels in the Y→A direction under the driving and loading conditions specified in Table 1. t S KEW , Y→A Difference between propagation delays on any two channels when translating logic levels in the Y→A direction. t PPSKEW , Y→A Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/ loading conditions) when translating in the Y→A direction. V CCA V CCA supply voltage. V CCY V CCY supply voltage. I CCA V CCA supply current. I CCY V CCY supply current. I Hi-Z, A V CCA supply current during three-state mode (EN = 0). I Hi-Z, Y V CCY supply current during three-state mode (EN = 0).Data SheetADG3304 Rev. E | Page 17 of 21THEORY OF OPERATIONThe ADG3304 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used. The device requires two supplies, V CCA and V CCY (V CCA ≤ V CCY ). These supplies set the logic levels on each side of the device. When driving the A pins, the device translates the V CCA -compatible logic levels to V CCY -compatible logic levels available at the Y pins. Similarly, because the device is capable of bidirectional translation, when driving the Y pins, the V CCY -compatible logic levels are translated to V CCA -compatible logic levels available at the A pins. When EN = 0, Pin A1 to Pin A4 and Pin Y1 to Pin Y4 are three-stated. When EN is driven high, the ADG3304 goes into normal operation mode and performs level translation. LEVEL TRANSLATOR ARCHITECTURE The ADG3304 consists of four bidirectional channels. Each channel can translate logic levels in either the A→Y or the Y→A direction. It uses a one-shot accelerator architecture, which ensures excellent switching characteristics. Figure 39 shows a simplified block diagram of a bidirectional channel.Y 04860-053Figure 39. Simplified Block Diagram of an ADG3304 Channel The logic level translation in the A→Y direction is performed using a level translator (U1) and an inverter (U2), while the translation in the Y→A direction is performed using Inverter U3 and Inverter U4. The one-shot generator detects a rising or falling edge present on either the A side or the Y side of the channel. It sends a short pulse that turns on the PMOS transistors (T1 to T2) for a rising edge, or the NMOS transistors (T3 to T4) for a falling edge. This charges/discharges the capacitive load faster, which results in faster rise and fall times.The inputs of the unused channels (A or Y) should be tied to their corresponding V CC rail (V CCA or V CCY ) or to GND. INPUT DRIVING REQUIREMENTS To ensure correct operation of the ADG3304, the circuit that drives the input of the ADG3304 channels should have an output impedance of less than or equal to 150 Ω and a minimum peak current driving capability of 36 mA. OUTPUT LOAD REQUIREMENTS The ADG3304 level translator is designed to drive CMOS-compatible loads. If current-driving capability is required, it is recommended to use buffers between the ADG3304 outputs and the load. ENABLE OPERATIONThe ADG3304 provides three-state operation at the A and Y I/O pins by using the enable pin (EN), as shown in Table 5. Table 5. Truth TableENY I/O Pins A I/O Pins 0Hi-Z 1 Hi-Z 1 1Normal operation 2Normal operation 21High impedance state.2 In normal operation, the ADG3304 performs level translation.While EN = 0, the ADG3304 enters into three-state mode. In this mode, the current consumption from both the V CCA and V CCY supplies is reduced, allowing the user to save power, which is critical, especially on battery-operated systems. The EN input pin can be driven with either V CCA -compatible or V CCY -compatible logic levels.POWER SUPPLIESFor proper operation of the ADG3304, the voltage applied to the V CCA must be less than or equal to the voltage applied to V CCY . To meet this condition, the recommended power-up sequence is V CCY first and then V CCA . The ADG3304 operates properly only after both supply voltages reach their nominal values. It is not recommended to use the part in a system where, during power-up, V CCA can be greater than V CCY due to a significant increase in the current taken from the V CCA supply. For optimum performance, the V CCA pin and V CCY pin should be decoupled to GND as close as possible to the device.。
半导体传感器AD7711ARZ中文规格书
AD7705/AD7706Rev. C | Page 34 of 44 MICROCOMPUTER/MICROPROCESSORINTERFACINGThe flexible serial interface of the AD7705/AD7706 allows easy interfacing to most microcomputers and microprocessors. The flowchart in Figure 21 outlines the sequence to follow when interfacing a microcontroller or microprocessor to the AD7705/AD7706. Figure 22 through Figure 24 show typical interface circuits.The serial interface is capable of operating from three wires and is compatible with SPI interface protocols. The 3-wire operation makes these parts ideal for an isolated system in which minimizing the number of interface lines minimizes the number ofopto-isolators required in the system. The serial clock input is a Schmitt-triggered input to accommodate slow edges from opto-couplers. The rise and fall times of other digital inputs to the AD7705/AD7706 should be no longer than 1 μs.Most of the registers on the AD7705/AD7706 are 8-bit registers, which facilitates easy interfacing to the 8-bit serial ports of micro-controllers. The data register on the AD7705/AD7706 is 16 bits, and the offset and gain registers are 24-bit registers, but data transfers to these registers can consist of multiple 8-bit transfers to the serial port of the microcontroller. DSP processors and microprocessors generally transfer 16 bits of data in a serial data operation. Some of these processors, such as the ADSP-2105, have the facility to program the number of cycles in a serial transfer. This allows the user to tailor the number of bits in any transfer to match the length of the required register in the AD7705/AD7706.Because some registers on the AD7705/AD7706 are only 8 bits long, successive write operations to two of these registers can be handled as a single 16-bit data transfer. For example, to update the setup register, the processor must write to the communication register to indicate that the next operation is a write to the setup register, and then write 8 bits to the setup register. This can be done in a single 16-bit transfer, because once the eight serial clocks of the write operation to the communication register are complete, the part immediately sets up for a write operation to the setup register. AD7705/AD7706-to-68HC11 InterfaceFigure 22 shows an interface between the AD7705/AD7706 and the 68HC11 microcontroller. The diagram shows the minimum (3-wire) interface with CS on the AD7705/AD7706 hardwired low. In this scheme, the DRDY bit of the communication register is monitored to determine when the data register is updated. An alternative scheme, which increases the number of interface lines to four, is to monitor the DRDY output line from the AD7705/ AD7706. Monitoring the DRDY line can be done in two ways. First, DRDY can be connected to a 68HC11 port bit (such as PC0) that is configured as an input. This port bit is then polled to determine the status of DRDY .The second scheme is to use an interrupt-driven system, in which case the DRDY output is connected to the IRQ input of the 68HC11. For interfaces that require control of the CS input on the AD7705/AD7706, a port bit of the 68HC11 (such as PC1) that is configured as an output can be used to drive the CS input.01166-022Figure 22. AD7705/AD7706-to-68HC11 Interface The 68HC11 is configured in master mode with its CPOL and CPHA bits set to Logic 1. When the 68HC11 is configured like this, its SCLK line idles high between data transfers. The AD7705/ AD7706 are not capable of a full duplex operation. If the AD7705/ AD7706 are configured for a write operation, no data appears on the DOUT lines, even when the SCLK input is active. Similarly, if the AD7705/AD7706 are configured for a read operation, data presented to the part on the DIN line is ignored, even when SCLK is active. Coding for an interface between the 68HC11 and the AD7705/ AD7706 is given in the C Code for Interfacing AD7705 to 68HC11 section. In this example, the DRDY output line of the AD7705 is connected to the PC0 port bit of the 68HC11 and is polled to determine its status.01166-023Figure 23. AD7705/AD7706-to-8XC51 InterfaceAD7705/AD7706Rev. C | Page 35 of 44AD7705/AD7706-to-8051 InterfaceAn interface circuit between the AD7705/AD7706 and the 8XC51 microcontroller is shown in Figure 23. The diagram shows the minimum number of interface connections with CS on the AD7705/AD7706 hardwired low. In the case of the 8XC51interface, the minimum number of interconnects is two. In this scheme, the DRDY bit of the communication register is monitored to determine when the data register is updated. The alternative scheme, which increases the number of interface lines to three, is to monitor the DRDY output line from the AD7705/AD7706. Monitoring the DRDY line can be done in two ways. First, DRDY can be connected to a 8XC51 port bit (such as P1.0) that is configured as an input. This port bit is then polled to determine the status of DRDY . The second scheme is to use an interrupt-driven system, in which case the DRDY output is connected to the INT1 input of the 8XC51. For interfaces that require control of the CS input on the AD7705/AD7706, a port bit of the 8XC51 (such as P1.1) that is configured as an output can be used to drive the CS input. The 8XC51 is configured in Mode 0 serial interface mode. Its serial interface contains a single data line. As a result, the DOUT and DIN pins of the AD7705/AD7706 should be connected together with a 10 kΩ pull-up resistor. The serial clock on the 8XC51 idles high between data transfers. During a write operation, the 8XC51 outputs the LSB first. Because the AD7705/AD7706 expect the MSB first, the data must be rearranged before being written to the output serial register. Similarly, during a read operation, the AD7705/ AD7706 output the MSB first, and the 8XC51 expects the LSB first. Therefore, the data read into the serial buffer must be rearranged before the correct data-word from the AD7705/ AD7706 is available in the accumulator.01166-024Figure 24. AD7705/AD7706-to-ADSP-2103/ADSP-2105 InterfaceAD7705/AD7706-to-ADSP-2103/ADSP-2105 Interface Figure 24 shows an interface between the AD7705/AD7706 and the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, the DRDY bit of the communication register is monitored to determine when the data register is updated. The alternative scheme is to use an interrupt-driven system, in which case the DRDY output is connected to the IRQ2 input of the ADSP-2103/ ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105 is set up for alternate framing mode. The RFS and TFS pins of the ADSP-2103/ADSP-2105 are configured as active low outputs, and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is configured as an output. The CS for the AD7705/AD7706 is active when either the RFS or TFS outputs from the ADSP-2103/ ADSP-2105 are active. The serial clock rate on the ADSP-2103/ ADSP-2105 should be limited to 3 MHz to ensure correct operation with the AD7705/AD7706. CODE FOR SETTING UP THE AD7705/AD7706 The following section shows a set of read and write routines in C code for interfacing the 68HC11 microcontroller to the AD7705. The sample program sets up the various registers on the AD7705 and reads 1000 samples from one channel into the 68HC11. The setup conditions on the part are the same as those outlined for the flowchart of Figure 21. In the example code given here, the DRDY output is polled to determine if a new valid word is available in the data register. The same sequence is applicable for the AD7706. The sequence of events in this program are as follows: 1.Write to the communication register, selecting Channel 1as the active channel and setting the next operation to be a write to the clock register.2.Write to the clock register, setting the CLKDIV bit, which divides the external clock internally by two. This assumesthat the external crystal is 4.9512 MHz. The update rate is selected to be 50 Hz.3.Write to the communication register selecting Channel 1 as the active channel and setting the next operation to be a write to the setup register.4.Write to the setup register, setting the gain to 1, setting bipolar mode, buffer off, clearing the filtersynchronization, and initiating a self-calibration.5.Poll the DRDY output.6.Read the data from the data register.7.Repeat Steps 5 and 6 (loop) until the specified number of samples has been taken from the selected channel.。
FPGA可编程逻辑器件芯片AD8561ARZ-REEL7中文规格书
AD8561PIN CONFIGURATIONSFEATURES7 ns Propagation Delay at 5 VSingle Supply Operation: 3 V to 10 V Low Power Latch Function TSSOP PackagesAPPLICATIONS High Speed TimingClock Recovery and Clock Distribution Line ReceiversDigital Communications Phase DetectorsHigh Speed Sampling Read Channel Detection PCMCIA CardsUpgrade for LT1016 DesignsGENERAL DESCRIPTIONThe AD8561 is a single 7 ns comparator with separate input and output sections. Separate supplies enable the input stage to be operated from ±5 V dual supplies and +5 V single supplies.Fast 7 ns propagation delay makes the AD8561 a good choice for timing circuits and line receivers. Propagation delays for rising and falling signals are closely matched and track over temperature. This matched delay makes the AD8561 a good choice for clock recovery, since the duty cycle of the output will match the duty cycle of the input.The AD8561 has the same pinout as the LT1016, with lower supply current and a wider common-mode input range, which includes the negative supply rail.The AD8561 is specified over the industrial (–40°C to +85°C) temperature range. The AD8561 is available in the 8-leadplastic DIP, 8-lead TSSOP , and 8-lead narrow SO IC surface - mount packages.8-Lead Narrow BodySO IC (R -8)8-Lead Plastic DIP(N-8)8-Lead TSSOP(RU-8)؉؊V OUT GND LATCHOUT V ؉V ؉IN ؊IN OUT OUT GNDLATCHV V ؉IN V ؊OUT OUT GND LATCHAD8561–SPECIFICATIONSELECTRICAL SPECIFICATIONS(@ V+ = +5.0 V, V– = V GND = 0 V, T A = +25؇C unless otherwise noted)Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICSOffset Voltage V OS 2.37mV–40°C ≤ T A≤ +85°C8mV Offset Voltage DriftΔV OS/ΔT4μV/°C Input Bias Current I B V CM = 0 V–6–3μAI B–40°C ≤ T A≤ +85°C–7–3.5μA Input Offset Current I OS V CM = 0 V±4μA Input Common-Mode Voltage Range V CM0.0+3.0V Common-Mode Rejection Ratio CMRR0 V ≤ V CM≤ +3.0 V6585dB Large Signal Voltage Gain A VO R L = 10 kΩ3000V/V Input Capacitance C IN 3.0pF LATCH ENABLE INPUTLogic “1” Voltage Threshold V IH 2.0 1.65V Logic “0” Voltage Threshold V IL 1.600.8V Logic “1” Current I IH V LH = 3.0 V–1.0–0.3μA Logic “0” Current I IL V LL = 0.3 V–4–2μA Latch EnablePulsewidth t PW(E)6ns Setup Time t S1ns Hold Time t H 1.2ns DIGITAL OUTPUTSLogic “1” Voltage V OH I OH = –50 μA, ΔV IN > 250 mV 3.5V Logic “1” Voltage V OH I OH = –3.2 mA, ΔV IN > 250 mV 2.4 3.5V Logic “0” Voltage V OL I OL = 3.2 mA, ΔV IN > 250 mV0.250.4V DYNAMIC PERFORMANCEPropagation Delay t P200 mV Step with 100 mV Overdrive 6.759.8ns–40°C ≤ T A≤ +85°C813ns Propagation Delay t P100 mV Step with 5 mV Overdrive8ns Differential Propagation Delay(Rising Propagation Delay vs.Falling Propagation Delay)Δt P100 mV Step with 100 mV Overdrive10.5 2.0ns Rise Time20% to 80% 3.8ns Fall Time80% to 20% 1.5ns POWER SUPPLYPower Supply Rejection Ratio PSRR+4.5 V ≤ V+ ≤ +5.5 V5065dB Positive Supply Current I+ 4.5 6.0mA–40°C ≤ T A≤ +85°C7.5mA Ground Supply Current I GND V O = 0 V, R L = ∞ 2.2 3.3mA–40°C ≤ T A≤ +85°C 3.8mA Analog Supply Current I– 2.3 4.5mA–40°C ≤ T A≤ +85°C 5.5mANOTES1 Guaranteed by design.Specifications subject to change without notice.Rev. DAD8561 ELECTRICAL SPECIFICATIONS(@ V+= +5.0 V, V– = V GND = 0 V, V– = –5 V, T A = +25؇C unless otherwise noted)Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICSOffset Voltage V OS17mV–40°C ≤ T A≤ +85°C8mV Offset Voltage DriftΔV OS/ΔT4μV/°C Input Bias Current I B V CM = 0 V–6–3μAI B–40°C ≤ T A≤ +85°C–7–2.5μA Input Offset Current I OS V CM = 0 V±4μA Input Common-Mode Voltage Range V CM–5.0+3.0V Common-Mode Rejection Ratio CMRR–5.0 V ≤ V CM≤ +3.0 V6585dB Large Signal Voltage Gain A VO R L = 10 kΩ3000V/V Input Capacitance C IN 3.0pF LATCH ENABLE INPUTLogic “1” Voltage Threshold V IH 2.0 1.65V Logic “0” Voltage Threshold V IL 1.600.8V Logic “1” Current I IH V LH = 3.0 V–1–0.520μA Logic “0” Current I IL V LL = 0.3 V–4–220μA Latch EnablePulsewidth t PW(E)6ns Setup Time t S 1.0ns Hold Time t H 1.2ns DIGITAL OUTPUTSLogic “1” Voltage V OH I OH = –3.2 mA 2.6 3.5V Logic “0” Voltage V OL I OL = 3.2 mA0.20.3V DYNAMIC PERFORMANCEPropagation Delay t P200 mV Step with 100 mV Overdrive 6.59.8ns–40°C ≤ T A≤ +85°C813ns Propagation Delay t P100 mV Step with 5 mV Overdrive7ns Differential Propagation Delay(Rising Propagation Delay vs.Falling Propagation Delay)Δt P100 mV Step with 100 mV Overdrive10.52nsRise Time20% to 80% 3.8nsFall Time80% to 20% 1.5nsDispersion1ns POWER SUPPLYPower Supply Rejection Ratio PSRR±4.5 V ≤ V CC and V EE≤±5.5 V5570dB Supply Current V O = 0 V, R L = ∞Positive Supply Current I+ 4.7 6.5mA–40°C ≤ T A≤ +85°C7.5mA Ground Supply Current I GND V O = 0 V, R L = ∞ 2.2 3.3mA–40°C ≤ T A≤ +85°C 3.8mA Negative Supply Current I– 2.4 4.5mA–40°C ≤ T A≤ +85°C 5.5mANOTES1 Guaranteed by design.Specifications subject to change without notice.Rev. DAD8561–SPECIFICATIONSELECTRICAL SPECIFICATIONSParameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICSOffset Voltage V OS7mV Input Bias Current I B V CM = 0 V–6–3.0μAI B–40°C ≤ T A≤ +85°C–7–4μA Input Common-Mode Voltage Range V CM0+1.5V Common-Mode Rejection Ratio CMRR0.1 V ≤ V CM≤ 1.5 V60dBOUTPUT CHARACTERISTICSOutput High Voltage V OH I OH = –3.2 mA, V IN > 250 mV 1.21V Output Low Voltage V OL I OL = +3.2 mA, V IN > 250 mV0.3V POWER SUPPLYPower Supply Rejection Ratio PSRR+2.7 V ≤ V CC, V EE≤ +6 V40dB Supply Currents V O = 0 V, R L = ∞V+ Supply Current I+ 4.0 4.5mA–40°C ≤ T A≤ +85°C 5.5mA Ground Supply Current I GND 1.6 2.5mA–40°C ≤ T A≤ +85°C 3.0mA V– Supply Current I– 2.4 3.3mA–40°C ≤ T A≤ +85°C 3.8mA DYNAMIC PERFORMANCEPropagation Delay t P100 mV Step with 20 mV Overdrive28.59.8nsNOTES1Output high voltage without pull-up resistor. It may be useful to have a pull-up resistor to V+ for 3 V operation.2Guaranteed by design.Specifications subject to change without notice.(@ V+= +3.0 V, V– = V GND = 0 V, T A = +25؇C unless otherwise noted)ABSOLUTE MAXIMUM RATINGSTotal Supply Voltage from V– to V+ . . . . . . . . . . . . . . . . . 14 V Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7 VDifferential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .±8 V Output Short-Circuit Duration to GND . . . . . . . . .Indefinite Storage Temperature RangeN, R, RU Package . . . . . . . . . . . . . . . . . .–65°C to +150°COperating Temperature Range . . . . . . . . . . .–40°C to +85°C Junction Temperature RangeN, R, RU Package . . . . . . . . . . . . . . . . . .–65°C to +150°C Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 350°C Package TypeJA2JC Units 8-Lead Plastic DIP (N)10343°C/W8-Lead SO (R)15843°C/W8-Lead TSSOP24043°C/W NOTES1The analog input voltage is equal to ±7 V or the analog supply voltage, whichever is less.2θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket for P-DIP and θJA is specified for device soldered in circuit board for SOIC and TSSOP packages.Rev. DAD8561Rev. D。
FPGA可编程逻辑器件芯片AD8551ARZ-REEL7中文规格书
The AD8551/AD8552/AD8554 provide the benefits previously found only in expensive auto-zeroing or chopper-stabilized amplifiers. Using Analog Devices, Inc. topology, these new zero-drift amplifiers combine low cost with high accuracy. No external capacitors are required.
With an offset voltage of only 1 μV and drift of 0.005 μV/°C, the AD8551/AD8552/AD8554 are perfectly suited for applications in which error sources cannot be tolerated. Temperature, position and pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range. The rail-to-rail input and output swings provided by the AD8551/AD8552/AD8554 make both high-side and low-side sensing easy.
AD8321ARZ中文资料
Interactive CATV Set-Top Boxes
CATV Plant Test Equipment
General Purpose IF Variable Gain Block
VCC
Gain Programmable CATV Line Driver AD8321
FUNCTIONAL 43; INV VIN– ATTENUATOR CORE
PWR AMP VOUT REVERSE AMP
DATA LATCH DATA SHIFT REGISTER POWERDOWN/ SWITCH INTER PD
DATA SHIFT REGISTER
All Gain Codes f = 65 MHz f = 65 MHz All Gain Codes, Full Temperature Range Max Gain, f = 10 MHz Min Gain, f = 10 MHz Output Noise Temperature Sensitivity 0 £ TA £ +70∞C, Min Gain Power-Down Spectral Density 1 dB Compression Point Max Gain, f = 10 MHz Output Impedance Power-Up and Power-Down f = 42 MHz, POUT = 11 dBm, VCC = +9 V f = 65 MHz, POUT = 11 dBm, VCC = +9 V –40∞C £ TA £ +85∞C f = 10 MHz, All Gain Codes 0 £ TA £ +70∞C Min to Max Gain, VIN = 0 V Max Gain, VIN = 0.15 V Step Power Down, 65 MHz, Min Gain VIN = 0.137 V p-p Max Gain, VIN = 0 Max Gain, VIN = 0 Max Gain, VIN = 0 Max Gain, VIN = 0 Power-Up, VCC = +9 V Power-Down, VCC = +9 V
FPGA可编程逻辑器件芯片AD8542ARZ-REEL7中文规格书
Figure 3. 8-Lead SOIC, 8-Lead MSOP, and 8-Lead TSSOP (R, RM, and RU Suffixes)
OUT A 1
14 OUT D
–IN A 2
13 –IN D
+IN A 3 V+ 4
+IN B 5
AD8544
12 +IN D 11 V– 10 +IN C
00935-036
Figure 38 is an example of the AD8544 in a notch filter circuit. The frequency dependent negative resistance (FDNR) notch filter has fewer critical matching requirements than the twin-T notch, where as the Q of the FDNR is directly proportional to a single resistor R1. Although matching component values is still important, it is also much easier and/or less expensive to accomplish in the FDNR circuit. For example, the twin-T notch uses three capacitors with two unique values, whereas the FDNR circuit uses only two capacitors, which may be of the same value. U3 is simply a buffer that is added to lower the output impedance of the circuit.
LA7311中文资料
No.2310–2/6
元器件交易网
LA7311
S1
S2
S3
S4
S5
S6
Conditions
ICC
off
off
off
off
off
off V9=5V
∆VP ∆VR
B
↓
↓
↓
↓
↓
100mVp-p, difference between V8 (or V12) potential at 4.4MHz input and V8 (or V12) potential at 4.25MHz input
ICC
∆VP
∆VR
V8-12 V3TH V7TH V11TH V10TH V2TH V13 V15 I13(leak) I15(leak) V12 VIN V14 V16
Difference between output at 4.4MHz and output at 4.25MHz Difference between output at 4.4MHz and output at 4.25MHz
MEMORY存储芯片ADM3485EARZ-REEL7中文规格书
Logic Inputs Input Low Voltage Input High Voltage Logic Input Current
ADM3485E
RO
R
RE
B
A DE
DI
D
03338-001
Figure 1.
should be enabled at any time, the output of a disabled or powered-down driver is tristated to avoid overloading the bus. The receiver has a fail-safe feature that ensures a logic high output when the inputs are floating. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. The part is fully specified over the industrial temperature range and is available in an 8-lead narrow SOIC package.
ADM3485E
SPECIFICATIONS
FPGA可编程逻辑器件芯片AD822ARZ-REEL7中文规格书
Low noise 13 nV/√Hz at 10 kHz No phase inversion
TMIN to TMAX
Test Conditions/Comments VCM = 0 V to 2 V VCM = 0 V to 2 V
ISINK = 20 µA ISOURCE = 20 µA ISINK = 2 mA ISOURCE = 2 mA ISINK = 15 mA ISOURCE = 15 mA
Rev. J | Page 5 of 24
AD822
ABSOLUTE MAXIMUM RATINGS
Table 4. Parameter Supply Voltage Internal Power Dissipation
8-Lead PDIP (N) 8-Lead SOIC_N (R) 8-Lead MSOP (RM) Input Voltage1
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
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Low Cost, High SpeedDifferential DriverAD8131 Rev.BInformation furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.461.3113©2005 Analog Devices, Inc. All rights reserved.FEATURESHigh speed400 MHz, −3 dB full power bandwidth2000 V/μs slew rateFixed gain of 2 with no external componentsInternal common-mode feedback to improve gain and phase balance: −60 dB @ 10 MHzSeparate input to set the common-mode output voltage Low distortion: 68 dB SFDR @ 5 MHz 200 Ω loadPower supply range +2.7 V to ±5 VAPPLICATIONSVideo line driverDigital line driverLow power differential ADC driverDifferential in/out level shiftingSingle-ended input to differential output driver FUNCTIONAL BLOCK DIAGRAMNC = NO CONNECT–DV+D INNCV––OUT172-1Figure 1.GENERAL DESCRIPTIONThe AD8131 is a differential or single-ended input to differential output driver requiring no external components for a fixed gain of 2. The AD8131 is a major advancement over op amps for driving signals over long lines or for driving differential input ADCs. The AD8131 has a unique internal feedback feature that provides output gain and phase matching that are balanced to −60 dB at 10 MHz, reducing radiated EMI and suppressing harmonics. Manufactured on the Analog Devices, Inc. next generation XFCB bipolar process, theAD8131 has a −3 dB bandwidth of 400 MHz and delivers a differential signal with very low harmonic distortion.The AD8131 is a differential driver for the transmission of high-speed signals over low-cost twisted pair or coax cables. The AD8131 can be used for either analog or digital video signals or for other high-speed data transmission. The AD8131 driver is capable of driving either Cat3 or Cat5 twisted pair or coax with minimal line attenuation. The AD8131 has considerable cost and performance improvements over discrete line driver solutions.The AD8131 can replace transformers in a variety of applications, preserving low frequency and dc information. The AD8131 does not have the susceptibility to magnetic interference and hysteresis of transformers. It is smaller, easier to work with, and has the high reliability associated with ICs.–20–30–40–50–60–70–801101001000 BALANCEERROR(dB)FREQUENCY (MHz)172-2Figure 2. Output Balance Error vs. FrequencyThe AD8131’s differential output also helps balance the input for differential ADCs, optimizing the distortion performance of the ADCs. The common-mode level of the differential output is adjustable by a voltage on the V OCM pin, easily level-shifting the input signals for driving single-supply ADCs with dual supply signals. Fast overload recovery preserves sampling accuracy. The AD8131 is available in both SOIC and MSOP packages for operation over −40°C to +125°C.AD8131Rev. B | Page 2 of 20TABLE OF CONTENTSSpecifications.....................................................................................3 ±D IN to ±OUT Specifications......................................................3 V OCM to ±OUT Specifications.....................................................4 ±D IN to ±OUT Specifications......................................................5 V OCM to ±OUT Specifications.....................................................6 Absolute Maximum Ratings............................................................7 ESD Caution..................................................................................7 Pin Configuration and Function Descriptions.............................8 Typical Performance Characteristics.............................................9 Operational Description................................................................15 Theory of Operation......................................................................16 Analyzing an Application Circuit.............................................16 Closed-Loop Gain......................................................................16 Estimating the Output Noise Voltage......................................16 Calculating the Input Impedance of anApplication Circuit.....................................................................16 Input Common-Mode Voltage Range inSingle-Supply Applications.......................................................17 Setting the Output Common-Mode Voltage..........................17 Driving a Capacitive Load.........................................................17 Applications.....................................................................................18 Twisted-Pair Line Driver...........................................................18 3 V Supply Differential A-to-D Driver....................................18 Unity-Gain, Single-Ended-to-Differential Driver.................19 Outline Dimensions.......................................................................20 Ordering Guide.. (20)REVISION HISTORY6/05—Rev. A to Rev. BUpdated Format..................................................................Universal Changed Upper Operating Limit.....................................Universal Changes to Ordering Guide. (20)AD8131Rev. B | Page 3 of 20SPECIFICATIONS±D IN TO ±OUT SPECIFICATIONS25°C, V S = ±5 V , V OCM = 0 V , G = 2, R L, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 1.Parameter Conditions M in Typ M ax Unit DYNAMIC PERFORMANCE −3 dB Large Signal Bandwidth V OUT = 2 V p-p 400 MHz −3 dB Small Signal Bandwidth V OUT = 0.2 V p-p 320 MHz Bandwidth for 0.1 dB Flatness V OUT = 0.2 V p-p 85 MHz Slew Rate V OUT = 2 V p-p, 10% to 90% 2000 V/μs Settling Time 0.1%, V OUT = 2 V p-p 14 ns Overdrive Recovery Time V IN = 5 V to 0 V Step 5 ns NOISE/HARMONIC PERFORMANCE Second Harmonic V OUT = 2 V p-p, 5 MHz, R L, dm = 200 Ω −68 dBc V OUT = 2 V p-p, 20 MHz, R L, dm = 200 Ω −63 dBc V OUT = 2 V p-p, 5 MHz, R L, dm = 800 Ω −95 dBc V OUT = 2 V p-p, 20 MHz, R L, dm = 800 Ω −79 dBc Third Harmonic V OUT = 2 V p-p, 5 MHz, R L, dm = 200 Ω −94 dBc V OUT = 2 V p-p, 20 MHz, R L, dm = 200 Ω −70 dBc V OUT = 2 V p-p, 5 MHz, R L, dm = 800 Ω −101 dBc V OUT = 2 V p-p, 20 MHz, R L, dm = 800 Ω −77 dBc IMD 20 MHz, R L, dm = 800 Ω −54 dBc IP3 20 MHz, R L, dm = 800 Ω 30 dBm Voltage Noise (RTO) f = 20 MHz 25 nV/√Hz Differential Gain Error NTSC, R L, dm = 150 Ω 0.01 % Differential Phase Error NTSC, R L, dm = 150 Ω 0.06 degrees INPUT CHARACTERISTICS Input Resistance Single-ended input 1.125 kΩ Differential input 1.5 kΩ Input Capacitance 1 pF Input Common-Mode Voltage −7.0 to +5.0 V CMRR ΔV OUT, dm /ΔV IN, cm ; ΔV IN, cm = ±0.5 V −70 dB OUTPUT CHARACTERISTICS Offset Voltage (RTO) V OS, dm = V OUT, dm ; V DIN+ = V DIN− = V OCM = 0 V ±2 ±7 mV T MIN to T MAX variation ±8 μV/°C V OCM = float ±4 mV T MIN to T MAX variation ±10 μV/°C Output Voltage Swing Maximum ΔV OUT ; single-ended output −3.6 to +3.6 V Linear Output Current 60 mA Gain ΔV OUT, dm /ΔV IN, dm ; ΔV IN, dm = ±0.5 V 1.97 2 2.03 V/V Output Balance Error ΔV OUT, cm /ΔV OUT, dm ; ΔV OUT, dm = 1 V −70 dBAD8131Rev. B | Page 4 of 20V OCM TO ±OUT SPECIFICATIONS25°C, V S = ±5 V , V OCM = 0 V , G = 2, R L, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 2.Parameter Conditions M in Typ Max UnitDYNAMIC PERFORMANCE −3 dB Bandwidth ΔV OCM = 600 mV 210 MHz Slew Rate V OCM = −1 V to +1 V 500 V/μs DC PERFORMANCE Input Voltage Range ±3.6 V Input Resistance 120 kΩ Input Offset Voltage V OS, cm = V OUT, cm ; V DIN+ = V DIN− = V OCM = 0 V ±1.5 ±7 mV V OCM = float ±2.5 mV Input Bias Current 0.5 μAVOCM CMRR ΔV OUT, dm /ΔV OCM ; ΔV OCM = ±0.5 V −60 dB Gain ΔV OUT, cm /ΔV OCM ; ΔV OCM = ±1 V 0.988 1 1.012 V/V POWER SUPPLY Operating Range ±1.4 ± 5.5 V Quiescent Current V DIN+ = V DIN− = V OCM = 0 V 10.5 11.5 12.5 mA T MIN to T MAX variation 25 μA/°C Power Supply Rejection Ratio ΔV OUT, dm /ΔV S ; ΔV S = ±1 V −70 −56 dB OPERATING TEMPERATURE RANGE−40 +125 °CAD8131Rev. B | Page 5 of 20±D IN TO ±OUT SPECIFICATIONS25°C, V S = 5 V , V OCM = 2.5 V , G = 2, R L, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 3.Parameter Conditions M in Typ Max Unit DYNAMIC PERFORMANCE −3 dB Large Signal Bandwidth V OUT = 2 V p-p 385 MHz −3 dB Small Signal Bandwidth V OUT = 0.2 V p-p 285 MHz Bandwidth for 0.1 dB Flatness V OUT = 0.2 V p-p 65 MHz Slew Rate V OUT = 2 V p-p, 10% to 90% 1600 V/μs Settling Time 0.1%, V OUT = 2 V p-p 18 ns Overdrive Recovery Time V IN = 5 V to 0 V Step 5 ns NOISE/HARMONIC PERFORMANCE Second Harmonic V OUT = 2 V p-p, 5 MHz, R L, dm = 200 Ω −67dBcV OUT = 2 V p-p, 20 MHz, R L, dm = 200 Ω −56 dBcV OUT = 2 V p-p, 5 MHz, R L, dm = 800 Ω −94 dBcV OUT = 2 V p-p, 20 MHz, R L, dm = 800 Ω −77 dBc Third Harmonic V OUT = 2 V p-p, 5 MHz, R L, dm = 200 Ω −74dBcV OUT = 2 V p-p, 20 MHz, R L, dm = 200 Ω −67 dBcV OUT = 2 V p-p, 5 MHz, R L, dm = 800 Ω −95 dBcV OUT = 2 V p-p, 20 MHz, R L, dm = 800 Ω −74 dBc IMD 20 MHz, R L, dm = 800 Ω −51 dBc IP3 20 MHz, R L, dm = 800 Ω 29dBm Voltage Noise (RTO) f = 20 MHz 25 nV/√Hz Differential Gain Error NTSC, R L, dm = 150 Ω 0.02 % Differential Phase Error NTSC, R L, dm = 150 Ω 0.08 degrees INPUT CHARACTERISTICS Input Resistance Single-ended input 1.125kΩ Differential input 1.5kΩ Input Capacitance 1 pF Input Common-Mode Voltage −1.0 to +4.0 V CMRR ΔV OUT, dm /ΔV IN, cm ; ΔV IN, cm = ±0.5 V −70 dB OUTPUT CHARACTERISTICS Offset Voltage (RTO) V OS, dm = V OUT, dm ; V DIN+ = V DIN− = V OCM = 2.5 V±3 ±7 mVT MIN to T MAX variation ±8 μV/°CV OCM = float ±4 mVT MIN to T MAX variation ±10 μV/°C Output Voltage Swing Maximum ΔV OUT ; single-ended output 1.0 to 3.7 V Linear Output Current 45 mA Gain ΔV OUT, dm /ΔV IN, dm ; ΔV IN, dm = ±0.5 V 1.96 2 2.04 V/V Output Balance Error ΔV OUT, cm /ΔV OUT, dm ; ΔV OUT, dm = 1 V −62dBAD8131Rev. B | Page 6 of 20V OCM TO ±OUT SPECIFICATIONS25°C, V S = 5 V , V OCM = 2.5 V , G = 2, R L, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 4.Parameter Conditions M in Typ Max UnitDYNAMIC PERFORMANCE−3 dB Bandwidth ΔV OCM = 600 mV 200 MHz Slew Rate V OCM = 1.5 V to 3.5 V 450V/μs DC PERFORMANCEInput Voltage Range 1.0 to 3.7 V Input Resistance 30kΩ Input Offset Voltage V OS, cm = V OUT, cm ; V DIN+ = V DIN− = V OCM = 2.5 V±5 ±12 mVV OCM = float ±10 mV Input Bias Current 0.5 μA V OCM CMRR ΔV OUT, dm /ΔV OCM ; ΔV OCM = 2.5 V ±0.5 V −60dB Gain ΔV OUT, cm /ΔV OCM ; ΔV OCM = 2.5 V ±1 V 0.985 1 1.015 V/V POWER SUPPLY Operating Range 2.7 11 V Quiescent Current V DIN+ = V DIN− = V OCM = 2.5 V9.25 10.25 11.25 mAT MIN to T MAX variation 20μA/°C Power Supply Rejection Ratio ΔV OUT, dm /ΔV S ; ΔV S = ±0.5 V−70 −56 dB OPERATING TEMPERATURE RANGE−40 +125 °CAD8131Rev. B | Page 7 of 20ABSOLUTE MAXIMUM RATINGSTable 5.1Parameter Rating Supply Voltage ±5.5 V V OCM ±V S Internal Power Dissipation 250 mW Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 10 sec) 300°C1Thermal resistance measured on SEMI standard 4-layer board. 8-lead SOIC: θJA = 121°C/W. 8-lead MSOP: θJA = 142°C/W.Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AMBIENT TEMPERATURE (°C)–502.01.51.0M A X I M U M P O W E R D I S S I P A T I O N (W )–20101001300.5407001072-044Figure 3. Plot of Maximum Power Dissipation vs. TemperatureESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performancedegradation or loss of functionality.AD8131Rev. B | Page 8 of 20PIN CONFIGURATION AND FUNCTION DESCRIPTIONSNC = NO CONNECT–D V +D IN NC V––OUT01072-003Figure 4. Pin ConfigurationTable 6. Pin Function DescriptionsPin No. Mnemonic Description 1 −D IN Negative Input.2 V OCMCommon-Mode Output Voltage. Voltage applied to this pin sets the common-mode output voltage with a ratio of 1:1. For example, 1 V dc on V OCM will set the dc bias level on +OUT and −OUT to 1 V.3 V+ Positive Supply Voltage.4 +OUT Positive Output. Note: the voltage at −D IN is inverted at +OUT.5 −OUT Negative Output. Note: the voltage at +D IN is inverted at −OUT.6 V− Negative Supply Voltage.7 NC No Connect.8 +D IN Positive Input.AD8131Rev. B | Page 9 of 20TYPICAL PERFORMANCE CHARACTERISTICSFigure 5. Basic Test Circuit12963–3G A IN (d B )FREQUENCY (MHz)01072-005Figure 6. Small Signal Frequency Response12963–3G A I N (dB )FREQUENCY (MHz)01072-006Figure 7. Small Signal Frequency Response12963–3G AI N (d B )FREQUENCY (MHz)01072-007Figure 8. Large Signal Frequency Response12963–3G A I N (d B )1101001000FREQUENCY (MHz)01072-008Figure 9. Large Signal Frequency ResponseFigure 10. Harmonic Distortion Test Circuit (R L, dm = 800 Ω)AD8131Rev. B | Page 10 of 20–50–60–70–80–90–100–110D I S T O R T I O N (d B c )40506070FREQUENCY (MHz)010203001072-010Figure 11. Harmonic Distortion vs. Frequency40506070FREQUENCY (MHz)0102030–40–50–60–70–80–100–110D I S T O R T I O N (d B c )–9001072-011Figure 12. Harmonic Distortion vs. Frequency–55–65–75–85–95–105–1153456DIFFERENTIAL OUTPUT VOLTAGE (V p-p)12D I S T O R T I O N (d B c )01072-012Figure 13. Harmonic Distortion vs. Differential Output Voltage–50–60–70–80–90–100–110D I S T O R T I O N (d B c )2.53.0 3.54.0DIFFERENTIAL OUTPUT VOLTAGE (V p-p)1.01.52.00.5001072-013Figure 14. Harmonic Distortion vs. Differential Output Voltage–50–60–70–80–90–100–110D I S T O R T I O N (d B c )1.25 1.51.75DIFFERENTIAL OUTPUT VOLTAGE (V p-p)0.75 1.00.500.2501072-014Figure 15. Harmonic Distortion vs. Differential Output Voltage–50–60–70–80–90–100–110D I S T O R T I O N (d B c )R LOAD (Ω)01072-015Figure 16. Harmonic Distortion vs. R LOADAD8131–50–60–70–80–90–100–110D I S T O R T I O N (d B c )R LOAD (Ω)01072-016Figure 17. Harmonic Distortion vs. R LOAD–50–60–70–80–90–100–110D I S T O R T I ON (d B c )7008009001000R LOAD (Ω)40050060030020001072-017Figure 18. Harmonic Distortion vs. R LOAD100–10–20–30–4049.550.050.5P O U T (d B m )FREQUENCY (MHz)–50–60–70–80–90–100–11001072-018Figure 19. Intermodulation Distortion45403530252015I N T ER C E P T (d B m )FREQUENCY (MHz)01072-019Figure 20. Third Order Intercept vs. Frequency01072-020Figure 21. Large Signal Transient Response01072-021Figure 22. Small Signal Transient ResponseAD813101072-022Figure 23. Large Signal Transient Response01072-023Figure 24. Large Signal Transient Response01072-024Figure 25. 0.1% Settling TimeFigure 26. Capacitor Load Drive Test Circuit01072-026Figure 27. Large Signal Transient Response for Various Capacitor Loads–10–20–30–40P S R R (d B )FREQUENCY (MHz)–50–60–70–8001072-027Figure 28. PSRR vs. FrequencyAD8131OUT, cm01072-028Figure 29. CMRR Test Circuit–20–30–40–50–60–70–801101001000CM R R (d B )FREQUENCY (MHz)01072-029Figure 30. CMRR vs. Frequency1001010.1110100I M P E D A N C E (Ω)FREQUENCY (MHz)01072-030Figure 31. Single-Ended Z OUT vs. FrequencyFigure 32. Output Balance Error Test Circuit–20–30–40–50–60–70–801101001000B A L A NC E E R R O R (d B )FREQUENCY (MHz)01072-032Figure 33. Output Balance Error vs. Frequency151311975S U P P L Y C U R R E N T (m A )–50–201040TEMPERATURE (°C)7010013001072-034Figure 34. Quiescent Current vs. TemperatureAD8131–20–30–40–50–60–70–801101001000C M R R (d B )FREQUENCY (MHz)–9001072-0371109070503010N O I S E (n V /√H z )0.1k1k 10k100k FREQUENCY (Hz)1M 10M 100M01072-035Figure 37. V OCM CMRR vs. FrequencyFigure 35. Voltage Noise vs. Frequency63–3–6–91101001000G A I N (d B )FREQUENCY (MHz)01072-03601072-038Figure 38. V OCM Transient ResponseFigure 36. V OCM Gain ResponseAD8131OPERATIONAL DESCRIPTIONR –OUT+OUT+D IN –D INV OCM 01072-039Figure 39. Circuit DefinitionsDifferential voltage refers to the difference between two node voltages. For example, the output differential voltage (or equivalently output differential-mode voltage) shown in Figure 39 is defined as()OUT OUT dm OUT V V V −+−=,V +OUT and V –OUT refer to the voltages at the +OUT and −OUT terminals with respect to a common reference.Common-mode voltage refers to the average of two node voltages. The output common-mode voltage is defined as()2,OUT OUT cm OUT V V V −++=Balance is a measure of how well differential signals arematched in amplitude and exactly 180 degrees apart in phase. Balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes andcomparing the magnitude of the signal at the divider’s midpoint with the magnitude of the differential signal. By this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential-mode voltage.dmOUT cm OUT V V Error Balance Output ,,=AD8131THEORY OF OPERATIONThe AD8131 differs from conventional op amps in that it has two outputs whose voltages move in opposite directions. Like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. TheAD8131 behaves much like a standard voltage feedback op amp and makes it easy to perform single-ended-to-differential conversion, common-mode level-shifting, and amplification of differential signals.Previous discrete and integrated differential driver designs used two independent amplifiers and two independent feedback loops, one to control each of the outputs. When these circuits are driven from a single-ended source, the resulting outputs are typically not well balanced. Achieving a balanced output typically required exceptional matching of the amplifiers and feedback networks.DC common-mode level shifting has also been difficult with previous differential drivers. Level shifting required the use of a third amplifier and feedback loop to control the output common-mode level. Sometimes the third amplifier has also been used to attempt to correct an inherently unbalanced circuit. Excellent performance over a wide frequency range has proven difficult with this approach.The AD8131 uses two feedback loops to separately control the differential and common-mode output voltages. The differential feedback, set by internal resistors, controls only the differential output voltage. The common-mode feedback controls only the common-mode output voltage. This architecture makes it easy to arbitrarily set the common-mode output level. It is forced, by internal common-mode feedback, to be equal to the voltage applied to the V OCM input, without affecting the differential output voltage.The AD8131 architecture results in outputs that are very highly balanced over a wide frequency range without requiring external components or adjustments. The common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. The result is nearly perfectly balanced differential outputs, of identical amplitude and exactly 180 degrees apart in phase.ANALYZING AN APPLICATION CIRCUITThe AD8131 uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. The differential error voltage is defined as the voltage between the differential inputs labeled +IN and −IN inFigure 39. For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to V OCM can also be assumed to be zero. Starting from these two assumptions, any application circuit can be analyzed.CLOSED-LOOP GAINThe differential mode gain of the circuit in Figure 39 can be described by the following equation:2==GFdmIN,dmOUT,RRVVwhere R F = 1.5 kΩ and R G = 750 Ω nominally. ESTIMATING THE OUTPUT NOISE VOLTAGE Similar to the case of a conventional op amp, the differential output errors (noise and offset voltages) can be estimated by multiplying the input referred terms, at +IN and −IN, by the circuit noise gain. The noise gain is defined as31=⎟⎟⎠⎞⎜⎜⎝⎛+=GFN RRGThe total output referred noise for the AD8131, including the contributions of R F, R G, and op amp, is nominally 25 nV/√Hz at 20 MHz.CALCULATING THE INPUT IMPEDANCE OF AN APPLICATION CIRCUITThe effective input impedance of a circuit such as that in Figure 39, at +D IN and −D IN, will depend on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, the input impedance (R IN, dm) between the inputs (+D IN and −D IN) isΩ=×=k5.12,GdmINRRIn the case of a single-ended input signal (for example if −D IN is grounded and the input signal is applied to +D IN), the input impedance becomes()Ω=⎟⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎜⎝⎛+×−=k125.121,FGFGdmINRRRRRThe input impedance is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor R G.AD8131INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE-SUPPLY APPLICATIONSThe AD8131 is optimized for level-shifting ground referenced input signals. For a single-ended input this would imply, for example, that the voltage at −D IN in Figure 39 would be zero volts when the amplifier’s negative power supply voltage (at V−) was also set to zero volts.SETTING THE OUTPUT COMMON-MODE VOLTAGE The AD8131’s V OCM pin is internally biased at a voltage approximately equal to the midsupply point (average value of the voltages on V+ and V−). Relying on this internal bias results in an output common-mode voltage that is within about 25 mV of the expected value. In cases where more accurate control of the output common-mode level is required, it is recommended that an external source, or resistor divider (made up of 10 kΩ resistors), be used. DRIVING A CAPACITIVE LOADA purely capacitive load can react with the pin and bondwire inductance of the AD8131 resulting in high frequency ringing in the pulse response. One way to minimize this effect is to place a small resistor in series with the amplifier’s outputs as shown in Figure 26.AD8131 APPLICATIONSTWISTED-PAIR LINE DRIVERThe AD8131 has on-chip resistors that provide for a gain of 2 without any external parts. Several on-chip resistors are trimmed to ensure that the gain is accurate, the common-mode rejection is good, and the output is well balanced. This makes the AD8131 very suitable as a single-ended-to-differential twisted-pair line driver.Figure 40 shows a circuit of an AD8131 driving a twisted-pair line, like a Category 3 or Category 5 (Cat3 or Cat5), that is already installed in many buildings for telephony and data communications. The characteristic impedance of such a transmission line is usually about 100 Ω. The outstanding balance of the AD8131 output will minimize the common-mode signal and therefore the amount of EMI generated by driving the twisted pair.The two resistors in series with each output terminate the line at the transmit end. Since the impedances of the outputs of the AD8131 are very low, they can be thought of as a short-circuit, and the two terminating resistors form a 100 Ω termination at the transmit end of the transmission line. The receive end is directly terminated by a 100 Ω resistor across the line.This back-termination of the transmission line divides the output signal by two. The fixed gain of 2 of the AD8131 will create a net unity gain for the system from end to end.In this case, the input signal is provided by a signal generator with an output impedance of 50 Ω. This is terminated with a 49.9 Ω resistor near +D IN of the AD8131. The effective parallel resistance of the source and termination is 25 Ω.The 24.9 Ω resistor from −D IN to ground matches the +D IN source impedance and minimizes any dc and gain errors.If +D IN is driven by a low-impedance source over a short distance, such as the output of an op amp, then no termination resistor is required at +D IN. In this case, the −D IN can be directly tied to ground.Figure 40. Single-Ended-to-Differential 100 Ω Line Driver 3 V SUPPLY DIFFERENTIAL A-TO-D DRIVERMany newer ADCs can run from a single 3 V supply, which can save significant system power. In order to increase the dynamic range at the analog input, they have differential inputs, which double the dynamic range with respect to a single-ended input. An added benefit of using a differential input is that the distortion can be improved.The low distortion and ability to run from a single 3 V supply make the AD8131 suited as an A-to-D driver for some 10-bit, single-supply applications. Figure 41 shows a schematic for a circuit for an AD8131 driving an AD9203, a 10-bit, 40 MSPS ADC.The common mode of the AD8131 output is set at midsupply by the voltage divider connected to V OCM, and ac-bypassed with a 0.1 μF capacitor. This provides for maximum dynamic range between the supplies at the output of the AD8131. The 110 Ω resistors at the AD8131 output, along with the shunt capacitors form a one pole, low-pass filter for lowering noise and antialiasing.0.1F172-41 Figure 41. Test Circuit for AD8131 Driving an AD9203, 10-Bit, 40 MSPS ADC Figure 42 shows an FFT plot that was taken from the combined devices at an analog input frequency of 2.5 MHz and a 40 MSPS sampling rate. The performance of the AD8131 compares very favorably with a center-tapped transformer drive, which has typically been the best way to drive this ADC. The AD8131 has the advantage of maintaining dc performance, which a transformer solution cannot provide.。