单片机外文文献翻译--基于MSP430的FSK调制解调
单片机外文翻译—基于MSP430F149单片机实现的步进电机通用控制器
Step of electric machine universal controller realizes which based on the MSP430F149 Single Chip Microcomputer.Abstract:With the infiltration in the social field of the computer in recent years, the application of the one-chip computer is moving towards deepening constantly, drive tradition is itmeasure crescent benefit to upgrade day to control at the same time. In measuring in real time andautomatically controlled one-chip computer application system, the one-chip computer often usesas a key part, only one-chip computer respect knowledge is not enough, should also follow thestructure of the concrete hardware , and direct against and use the software of target'scharacteristic to combine concretely, in order to do perfectly.This article mainly introduced realizes a step of machine universal controller based on the MSP430F149 monolithic integrated circuit. This controller may simultaneously control the multi-tablecloths machine according to the curve way movement, including adds and subtracts fast, the localization and the commutation function and so on. In the article discussed with emphasis step machine has risen to low the speed and the curve design proposal and its the realization method.1. a preface:based on the step of machine control system, except step machine generally also needs the special actuation power source, actuates the power source merely to complete the power actuation part, the user certainly cannot cause the entire control system according to prearrange, the expectation active status movement, must control to its actuation power source, the user needs to develop once more.In view of this, has designed a step of machine universal controller which realizes based on the MSP430F149 monolithic integrated circuit, may satisfy the majority controllingfield originally request. The controller main function is:(1) May control the multi- wraps step of machine actuation system; At present may simultaneously control 3 sets of systems.(2) work way is flexible, may according to the hypothesis curve movement, the curve most reach 8 sections; May according to the control signal movement which exterior examines; May according to the simulation adjustment test function movement;2. Systems designs2.1 systems structureThis controller has mainly realized thematic- tablecloths machine in the multistage curve operating control.2.2 microprocessors choiceThis design has selected MSP which Incorporation produces series monolithic integrated circuit MSP430F149.The goal is applies its rich connection resources and the formidable timer function, the MSP430F149 performance characteristic as follows:(1) 6 eight bit parallel connections; Definitely may realize this system all signals input, the output, does not need the hardware to expand, P1, the P2 eight bit parallel ports each mouth line all has the severance function, softly causes the keyboard, the hardware design to change is extremely simple.(2) 12 A/D switch ADC; Completes the simulation hypothesis function.(3) Formidable timer function; TIMER-A3, TIMER-B7 respectively be have3 and 7 captures/compares the register 16 timers, may satisfy the system speed the hypothesis and the curve fixed time request.(4)Liquid crystal actuation module;(5) In sets at 2KB RAM, 60KB FLASH;MSP430F149 provides the rich resources, the periphery hardware expands only must do thevery few work, not only designs changes extremely imply, and moreover this controller volume small, the reliability is high.2.3 steps of machine starting and add/decelerate the control planThe step of motive highest starting frequency (step frequency) generally is 0.1KHz arrives 3-4KHz, but the highest movement frequency may achieve N*102 KHz. Surpasses the highest starting frequency the frequency direct-on starting, will appear\" Falls out of step \" Phenomenon, even is unable to start.The more ideal starting curve should be according to the index rule starting. But the practical application to starts the section processing to be possible to use according to the fitting a straight Line method, namely \" Steps and ladders law \”. May according to two kind of situations processing, (1) known frequency press the frequency partition to start, the partition counts n=f/f q.(2) Unknown frequency, then to assigns according to the section. Uses \" Steps and ladders law \" Continuously raises the speed the speed which needs, then locking, according to pre-placed curve movement. Fitting the starting frequency, after each section of frequencies hand over the increase (to call steps and ladders frequency) △f=f/8, namely uses 8 sections of fitting. In the operating control process, (frequency) divides into the outset speed n minute achievement steps and ladders frequency, When 2.4 steps of machine commutation questions step of machine commutation, certainly must stop in the electrical machinery or fall commutates again to the frequency range in, in order to avoid has a bigger impact to damage the electrical machinery. The commutation signal certainly must last the CP pulse finish after the preceding direction as well as in front of the next direction first CP pulse sends out.2.4 steps of machine commutation questionsStep of machine commutation, certainly must stop in the electrical machinery or fall commutates again to the frequency range in, in order to avoid has a bigger impact to damage the electrical machinery. The commutation signal certainly must last the CP pulse finish after the preceding direction as well as in front of the next direction first CP pulse sent out in some highspeed under, the reverse cut essence has contained -> the commutation -> three processes2.5 speeds and the timer starting value transformationThis system speed control is the dependence fixed time produces; the hypothesis speed which the CP pulse completes with has the CP pulse timer starting value to have the certain relations. The MSP430F149 timer work way has many kinds of, this design timer work under continual way. In the continual pattern, the timer starts from its current value to count, after counts to 0FFFFH from \" 0\" Starts redo count. Under this way, compares the timer current value and comparison register CCRX, if equal has the severance, and May the time which has the next event add to in this interrupt service is on comparison register CCRX.Fixed time the starting value = must fixed time the value/count the cycle; Often assigns regarding the step of machine its speed value by the frequency form, such as movement under 20KHZ, therefore the previous type may transform is: Fixed time the starting value = counts the frequency/speed value. (Counts frequency for system clock frequency)3. ConcludingRemark this controller may realize step machine under the multistage hypothesis curve operating control, has the hardware simply, the reliable high characteristic, has used in on the electric wire production line platoon line control section it, has obtained the satisfying effect. This topic funds the project for the north industry big school scientific research foundation.译文译文基于MSP430F149单片机实现的步进电机通用控制器。
FSK调制及解调实验报告
FSK调制及解调实验报告FSK调制及解调实验报告一、实验目的1.深入理解频移键控(FSK)调制的基本原理和特点;2.掌握FSK调制和解调的实验方法和技能;3.通过实验观察和分析FSK调制解调的性能和应用。
二、实验原理频移键控(Frequency Shift Keying,FSK)是一种常见的数字调制方法,它利用不同频率的信号代表二进制数据中的“0”和“1”。
在FSK调制中,输入信号被分为两种频率,通常表示为f1和f2,分别对应二进制数据中的“0”和“1”。
FSK调制的基本原理是将输入的二进制数据序列通过频率切换的方式转换为高频信号序列。
具体来说,当输入数据为“0”时,选择频率为f1的信号进行传输;当输入数据为“1”时,选择频率为f2的信号进行传输。
解调过程中,接收端将收到的混合信号进行滤波处理,根据不同的频率将其分离,再通过低通滤波器恢复出原始的二进制数据序列。
三、实验步骤1.FSK调制过程(1) 将输入的二进制数据序列通过串并转换器转换为并行数据序列;(2) 利用FSK调制器将并行数据序列转换为FSK信号;(3) 通过高频信道发送FSK信号。
2.FSK解调过程(1) 通过高频信道接收FSK信号;(2) 利用FSK解调器将FSK信号转换为并行数据序列;(3) 通过并串转换器将并行数据序列转换为原始的二进制数据序列。
四、实验结果与分析1.FSK调制结果与分析在FSK调制实验中,我们选择了两种不同的频率f1和f2分别表示二进制数据中的“0”和“1”。
通过对输入的二进制数据进行FSK调制,我们成功地将原始的二进制数据转换为FSK信号,并可以通过高频信道进行传输。
在调制过程中,我们需要注意信号转换的准确性和稳定性,以确保传输的可靠性。
2.FSK解调结果与分析在FSK解调实验中,我们首先接收到了通过高频信道传输过来的FSK信号,然后利用FSK解调器将信号转换为并行数据序列。
最后,通过并串转换器将并行数据序列恢复为原始的二进制数据序列。
FSK调制解调实验报告
FSK调制解调实验报告实验报告:FSK调制解调引言:FSK (Frequency Shift Keying)调制解调是一种将数字信号转换为模拟信号的调制技术,通过改变信号的频率来表示数字信息。
FSK调制解调器在通信系统中起着重要的作用,因此,理解FSK调制解调原理并进行实验验证是非常有意义的。
实验目的:1.理解FSK调制解调原理。
2.使用软件(如MATLAB)进行FSK调制解调仿真。
3.通过硬件电路搭建进行FSK调制解调实验。
实验原理:FSK解调:FSK解调器将接收到的数字信号转换为模拟信号,并检测信号的频率以恢复原始的二进制序列。
解调器通过比较两个频率的能量来确定输入信号的频率,然后根据已知的频率对照表将其转换为对应的二进制数字。
实验步骤:1.使用软件(如MATLAB)进行FSK调制仿真:a.设计一个数据源,例如一个随机生成的二进制序列。
b.将二进制序列转换为FSK调制信号,即将0转换为低频率信号,将1转换为高频率信号。
c.添加噪声以模拟真实通信环境。
d.绘制调制后的信号波形。
2.使用软件进行FSK解调仿真:a.使用接收到的调制信号作为输入信号。
b.设计一个解调器来检测信号的频率以恢复原始的二进制序列。
c.绘制解调后的信号波形,并与原始信号进行比较。
3.使用硬件电路进行FSK调制解调测试:a.搭建FSK调制电路,将输入的二进制序列转换为FSK信号。
b.使用示波器观察调制后的信号波形。
c.搭建FSK解调电路,将接收到的调制信号转换为原始的二进制序列。
d.使用示波器观察解调后的信号波形,并与原始信号进行比较。
实验结果与分析:通过软件仿真可以得到调制后的信号波形,并通过解调获得原始的二进制序列。
这些结果可以与原始输入信号进行比较,以验证FSK调制解调的准确性。
通过硬件电路测试,可以观察到调制后的信号波形以及解调后的信号波形,进一步验证了FSK调制解调的可行性。
结论:通过FSK调制解调实验,我们可以更好地理解FSK调制解调的原理,并通过软件仿真和硬件搭建实验来验证其可行性。
基于FPGA的FSK调制解调器的设计
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所谓的2FSK就是有两个载波信号,分别对应基带信号的0、1,对于 所谓的2FSK就是有两个载波信号,分别对应基带信号的0、1,对于 具体的如何对应,并没有明确地要求,只要保持调制和解调的对应关系一 具体的如何对应,并没有明确地要求,只要保持调制和解调的对应关系 样便可以实现正确的解调,如下是我设计的 2FSK调制器的实际设计原理框 一样便可以实现正确的解调,如下是我设计的2FSK调制器的RTL图。 图。
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FSK调制解调实验报告
FSK调制解调实验报告实验报告:FSK调制解调实验一、实验目的FSK调制解调是数字通信中常用的调制解调方式之一,通过本次实验,我们学习FSK调制解调的原理、实现方法和实验技巧,理解其在数字通信中的应用。
同时,通过实验验证FSK调制解调的正确性和稳定性,并掌握实验数据的分析和处理方法。
二、实验原理FSK调制在信号传输中广泛应用,其原理是将数字信号调制成两个不同的频率信号,通常用0和1两个数字分别对应两个不同的频率。
在调制端,通过将0和1信号分别转换成相应的频率信号,并通过切换不同的载波波形来实现不同频率信号的调制。
在解调端,通过将接收到的调制信号分别和两个对应的参考频率信号进行相关运算,从而还原出原始的0和1信号。
实验所需材料:1.FSK调制解调器2.函数发生器3.示波器4.电缆和连接线实验步骤:1.将函数发生器的输出信号接入FSK调制器的MOD输入端,调整函数发生器的频率和幅度,使其适配FSK调制器的输入端。
2.调整FSK调制器的MOD输入切换开关,选择合适的调制波形(常用的有正弦波和方波两种)。
3.通过示波器观察和记录已调制的FSK信号波形。
4.将已调制的信号通过电缆传输到解调器端。
5.调整解调器的参考频率和解调器的解调方式。
6.通过示波器观察和记录解调器输出的数字信号波形。
7.将解调输出与调制前的原始信号进行比较,验证FSK调制解调的正确性。
三、实验结果和数据分析根据实验步骤的指导,我们依次完成了FSK调制解调的实验,在观察示波器上的波形时,我们发现调制波形的频率随着输入数据的0和1的变化而变化,已达到我们的预期效果。
在解调端,我们观察到解调输出的数字信号与调制前的原始信号一致,由此可验证FSK调制解调的正确性。
对于实验数据的分析和处理,我们应注意以下几点:1.频率的选择:合适的调制频率和解调频率能够保证调制解调的稳定和正确性,应根据具体情况进行选择。
2.调制波形的选择:正弦波和方波是常见的调制波形,两者各有优缺点,可根据实际需要进行选择。
毕业设计 MSP430混合信号微控制器 外文文献及翻译
本科毕业设计外文文献及译文文献、资料题目:MPS430 Mixed Signal Microcontroller 文献、资料来源:期刊(著作、网络等)文献、资料发表(出版)日期:2005.3.25学院:信息与电气工程学院专业:通信工程班级:通信姓名:学号:2006081060指导教师:翻译日期:2010.4.8外文文献:MSP430 MIXED SIGNAL MICROCONTROLLER _ Low Supply-Voltage Range, 1.8 V . . . 3.6 V_ Ultralow-Power Consumption:− Active Mode: 330μA at 1 MHz, 2.2 V− Standby Mode: 1.1μA− Off Mode (RAM Retention): 0.1μA_ Five Power-Saving Modes_ Wake-Up From Standby Mode in less than 6μs_ 16-Bit RISC Architecture, 125-ns Instruction Cycle Time_ Three-Channel Internal DMA_ 12-Bit A/D Converter With InternalReference, Sample-and-Hold and Autoscan Feature_ Dual 12-Bit D/A Converters With Synchronization_ 16-Bit Timer_A With Three Capture/Compare Registers_ 16-Bit Timer_B With Three or Seven Capture/Compare-With-Shadow Registers _ On-Chip Comparator_ Serial Communication Interface (USART0), Functions as Asynchronous UART or Synchronous SPI or I2CTM Interface_ Serial Communication Interface (USART1), Functions as Asynchronous UART or Synchronous SPI Interface_ Supply Voltage Supervisor/Monitor With Programmable Level Detection_ Brownout Detector_ Bootstrap Loader_ Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by SecurityFuse_ Family Members Include:− MSP430F155:16KB+256B Flash Memory512B RAM− MSP430F156:24KB+256B Flash Memory1KB RAM− MSP430F157:32KB+256B Flash Memory,1KB RAM− MSP430F167:32KB+256B Flash Memory,1KB RAM− MSP430F168:48KB+256B Flash Memory,2KB RAM− MSP430F169:60KB+256B Flash Memory,2KB RAM− MSP430F1610:32KB+256B Flash Memory5KB RAM− MSP430F1611:48KB+256B Flash Memory10KB RAM− MSP430F1612:55KB+256B Flash Memory5KB RAM_ Available in 64-Pin Quad Flat Pack (QFP) and 64-pin QFN (see Available Options) _ For Complete Module Descriptions, See the MSP430x1xx Family User’s Guide, Literature Number SLAU049descriptionThe Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6μs.The MSP430x15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bitA/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), I2C, DMA, and 48 I/O pins. In addition, the MSP430x161x series offersextended RAM addressing for memory-intensive applications and large C-stack requirements. Typical applications include sensor systems, industrial control applications, hand-held meters, etc.MSP430F169 MIXED SIGNAL MICROCONTROLLERshort-form descriptionCPUThe MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.instruction setThe instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.operating modesThe MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.The following six operating modes can be configured by software:_ Active mode AM;− All clocks are active_ Low-power mode 0 (LPM0);− CPU is disabledACLK and SMCLK remain active. MCLK is disabled_ Low-power mode 1 (LPM1);− CPU is disabledACLK and SMCLK remain active. MCLK is disabledDCO’s dc-generator is disabled if DCO not used in active mode_ Low-power mode 2 (LPM2);− CPU is disabledMCLK and SMCLK are disabledDCO’s dc-generator remains enabledACLK remains active_ Low-power mode 3 (LPM3);− CPU is disabledMCLK and SMCLK are disabledDCO’s dc-generator is disabledACLK remains active_ Low-power mode 4 (LPM4);− CPU is disabledACLK is disabledMCLK and SMCLK are disabledDCO’s dc-generator is disabledCrystal oscillator is stoppedinterrupt vector addressesThe interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence special function registersMost interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.interrupt enable 1 and 2WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected.Active if watchdog timer is configured as general-purpose timer.OFIE: Oscillator-fault-interrupt enableNMIIE: Nonmaskable-interrupt enableACCVIE: Flash memory access violation interrupt enableURXIE0: USART0: UART and SPI receive-interrupt enableUTXIE0: USART0: UART and SPI transmit-interrupt enableURXIE1 : USART1: UART and SPI receive-interrupt enableUTXIE1 : USART1: UART and SPI transmit-interrupt enableURXIE1 and UTXIE1 are not present in MSP430x15x devices.interrupt flag register 1 and 2WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation Reset on VCC power-on, or a reset condition at the RST/NMI pin in reset mode OFIFG: Flag set on oscillator faultNMIIFG: Set via RST/NMI pinURXIFG0: USART0: UART and SPI receive flagUTXIFG0: USART0: UART and SPI transmit flagURXIFG1 : USART1: UART and SPI receive flagUTXIFG1 : USART1: UART and SPI transmit flagmodule enable registers 1 and 2URXE0: USART0: UART mode receive enableUTXE0: USART0: UART mode transmit enableUSPIE0: USART0: SPI mode transmit and receive enableURXE1 : USART1: UART mode receive enableUTXE1 : USART1: UART mode transmit enableUSPIE1 : USART1: SPI mode transmit and receive enableURXE1, UTXE1, and USPIE1 are not present in MSP430x15x devices.flash memoryThe flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:_ Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size._ Segments 0 to n may be erased in one step, or each segment may be individually erased._ Segments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory._ New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use.peripheralsPeripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family Use r’s Guide, literature number SLAU049.DMA controllerThe DMA controller allows movement of data from one memory address to another without CPU intervention.For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.oscillator and system clockThe clock system in the MSP430x15x and MSP430x16x(x) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The basic clock module provides the following clock signals:_ Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. _ Main clock (MCLK), the system clock used by the CPU._ Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. brownout, supply voltage supervisorThe brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).digital I/OThere are six 8-bit I/O ports implemented—ports P1 through P6:_ All individual I/O bits are independently programmable._ Any combination of input, output, and interrupt conditions is possible._ Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2._ Read/write access to port-control registers is supported by all instructions.watchdog timerThe primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.hardware multiplier (MSP430x16x/161x Only)The multiplication operation is supported by a dedicated peripheral module. The module performs 16_16, 16_8, 8_16, and 8_8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.peripheralsPeripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049.DMA controllerThe DMA controller allows movement of data from one memory address to another without CPU intervention.For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.oscillator and system clockThe clock system in the MSP430x15x and MSP430x16x(x) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than6μs. The basic clock module provides the following clock signals:_ Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. _ Main clock (MCLK), the system clock used by the CPU._ Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. brownout, supply voltage supervisorThe brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision(the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).digital I/OThere are six 8-bit I/O ports implemented—ports P1 through P6:_ All individual I/O bits are independently programmable._ Any combination of input, output, and interrupt conditions is possible._ Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2._ Read/write access to port-control registers is supported by all instructions.watchdog timerThe primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.hardware multiplier (MSP430x16x/161x Only)The multiplication operation is supported by a dedicated peripheral module. The module performs 16_16, 16_8, 8_16, and 8_8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles arerequired.USART0The MSP430x15x and the MSP430x16x(x) have one hardware universalsynchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered transmit and receive channels.The I2C support is compliant with the Philips I2C specification version 2.1 and supports standardmode (up to 100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported, as well as master and slave modes. The USART0 also supports 16-bit-wide I2C data transfers and has two dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I2C mode.USART1 (MSP430x16x/161x Only)The MSP430x16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit (USART1) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. With the exception of I2C support, operation of USART1 is identical to USART0.timer_A3Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.timer_B3 (MSP430x15x Only)Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.timer_B7 (MSP430x16x/161x Only)Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.comparator_AThe primary function of the comparator_A module is to support precision slopeanalog−to−digital conversions, battery−voltage supervision, and monitoring of external analog signals.ADC12The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 wordconversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.DAC12The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.中文译文:MSP430混合信号微控制器●低供电电压范围:1.8V…3.6V●超低功耗:-活动模式:1MHz,2.2V 时为280μA-等待模式:1.6μA-关闭模式(RAM 保持):0.1μA●五种省电模式●6μS 内从等待状态唤醒●16 位精简指令结构,125 纳秒指令时间周期●三个内部DMA 通道●具有内部参考电平、采样保持和自动扫描特性的12 位A/D 转换器●同步的双12 位D/A 转换器●带有三个捕捉/比较寄存器的16 位定时器A●带有三个或七个捕捉/比较影子寄存器的16 位定时器B●片内集成比较器●串行通讯接口(USART1),具有异步UART 或者同步SPI 接口的功能●串行通讯接口(USART0),具有异步UART 或者同步SPI 或者I2C 接口●具有可编程电平检测的供电电压管理器/监视器●欠电压检测器●串行在线编程,无需外部编程电压,可编程的安全熔丝代码保护●Bootstrap Loader●器件系列包括:-MSP430F155:16KB+256B flash 存储器512B RAM-MSP430F156:24KB+256B flash 存储器1KB RAM-MSP430F157:32KB+256B flash 存储器1KB RAM-MSP430F167:32KB+256B flash 存储器1KB RAM-MSP430F168:48KB+256B flash 存储器2KB RAM-MSP430F169:60KB+256B flash 存储器2KB RAM-MSP430F1610:32KB+256B flash 存储器5KB RAM-MSP430F161148KB+256B flash 存储器;10KB RAM●64 引脚Quad Flat Pack(QFP)封装●要获得完整的模块描述参见MSP430x1xx 系列用户手册,文献号SLAU049说明德州仪器公司的MSP430 系列超低功耗微控制器,由针对各种不同应用目标具有不同外围设备的芯片系列组成。
毕业论文外文翻译--基于MSP430F149单片机的最小系统设计及其应用
毕业设计外文资料翻译题目基于MSP430F149单片机的时钟设计专业机械设计制造及其自动化班级学生学号指导教师SmartGrid,2013,3,91-95doi:10.12677/sg.2013.33016Published Online June 2013Based on MSP430F149 SCM smallest system designand applicationByAE TuumlDepartment of Mechanical and Electronic Engineering, CollegeChina University of Geosciences,430200Abstract:Single chip microcomputer minimum system, or the minimum application system, refers to the element with the least amount of single-chip microcomputer system can work. For the single chip MSP430 series Machine, the smallest system generally includes: single chip microcomputer, the power supply module, crystal vibration module, reset circuit module, JTAG interface circuit. This paper introduces the MSP430F149 single the characteristics of the machine and the minimum system based on MSP430F149 MCU design and its application, and introduces the composition and function of each module. Include digital tube display module, The LED display module, LCD liquid crystal display module, eight independent keyboard and other circuit module and extended application. The minimum system can download, online simulation and debugging, Proved by the experiment principle of correct and reliable, and can be widely used in teaching, scientific research and electronic design field. By loading the corresponding modules can be made into useful products, has the very great practicality.Keywords: MSP430; smallest system; circuit design; simulation; testBased on MSP430F149 SCM smallest system designand applicationIntroductionWith the rapid development of modern electronic technology and computer technology, microcontroller technology has penetrated into every aspect of human life, in automation, intelligent instrumentation, process control and increasing use of household appliances and many other fields, microcontroller family is becoming more and more big, more and more varieties, and in technology have distinguishing feature each, Texas instruments (TI) new MSP430F149 Single-chip low power consumption, powerful, for the majority of hardware designers.Single-chip microcomputer with necessary external device, generally including power supply into the power switch, reset circuit, crystals, input and output circuit can constitute a minimum system, such as simple structureMSP430F149 chip has 60 KB FLASH + 256 bytes, 2 karma, including the basic clock module, the watchdog timer, with three capture/compare registers and PWM output 16-bit timers, with seven capture/compare registers and PWM output, two 16 bit timer interrupt function of 8 bits parallel port, four 8-bit parallel port, analog comparator, 12 bit A/D converter, and the two serial communication interface module, etc. MSP430F149 chip has the following characteristics:(1) Low power consumption, voltage of 2.2 V, 1 MHZ clock frequency, the current activity pattern chip is 200 mu A, closed mode current is only 0.1 A;(2) Efficient 16-bit RISC CPU, 27 instruction, 8 MHZ clock frequency, the instruction cycle time Of 125 ns, the vast majority of instructions completed in one clock cycle;(3) Low voltage power supply, wide working voltage range: 1.8 ~ 3.6 V;(4)Flexible clock system: two external clock and an internal clock; (5)Low clock frequency can realize high-speed communication; (6) With serial online programming ability;(7) interrupt functions; (8) wake up time is short, wake up just from the low power mode6 mu s; (9) ESD protection, strong anti-interference; (10) fan running environment temperature - 40 ~ + 85 ℃, suitable for the industrial environment.Of all peripheral modules MSP430 series MCU control is achieved through special registers, so it is relatively easy to write. When programming development through the special programmer, you can choose to assembly or C language programming, IAR for MSP430 series MCU development the company dedicated C430 languages, can directly by the WORKBENCH and C - SPY compiler debugging, using flexible and simple.1 The minimum system designMinimum system is a necessary to ensure reliable processors work of basic circuit, including power supply module, the module of crystal vibration and reset circuit module, JTAG interface circuit, display module, etc1.1 The power supply moduleThis system need to use the + 5 V and + 3.3 V dc regulated power supply; including MSP430Fl49 and some peripheral devices need to + 3.3 V power supply, the other part need to + 5 V power supply. In this system, in order to + 5 V dc voltage for the input voltage, 3.3 V + linear step-down directly by the + 5 V.1.2 Crystal vibration moduleMSP430 series MCU clock module includes numerical control oscillator (DCO), high-Speed of crystal oscillator and crystal oscillator at low speed clock source. This is to understand System of rapid processing data and low power requirements of contradiction, through the design multiple clock source or for clock design all sorts of different working mode, can solve some Peripheral parts clock requirements of real-time applications, such as low frequency communication, LCD display, timing Device, counter, etc. Digital control oscillator DCO is integrated within the MSP430, in the system need to design high speed crystal oscillator and the low speed crystalLow-speed crystal oscillator (L X F T L) can meet the requirements of low power consumption and the use of 32.768 kHz crystal vibration. Default LFXTL oscillator work in low frequency mode, the 32.768 kHz, but can be by external 450 kHz ~ 8 MHZ crystal vibration at a high speed Oscillation device or ceramic resonator working in high frequency mode, in this system using low frequency mode Type, crystals external 2 33 PF capacitor after XIN and XOUT connected to the MCU. High-speed chip, also known as the second oscillator XT2, it in working for the MSP430F149High frequency mode provides a clock, XT2 up to 8 MHZ. XT2 adopted in the system4 MHZ crystal, XT2 external 2 33 PF capacitor after XT2IN and XT2OUT connection To the MCU.1.3 Reset circuit moduleManual reset is minimal systems commonly used functions, this system adopts the manual reset button switches and RC circuit implementation, the circuit structure is simple.1.4 The JTAG interface circuitJTAG technology is a kind of embedded debugging technology, chip internal encapsulates the special electrical test TAP (test access port), through special JTAG test tools to test and control of internal nodes, At present most of the ARM device support JTAG protocol, standard JTAG interface is 4 line; TMS (test mode selection), TCK (the clock) and TDI (test data serial input), TDO serial output (test data). JTAG interface connection there are two standards that 14 needle JTAG interface MC9328MX1 connection circuit. Is used here consists of three state output 74 hc244d eight-way buffer of 14 needle JTAG interface circuit.2 Application circuit design based on minimum system2.1 digital tube display moduleA digital tube display need 74 hc164 drive, 74 hc164 serial input and parallel output. Its parallel output actually there is a delay, just delay time is small, can be considered as parallel output. Here is the way a serial port 0, 0 is and communication of the shift register. TXD, RXD at this time is not like other ways a send, a receiver, but RXD can also input, output TXD shift pulse.Sending and receiving data must be 8, bit rate fixed is 1/12 of the crystals. When set mode 0, it is automatically put the TXD make shift pulse. In detecting RXD TXD high levels, if high level 74 hc164 study into 1, if it is a low level, enter 0.Receiving process: REN first to buy 1, then 1 TXD, read RXD condition, high level will receive 1, receive low level 0; Then pull down the TXD, after a slight delay TXD again high, read RXD, high level will receive 1, low level 0, and so on.Read until 8 bits. Send SBUF process: is sent automatically. Send 1 RXD high first, TXD again get higher; And TXD become low, send 0 RXD lower first, TXD again get higher; Then the TXD become low, and so on. This process is done automatically, need not special programming. Digital tube look from the front, the decimal point in the lower right foot, the pin above from left to right are respectively under the public side of A and B, F, G of pins from left to right, respectively, E, C, common (decimal).2.2 The LED display modulePick up a few LED through the I/O port, through the programming a simple program, which can realize the LED flashing, so as to achieve the test circuit and chip is normal.2.3 D/A conversion moduleMSP430F149 MCU with 12 bit A/D converter, but no D/A conversion, need external D/A conversion circuit. So choose DAC0832 d/a conversion chip, and UA741 high-gain general amplifier composed of d/a conversion circuit operation. UA741 chip pins as shown in figure 1.DAC0832 is 8 of D/A conversion chip. Complete compatible with microprocessor. The DA chip with its low cost, simple interface, convert the advantages of easy control, widely used in the MCU application system. D/A converter by eight input latch, 8-bit DAC registers, 8 D/A conversion circuit and control circuit.DAC0832 is sampling frequency for 8 D/A conversion chip,Integrated circuit has two levels of input register, DAC0832 chip with double buffer, single buffer and through three kinds of input methods, in order to fit for the needs of the various circuit (such as requirement asynchronous input, synchronous multi-channel D/A conversion, etc.). The 8 bit D/A converter has eight input end (where each input is one of 8 bit binary number), has an analog output. Input can have 28 = 256 different binary configuration, output is one of 256 voltage, the output voltage is not arbitrary value throughout the whole voltage range, and can only be 256 possible values.2.4 LCD display moduleA/D conversion output data, need to use the LCD display.2.5 Eight independent type keyboard moduleThe keyboard in the microcomputer application system, realize the function of the input data, transmit command, and is a major means of human intervention. Keyboard with coding and non coding keyboard, independent type button structure, matrix structure key. First, monitoring any key press, the key of closed or not, reflect on the voltage is present a high level or low level, so through the detection level of high and low status, can confirm button pressed or not. Second, determine which key is pressed.interrupt scanning way. Keyboard circuit used in hc2 74 is a high-speed Si - gate CMOS1 integration chip, the pin compatible with low power consumption. Belong to the Scotty TTL (input channel). The 74 hc21 provides 4 - input and function.2.6 The software designUsing the IAR Embedded Workbench Evaluation for MSP4305.10.1 software programming, the basic idea: the LED lights, digital tube as the main program, the 7 key as interrupt, LCD is used to enter the interrupt and A/D conversion output display output.2.7 extensionsBy extending the mouth can facilitate the single-chip microcomputer and peripheral module, resources, make full use of the chip pin real MSP430 single chip microcomputer powerful function into full play. Loading other modules in the extension mouth, through debugging, testing can produce a corresponding products on the market, strong practicability and wide prospect of market.Load on minimum system for example, a pressure sensor, electronic scale, what you can accomplish through programming, download again due to the low power consumption system, can make it portable, bring great convenience to people's life;On the basis of minimum system loads a high-precision ultrasonic ranging module, also, you can accomplish through programming, download electronic scale, so as to replace the traditional tape, tape can make up for some disadvantages; If combined with speakers, programming downloads, encapsulate the whole system into modules, can be applied to the car, when the car in the process of driving the car away from less than a certain distance, through the voice to remind the driver, please keep the vehicles, and other related applications.3 ConclusionsMinimum system can directly as a core component used in the engineering and scientific research, has good versatility and expansibility. On the basis of the minimum system, can be easily to carry on the secondary development and function extension, can shorten the development cycle, and reduce development costs. This paper realized the basic functionof the minimum system, each module of hardware circuit is introduced. And on this basis to build a simple application platform. The minimum system can be used as learning, practice teaching experiment board. Also can appropriately modify computer applied in electronic design, teaching and scientific research, industrial control and other fields, can also by loading the corresponding module, converted into useful products, put into the market.References:[1] Cao lei. MSP430 microcontroller C program design and practice [M]. BeijingUniversity of aeronautics and astronautics Press, 2007:105-2007.[2] Xiao Xing gong, strong bum then asked xiong-ying wu. MSP430 single chipmicrocomputer based and practice [M].Beijing University of aeronautics and astronautics press, 2008:84-85.[3] Texas Instr ument, MSP430x14xFamilyUser’sGuide[S].2003.(.).[4] jian-hua shen. MSP430 series 16 ultra-low power MCU principle and practice [M].Beijing University of aeronautics and astronautics press, 2008:202-202. The Modern Construction of Modern Construction.SmartGrid,2013,3,91-95doi:10.12677/sg.2013.33016Published Online June 2013基于MSP430F149单片机的最小系统设计及其应用AE TuumlDepartment of Mechanical and Electronic Engineering, CollegeChina University of Geosciences, 430200摘要:单片机最小系统,或称为最小应用系统,是指用最少的元件组成的单片机可以工作的系统。
外文翻译--用于FIR滤波器的MSP430有效代码综合
用于FIR滤波器的MSP430有效代码综合摘要利用MSP430高效的乘法器可以很容易的实现数字滤波。
[1]这个工具附带的文件可以自动的将FIR滤波器系数转化成MSP430的汇编代码,而这个代码可以被用到任何的应用程序中。
Horner算法和CSD格式用来实现高效的乘法操作。
在MSP430上的滤波器的性能通过对穿过所有频率的评价来表现出来。
MSP430上的滤波器的性能在CPU的周期,代码的大小,低通、高通、带通、带阻滤波器和陷波滤波器的频率响应等方面的表现在附录A 中。
在附录C中,这篇应用报告介绍如何比较超功低耗单片机。
它讨论了在现在流行的单片机之间的关键的不同点,和怎样说明它们的特点和规范,并提供了它们应用的条件。
内容1绪论....................................................... (2)2FIR滤波器代码合成器............................................................... (2)3参考书目....................................................... (4)附录A FIR滤波器举例................................................................... (5)附录B 文件目录................................................................... (10)附录C 选择超功低耗单片机 (12)图表目录A-1低通FIR滤波器响应 .................................................................. . (5)A-2高通FIR滤波器响应 .................................................................. . (6)A-3带通FIR滤波器响应 .................................................................. . (7)A-4带阻FIR滤波器响应 .................................................................. (8)A-5陷波FIR滤波器响应 .................................................................. (9)1绪论FIR滤波器,以其固有的稳定性和线性相位的特性而闻名,有时是数字滤波器的理想选择对象。
fsk调制解调设计系统毕业设计(论文)word格式[管理资料]
毕业设计摘要随着社会的不断发展,,,在这方面数字通信系统具有先天的优势。
这主要是因为数字通信系统中传输的是离散的数字信号,由于信号是离散的,被噪声干扰后的信号只要没有超过门限,接收端就能够完全正确地判断出传输的信息;而对于模拟传输系统,只要有稍微的干扰都会使传输的信息产生错误。
也正是由于这样的原因,数字通信系统才能在各方面逐渐代替模拟通信系统成为现代通信的最基本方式。
为了便于区别信号与噪声,使通信不失真和不受干扰,往往给测量信号赋以一定特征,这就是调制的主要功能。
调制就是用一个信号(称为调制信号)去控制另一作为载体的信号(称为载波信号),让后者的某一特征参数按前者变化。
再将测量信号调制,并将它和噪声分离,放大等处理后,还要从已经调制的信号中提取反映被测量值的测量信号,这一过程称为解调。
为了更好地利用通信信道的带宽并使信号能够传送更大的距离, 在数字载波通信中,我们采用了三种解调方式: 幅移键控(ASK)频移键控(FSK)和相移键控(PSK)。
调制信号为二进制信号的调制称为二进制数字调制, 二进制调制又分为二进制幅移键控(2ASK)、二进制频移键控(2FSK)、二进制相移键控(2PSK)和差分二进制相移键控(2DPSK)等多种基本的类型,本课题主要是数字频率调制又称频移键控(FSK)。
同时利用system view软件实现对FSK系统的仿真和分析,从而通过运用模拟的视觉化的手段来实现达到解调调制的目的。
关键词数字通信;FSK信号;非相干数字解调SummaryAlong with society of continuously development, correspondence more and more show to us offor the correspondence technique, the quality of the correspondence also show very of of root mission is how assurance long-distance leave to deliver an information of accuracy, in this aspect numeral correspondence the system have inborn of main is because of numeral correspondence what to deliver be long-lost in the system of numeral signal, because of the signal be long-lost, drive Zao voice interference empress of signal want ~only have no exceed threshold, receive to carry can complete with accuracy judgment the information for deliver;But for imitate to deliver system, as long as have a little bit of the interference will make the information creation for deliver exactly also because of so of reason, numeral correspondence system then can ineveryone's noodles gradual replace imitate correspondence system to become modern correspondence of the most basic the sake of easy to differentiation signal and Zao voice, make correspondence don't lose true with be free from interference, usually give diagraph signal to endow with with certain characteristic, this be the main function for is the signal(be called to carry a signal) which use a signal(be called to make signal) to carry a body to control's another a conduct and actions, let the latter of some characteristic parameter press the former measure signal to make again, and will it with Zao voice separate, after enlarge etc. processing, return want to withdraw reflection from have already make of the signal quilt measured value of measure signal, this process be called solution to bandwidth using correspondence letter way for the sake of better land utilization also make signal can transmission larger of distance, in the numeral carry the wave the correspondence, we adoption three kinds of solution adjust a way: Move key to control(ASK) Pin to move key to control(FSK) with mutually move key to control(PSK).Make signal be called binary system numeral to make for the make of binary system signal, the binary system make and is divided into a binary system to move key to control(2 ASK), the binary system Pin move key to control(2 FSK), the binary system mutually move key to control(2 PSK) with bad cent the binary system mutually move key to control(2 DPSK) etc. variety basic type, this topic main is numeral the frequency make and call Pin to move key to control(FSK).In the meantime make use of system view software realization to imitate FSK system true with analysis, pass an usage imitate thus of the sense of vision turn of means to realization attain solution toadjust of purpose.Keyword:The Pin move key to control、Move key to control、Mutually move key to control、Losetrue、Correspondence.前言系统仿真是20世纪40年代末以来伴随着计算机技术的发展而逐步形成的一门新兴学科。
FSK调制与解调系统设计
FSK调制与解调系统设计一、FSK调制与解调系统原理FSK调制(Frequency Shift Keying)是一种基于载波频率变化来传输数字信息的调制技术。
在FSK调制中,数字信号被转换为两个不同频率的载波信号,分别对应数字信号的“0”和“1”。
FSK调制使用两个不同频率的载波信号来区分数字信号的不同状态,从而实现信号的传输。
1.将数字信号划分为一段一段的离散时间片段。
2.对于每个时间片段,根据数字信号的状态选择对应的载波频率。
3.将选择的载波频率的信号与数字信号进行调制,生成FSK信号。
FSK解调(Frequency Shift Keying demodulation)是将接收到的FSK信号还原为原始的数字信号的过程。
FSK解调系统需要对接收到的FSK信号进行解调,将不同频率的载波信号转换为数字信号的“0”和“1”。
FSK解调使用了两个不同频率的载波信号,并将接收到的信号与这两个频率的载波信号进行频率对比,从而实现信号的解调。
FSK解调的原理如下:1.接收到FSK信号,并提取出信号中的两个频率分量。
2.对接收到的信号进行滤波和放大,增强信号的稳定性和可靠性。
3.判断接收到的信号的频率与载波频率的对比结果,从而得出数字信号的状态。
二、FSK调制与解调系统设计方法1.信号生成:在FSK调制系统中,根据数字信号的状态选择对应的载波频率信号。
这可以通过频率可调的震荡器来实现,通过控制震荡器输出频率的方式来生成不同频率的载波信号。
2.滤波和放大:在FSK解调系统中,接收到的FSK信号会包含噪声和其他干扰信号。
为了增强信号的稳定性和可靠性,需要对接收到的信号进行滤波和放大处理。
滤波可以通过低通滤波器来实现,将高频噪声滤除,同时放大信号的幅度以提高解调的灵敏度。
3. 频率对比:接收到的FSK信号中会包含两个不同频率的载波信号。
为了将接收到的信号从载波信号转换为数字信号,需要进行频率对比。
可以通过相位锁定环(Phase-Locked Loop)来实现频率对比。
基于MSP430的变点数FFT算法研究与实现
采用额定电压36 V,额定功率250 W的电机作 为样机,对该控制器进行测试,得到图6所示的电机 各特性曲线。
另一种是利用DSP芯片为核心,通过DSP芯片 提供的资源,高效快速的信号处理能力,使涡街流量 计的精度很高,同时可以选择较为先进、复杂的算 法。由于DSP属于高档微处理器,研发周期较长,
收稿日期:2007—10一18 作者简介:陈荣保(1960一),男,上海人,副教授,博士生,研究 方向为仪表自动化与图像处理。
软件部分除了常规软件外,数据处理程序是该 系统的重点。程序包括信号采样和数据处理两部 分,信号采样程序如图4所示。
图4软件主程序流程图
数据处理是软件设计的核心,采用DSP微处理 器时,高效的FF-I'保证了涡街流量计信号的高精度 和流量计的高层次。由于MSP430有限的运行速 度,无法达到2 048或4 096的多点采集和非周期采 样。数据处理根据F兀'计算的频率,确定下个周期 的整周期采样点数。 4 总结
万方数据
2008年第4期
工业仪表与自动化装置
·77·
谱分析信号所包含的频率分量,能得到较强的噪声
抑制效果。根据涡街流量计的流量计算基于信号频
率,对信号的相位、幅度均无严格要求的特点,当信
号经时频转换后,在频域内进行频谱分析和频率计
算,可有效地抑制噪声。
离散化后的DFF公式为:
Ⅳ一1
2_
X(后)=∑石(凡)e一厢
整个信号调理是系统的关键,分析压电元件的 信号特点和流场扰动、流量管道振动、电磁干扰等因 素,考虑到实时性要求和FFT的特点,调理通道选 用高性能低功耗运放完成电荷放大器、滤波、陷波和 放大功能。软件设计了低采样点数的FFT运算。
若外供直流24 V,流量计增加D/A转换和4— 20 mA输出。LCD显示器常态显示。 3软件实现
fsk调制与解调实验报告
fsk调制与解调实验报告实验报告:FSK调制与解调引言:FSK(Frequency Shift Keying)调制与解调是一种常用的数字调制解调技术,它通过改变载波频率的方式来传输数字信号。
在本实验中,我们将学习并掌握FSK调制与解调的原理和实现方法,并通过实验验证其性能。
一、实验目的:1. 了解FSK调制与解调的原理和工作方式;2. 掌握FSK调制与解调电路的设计和搭建方法;3. 验证FSK调制与解调的性能,如传输速率、误码率等。
二、实验原理:FSK调制是将数字信号转换为频率变化的模拟信号,然后通过载波进行传输。
在FSK调制中,两个不同的频率代表两个不同的二进制数字,通常用0和1表示。
调制过程中,数字信号的0和1分别对应两个不同的频率,例如0对应低频率f1,1对应高频率f2。
FSK解调是将接收到的FSK信号转换回数字信号的过程。
解调器通过检测信号的频率变化来判断接收到的是0还是1。
通常使用频率鉴别器或相干解调器来实现。
三、实验步骤:1. 设计和搭建FSK调制电路:a. 使用555定时器作为多谐振荡器,设置两个不同的频率f1和f2作为调制信号;b. 将调制信号与载波信号进行混合,得到FSK调制信号。
2. 设计和搭建FSK解调电路:a. 使用频率鉴别器或相干解调器来实现FSK解调;b. 解调器将接收到的FSK信号转换为数字信号。
3. 进行实验测试:a. 输入一组二进制数字信号,通过FSK调制电路将其转换为FSK信号;b. 将FSK信号输入到FSK解调电路,观察解调结果是否与输入信号一致;c. 测试不同的传输速率,记录误码率。
四、实验结果与分析:1. 实验测试结果表明,FSK调制与解调能够实现数字信号的传输和还原,解调结果与输入信号一致。
2. 传输速率对FSK调制与解调的性能影响较大。
传输速率过高可能导致误码率增加,传输速率过低可能导致传输延迟。
3. 在实验中,我们可以根据实际需求选择合适的调制频率和解调方法,以达到较低的误码率和较高的传输速率。
FSK调制及解调实验报告
FSK调制及解调实验报告实验目的:掌握FSK调制与解调的原理和方法,熟悉FSK信号的产生、调制和解调过程,加深对调制解调技术的理解。
实验原理:FSK是一种调频调制方式,常用于数字通信中。
FSK信号是由两个频率不同的正弦波叠加而成,一个频率代表0,另一个频率代表1、FSK调制器的主要工作是将数字信号转换为对应的频率信号,具体方法为使用两个中心频率分别对应于0和1,并通过切换两个频率来表示数字信号。
FSK调制的具体步骤如下:1.将数字信号转换为二进制信号,0对应一个频率,1对应另一个频率。
2.将二进制信号经过调制器,通过选择器选择对应的频率信号进行输出。
FSK解调器的主要工作是还原出原始的数字信号,具体方法为使用一个带宽限制的滤波器来选择对应的频率信号进行解调。
FSK解调的具体步骤如下:1.将带有FSK信号的信号进行滤波,只保留信号中的一个频率成分。
2.对滤波后的信号进行切片,判断信号频率为0还是13.将切片后的信号通过数字信号转换器转换为对应的数字信号。
实验装置:1.函数信号发生器:用于产生模拟信号。
2.数字信号发生器:用于产生数字信号。
3.混频器:用于合成两个频率不同的正弦信号。
4.带宽限制滤波器:用于解调信号。
5.示波器:用于观测信号波形。
实验步骤:1.连接实验装置,将函数信号发生器和数字信号发生器连接到混频器的输入端,将混频器的输出端连接到带宽限制滤波器的输入端,将带宽限制滤波器的输出端连接到示波器。
2.设置函数信号发生器和数字信号发生器,使其产生期望的信号波形。
3.调节混频器,选择期望的中心频率,并调整幅度,使得混频器的输出信号为调制后的FSK信号。
4.调节示波器的触发方式和触发电平,使得信号波形能够稳定显示。
5.调节带宽限制滤波器,选择期望的频率成分,并调节带宽,使得滤波器能够准确解调FSK信号。
6.结合调制解调的原理和步骤,观察信号波形,验证实验结果。
实验结果分析:通过上述实验步骤,成功实现了FSK调制和解调的过程,并通过示波器观察到了调制前后的信号波形。
基于MSP430单片机的2FSK通信系统设计
基于MSP430单片机的2FSK通信系统设计摘要使用TI公司的超低功耗单片机MSP430F149设计并实现了一种2FSK 通信系统。
关键词MSP430 2FSK 调制解调Abstract: using TI company’s low power consumption MCU MSP430F149 designed and realized a 2 FSK communication system.Keywords: MSP430 2 FSK demodulation在某些带通型模拟信道,如在有线电话信道中进行数据传输,目前最通用的方法是将数字基带信号调制在话带内的音频载波上,形成适合话带传输的已调信号进行数字传输,而二进制频移键控2FSK调制是一种基本的较常用的数字频带调制方式。
在话带内实现FSK调制的技术已经非常成熟,并且有丰富的套片可供选择,本文介绍的是一种通过电感线圈耦合实现半双工2FSK串行通信的无线通信系统,载波频率在25kHz附近,现有话带调制解调套片并不适用。
传统的设计方法是使用2FSK调制解调功能的集成芯片,利用锁相环路的鉴频功能进行非相干解调,但其功耗较大,在使用电池供电的设备上并不让人满意,并且还有另外一个缺点,就是因为其调制频率由电阻电容确定,故频率稳定性不好,影响通信的可靠性,且调试麻烦。
本文通过MSP430F149单片机实现的2FSK软件调制解调通信系统,则正是克服了这两个缺点。
1MSP430F1XX单片机简介MSP430F1XX系列单片机是一种超低功耗的混合信号控制器,它根据不同的应用提供不同的具体型号的单片机,以满足不同用户的需求,应用范围非常广阔,它主要有以下特点。
低电压、超低功耗。
MSP430F1XX系列单片机在1.8V~3.6V的工作电压、1MHz的时钟频率下运行,耗电电流在0.1μA~400μA之间,这个和不同的工作模式有关。
强大的处理能力。
MSP430F1XX系列单片机为16位的RSIC结构,具有丰富的寻址方式、简洁的指令、大量的寄存器,在8MHz时钟下运算能力达到1MIPS。
基于MSP430的FSK调制解调器
基于MSP430的FSK调制解调器 作者:方彦军;孙军;朱小平 作者机构:武汉大学,湖北武汉,430072;武汉大学, 来源:仪表技术与传感器
ISSN:1002-1841 年:2008 卷:000 期:007 页码:60-61,64 页数:3 中图分类:TN919 正文语种:chi 关键词:频移键控;MSP430;调制;解调 摘要:提出了一种基于TI MSP430单片机的FSK调制解调器设计方案.根据FSK调制解调的原理与方法,选用MSP430F147单片 机,设计了CCITT V2.1协议下的300波特调制解调器,并给出了实现调制解调器的硬件电路和程序流程图.实践证明:该设计方案结 构简单、可靠性高、抗干扰能力强,有较高的性价比.
基于SOPC的FSK数字调制与解调器(doc 41页)
基于SOPC的FSK数字调制与解调器(doc 41页)湖南工程学院应用技术学院毕业设计论文题目:基于SOPC的FSK数字调制与解调器研究与实现专业班级:电子信息工程1281学生姓名:杨浩然学号:05完成日期:2016年5月24日指导教师:贺富朋讲师评阅教师:陈军根讲师基于SOPC的FSK数字调制与解调器研究与实现2016 年 6 月湖南工程学院应用技术学院毕业设计(论文)任务书设计(论文)题目:基于SOPC的FSK 数字调制与解调器研究与实现姓名杨浩然专业电子信息工程班级1281 学号05 指导老师贺富朋职称讲师教研室主任陈军根一、基本任务及要求:利用SOPC技术,设计一套FSK数字通信传输系统,要求建立MFSK的SOPC技术实现模型,主要完成2FSK调制器与解调器的编程,并通过软件仿真,且通过硬件实现与测试。
重点研究内容:MFSK的实现原理;SOPC实现2FSK调制模型。
基于SOPC的FSK数字调制与解调器研究与实现二、进度安排及完成时间:第1-3周查阅资料、撰写文献综述及开题报告第4-5周原理框图、总体方案设计第6-9周软、硬件部分设计,调试结果第10-11周撰写毕业设计说明书第12周指导老师检查毕业设计说明书第13周修改、装订毕业设计说明书、指导老师评阅第14周毕业设计答辩目录摘要: (2)ABSTRACT: (3)第一章绪论 (1)1.1 历史发展: (1)1.2 基本定义 (1)1.3 基本原理 (2)1.4 主要研究内容 (2)第二章调制与解调器研究与实现 (3)2.1 概述 (3)2.2 二进制频移键控(FSK)的调制与解调 (3)2.2.1 FSK信号的产生 (3)2.2.2 直接调频法 (3)2.2.3 频率键控法 (5)2.3 FSK信号的解调 (7)2.3.1 同步解调法 (7)2.3.2 包络解调法 (7)2.3.3 过零检测法 (8)2.4 Verilog HDL和VHDL简介 (8)第三章系统总体方案设计与FPGA 设计开发 (11)3.1 FPGA 设计流程 (11)3.2 调制器设计 (14)3.2.1 调制原理 (14)3.2.2 调制器子模块设计 (16)3.2.3 调制程序 (20)3.2.4 调制程序仿真图及注释 (22)3.3 解调器设计 (24)3.3.1 解调原理 (24)3.3.2 解调器子模块设计 (26)3.3.3 MFSK解调程序 (31)3.3.4 解调程序仿真图及注释 (33)第五章结论 (35)参考文献 (36)致谢 (38)基于SOPC的FSK数字调制与解调器研究与实现摘要:一直以来调制解调器都是学校数字信号调制教学的重点内容。
FSK调制解调器的单片机实现方案
FSK调制解调器的单片机实现通信5班 001号张三002号李四一、FSK调制解调原理FSK已广泛应用于中低速远程数据通信。
近年来,随着通信技术的发展,改进的FSK调制解调方法也开始应用于高速数据通信。
FSK信号由频率调制器产生不同的频率,常用的是f1和f2两种频率,其中,f1代表码元“0”(或称空号),f2代表码元“1”(又称传号)。
调制数据的码元决定频率调制器的输出频率,实现FSK有频率选择法、调频法和数字调频法。
频率选择法输出频率稳定、准确,但相位不连续,容易产生带外辐射,影响邻近信道。
调频法虽然相位连续,但是频率精度不高,稳定性差,外界条件变化时,容易产生频率漂移。
数字调频法解决了上述问题,又兼有两种方法的优点。
数字调频法的原理框图如图1所示。
图1 数字调频器原理框图FSK解调就是从FSK载波信号中恢复调制码元,其方法有相干解调和非相干解调两类,但非相干解调容易实现,所以,常用的是非相干解调,其原理框图如图2所示。
图2 非相干FSK解调原理框图载波信号经带通滤波后整形成宽度不同的方法,这些方波代表不同码元:鉴频器确定对应载波频率,根据频率判决对应码元。
实现FSK解调涉及的技术问题比解调难度大,一般要使用带通滤波器、倍频器、锁相环等,电路较为复杂。
二、 单片机实现调制解调的原理 MCS51系列单片机内部具有较强的数值运算和逻辑运算能力,并有两个16位定时/计数器,所以完全能够实现FSK 的调制和解调,用单片机实现调制解调,除图1和图2中的波形变换和整形电路外,其余部分都可以在单片机内部实现,因而电路结构十分简单。
三、 实验硬件实现 根据上述原理和实际需要,我们设计了一个满足Bell03建议的FSK 调制解调器。
1f =850Hz ,2f =1530Hz ,0f =1190Hz ,频偏f = 680Hz ,码元速率B f =200,调制指数H=6.8. 用89S52做CPU ,LM324作整形放大器,12MHz 晶振,定时器T0作可变分频器,T1作测宽记数器,P3.4作载波整形输入,P3.2作调制码元输入,P3.5作解调码元输出。
基于 CPLD 的 FSK 调制解调电路及其测试
基于 CPLD 的 FSK 调制解调电路及其测试武立华;黄玉;王姣;赵恩铭;刘志海【期刊名称】《物理实验》【年(卷),期】2014(000)004【摘要】根据数字式FSK调制和解调的工作原理,对比分析了基于CPLD和单片机的2种电路实现方案。
设计了基于CPLD的FSK调制解调模块,利用 Quartus Ⅱ开发平台对CPLD进行编程,实现了 FSK 调制与解调功能,用 IAR FOR AVR 平台对单片机ATMEGA16进行编程,实现了位同步功能,同时与外部用SPI接口进行通信。
搭建了实际的硬件电路,仿真与实验测试均验证了设计的正确性。
%According to the working principle of digital FSK modulation and demodulation ,two kinds of circuit schemes based on CPLD and single chip were compared .FSK modulation and demodu-lation module based on CPLD was designed and programmed by Quartus II software .ATMEGA16 single chip was programmed by IAR FOR AVR software to carry out the function of bit synchroniza-tion and communication with outside through SPI interface .Both simulations and experimental tests proved the exactness of design .【总页数】5页(P19-22,25)【作者】武立华;黄玉;王姣;赵恩铭;刘志海【作者单位】哈尔滨工程大学理学院理学之光科技创新中心,黑龙江哈尔滨150001;哈尔滨工程大学理学院理学之光科技创新中心,黑龙江哈尔滨150001;哈尔滨工程大学信息与通信工程学院,黑龙江哈尔滨150001;哈尔滨工程大学理学院理学之光科技创新中心,黑龙江哈尔滨150001;哈尔滨工程大学理学院理学之光科技创新中心,黑龙江哈尔滨150001【正文语种】中文【中图分类】TP212【相关文献】1.用数字集成电路实现的CP—FSK调制解调器 [J], 汤斌2.一种基于CPLD的QDPSK调制解调电路设计 [J], 龙光利3.一种FSK信号调制解调电路的设计 [J], 郭颖娜4.一种用CPLD实现的CPFSK调制解调器 [J], 王兰勋;常铁原5.FSK调制解调电路仿真实现 [J], 刘新红因版权原因,仅展示原文概要,查看原文内容请购买。
fsk调制解调原理及设计
一.2FSK 调制原理:1、2FSK 信号的产生:2FSK 是利用数字基带信号控制在波的频率来传送信息。
例如,1码用频率f1来传输,0码用频率f2来传输,而其振幅和初始相位不变。
故其表示式为 {)cos()cos(21122)(θωθωϕ++=t A t A FSK t 时发送时发送"1""0"式中,假设码元的初始相位分别为1θ和2θ;112f π=ω和222f π=ω为两个不同的码元的角频率;幅度为A 为一常数,表示码元的包络为矩形脉冲。
2FSK 信号的产生方法有两种:(1)模拟法,即用数字基带信号作为调制信号进行调频。
如图1-1(a )所示。
(2)键控法,用数字基带信号)(t g 及其反)(t g 相分别控制两个开关门电路,以此对两个载波发生器进行选通。
如图1-1(b )所示。
这两种方法产生的2FSK 信号的波形基本相同,只有一点差异,即由调频器产生的2FSK 信号在相邻码元之间的相位是连续的,而键控法产生的2FSK 信号,则分别有两个独立的频率源产生两个不同频率的信号,故相邻码元的相位不一定是连续的。
(a) (b)2FSK 信号产生原理图由键控法产生原理可知,一位相位离散的2FSK 信号可看成不同频率交替发送的两个2ASK 信号之和,即)cos(])([)cos(])([)cos(·)()cos()()(221122112θωθωθωθωϕ+-++-=+++=∑∑∞-∞=∞-∞=t nT t g a t nT t g a t t g t t g t n s n n s n FSK其中)(t g 是脉宽为s T 的矩形脉冲表示的NRZ 数字基带信号。
{P,0P 11概率,概率-=n a {P 1,0P 1-=概率,概率n a 其中,n a 为n a 的反码,即若1=n a ,则0=n a ;若0=n a ,则1=n a 。
2、2FSK 信号的频谱特性:由于相位离散的2FSK 信号可看成是两个2ASK 信号之和,所以,这里可以直接应用2ASK 信号的频谱分析结果,比较方便,即)]()()()([]|)(||)(||)(||)([|)()()(2211161222221211622221f f f f f f f f T f f Sa T f f Sa T f f Sa T f f Sa f S f S f S S S S S T ASK ASK FSK S ++-+++-+++-+++-=+=δδδδππππ2FSK 信号带宽为 s s FSK R f f f f f B 2||2||21212+-=+-≈ 式中,s s f R =是基带信号的带宽。
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中文翻译材料英文题目FSK Modulation and Demodulation With the MSP430 Microcotroller中文题目基于MSP430的FSK调制解调学院:计算机科学与技术学院专业:通信工程学生姓名:指导教师:二O一三年六月IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PR OPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright 1998, Texas Instruments IncorporatedContents1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (1)2 Demodulation Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.1 Choosing the Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2 Front End Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3 FSK Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.4 Bit Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Modulation Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1 Choosing the Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2 Constructing the Look Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3 FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 2 2 3 4 4 4 44 Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5)4.1 A/D Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5)4.2 D/A Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5)5 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (6)6 Exercising the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (7)6.1 FSK Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (7)6.2 FSK Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (7)7 Example Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (8)7.1 Using the MSP430C325 as Main Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (8)7.2 Example Telephone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (8)8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (10)9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (11)FSK Modulation and Demodulation With the MSP430 MicrocontrolleriFSK Modulation and Demodulation With the MSP430MicrocontrollerABSTRACTThis application report describes a software program for performing V.23 FSK modemtransceiver functions using an MSP430 microcontroller. It makes use of novel filterarchitecture to perform DSP functions on a processor with only shift and add capabilities.1 IntroductionMany measurement applications (for example, electric and gas meters) requirea way to communicate electronically with a central office so that measured datacan be reported back to the central office and new tariffs can be set in the remotesite. Telephony provides a convenient means of data communication.Frequency shift keying (FSK) and dual tone multi frequency (DTMF) are twopopular methods of representing binary data over telephone circuits. Thisapplication report describes a V.23-compliant FSK transceiver software module.Integrating the measurement and communication functions onto the same chipyields cost as well as power-saving benefits. Using the MSP430, a high MIPs ultralow power microprocessor, allows power to be drawn from the telephone line insome cases.This report describes the mathematical formulas for FSK signal transmission anddetection. A list of the software modules is included with a reference schematicfor telephone interface and low cost A/D converter. The schematic is only areference, since the precise implementation can vary from country to country.1Demodulation Theory2 Demodulation TheoryA quadrature demodulator provides the FSK demodulation. In this type ofdemodulation, the signal and its delayed version are multiplied together and then low-pass filtered. If the delay, T, is set such that Wcarrier ⋅ T = /2, then thelow-pass filter result is proportional to the frequency deviation from the carrier and therefore represents the bit value sent.If wWcarrierwhere w = 2π ⋅ f : + " Wdelta and T+ Wcarrier +p 2 ³2.1 cos[wt].cos[w(t –T)]coswT coswTsin[" Wdelta] + ) cos(2wt –wT) ³ Low Pass Filter +" sin[Wdelta]_ Choosing the Sampling RateThe sampling is chosen to be Fcarrier4 for the purpose of obtaining thedelayed sample without computational overhead. For V.23, the F carrierfrequency is 1700 Hz and therefore the sampling rate becomes 6800 Hz. Using a 32768-Hz crystal yields 6793.3 Hz, which is 0.1% out. The sampling frequency is set by the 8-bit interval timer. Because this timer is limited to 256 counts, the interrupt rated is set to twice the sampling rate and the processing is divided into two halves with signal sampling performed every other interrupt.2.2 Front End ProcessingMost A/D converters, including the successive approximation A/D converter in the MSP430C325, need a dc bias; this yields an unsigned integer sample with an offset. Before this sample can be processed further, it needs to go through an unbias filter to take out the dc bias and turn the sample into a signed integer value. This unbias filtering also gives 30 dB or so of rejection for main frequencies.2.3 FSK DemodulationThe signed integer sample and its delayed version are multiplied together; in this application, an 8×8 signed multiplication loop is used.The product, made up of two frequency elements, is low-pass filtered to remove the double frequency element. The remainder is a signed integer valuerepresenting the original bit value transmitted.The low-pass filter uses the digital wave filtering technique. This technique gives stable characteristics with very good coefficient tolerance. All multiplication is done through shifts and adds with the number of shift/add operations minimized through rounding off the coefficients. Because the filter has good coefficienttolerance, this rounding off does not affect the filter performance. The Butterworth filter used here gives approximately 40-dB attenuation in the stop band with 1-dB pass and ripple.2SLAA037Demodulation Theory2.4Bit SynchronizationThe bit values coming out from demodulation need to be determined andsynchronized to produce the incoming data bit stream. This process is alsoknown as bit slicing and clock recovery. Because the sampling rate at 6800 is notan integer multiple of the data rate (baud rate) at 1200, an additional step isneeded to consolidate between the two rates. This is done through a count-downcounter with a sequence of preload value (5,6,5). Every 17 samples, the samplingrate and the data baud rate are resynchronized. Bit synchronization or clockrecovery is done by monitoring bit value transitions. Lead or lag information isthen obtained and the count-down counter is adjusted accordingly. Because ofthe difference between the sampling clock and the data clock, the data bit is neversampled at the middle of the baud period; instead a –5% to 13% variation isintroduced. However, this should not have any adverse effect on the accuracy ofthe system, as it has been verified experimentally.3FSK Modulation and Demodulation With the MSP430 MicrocontrollerModulation Theory3 Modulation TheoryFSK modulation involves alternating the value of a delta frequency from a carrierfrequency according to the value of the bit to be represented. For V.23, a bit valueof 0 = 400 Hz and a bit value of 1 = –400 Hz.FSK signal + Amplitudecos[t| 2p(Fcarrier" Fdelta)]The sinusoidal signal is generated through a lookup table which contains cosine values from 0 to 2π. A parameter called PHASER (16 bit) represents the current angle: 0=0 degree, 8000 hex = 180 degree 10000 hex = 360 degree. With each sample, this angle is advanced by another parameter DELTA (16 bit) which determines the frequency of the signal (larger DELTA value = higher frequency). Frequency modulation is realized by changing the DELTA value according to the bit value to be transmitted at each baud period, according to the following formula:DELTA + Fdesired Fsampling65536.The advantage of this method over a digital oscillator method is that this methodpreserves the phase relationship even when the frequency is shifted from sampleto sample.3.1Choosing the Sampling RateThe 8-bit interval timer sets the sampling rate to 19200 samples/s. This rate issubdividable into the data baud rate of 1200. Also, it is sufficiently high to makethe D/A process simpler.3.2Constructing the Look Up TableTo save ROM space, only the first quadrant (0 to 127 degrees) in Q7 format iscoded. This is done by dividing the first quadrant (90 degrees) into 128 steps ofapproximately 0.7 degrees each. The remaining three quadrants can be workedout from this first quadrant table using additional computation.3.3FSK ModulationThe parameter PHASER is advanced by the amount DELTA at every interrupt.The first 9 bits of the PHASER is used to look up the cosine value. For the cosinefunction, the third and fourth quadrant are the same as the second and firstquadrant, and so only the absolute value of the first 9 bits of PHASER is used.Next, all second quadrant values are derived from the first quadrant ROM table.The 8-bit result value is stored onto P0.OUT.Every 16 interrupts, the parameter DELTA is updated with the next frequency bylooking at the next bit to be transmitted.4SLAA037Data Conversion 4 Data ConversionThis section describes the required digital-to-analog (D/A) and analog-to-digital(A/D) data conversions.4.1A/D ConversionThe most straightforward way to digitize the incoming FSK signal is to use the12-bit mode of the internal 14-bit A/D converter of the MSP430C325. However,not all of the 12 bits are needed to achieve good dynamic range for the FSKdemodulation. Simulation results indicate that an 8-bit A/D stage gives gooddynamic range up to 25 dB using internal AGC software. With an additionalexternal AGC stage, the dynamic range can be further widened. As economicalmeans of building 8-bit single slope A/D exists, this extends the application of thismodule to the rest of the MSP430 family. The application software included hereuses a single slope A/D (universal timer with external comparator) for thedemodulator. This makes the software universally applicable for the whole family.4.2D/A ConversionA 6-bit external R–2R ladder is used to construct the D/A converter. Because thecarrier frequency of 19200 Hz is nine times the highest frequency of the FSK of2100 Hz, the post filtering stage should be relatively simple. In the applicationcircuit, a single capacitor forms a single pole low pass filter but more poles canbe realized using additional passive networks.5FSK Modulation and Demodulation With the MSP430 MicrocontrollerPower Consumption5 Power ConsumptionThe FSK concept is designed with low power in mind. The FSK demodulatortakes less than 2 MIPs. With a low power op-amp as a front-end, total powerconsumption of less that 1.5 mA should be achievable. Thus, it is possible thatthe power can be derived entirely from the telephone line. A schematic is includedfor a suggested telephone line interface. The precise configuration may vary fromcountry to country.SLAA0376Exercising the Software 6 Exercising the SoftwareThis section describes operation of the software.6.1FSK ReceiverThe FSK signal is derived from the telecom interface circuit. This signal shouldhave a dc bias of 1.2 V and a peak-to-peak level of 400 mV. The software decodesthis FSK signal and produces three outputs which lets the user monitor thedemodulated data.TP.3. This is the clock signal recovered from the input FSK.TP.5. This is the data recovered from the input FSK; data is latched out everyrising edge of TP.3.P0.2–P0.7. These six bits output the low pass filtered result. With an externalR–2R ladder this becomes very useful in monitoring the analogue FSKdemodulator output level. It is hard limited to 8 bits with the MSB 6 bits loadedto port P06.2FSK TransmitterThe transmitter software outputs an FSK signal according to the BIT MAP datadefined in TX_DATA_TABLE. The bitmap pattern starts with a preamble followedby a long MARK period. Then the actual data is transmitted. This table uses a zeroword as an end marker, and the software restarts the whole data sequence uponreaching a zero value in the bit map data.7FSK Modulation and Demodulation With the MSP430 MicrocontrollerExample Circuits7 Example CircuitsThis section shows and describes example circuits.7.1Using the MSP430C325 as Main ProcessorFigure 1 shows an example circuit using the MSP430C325 as the mainprocessor. The circuit is tested with 400 mV peak-to-peak FSK input. To obtainthe same results, Rx needs to be biased at 1.2 V with a 400 mV peak-to-peak FSKsignal superimposed.VSSR1 R2PO.2PO.3PO.4PO.5PO.6PO.7MSP430E325TP.5TP.1 TP.4 CIN TP.3RX_CLKLine InterfaceRXTXHook 14066AC13VCC1N414833 kΩVoltage RampPNPSample_HoldNPN 1 nF 6_ 5+B 2RX_DATA7Figure 1. Main Processor and A/D Converter7.2Example Telephone InterfaceFigure 2 shows an example telephone interface, and Table 1 lists FSK transceiverperformance data.8SLAA037Example Circuits 20 kΩ1 ∝Φ+ 1 kΩ1 kΩVREF(1.5 V)TLC22796_5+33 kΩ20 kΩ20 kΩ20 kΩ10 kΩ9_10+Telephone LineAB33 nF500 &6–8 V ZenersTuning ForMinimum Side Tone6–8 V ZenersTX7DC TelephoneIsolationTransformer8150 kΩ400 mV pk–pkRX 1 ∝Φ+–+131233 kΩ33 kΩ680Hook150 kΩ14This is a reference circuit only and may not be applicable under some circumstances.Figure 2. Telephone InterfaceTable 1. FSK Transceiver PerformanceRAM (BYTES)FSK Receiver FSK Transmitter1812ROM (BYTES)512400MIPS (APPROX.)21.4FSK Modulation and Demodulation With the MSP430 Microcontroller9Summary8 SummaryFSK transceivers are normally realized by either analog means or by the use ofDSPs with hardware MAC units. Using an MSP430 RISC processor without ahardware MAC to achieve the transceiver function is a very unusual approach.The ability to create filters using digital wave filtering techniques, together with theorthogonal instruction set and the 16 bit architecture of the MSP430, makes thecode very ROM and MIPs efficient. Moreover, the ultra low power capability of theMSP430 means that power can readily be derived from the phone line. This leadsto component-efficient designs. The author has conducted other tests toconclude that, with some enhancements, the FSK receiver can work with an 8-bitA/D converter with enough sensitivity. Therefore the FSK transceiver can beimplemented economically across the whole MSP430 family.SLAA03710References9 References1. Texas Instruments: MSP430 Family, Architecture User’s Guide and ModuleLibrary.2. Texas Instruments Digital Signal Processing Application with the TMS320Family Volume 2.3. Gaszi, L: Explicit Formulas for Lattice Wave Digital Filters; IEEE Trans. OnCircuits and Systems VOL. CAS-32, NO. 1, January 198511FSK Modulation and Demodulation With the MSP430 Microcontroller基于MSP430的FSK调制解调——应用报告声明德州仪器(TI)及其附属公司(TI)保留改进产品或停止任何服务的权力,并且不再另行通知,建议客户获核实最新版本或相关信息,在下订单前,该信息是当前最有效和完整的。