DAC7811IDGSR中文资料

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DAC解码器选购指南

DAC解码器选购指南点评几款DIY的DAC解码器(增加常见dac指标大全)本帖最后由 love957 于 2021-5-13 14:42 编辑在80注册快二年，一直在此下些APE和高清，现在看看80玩DAC的人多了，一时兴起，信手涂鸦:近日时逢寒潮，不便外出之余，终于静下心来把手头的这几个dac装好。

没有多大的感觉，十多年玩pchifi，犹如弹指瞬间，从第一台用YMH724推挑战者一号开始，玩过创新AW64 SB CT 到XIFIDIY过玩过各版1305 1541dac等换过各种甲乙类，甲类，甚至专业类攻放有时在问自已，什么样的声音才是自己需要的，什么样的声音才是适合自已的,什么样的声音才是令自已感动的.初入发烧时，十多年前李楠的一对低频霸主，就觉得气势宏伟的低音是自己完美的追求，随后又被蔡大姐童丽的美妙的人声所征服，刚过而立之年，又觉得淡雅的声音，均衡的三段又正是自已此时静若止水的心境浅写意。

人生何其短。

浮生偷得半日闲.庸者不败最早听到扫把明版的1305是在去年东莞的聚会上，1305dac用9v电池供电，简单声好，是那次聚会的亮点,于是收了块玩玩,不听还好，一听1305DAC，此时我那些珍藏的ymh724 SBLOVE ct4630 xfi等等，全扔到床底下。

一年里明版的1305DAC不断的通过改进线路来改善声音，出了近六个版，我有幸装过他四个版的1305DAC，现在装的是1305终结版。

明版的1305DAC试听的最大特色在于耐听，属于那种不温不火从从容的风格。

玩尽明四个版的1305，有用过用12伏电瓶供电给1305DAC，为什么选用12伏（从台坏的UPS拆下来），因为我试过用9伏干电池和12伏电瓶及电脑开关电源及单12交流供电，个人感觉用9伏干电池供电声音过于柔和，懒洋洋的，单12交流供电像1305刚刚睡醒，声音过于阳刚，三端稳压热到烫手，电脑开关电源供电有噪音，声音干燥，还是12伏电瓶供电不温不火，刚柔并济，适合本人性恪：中庸。

G781中文资料

±1°C Remote and Local Temperature Sensor with SMBus Serial InterfaceFeaturesTwo Channels: Measures Both Remote andLocal Temperatures No Calibration RequiredSMBus 2-Wire Serial InterfaceProgrammable Under/Overtemperature Alarms Supports SMBus Alert Response Accuracy:±1°C (+60°C to +100°C, remote) ±3°C (+60°C to + 100°C, local)320µA (typ) Average Supply Current During Conversion+3V to +5.5V Supply Range Small 8-Lead SO PackageApplications Desktop and Notebook Central Office Computers Telecom Equipment Smart Battery Packs Test and Measurement LAN Servers Multi-Chip Modules Industrial Controllers General DescriptionThe G781 is a precise digital thermometer that reports the temperature of both a remote sensor and its own package. The remote sensor is a diode-connected transistor typically a low-cost, easily mounted 2N3904 NPN type that replace conventional thermistors or thermocouples. Remote accuracy is ±1°C with no cali-bration needed. The remote channel can also meas-ure the die temperature of other ICs, such as micro-processors, that contain an on-chip, diode-connected transistor.The 2-wire serial interface accepts standard System Management Bus (SMBus) Write Byte, Read Byte, Send Byte, and Receive Byte commands to program the alarm thresholds and to read temperature data.The data format is 11bits plus sign, with each bit cor-responding to 0.125°C, in two’s-complement format. Measurements can be done automatically and autonomously, with the conversion rate programmed by the user or programmed to operate in a single-shot mode. The adjustable rate allows the user to control the supply current drain.The G781 is available in a small, 8-pin SOP sur-face-mount package.Ordering InformationPART* TEMP. RANGE PIN-PACKAGEG781-20°C to +120°C8-SOPPin ConfigurationTypical Operating Circuit3V TO 5.5VEACHCLOCK DATAINTERRUPT TO µCSMBDATA SMBCLK GNDG781ALERTAbsolute Maximum RatingsVCC to GND………….….……..………….-0.3V to +6V DXP to GND……….……………..…-0.3V to VCC + 0.3V DXN to GND……………..……………..-0.3V to +0.8V SMBCLK, SMBDATA,ALERT to GND..…-0.3V to +6V SMBDATA,ALERT Current………….-1mA to +50mA DXN Current……………………..………………….±1mA ESD Protection (SMBCLK, SMBDATA,ALERT , humanbody model).……………………………………….2000V ESD Protection (other pins, human body model)..2000V Continuous Power Dissipation (T A = +70°C) ..SOP (derate 8.30mW/°C above +70°C)…………......667mW Operating Temperature Range………-20°C to +120°C Junction Temperature………………….………..+150°C Storage temperature Range………….-65°C to +165°C Lead Temperature (soldering, 10sec)……..……...+300°CStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the opera-tional sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Electrical Characteristics(VCC = + 3.3V, T A = 0°C to +85°C, unless otherwise noted.)PARAMETER CONDITIONS MIN TYP MAX UNITST R = +60°C to +100°C, VCC = 3.0V to 3.6V-1+1Temperature Error, Remote Di-ode (Note 1)T R = 0°C to +125°C (Note 2)-3 +3 °CT A = +60°C to +100°C-3 +3Temperature Error, Local DiodeT A = 0°C to +85°C (Note 2)-5 +5°CSupply-Voltage Range3.0 5.5 V Undervoltage Lockout Threshold VCC input, disables A/D conversion, rising edge 2.8 V Undervoltage Lockout Hysteresis 50 mV Power-On Reset Threshold VCC, falling edge 1.7 V POR Threshold Hysteresis 50 mVSMBus static3Standby Supply Current Logic inputs forced to VCC or GND Hardware or softwarestandby, SMBCLK at 10kHz4 µA0.5 conv/sec 35Average Operating Supply CurrentAuto-convert mode. Logic inputs forced to VCC or GND 8.0 conv/sec 320 µAConversion Time From stop bit to conversion complete (both channels) 125 ms Conversion Rate Timing Conversion-Rate Control Byte=04h, 1Hz 1 sec High level176Remote-Diode Source CurrentDXP forced to 1.5VLow level11µAElectrical Characteristics (continued)(VCC = + 3.3V, T A = 0 to +85°C, unless otherwise noted.)Note 1: A remote diode is any diode-connected transistor from Table1. T R is the junction temperature of the remote of the remote diode. See Remote Diode Selection for remote diode forward voltage requirements.Note 2: Guaranteed by design but not 100% tested.Pin DescriptionDetailed DescriptionThe G781 is a temperature sensor designed to work in conjunction with an external microcontroller (µC) or other intelligence in thermostatic, process-control, or monitoring applications. The µC is typically a power- management or keyboard controller, generating SMBus serial commands by “bit-banging” general- purpose input-output (GPIO) pins or via a dedicated SMBus interface block.Essentially an serial analog-to digital converter (ADC) with a sophisticated front end, the G781 contains a switched current source, a multiplexer, an ADC, an SMBus interface, and associated control logic (Figure 1). Temperature data from the ADC is loaded into two data registers, where it is automatically compared with data previously stored in several over/under- tem-perature alarm registers.ADC and MultiplexerThe ADC is an averaging type that integrates over a 60ms period (each channel, typical), with excellent noise rejection.The multiplexer automatically steers bias currents through the remote and local diodes, measures their forward voltages, and computes their temperatures. Both channels are automatically converted once the conversion process has started, either in free-running or single-shot mode. If one of the two channels is not used, the device still performs both measurements, and the user can simply ignore the results of the un-used channel. If the remote diode channel is unused, tie DXP to DXN rather than leaving the pins open. The worst-case DXP-DXN differential input voltage range is 0.25V to 0.95V.Excess resistance in series with the remote diode causes about +0.6°C error per ohm. Likewise, 240µV of offset voltage forced on DXP-DXN causes about 1°C error.Figure 1. Functional DiagramSMBDATA SMBCLKA/D Conversion SequenceIf a Start command is written (or generated automati-cally in the free-running auto-convert mode), both channels are converted, and the results of both meas-urements are available after the end of conversion. A BUSY status bit in the status byte shows that the de-vice is actually performing a new conversion; however, even if the ADC is busy, the results of the previous conversion are always available.Remote Diode SelectionTemperature accuracy depends on having a good- quality, diode-connected small-signal transistor. The G781 can also directly measure the die temperature of CPUs and other integrated circuits having on-board temperature-sensing diodes.The transistor must be a small-signal type with a rela-tively high forward voltage; otherwise, the A/D input voltage range can be violated. The forward voltage must be greater than 0.25V at 10µA; check to ensure this is true at the highest expected temperature. The forward voltage must be less than 0.95V at 300µA; check to ensure this is true at the lowest expected temperature. Large power transistors don’t work at all. Also, ensure that the base resistance is less than 100Ω. Tight specifications for forward-current gain (+50 to +150, for example) indicate that the manufac-turer has good process controls and that the devices have consistent V be characteristics.Thermal Mass and Self-HeatingThermal mass can seriously degrade the G781’s ef-fective accuracy. The thermal time constant of the SOP- package is about 140 in still air. For the G781 junction temperature to settle to within +1°C after a sudden +100°C change requires about five time con-stants or 12 minutes. The use of smaller packages for remote sensors, such as SOT23s, improves the situa-tion. Take care to account for thermal gradients be-tween the heat source and the sensor, and ensure that stray air currents across the sensor package do not interfere with measurement accuracy. Self-heating does not significantly affect measurement accuracy. Remote-sensor self-heating due to the diode current source is negligible. For the local diode, the worst-case error occurs when auto-converting at the fastest rate and simultaneously sinking maximum current at the ALERT output. For example, at an 8Hz rate and with ALERT sinking 1mA, the typical power dissipation isVCC x 320µA plus 0.4V x 1mA. Package theta J-A is about 120°C /W, so with VCC = 3.3V and no copper PC board heat-sinking, the resulting temperature rise is:dT =1.45mW x 120°C /W =0.17°CEven with these contrived circumstances, it is difficultto introduce significant self-heating errors.Table 1. Remote-Sensor Transistor Manufacturers MANUFACTURER MODELNUMBER Philips PMBS3904Motorola(USA) MMBT3904 National Semiconductor (USA) MMBT3904Note:Transistors must be diode-connected (baseshorted to collector).ADC Noise FilteringThe ADC is an integrating type with inherently good noise rejection. Micropower operation places con-straints on high-frequency noise rejection; therefore, careful PC board layout and proper external noise fil-tering are required for high-accuracy remote meas-urements in electrically noisy environments.High-frequency EMI is best filtered at DXP and DXNwith an external 2200pF capacitor. This value can be increased to about 3300pF(max), including cable ca-pacitance. Higher capacitance than 3300pF introduces errors due to the rise time of the switched current source.Nearly all noise sources tested cause the ADC meas-urements to be higher than the actual temperature, typically by +1°C to 10°C, depending on the frequencyand amplitude.PC Board LayoutPlace the G781 as close as practical to the remote diode. In a noisy environment, such as a computer motherboard, this distance can be 4 in. to 8 in. (typical)or more as long as the worst noise sources (such as CRTs, clock generators, memory buses, and ISA/PCI buses) are avoided.Do not route the DXP-DXN lines next to the deflection coils of a CRT. Also, do not route the traces across a fast memory bus, which can easily introduce +30°C error, even with good filtering, Otherwise, most noise sources are fairly benign.Route the DXP and DXN traces in parallel and in close proximity to each other, away from any high-voltage traces such as +12V DC. Leakage currents from PC board contamination must be dealt with carefully, since a 10MΩ leakage path from DXP to ground causes about +1°C error.Connect guard traces to GND on either side of the DXP-DXN traces (Figure 2). With guard traces in place, routing near high-voltage traces is no longer an issue.Route through as few vias and crossunders as possible to minimize copper/solder thermocouple ef-fects.When introducing a thermocouple, make sure that both the DXP and the DXN paths have matching thermocouples. In general, PC board-induced ther-mocouples are not a serious problem, A copper-solder thermocouple exhibits 3µV/°C, and it takes about 240µV of voltage error at DXP-DXN to cause a +1°C measurement error. So, most parasitic thermocouple errors are swamped out.Use wide traces. Narrow ones are more inductive and tend to pick up radiated noise. The 10 mil widths and spacing recommended on Figure 2 aren’t absolutely necessary (as they offer only a minor improvement in leakage and noise), but try to use them where practi-cal.Keep in mind that copper can’t be used as an EMI shield, and only ferrous materials such as steel work will. Placing a copper ground plane between the DXP-DXN traces and traces carrying high-frequency noise signals does not help reduce EMI.PC Board Layout ChecklistPlace the G781 close to a remote diode.Keep traces away from high voltages (+12V bus).Keep traces away from fast data buses and CRTs. Use recommended trace widths and spacing.Place a ground plane under the tracesUse guard traces flanking DXP and DXN and con necting to GND.Place the noise filter and the 0.1µF VCC bypass capacitors close to the G781.Figure 2. Recommended DXP/DXN PC Traces Twisted Pair and Shielded CablesFor remote-sensor distances longer than 8 in., or in particularly noisy environments, a twisted pair is rec-ommended. Its practical length is 6 feet to 12feet (typi cal) before noise becomes a problem, as tested in a noisy electronics laboratory. For longer distances, the best solution is a shielded twisted pair like that used for audio microphones. Connect the twisted pair to DXP and DXN and the shield to GND, and leave the shield’s remote end unterminated.Excess capacitance at DX_limits practical remote sen-sor distances (see Typical Operating Characteristics), For very long cable runs, the cable’s parasitic capaci-tance often provides noise filtering, so the 2200pF ca-pacitor can often be removed or reduced in value. Ca-ble resistance also affects remote-sensor accuracy; 1Ωseries resistance introduces about + 0.6°C error.Low-Power Standby ModeStandby mode disables the ADC and reduces the supply-current drain to about 10µA. Enter standby mode by forcing high to the RUN/STOP bit in the con-figuration byte register. Software standby mode be-haves such that all data is retained in memory, and the SMB interface is alive and listening for reads and writes.Software standby mode is not a shutdown mode. With activity on the SMBus, extra supply current is drawn (see Typical Operating Characteristics). In software standby mode, the G781 can be forced to perform A/D conversions via the one-shot command, despite the RUN/STOP bit being high.10 MILSMINIMUM10 MILS10 MILSIf software standby command is received while a con-version is in progress, the conversion cycle is trun-cated, and the data from that conversion is not latched into either temperature reading register. The previous data is not changed and remains available.Supply-current drain during the 125ms conversion period is always about 320µA. Slowing down the con-version rate reduces the average supply current (see Typical Operating Characteristics). In between con-versions, the instantaneous supply current is about 25µA due to the current consumed by the conversion rate timer. In standby mode, supply current drops to about 3µA. At very low supply voltages (under the power-on-reset threshold), the supply current is higher due to the address pin bias currents. It can be as high as 100µA, depending on ADD0 and ADD1 settings. SMBus Digital InterfaceFrom a software perspective, the G781 appears as a set of byte-wide registers that contain temperature data, alarm threshold values, or control bits, A stan-dard SMBus 2-wire serial interface is used to read temperature data and write control bits and alarm threshold data.Each A/D channel within the device responds to the same SMBus slave address for normal reads and writes.The G781 employs four standard SMBus protocols: Write Byte, Read Byte, Send Byte, and Receive Byte (Figure 3). The shorter Receive Byte protocol allows quicker transfers, provided that the correct data regis-ter was previously selected by a Read Byte instruction. Use caution with the shorter protocols in multi-master systems, since a second master could overwrite the command byte without informing the first master.The temperature data format is 11bits plus sign in twos-complement form for remote channel, with each data bit representing 0.125°C (Table 2,Table 3), transmitted MSB first. Table 2. Temperature Data Format(Two’s-Complement)DIGITAL OUTPUTDATA BITSTEMP.(°C)SIGN MSB LSB EXT+127.875 0 111 1111 111+126.375 0 111 1110 011+25.5 0 001 1001 100+1.75 0 000 0001 110+0.5 0 000 0000 100+0.125 0 000 0000 001-0.125 1 111 1111 111-1.125 1 111 1110 111-25.5 1 110 0110 100-55.25 1 100 1000 110-65.000 1 011 1111 000Table 3. Extended Temperature Data FormatEXTENDEDRESOLUTIONDATA BITS0.000°C 000000000.125°C 001000000.250°C 010000000.375°C 011000000.500°C 100000000.625°C 101000000.750°C 110000000.875°C 11100000Slave AddressThe G781 appears to the SMBus as one device hav-ing a common address for both ADC channels. The G781 device address is set to 1001100.The G781 also responds to the SMBus Alert Re-sponse slave address (see the Alert Response Ad-dress section).One-Shot RegisterThe One-shot register is to initiate a single conversion and comparison cycle when the device is in standby mode and auto conversion mode. The write operation to this register causes one-shot conversion and the data written to it is irrelevant and is not stored.Serial Bus Interface ReinitializationWhen SMBCLK are held low for more than 30ms (typical) during an SMBus communication the G781 will reinitiateits bus interface and be ready for a new transmission. Alarm Threshold RegistersFour registers store alarm threshold data, with high-temperature (T HIGH) and low-temperature (T LOW) registers for each A/D channel. If either measured temperature equals or exceeds the corresponding alarm threshold value, an ALERT interrupt is as-serted.The power-on-reset (POR) state of both T HIGH registers is full scale (01010101, or +85°C). The POR state of both T LOW registers is 0°C.Diode Fault AlarmThere is a fault detector at DXP that detects whether the remote diode has an open-circuit condition. At the beginning of each conversion, the diode fault is checked, and the status byte is updated. This fault de-tector is a simple voltage detector. If DXP rises above VCC – 1V (typical) due to the diode current source, a fault is detected and the device alarms through pulling ALERT low while the remote temperature reading doesn’t update in this condition. Note that the diode fault isn’t checked until a conversion is initiated, so im-mediately after power-on reset the status byte indicates no fault is present, even if the diode path is broken.If the remote channel is shorted (DXP to DXN or DXP to GND), the ADC reads 1000 0000(-128°C) so as not to trip either the T HIGH or T LOW alarms at their POR settings. ALERT InterruptsThe ALERT interrupt output signal is latched and canonly be cleared by reading the Alert Response ad-dress. Interrupts are generated in response to T HIGHand T LOW comparisons and when the remote diode is disconnected (for fault detection). The interrupt doesnot halt automatic conversions; new temperature datacontinues to be available over the SMBus interfaceafter ALERT is asserted. The interrupt output pin isopen-drain so that devices can share a common in-terrupt line. The interrupt rate can never exceed theconversion rate.The interface responds to the SMBus Alert Responseaddress, an interrupt pointer return-address feature(see Alert Response Address section). Prior to takingcorrective action, always check to ensure that an in-terrupt is valid by reading the current temperature.Alert Response AddressThe SMBus Alert Response interrupt pointer providesquick fault identification for simple slave devices thatlack the complex, expensive logic needed to be a busmaster. Upon receiving an ALERT interrupt signal,the host master can broadcast a Receive Byte trans-mission to the Alert Response slave address (0001100). Then any slave device that generated an inter-rupt attempts to identify itself by putting its own ad-dress on the bus (Table 4).The Alert Response can activate several differentslave devices simultaneously, similar to the SMBusGeneral Call. If more than one slave attempts to re-spond, bus arbitration rules apply, and the device withthe lower address code wins. The losing device doesnot generate an acknowledge and continues to holdthe ALERT line low until serviced (implies that thehost interrupt input is level-sensitive). Successfulreading of the alert response address clears the inter-rupt latch.Table 4. Read Format for Alert Response Address(0001 100)BIT NAME7(MSB) ADD76 ADD65 ADD54 ADD43 ADD32 ADD21 ADD10(LSB) 1Command Byte FunctionsThe 8-bit command byte register (Table 5) is the mas-ter index that points to the various other registers within the G781. The register’s POR state is 0000 0000, so that a Receive Byte transmission (a protocol that lacks the command byte) that occurs immediately after POR returns the current local temperature data.The one-shot command immediately forces a new conversion cycle to begin. In software standby mode (RUN/STOP bit = high), a new conversion is begun, after which the device returns to standby mode. If a conversion is in progress when a one-shot command is received in auto-convert mode (RUN/STOP bit = low) between conversions, a new conversion begins, the conversion rate timer is reset, and the next auto-matic conversion takes place after a full delay elapses.Configuration Byte FunctionsThe configuration byte register (Table 6) is used to mask interrupts and to put the device in software standby mode. The other bits are empty. Status Byte FunctionsThe status byte register (Table 7) indicates which (if any) temperature thresholds have been exceeded. This byte also indicates whether or not the ADC is converting and whether there is an open circuit in the remote diode DXP-DXN path. After POR, the normal state of all the flag bits is zero, assuming none of the alarm conditions are present. The status byte is cleared by any successful read of the status, unless the fault persists. Note that the ALERT interrupt latch is not automatically cleared when the status flag bit is cleared.When reading the status byte, you must check for in-ternal bus collisions caused by asynchronous ADC timing, or else disable the ADC prior to reading the status byte (via the RUN/STOP bit in the configura-tion byte). In one-shot mode, read the status byte only after the conversion is complete, which is approxi-mately 125ms max after the one-shot conversion is commanded.Table 5. Command-Byte Bit Assignments*If the device is in standby mode at POR, both temperature registers read 0°C.Table 6. Configuration-Byte Bit AssignmentsTable 7. Status-Byte Bit Assignments*These flags stay high until cleared by POR, or until the status byte register is read.Table 8. Conversion-Rate Control ByteDATA CONVERSION RATE (Hz)00h 0.062501h 0.12502h 0.2503h 0.504h 105h 206h 407h 808h 16 09h to FFh RFUTo check for internal bus collisions, read the status byte. If the least significant seven bits are ones, dis-card the data and read the status byte again. The status bits LHIGH, LLOW, RHIGH, and RLOW are refreshed on the SMBus clock edge immediately fol-lowing the stop condition, so there is no danger of los-ing temperature-related status data as a result of an internal bus collision. The OPEN status bit (diode con-tinuity fault) is only refreshed at the beginning of a conversion, so OPEN data is lost. The ALERT inter-rupt latch is independent of the status byte register, so no false alerts are generated by an internal bus colli-sion. When auto-converting, if the THIGH and TLOW limits are close together, it’s possible for both high-temp and low-temp status bits to be set, depending on the amount of time between status read operations (espe-cially when converting at the fastest rate). In these circumstances, it’s best not to rely on the status bits to indicate reversals in long-term temperature changes and instead use a current temperature reading to es-tablish the trend direction.For bit 1 and bit 0, a high indicates a temperature alarm happened for remote and local diode respec-tively. THERM pin also asserts. These two bits wouldn’t be cleared when reading status byte.Conversion Rate ByteThe conversion rate register (Table 8) programs the time interval between conversions in free-running auto-convert mode. This variable rate control reduces the supply current in portable-equipment applications. The conversion rate byte’s POR state is 08h (16Hz). The G781 looks only at the 4 LSB bits of this register, so the upper 4 bits are “don’t care” bits, which should be set to zero. The conversion rate tolerance is ±25% at any rate setting.Valid A/D conversion results for both channels are available one total conversion time (125ms,typical) after initiating a conversion, whether conversion is initiated via the RUN/STOP bit, one-shot command, or initial power-up.POR AND UVLOThe G781 has a volatile memory. To prevent ambiguous power-supply conditions from corrupting the data in memory and causing erratic behavior, a POR voltage detector monitors VCC and clears the memory if VCC falls below 1.7V (typical, see Electrical Characteristics table). When power is first applied and VCC rises above 1.7V (typical), the logic blocks begin operating, although reads and writes at V CC levels below 3V are not recom-mended. A second VCC comparator, the ADC UVLO comparator, prevents the ADC from converting until there is sufficient headroom (VCC= 2.8V typical).ALERT Fault QueueTo suppress unwanted ALERT triggering the G781 em-bedded a fault queue function. The ALERT won’t as-sert until consecutive out of limit measurements have reached the queue number. The mapping of fault queue register (ALERTFQ, 22h) value to fault queue number is shown in the Table 9.Table 9. Alert Fault QueueALERTFQVALUEFAULT QUEUE NUMBER XXXX000X 1XXXX001X 2XXXX010X 3XXXX011X 3XXXX100X 4XXXX101X 4XXXX110X 4XXXX111X 4 Operation of The THERM FunctionA local and remote THERM limit can be programmed into the G781 to set the temperature limit above which the THERM pin asserts low and the bit 1, of status byte will be set to 1 corresponding to remote and local over temperature. These two bits won’t be cleared to 0 by reading status byte it the over temperature condi-tion remain. A hysteresis value is provided by writing the register 21h to set the temperature threshold to release the THERM pin alarm state, The releasing temperature is the value of register 19h, 20h minus the value in register 21h. The format of register 21h is 2’s complement. The THERM signal is open drain and requires a pull-up resistor to power supply.Figure 4. SMBus Write Timing DiagramA = start condition H = LSB of data clocked into slaveB = MSB of address clocked into slave I = slave pulls SMBDATA line lowC = LSB of address clocked into slave J = acknowledge clocked into masterD = R/W bit clocked into slave K = acknowledge clocked pulseE = slave pulls SMBDATA line low L = stop condition data executed by slaveF = acknowledge bit clocked into master M = new start conditionG = MSB of data clocked into slaveFigure 5. SMBus Read Timing DiagramA = start condition G = MSB of data clocked into masterB = MSB of address clocked into slave H = LSB of data clocked into masterC = LSB of address clocked into slave I = acknowledge clocked pulseD = R/W bit clocked into slave J = stop conditionE = slave pulls SMBDATA line low K= new start conditionF =acknowledge bit clocked into master。

AD7813资料

元器件交易网aFEATURES 8-/10-Bit ADC with 2.3 s Conversion Time On-Chip Track and Hold Operating Supply Range: +2.7 V to +5.5 V Specifications at 2.7 V – 3.6 V and 5 V 10% 8-Bit Parallel Interface 8-Bit + 2-Bit Read Power Performance Normal Operation 10.5 mW, VDD = 3 V Automatic Power-Down 34.6 W @ 1 kSPS, VDD = 3 V Analog Input Range: 0 V to V REF Reference Input Range: 1.2 V to VDD+2.7 V to +5.5 V, 400 kSPS 8-/10-Bit Sampling ADC AD7813FUNCTIONAL BLOCK DIAGRAMVDD AGND VREFAD7813CHARGE REDISTRIBUTION DAC CLOCK OSC THREESTATE DRIVERSDB7DB0VINT/HCOMPCONTROL LOGICBUSY CS RD CONVSTGENERAL DESCRIPTIONPRODUCT HIGHLIGHTSThe AD7813 is a high-speed, microprocessor-compatible, 8-/10-bit analog-to-digital converter with a maximum throughput of 400 kSPS. The converter operates off a single +2.7 V to +5.5 V supply and contains a 2.3 µs successive approximation A/D converter, track/hold circuitry, on-chip clock oscillator and 8-bit wide parallel interface. The parallel interface is designed to allow easy interfacing to microprocessors and DSPs. The 10-bit conversion result is read by carrying out two 8-bit read operations. The first read operation accesses the 8 MSBs of the ADC conversion result and the second read accesses the 2 LSBs. Using only address decoding logic the AD7813 is easily mapped into the microprocessor address space. When used in its power-down mode, the AD7813 automatically powers down at the end of a conversion and powers up at the start of a new conversion. This feature significantly reduces the power consumption of the part at lower throughput rates. The AD7813 can also operate in a high speed mode where the part is not powered down between conversions. In this mode of operation the part is capable of providing 400 kSPS throughput. The part is available in a small, 16-lead, 0.3" wide, plastic dualin-line package (DIP), in a 16-lead, 0.15" wide, narrow body small outline IC (SOIC) and in a 16-lead thin shrink small outline package (TSSOP).1. Low Power, Single Supply Operation The AD7813 operates from a single +2.7 V to +5.5 V supply and typically consumes only 10.5 mW of power. The power dissipation can be significantly reduced at lower throughput rates by using the automatic power-down mode. 2. Automatic Power-Down The automatic power-down mode, whereby the AD7813 goes into power-down mode at the end of a conversion and powers up before the next conversion, means the AD7813 is ideal for battery powered applications; e.g., 34.6 µW @ 1 kSPS. (See Power vs. Throughput Rate section.) 3. Parallel Interface An easy to use 8-bit-wide parallel interface allows interfacing to most popular microprocessors and DSPs with minimal external circuitry. 4. Dynamic Specifications for DSP Users In addition to the traditional ADC specifications, the AD7813 is specified for ac parameters, including signal-to-noise ratio and distortion.REV. BInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: Fax: 781/326-8703 © Analog Devices, Inc., 2000元器件交易网AD7813–SPECIFICATIONS1 +105 C unless otherwise noted.)(GND = 0 V, VREF = +VDD = 3 VUnit dB min dB max dB max Parameter DYNAMIC PERFORMANCE Signal to (Noise + Distortion) Ratio1 Total Harmonic Distortion (THD)1 Peak Harmonic or Spurious Noise1 Intermodulation Distortion2 2nd Order Terms 3rd Order Terms DC ACCURACY Resolution Minimum Resolution for Which No Missing Codes Are Guaranteed Relative Accuracy1 Differential Nonlinearity (DNL)1 Gain Error1 Offset Error1 ANALOG INPUT Input Voltage Range Input Leakage Current2 Input Capacitance2 REFERENCE INPUTS2 VREF Input Voltage Range Input Leakage Current Input Capacitance LOGIC INPUTS2 VINH, Input High Voltage VINL, Input Low Voltage Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL High Impedance Leakage Current High Impedance Capacitance CONVERSION RATE Conversion Time Track/Hold Acquisition Time1 POWER SUPPLY V DD I DD Normal Operation Power-Down Power Dissipation Normal Operation Power-Down Auto Power-Down 1 kSPS Throughput 10 kSPS Throughput 100 kSPS Throughput Y Version 58 –66 –66 –67 –67 10 10 ±1 ±1 ±2 ± 2.0 0 VREF ±1 20 1.2 V DD ±3 15 2.0 0.4 ±1 8 2.4 0.4 ±1 15 2.3 100 2.7–5.5 3.5 1 17.5 5 34.6 346.5 3.4610% to 5 V10%. All specifications –40 C toTest Conditions/Comments fIN = 30 kHz, fSAMPLE = 350 kHzfa = 29.1 kHz, fb = 29.8 kHz dB typ dB typ Bits Bits LSB max LSB max LSB max LSB max V min V max µA max pF max V min V max µA max pF max V min V max µA max pF max V min V max µA max pF max µs max ns max Volts mA max µA max mW max µW max µW max µW max mW max For Specified Performance Digital Inputs = 0 V or VDD VDD = 5 V VDD = 5 V VDD = 3 V(0.8 V max, VDD = 5 V) Typically 10 nA, VIN = 0 V to VDDISOURCE = 200 µA ISINK = 200 µANOTES 1 See Terminology section. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice.–2–REV. B元器件交易网AD7813 TIMING CHARACTERISTICS1, 2Parameter tPOWER-UPt1 t2 t3 t4 t5 t 63 t73, 4 t8 t 93(–40 C to +105 C, unless otherwise noted)10% Unitµs (max) µs (max) ns (min) ns (max) ns (min) ns (min) ns (max) ns (max) ns (min) ns (min) ns (min)VDD = 3 V1 2.3 20 30 0 0 10 10 5 10 5010%VDD = 5 V1 2.3 20 30 0 0 10 10 5 10 50Conditions/CommentsPower-Up Time of AD7813 after Rising Edge of CONVST. Conversion Time. CONVST Pulsewidth. CONVST Falling Edge to BUSY Rising Edge Delay. CS to RD Setup Time. CS Hold Time after RD High. Data Access Time after RD Low. Bus Relinquish Time after RD High. Minimum Time Between MSB and LSB Reads. Rising Edge of CS or RD to Falling Edge of CONVST Delay.NOTES 1 Sample tested to ensure compliance. 2 See Figures 12, 13 and 14. 3 These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and 0.4 V or 2 V for V DD = 3 V ± 10%. 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.ABSOLUTE MAXIMUM RATINGS*VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Digital Input Voltage to DGND (CONVST, RD, CS) . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V Digital Output Voltage to DGND (BUSY, DB0–DB7) . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V REFIN to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V Analog Input . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . +105°C/W Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . +260°C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≥4 kV*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.200 AIOLTO OUTPUT PIN+1.6V CL 50pF 200 A IOHFigure 1. Load Circuit for Digital Output Timing SpecificationsORDERING GUIDEModelLinearity Error Package (LSB) DescriptionPackage OptionAD7813YN ± 1 LSB AD7813YR ± 1 LSB AD7813YRU ± 1 LSBPlastic DIP N-16 Small Outline IC R-16A Thin Shrink Small Outline RU-16 (TSSOP)REV. B–3–元器件交易网AD7813PIN FUNCTION DESCRIPTIONSPin No. 1 2 3 4Mnemonic VREF VIN GND CONVSTDescription Reference Input, 1.2 V to VDD. Analog Input, 0 V to VREF. Analog and Digital Ground. Convert Start. A low-to-high transition on this pin initiates a 1 µs pulse on an internally generated CONVST signal. A high-to-low transition on this line initiates the conversion process if the internal CONVST signal is low. Depending on the signal on this pin at the end of a conversion, the AD7813 automatically powers down. Chip Select. This is a logic input. CS is used in conjunction with RD to enable outputs. Read Pin. This is a logic input. When CS is low and RD goes low, the DB7–DB0 leave their high impedance state and data is driven onto the data bus. ADC Busy Signal. This is a logic output. This signal goes logic high during the conversion process. Data Bit 0 to 7. These outputs are three-state TTL-compatible. Positive power supply voltage, +2.7 V to +5.5 V.PIN CONFIGURATION DIP/SOIC5 6 7 8–15 16CS RD BUSY DB0–DB7 VDDVREF 1 VIN 2 GND 3 CONVST 416 VDD 15 DB7 14 DB613 DB5 TOP VIEW CS 5 (Not to Scale) 12 DB4 RD 6 11 DB3 10 DB2 9 DB1AD7813BUSY 7 DB0 8–4–REV. B元器件交易网AD7813TERMINOLOGY Signal to (Noise + Distortion) Ratio Relative AccuracyThis is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Thus for an 10-bit converter, this is 62 dB.Total Harmonic DistortionRelative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.Offset ErrorThis is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB.Offset Error MatchThis is the difference in Offset Error between any two channels.Gain ErrorTotal harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7813 it is defined as:V2 + V 3 + V 4 + V 5 + V6 V12 2 2 2 2This is the deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal, i.e., VREF – 1 LSB, after the offset error has been adjusted out.Gain Error MatchTHD (dB) = 20 logThis is the difference in Gain Error between any two channels.Track/Hold Acquisition Timewhere V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics.Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak.Intermodulation DistortionTrack/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ± 1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected VIN input of the AD7813. It means that the user must wait for the duration of the track/hold acquisition time after the end of conversion, or after a step input change to VIN, before starting another conversion, to ensure that the part operates to specification.With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The AD7813 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs.REV. B–5–元器件交易网AD7813CIRCUIT DESCRIPTION Converter OperationSUPPLY +2.7V TO +5.5V 10 F 0.1 F VDD VREF DB0-DB7 0V TO VREF INPUT PARALLEL INTERFACEThe AD7813 is a successive approximation analog-to-digital converter based around a charge redistribution DAC. The ADC can convert analog input signals in the range 0 V to VDD. Figures 2 and 3 below show simplified schematics of the ADC. Figure 2 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition and the sampling capacitor acquires the signal on VIN+.CHARGE REDISTRIBUTION DAC A VIN+ SW1 B ACQUISITION PHASE VDD/3 SW2 COMPARATOR CLOCK OSC SAMPLING CAPACITOR CONTROL LOGICAD7813VIN GND BUSY RD CS CONVSTC/ PFigure 4. Typical Connection DiagramAnalog InputAGNDFigure 2. ADC Track PhaseWhen the ADC starts a conversion (see Figure 3), SW2 will open and SW1 will move to Position B, causing the comparator to become unbalanced. The Control Logic and the Charge Redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor so as to bring the comparator back into a balanced condition. When the comparator is rebalanced the conversion is complete. The Control Logic generates the ADC output code. Figure 7 shows the ADC transfer function.CHARGE REDISTRIBUTION DAC A SW1 B CONVERSION PHASE VDD/3 SAMPLING CAPACITOR SW2 COMPARATOR CLOCK OSC CONTROL LOGICFigure 5 shows an equivalent circuit of the analog input structure of the AD7813. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. This will cause these diodes to become forward biased and start conducting current into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the part is 20 mA. The capacitor C2, in Figure 5, is typically about 4 pF and can be primarily attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a multiplexer and a switch. This resistor is typically about 125 Ω. The capacitor C1 is the ADC sampling capacitor and has a capacitance of 3.5 pF.VDDD1 VIN C2 4pF D2R1 125C1 3.5pF VDD/3CONVERT PHASE – SWITCH OPEN TRACK PHASE – SWITCH CLOSEDVIN+Figure 5. Equivalent Analog Input CircuitDC Acquisition TimeAGNDFigure 3. ADC Conversion PhaseTYPICAL CONNECTION DIAGRAMFigure 4 shows a typical connection diagram for the AD7813. The parallel interface is implemented using an 8-bit data bus, the falling edge of CONVST brings the BUSY signal high, and at the end of conversion the falling edge of BUSY is used to initiate an Interrupt Service Routine (ISR) on a microprocessor— see Parallel Interface section for more details. VREF is connected to a well decoupled VDD pin to provide an analog input range of 0 V to VDD. When VDD is first connected the AD7813 powers up in a low current mode, i.e., power-down. A rising edge on an internal CONVST input will cause the part to power up—see Power-Up Times. If power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power performance. See Power vs. Throughput Rate section of the data sheet.The ADC starts a new acquisition phase at the end of a conversion and ends on the falling edge of the CONVST signal. At the end of a conversion there is a settling time associated with the sampling circuit. This settling time lasts approximately 100 ns. The analog signal on VIN is also being acquired during this settling time; therefore, the minimum acquisition time needed is approximately 100 ns. Figure 6 shows the equivalent charging circuit for the sampling capacitor when the ADC is in its acquisition phase. R2 represents the source impedance of a buffer amplifier or resistive network, R1 is an internal multiplexer resistance and C1 is the sampling capacitor.R2 VIN R1 125 C1 3.5pFFigure 6. Equivalent Sampling Circuit–6–REV. B元器件交易网AD7813During the acquisition phase the sampling capacitor must be charged to within a 1/2 LSB of its final value. The time it takes to charge the sampling capacitor (TCHARGE) is given by the following formula: TCHARGE = 7.6 × (R2 + 125 Ω) × 3.5 pF For small values of source impedance, the settling time associated with the sampling circuit (100 ns) is, in effect, the acquisition time of the ADC. For example, with a source impedance (R2) of 10 Ω the charge time for the sampling capacitor is approximately 4 ns. The charge time becomes significant for source impedances of 2 kΩ and greater.AC Acquisition TimeINT CONVSTMODE 1VDD EXT CONVSTt POWER-UP1 sMODE 2VDD EXT CONVSTIn ac applications it is recommended to always buffer analog input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates.ADC TRANSFER FUNCTIONt POWER-UP1 s INT CONVSTt POWER-UP1 sFigure 8. Power-Up TimesPOWER VS. THROUGHPUT RATEThe output coding of the AD7813 is straight binary. The designed code transitions occur at successive integer LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/1024. The ideal transfer characteristic for the AD7813 is shown in Figure 7.By operating the AD7813 in Mode 2, the average power consumption of the AD7813 decreases at lower throughput rates. Figure 9 shows how the Automatic Power-Down is implemented using the external CONVST signal to achieve the optimum power performance for the AD7813. The AD7813 is operated in Mode 2, and the duration of the external CONVST pulse is set to be equal to or less than the power-up time of the device. As the throughput rate is reduced, the device remains in its powerdown state longer and the average power consumption over time drops accordingly.EXT CONVST111...111 111...110ADC CODE111...000 1LSB = VREF/1024 011...111 000...010 000...001 000...000 0V 1LSB ANALOG INPUT +VREF–1LSBt POWER-UPt CONVERT1 s INT CONVST 2.0 s POWER-DOWNFigure 7. Transfer CharacteristicPOWER-UP TIMESt CYCLE100 s @ 10kSPSThe AD7813 has a 1 µs power-up time. When VDD is first connected, the AD7813 is in a low current mode of operation. In order to carry out a conversion the AD7813 must first be powered up. The ADC is powered up by a rising edge on an internally generated CONVST signal, which occurs as a result of a rising edge on the external CONVST pin. The rising edge of the external CONVST signal initiates a 1 µs pulse on the internal CONVST signal. This pulse is present to ensure the part has enough time to power up before a conversion is initiated, as a conversion is initiated on the falling edge of gated CONVST. See Timing and Control section. Care must be taken to ensure that the CONVST pin of the AD7813 is logic low when VDD is first applied. When operating in Mode 2, the ADC is powered down at the end of each conversion and powered up again before the next conversion is initiated. (See Figure 8.)Figure 9. Automatic Power-DownFor example, if the AD7813 is operated in a continuous sampling mode, with a throughput rate of 10 kSPS, the power consumption is calculated as follows. The power dissipation during normal operation is 10.5 mW, VDD = 3 V. If the power-up time is 1 µs and the conversion time is 2.3 µs, the AD7813 can then be said to dissipate 10.5 mW for 3.3 µs (worst case) during each conversion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 µs and the average power dissipated during each cycle is (3.3/100) × (10.5 mW) = 346.5 µW.REV. B–7–元器件交易网AD7813 Typical Performance Characteristics10POWER – mW10.1At the end of conversion the sampling circuit goes back into its tracking mode again. The end of conversion is indicated by the BUSY signal going low. This signal may be used to initiate an ISR on a microprocessor. At this point the conversion result is latched into the output register where it may be read. The AD7813 has an 8-bit wide parallel interface. The 10-bit conversion result is accessed by performing two successive read operations. The first 8-bit read accesses the 8 MSBs of the conversion result and the second read accesses the 2 LSBs, as illustrated in Figure 13, where one performance of the two successive reads is highlighted after the falling edge of BUSY. The state of the external CONVST signal at the end of conversion also establishes the mode of operation of the AD7813.Mode 1 Operation (High Speed Sampling)0.01 0 5 10 15 20 25 30 35 THROUGHPUT – kSPS 40 45 50Figure 10. Power vs. Throughput0 –10 –20 –30 –40dBsAD7813 2048 POINT FFT SAMPLING 357.142kHz FIN 30.168kHzIf the external CONVST is logic high when BUSY goes low, the part is said to be in Mode 1 operation. While operating in Mode 1, the AD7813 will not power down between conversions. The AD7813 should be operated in Mode 1 for high speed sampling applications, i.e., throughputs greater than 100 kSPS. Figure 13 shows the timing for Mode 1 operation. From this diagram one can see that a minimum delay of the sum of the conversion time and read time must be left between two successive falling edges of the external CONVST. This is to ensure that a conversion is not initiated during a read.Mode 2 Operation (Automatic Power-Down)–50 –60 –70 –80 –90 –100 0 17 35 52 70 87 105 122 FREQUENCY – kHz 140 157 174Figure 11. SNRTIMING AND CONTROLThe AD7813 has only one input for timing and control, i.e., the CONVST (convert start signal). The rising edge of this CONVST signal initiates a 1 µs pulse on an internally generated CONVST signal. This pulse is present to ensure the part has enough time to power up before a conversion is initiated. If the external CONVST signal is low, the falling edge of the internal CONVST signal will cause the sampling circuit to go into hold mode and initiate a conversion. If, however, the external CONVST signal is high when the internal CONVST goes low, it is upon the falling edge of the external CONVST signal that the sampling circuitry will go into hold mode and initiate a conversion. The use of the internally generated 1 µs pulse, as previously described, can be likened to the configuration shown in Figure 12. The application of a CONVST signal at the CONVST pin triggers the generation of a 1 µs pulse. Both the external CONVST and this internal CONVST are input to an OR gate. The resulting signal has the duration of the longer of the two input signals. Once a conversion has been initiated the BUSY signal goes high to indicate a conversion is in progress.At slower throughput rates the AD7813 may be powered down between conversions to give a superior power performance. This is Mode 2 Operation and it is achieved by bringing the CONVST signal logic low before the falling edge of BUSY. Figure 14, overleaf, shows the timing for Mode 2 Operation. The falling edge of the external CONVST signal may occur before or after the falling edge of the internal CONVST signal, but it is the later occurring falling edge of both that controls when the first conversion will take place. If the falling edge of the external CONVST occurs after that of the internal CONVST, it means that the moment of the first conversion is controlled exactly, regardless of any jitter associated with the internal CONVST signal. The parallel interface is still fully operational while the AD7813 is powered down. The AD7813 is powered up again on the rising edge of the CONVST signal. The gated CONVST pulse will now remain high long enough for the AD7813 to fully power up, which takes about 1 µs. This is ensured by the internal CONVST signal, which will remain high for 1 µs.CONVST (PIN 4)EXT GATED INT1 sFigure 12.–8–REV. B元器件交易网AD7813t2EXT CONVSTt1t3 t POWER-UPINT CONVSTBUSYCS/RDDB7–DB08 MSBs2 LSBsFigure 13. Mode 1 OperationEXT CONVSTt POWER-UPINT CONVSTt1t3BUSYCS/RDDB7–DB08 MSBsFigure 14. Mode 2 OperationPARALLEL INTERFACEThe parallel interface of the AD7813 is eight bits wide. The output data buffers are activated when both CS and RD are logic low. At this point the contents of the data register are placed on the 8-bit data bus. Figure 15 shows the timing diagram for the parallel port. As previously explained, two successive read operations must take place in order to access the 10-bit conversion result. The first read places the 8 MSBs on the data bus and the second read places the 2 LSBs on the data bus. The 2 LSBs appear on DB7 and DB6, with DB5–DB0 set to logic zero.Further read operations will access the 8 MSBs and 2 LSBs of the 10-bit ADC conversion result again. The parallel interface of the AD7813 is reset when BUSY goes logic high. This feature allows the AD7813 to be used as an 8-bit converter if the user only wishes to access the 8 MSBs of the conversion. Care must be taken to ensure that a read operation does not occur while BUSY is high. Data read from the AD7813 while BUSY is high will be invalid. For optimum performance the read operation should end at least 100 ns (t10) prior to the falling edge of the next CONVST.CONVSTt3BUSYt2t9t1CSt8t4RDt5 t7 t68 MSBs 2 MSBsDB7–DB0Figure 15. Parallel Port TimingREV. B–9–。

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AC781x 数据手册说明书

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AC781x 数据手册适用于以下产品：型号子型号环境温度AC7811xxxx AC7811QBGE, AC7811OBGE, AC7811MBGE,AC7811QBFE, AC7811OBFE, AC7811MBFE, AC7811JBFE, AC7811QJGE, AC7811OJGE, AC7811MJGE, AC7811OJFE, AC7811MJFE, AC7811JJFE-40~125°CAC7813xxxx AC7813QBGE, AC7813OBGE, AC7813MBGE, AC7813OBFE, AC7813MBFE, AC7813JBFE -40~85°C AC7815xxxx AC7815QBGE, AC7815OBGE, AC7815MBGE, AC7815QBFE, AC7815OBFE, AC7815MBFE, AC7815JBFE-40~85°C修订记录文档目录修订记录 (2)文档目录 (3)1主要特性 (5)2器件标识 (6)2.1说明 (6)2.2格式 (6)2.3字段 (6)2.4示例 (6)3参数分类 (7)4额定值 (8)4.1热学操作额定值 (8)4.2湿度操作额定值 (8)4.3ESD 操作额定值 (8)4.4电压和电流操作额定值 (9)5通用 (10)5.1静态电气规格 (10)5.1.1电源和地引脚 (10)5.1.2DC 特性 (10)5.1.3电源电流特性 (13)5.2动态规格 (14)5.2.1控制时序 (14)5.2.2PWM模块时序 (15)5.3热规格 (16)5.3.1热特性 (16)6外设工作要求和行为 (18)6.1内核模块 (18)6.1.1SWD 电气规格 (18)6.2外部振荡器 (OSC) 和 ICS 特性 (18)6.2.1外部振荡器(OSC) 特性 (18)6.2.2内部RC 特性 (19)6.2.3PLL 特性 (19)6.3片内Flash 规格 (20)6.4模拟 (21)6.4.1ADC 特性 (21)6.4.2模拟比较器（ACMP）电气规格 (22)6.5通信接口 (22)6.5.1SPI 开关规格 (22)6.5.2CAN特性 (25)7尺寸 (26)7.1LQFP64封装信息 (26)7.2LQFP80封装信息 (28)8引脚分配 (30)8.1信号多路复用和引脚分配 (30)8.2器件引脚分配 (34)1主要特性∙操作特性电压范围：2.7 到5.5 V温度范围 (环境)： -40 到125°C∙性能高达100 MHz的 ARM® Cortex-M3内核单周期 32位 x 32位乘法器快速I/O访问接口∙存储器和存储器接口最高256 KB的片内Flash最高 64 KB的静态随机存储器∙时钟振荡器 (Oscillator) –支持4 MHz到 30 MHz 石英晶体振荡器；可选择低功耗或高增益振荡器内部时钟源 (ICS) –内部PLL ，集成内部或外部基准时钟源， 8 MHz预校准内部基准时钟源，可用于100 MHz系统时钟内部32 kHz低功耗振荡器 (LPO)∙系统外设电源管理模块(PMC) 有三个功率模式：运行、待机和停止低压检测复位电路 (LVD)带独立时钟源的看门狗(WDOG)可编程循环冗余校验(CRC)模块串行线调试(SWD) & JTAG 接口Cortex®-M3 嵌入式跟踪宏单元™SRAM 位处理映射区域 (BIT-BAND) 1个12 通道 DMA ∙人机接口68 个通用输入输出接口 (GPIO)外部中断 (IRQ)模块∙模拟模块1个多达 16通道、12位的SAR ADC，工作在停止模式，可选硬件触发器 (ADC)2个包含6位DAC和可编程参考输入的模拟比较器(ACMP)∙定时器1个6通道脉宽调制（PWM）单元3个双通道 PWM1个8通道周期性中断定时器(TIMER)1个脉宽定时器 (PWDT)1个实时时钟 (RTC)∙通信接口2个 SPI 模块6个 UART模块（其中一路兼容Software LIN）2个I2C 模块2个CAN 模块1个硬件 LIN 模块∙封装选项80引脚 LQFP64引脚LQFP2器件标识2.1说明芯片器件型号包含可识别具体器件的字段。

D-A Converter价格数据大全

TI(德州仪器)德州仪器，简称TI，全球约 30,300人，总部位于美国得克萨斯州的达拉斯，2008年营业额为185亿美元，是全球领先的半导体公司，为现实世界的信号处理提供创新的数字信号处理(DSP)及模拟技术，应用领域涵盖无线通讯、宽带、网络家电、数字马达控制与消费类市场。

D/A Converter介绍随着数字技术，特别是信息技术的飞速发展与普及，在现代控制。

通信及检测等领域，为了提高系统的性能指标，对信号的处理广泛采用了数字计算机技术。

由于系统的实际对象往往都是一些模拟量(如温度。

压力。

位移。

图像等),要使计算机或数字仪表能识别。

处理这些信号，必须首先将这些模拟信号转换成数字信号；而经计算机分析。

处理后输出的数字量也往往需要将其转换为相应模拟信号才能为执行机构所接受。

这样，就需要一种能在模拟信号与数字信号之间起桥梁作用的电路-模数和数模转换器。

将模拟信号转换成数字信号的电路，称为模数转换器(简称a/d转换器或adc,analog to digital converter)；将数字信号转换为模拟信号的电路称为数模转换器(简称d/a转换器或dac,digital to analog converter)；a/d转换器和d/a 转换器已成为信息系统中不可缺俚慕涌诘缏贰？br>为确保系统处理结果的精确度，a/d转换器和d/a转换器必须具有足够的转换精度；如果要实现快速变化信号的实时控制与检测，a/d与d/a转换器还要求具有较高的转换速度。

转换精度与转换速度是衡量a/d与d/a转换器的重要技术指标。

D/A Converter系列产品价格型号产品描述价格PCM1753DBQR IC DAC 24BIT MONO 192KHZ 16-QSOP $0.94 PCM1753DBQR IC DAC 24BIT MONO 192KHZ 16-QSOP $2.25 PCM1753DBQR IC DAC 24BIT MONO 192KHZ 16-QSOP $2.17 PCM1748E/2K IC 24-BIT STER AUD D/A 16QSOP $1.07 PCM1748KE/2K IC 24-BIT STER AUD D/A 16QSOP $1.23 DAC5571IDBVT 8 BIT 12C SINGLE CHANNEL D/A CON $1.30 DAC5571IDBVT 8 BIT 12C SINGLE CHANNEL D/A CON $2.14 DAC5571IDBVT 8 BIT 12C SINGLE CHANNEL D/A CON $2.14 DAC7311IDCKT IC DAC 12-BIT 1-CH LP SC70-6 $1.35 DAC7311IDCKT IC DAC 12-BIT 1-CH LP SC70-6 $2.17 DAC7311IDCKT IC DAC 12-BIT 1-CH LP SC70-6 $2.30 TLC5602CDWR IC DAC 8BIT VIDEO LOW-PWR 20SOIC $1.35TLC5602CDWR IC DAC 8BIT VIDEO LOW-PWR 20SOIC $3.22 TLC5602CDWR IC DAC 8BIT VIDEO LOW-PWR 20SOIC $3.19 DAC7512N/250 IC 12-BIT R-R D/A CONV SOT-23-6 $2.06 DAC7512N/250 IC 12-BIT R-R D/A CONV SOT-23-6 $3.39 DAC7512N/250 IC 12-BIT R-R D/A CONV SOT-23-6 $3.43 TLV5620CN IC QUAD 8-BIT SERIAL D/A 14-DIP $2.07 DAC7512E/250 IC 12-BIT R-R D/A CONV MSOP-8 $2.01 DAC7512E/250 IC 12-BIT R-R D/A CONV MSOP-8 $3.26 型号产品描述价格DAC7512E/250 IC 12-BIT R-R D/A CONV MSOP-8 $3.60 DAC7552IRGTR IC DAC 12BIT DUAL W/SPI 16-QFN $2.21 DAC7552IRGTR IC DAC 12BIT DUAL W/SPI 16-QFN $4.97 DAC7552IRGTR IC DAC 12BIT DUAL W/SPI 16-QFN $4.61 TLV5623CD IC 8-BIT SERIAL D/A 8-SOIC $2.22 TLV5620CD IC 8BIT 10US QUAD DAC 14-SOIC $2.33TLV5623CDGK IC 8 BIT 3US DAC S/O 8-MSOP $2.12 DAC7811IDGSR IC DAC 12BIT MULTIPLYING 10-MSOP $2.22 DAC7811IDGSR IC DAC 12BIT MULTIPLYING 10-MSOP $5.12 DAC7811IDGSR IC DAC 12BIT MULTIPLYING 10-MSOP $4.88 DAC7571IDBVT IC DAC R-R LP 12BIT SOT23-6 $2.21 DAC7571IDBVT IC DAC R-R LP 12BIT SOT23-6 $3.95 DAC7571IDBVT IC DAC R-R LP 12BIT SOT23-6 $3.53 DAC7513N/250 IC 12-BIT R-R D/A CONV SOT-23-8 $2.28 DAC7513N/250 IC 12-BIT R-R D/A CONV SOT-23-8 $3.55 DAC7513N/250 IC 12-BIT R-R D/A CONV SOT-23-8 $3.65 DAC7513E/250 IC 12-BIT R-R D/A CONV MSOP-8 $2.30 DAC7513E/250 IC 12-BIT R-R D/A CONV MSOP-8 $4.06 DAC7513E/250 IC 12-BIT R-R D/A CONV MSOP-8 $4.06 PCM1754DBQ IC AUDIO DAC 24BIT 16QSOP $2.50型号产品描述价格PCM1753DBQ IC AUDIO DAC 24BIT 16QSOP $2.44 DAC8571IDGKR IC DAC 16BIT I2C V-OUT LP 8-MSOP $2.67 DAC8571IDGKR IC DAC 16BIT I2C V-OUT LP 8-MSOP $5.58 DAC8571IDGKR IC DAC 16BIT I2C V-OUT LP 8-MSOP $5.65 TLC7528CN IC DUAL 8-BIT MLTPLY DAC 20-DIP $2.58 PCM1748E IC 24-BIT STER AUD D/A 16QSOP $2.67 TLC7524CN IC DAC 8 BIT MULTIPLYING 16-DIP $2.77 TLV5606CD IC 10-BIT SERIAL D/A 8-SOIC $3.01 PCM1748KE IC 24-BIT STER AUD D/A 16QSOP $2.92 PCM1770RGA IC 24BIT LP STEREO DAC 20-VQFN $3.38 PCM1773RGA IC 24BIT LP STEREO DAC 20-VQFN $3.02 DAC7571IDBVR IC DAC R-R LP 12BIT SOT23-6 $1.35 DAC7571IDBVR IC DAC R-R LP 12BIT SOT23-6 $3.28 DAC7571IDBVR IC DAC R-R LP 12BIT SOT23-6 $3.08TLC7524CD IC DAC 8 BIT MULTIPLYING 16-SOIC $3.12 TLC7524EN IC DAC 8 BIT MULTIPLYING 16-DIP $3.36 TLC7524CFN IC DAC 8 BIT MULTIPLYING 20-PLCC $3.36 TLC5615CP IC 10 BIT 12.5US DAC S/O 8-DIP $3.62 TLC5620CN IC QUAD 8-BIT D/A CONV 14-DIP $3.70 PCM1772PW IC 24BIT LP STEREO DAC 16-TSSOP $3.53型号产品描述价格TLC5615IP IC 10-BIT SERIAL D/A 8-DIP $3.80 TLC7628CN IC 8 BIT 0.1US MDAC P/O 20-DIP $3.80 PCM1742KE/2K IC DAC 24BIT STER 192KHZ 16-QSOP $1.75 PCM1742KE/2K IC DAC 24BIT STER 192KHZ 16-QSOP $3.90 PCM1742KE/2K IC DAC 24BIT STER 192KHZ 16-QSOP $3.72 THS5641IDW IC 8-BIT 100MSPS D/A 28-SOIC $3.82 TLV5625CD IC DUAL 8-BIT SERIAL D/A 8-SOIC $3.57TLV5624ID IC 8BIT 1.0-3.5US DAC S/O 8-SOIC $3.80 TLC5620IN IC 8 BIT 10US DAC S/O 14-DIP $3.76PCM1733U IC 18-BIT STEREO D/A 14-SOIC $4.00 PCM1772RGA IC 24BIT LP STEREO DAC 20-VQFN $4.20 PCM1771RGA IC 24BIT LP STEREO DAC 20-VQFN $3.95 DAC8541Y/250 IC D/A CONV LP 16-BIT 32-TQFP $4.29 DAC8541Y/250 IC D/A CONV LP 16-BIT 32-TQFP $6.14 DAC8541Y/250 IC D/A CONV LP 16-BIT 32-TQFP $6.22 DAC5578SRGET IC DAC 8BIT I2C OCTAL 24VQFN $4.09 DAC5578SRGET IC DAC 8BIT I2C OCTAL 24VQFN $6.06 DAC5578SRGET IC DAC 8BIT I2C OCTAL 24VQFN $6.37 TLC5620CD IC QUAD 8-BIT D/A CONV 14-SOIC $3.85TLC7226CN IC 8BIT 5US QUAD DAC P/O 20-DIP $4.02 型号产品描述价格TLV5626CD IC DUAL 8-BIT SERIAL D/A 8-SOIC $4.22TLV5628CN IC OCTAL 8-BIT SERIAL D/A 16-DIP $4.43 TLC7628CDW IC 8 BIT 0.1US MDAC P/O 20-SOIC $4.19 TLC5620ID IC QUAD 8-BIT D/A CONV 14-SOIC $4.55 DAC8580IPW IC DAC 16BIT HI-SPD LN 16-TSSOP $4.34 TLC5628CN IC OCT 8-BIT D/A CONV 16-DIP $4.50 DSD1793DB IC 24BIT STEREO AUD DAC 28-SSOP $4.34 TLC7226IN IC QUAD 8-BIT D/A CONV 20-DIP $4.32 TLV5627CD IC QUAD 8-BIT SERIAL D/A 16-SOIC $4.47 TLV5621ID IC QUAD 8-BIT SERIAL D/A 14-SOIC $4.47 PCM2704DBR IC DAC 16BIT STEREO W/USB 28SSOP $2.42 PCM2704DBR IC DAC 16BIT STEREO W/USB 28SSOP $4.71 PCM2704DBR IC DAC 16BIT STEREO W/USB 28SSOP $4.94 PCM1723E IC STEREO D/A W/PLL 24-SSOP $4.64PCM1716E IC 24-BIT STEREO D/A 28-SSOP $4.97 UC3910D IC 4-BIT DAC & V MONITOR 16-SOIC $4.79 PCM1720E IC STEREO AUDIO D/A 20-SSOP $5.14 DAC7611U IC 12-BIT SERIAL G.P. D/A 8-SOIC $4.89 THS8133BCPHP IC 10BIT 80MSPS DAC VID 48-HTQFP $5.29 THS8134BCPHP IC 8 BIT 80MSPS DAC VID 48-HTQFP $5.36型号产品描述价格DAC7613E IC 12-BIT V OUT D/A 24-SSOP $5.10 PCM1691DCA IC 24-BIT AUDIO 8CH DAC 48HTSSOP $5.23 DAC6578SRGET IC DAC 10BIT I2C OCTAL 24VQFN $5.59 DAC6578SRGET IC DAC 10BIT I2C OCTAL 24VQFN $8.32 DAC6578SRGET IC DAC 10BIT I2C OCTAL 24VQFN $8.72 PCM2704DB IC STEREO AUD DAC W/USB 28-SSOP $5.34 DAC8801IDGKT IC DAC 14BIT MULTIPLYING 8-MSOP $5.24 DAC8801IDGKT IC DAC 14BIT MULTIPLYING 8-MSOP $8.28DAC8801IDGKT IC DAC 14BIT MULTIPLYING 8-MSOP $8.18 DAC7574IDGSR IC 12BIT QUAD V-OUT DAC 10-MSOP $5.60 DAC7574IDGSR IC 12BIT QUAD V-OUT DAC 10-MSOP $9.86 DAC7574IDGSR IC 12BIT QUAD V-OUT DAC 10-MSOP $9.26 TLV5616CP IC 12 BIT 3US DAC S/O 8-DIP $5.40 PCM1690DCA IC DAC 24BIT 8CH 192KHZ 48HTSSOP $5.29 DAC908U IC 8BIT 165MSPS IOUT D/A 28-SOIC $5.22 DAC908E IC 8-BIT D/A CONV 28-TSSOP $5.43 DAC7621EG4 IC 12-BIT D/A PARALLEL 20-SSOP $5.89 TLV5616CDR IC 12 BIT 3US DAC S/O 8-SOIC $2.88TLV5616CDR IC 12 BIT 3US DAC S/O 8-SOIC $5.44TLV5616CDR IC 12 BIT 3US DAC S/O 8-SOIC $5.66 型号产品描述价格DAC7611UB IC 12-BIT SERIAL G.P. D/A 8-SOIC $5.59 DAC7611P IC 12-BIT SERIAL G.P. D/A 8-DIP $6.14 DAC8531IDRBT IC DAC 16BIT RRO LP 8-SON $3.89DAC8531IDRBT IC DAC 16BIT RRO LP 8-SON $6.06 DAC8531IDRBT IC DAC 16BIT RRO LP 8-SON $5.84 THS8200PFP IC TRPL 10BIT VIDEO DAC 80-HTQFP $5.80 TLV5616IDR IC 12 BIT 3US DAC S/O 8-SOIC $2.87 TLV5616IDR IC 12 BIT 3US DAC S/O 8-SOIC $6.00 TLV5616IDR IC 12 BIT 3US DAC S/O 8-SOIC $6.37 PCM1602APT IC DAC 24BIT 192KHZ 6CH 48-LQFP $4.03 PCM1602APT IC DAC 24BIT 192KHZ 6CH 48-LQFP $6.43 PCM1602APT IC DAC 24BIT 192KHZ 6CH 48-LQFP $5.90 TLV5629IDW IC 8BIT 1/3US DAC S/O 20-SOIC $6.60 DAC8552IDGKT IC DAC 16BIT DUAL 8-MSOP $3.97 DAC8552IDGKT IC DAC 16BIT DUAL 8-MSOP $6.58 DAC8552IDGKT IC DAC 16BIT DUAL 8-MSOP $6.58 DAC7612U IC 12-BIT DUAL/SER D/A 8-SOIC $6.54 TLV5637CD IC DUAL 10-BIT SERIAL D/A 8-SOIC $6.78DAC7621EB IC 12-BIT D/A PARALLEL 20-SSOP $6.46 PCM1740E IC PLL DAC WITH VCXO 24-SSOP $6.22 型号产品描述价格TLV5616CD IC 12-BIT SERIAL D/A 8-SOIC $6.94 DAC7558IRHBR IC DAC 12BIT OCTAL W/SPI 32-VQFN $6.67 DAC7558IRHBR IC DAC 12BIT OCTAL W/SPI 32-VQFN $12.32 DAC7558IRHBR IC DAC 12BIT OCTAL W/SPI 32-QFN $12.46 DAC7611PB IC 12-BIT SERIAL G.P. D/A 8-DIP $6.99 DAC900E IC 10-BIT D/A CONV 28-TSSOP $6.90 TLV5616IDGK IC 12 BIT 3US DAC S/O 8-MSOP $6.62 TLV5616ID IC 12-BIT SERIAL DAC 8-SOIC $7.13 TLV5619QDWREP IC DAC 12BIT 1CH 2.7-5.5V 20SOIC $3.41 TLV5619QDWREP IC DAC 12BIT 1CH 2.7-5.5V 20SOIC $7.30 TLV5619QDWREP IC DAC 12BIT 1CH 2.7-5.5V 20SOIC $6.61PCM1717E IC STEREO AUDIO D/A 20-SSOP $7.15 PCM2706PJT IC STEREO AUD DAC W/USB 32-TQFP $7.23 DAC8043U IC 12 BIT D/A CONVERTER 8 SOIC $7.20 PCM1795DBR IC DAC AUDIO 32BIT 192KHZ 28SSOP $3.54 PCM1795DBR IC DAC AUDIO 32BIT 192KHZ 28SSOP $7.03 PCM1795DBR IC DAC AUDIO 32BIT 192KHZ 28SSOP $7.48 DAC7612UB IC 12-BIT DUAL/SER D/A 8-SOIC $7.50 DAC7678SRGET IC DAC 12BIT I2C OCTAL 24VQFN $7.18 DAC7678SRGET IC DAC 12BIT I2C OCTAL 24VQFN $10.39 型号产品描述价格DAC7678SRGET IC DAC 12BIT I2C OCTAL 24VQFN $10.79 TLV5604CPW IC 10 BIT 3US DAC SER 16-TSSOP $7.37 TLV5619IPW IC 12-BIT PARALLEL D/A 20-TSSOP $7.45 THS5651AIPW IC 10-BIT 125 MSPS D/A 28-TSSOP $7.51TLV5604IPW IC 10-BIT QUAD SER DAC 16-TSSOP $7.86 TLC5618AQD IC 12 BIT 2.5US DAC S/O 8-SOIC $8.09 TLV5618AIP DUAL 12BIT DAC 8-DIP $8.33 DAC6574IDGS IC DAC 10-BIT QUAD I2C 10-MSOP $7.72 TLV5636CD IC 12-BIT SERIAL D/A 8-SOIC $7.68 DAC8801IDRBT IC DAC 14BIT MULTIPLYING 8-SON $5.38 DAC8801IDRBT IC DAC 14BIT MULTIPLYING 8-SON $8.18 DAC8801IDRBT IC DAC 14BIT MULTIPLYING 8-SON $8.37 TLV5638CD IC DUAL 12-BIT SERIAL D/A 8-SOIC $8.03 PCM1795DB IC DAC AUDIO 32BIT 192KHZ 28SSOP $8.38 DAC7565IAPW IC DAC 12BIT 4CH 16-TSSOP $8.67 PCM1737E IC 192KHZ STEREO DAC 28-SSOP $8.54 TLV5636ID IC 12 BIT 1US DAC S/O 8-SOIC $8.60 TLV5638ID IC 12 BIT 1-3.5US DAC S/O 8-SOIC $9.06 PCM1794ADBR IC DAC AUDIO 24BIT 192KHZ 28SSOP $8.74PCM1794ADBR IC DAC AUDIO 24BIT 192KHZ 28SSOP $16.50 型号产品描述价格PCM1794ADBR IC DAC AUDIO 24BIT 192KHZ 28SSOP $15.76 DAC7565ICPW IC DAC 12BIT 4CH 16-TSSOP $8.68 DAC8043UC IC 12-BIT D/A CONVERTER 8-SOIC $8.96 DAC2900Y/250 IC DUAL 10-BIT D/A CONV 48-TQFP $9.47 DAC2900Y/250 IC DUAL 10-BIT D/A CONV 48-TQFP $12.75 DAC2900Y/250 IC DUAL 10-BIT D/A CONV 48-TQFP $14.06 DAC8805QDBTR IC DAC 14BIT DUAL MULT 38TSSOP $5.19 DAC8805QDBTR IC DAC 14BIT DUAL MULT 38TSSOP $9.13 DAC8805QDBTR IC DAC 14BIT DUAL MULT 38TSSOP $8.90 DAC8532IDGK IC D/A CONV 2CH LP 16BIT 8-MSOP $9.06 TLV5631IPW IC 10 BIT DAC 8 CH S/O 20-TSSOP $9.23 DAC7641Y/250 IC 16-BIT V-OUTPUT D/A 32-TQFP $9.95DAC7641Y/250 IC 16-BIT V-OUTPUT D/A 32-TQFP $14.23 DAC7641Y/250 IC 16-BIT V-OUTPUT D/A 32-TQFP $15.12 DAC8881SRGET IC DAC 16BIT 1CH V-OUT 24-QFN $10.18 DAC8881SRGET IC DAC 16BIT 1CH V-OUT 24-QFN $14.57 DAC8881SRGET IC DAC 16BIT 1CH V-OUT 24-QFN $14.21 DAC7578SRGET IC DAC 12BIT I2C OCTAL 24VQFN $6.44 DAC7578SRGET IC DAC 12BIT I2C OCTAL 24VQFN $9.56 DAC7578SRGET IC DAC 12BIT I2C OCTAL 24VQFN $10.31型号产品描述价格DAC902E IC 12-BIT D/A CONV 28-TSSOP $10.55 DAC902U IC 12B 165MSPS IOUT D/A 28-SOIC $9.79 DAC7641YB/250 IC 16-BIT V-OUTPUT D/A 32-TQFP $10.72 DAC7641YB/250 IC 16-BIT V-OUTPUT D/A 32-TQFP $14.96 DAC7641YB/250 IC 16-BIT V-OUTPUT D/A 32-TQFP $14.60TLV5638MDREP IC DAC 12BIT DUAL LP W/REF 8SOIC $6.12 TLV5638MDREP IC DAC 12BIT DUAL LP W/REF 8SOIC $10.50 TLV5638MDREP IC DAC 12BIT DUAL LP W/REF 8SOIC $10.24 DAC7631E IC 16BIT LP 2.5MW D/A 20-SSOP $10.43 DSD1608PAH IC DAC 8CH CMOS MONO 52-TQFP $11.36 THS5661AIPW IC 12-BIT 125 MSPS D/A 28-TSSOP $11.80 DAC7614U IC QUAD/SERIAL 12-BIT D/A 16SOIC $11.87 DAC8554IPW IC DAC 16BIT QUAD W/SPI 16-TSSOP $11.95 DAC8555IPW IC DAC 16BIT QUAD 16-TSSOP $12.24 DAC5652IPFB IC DAC 10BIT DUAL 275MSPS 48TQFP $11.67 DAC1220E IC 20-BIT MONOLITHIC D/A 16-QSOP $12.12 DAC7615E IC 12-BIT QUAD D/A CONV 20-SSOP $11.74 DAC7631EB IC 16BIT LP 2.5MW D/A 20-SSOP $12.27 DAC7614UB IC QUAD/SERIAL 12-BIT D/A 16SOIC $11.84DAC7614EB IC 12-BIT QUAD D/A CONV 20-SSOP $12.30 型号产品描述价格DAC7742Y/250 IC DAC 16BIT PARALLEL LP 48-LQFP $12.38 DAC7742Y/250 IC DAC 16BIT PARALLEL LP 48-LQFP $17.92 DAC7742Y/250 IC DAC 16BIT PARALLEL LP 48-LQFP $17.92 DAC8165IAPW IC DAC 14BIT QUAD-CH 16-TSSOP $13.27 DAC8164IAPW IC DAC 14BIT QUAD-CH 16-TSSOP $12.50 DAC904E IC 14-BIT D/A CONV 28-TSSOP $12.41 DAC7741YC/250 IC D/A CONV LP 16-BIT 48-LQFP $13.41 DAC7741YC/250 IC D/A CONV LP 16-BIT 48-LQFP $16.97 DAC7741YC/250 IC D/A CONV LP 16-BIT 48-LQFP $18.50 DAC8822QBDBTR IC DAC 16BIT DUAL MULT 38TSSOP $7.48 DAC8822QBDBTR IC DAC 16BIT DUAL MULT 38TSSOP $12.38 DAC8822QBDBTR IC DAC 16BIT DUAL MULT 38TSSOP $12.86PCM56P IC SERIAL INPUT 16 BIT D/A 16DIP $14.15 DAC7728SRTQT IC DAC 12BIT OCTAL LP 56QFN $13.43 DAC7728SRTQT IC DAC 12BIT OCTAL LP 56QFN $18.98 DAC7728SRTQT IC DAC 12BIT OCTAL LP 56QFN $18.06 DAC7718SRGZT IC DAC 12BIT OCTAL LP 48VQFN $13.43 DAC7718SRGZT IC DAC 12BIT OCTAL LP 48VQFN $18.52 DAC7718SRGZT IC DAC 12BIT OCTAL LP 48VQFN $17.61 PCM2702E IC 16-BIT STER D/A 28-SSOP $13.45。

kinetisDAC模块详解(中文资料)

作者：潘峰北京联合大学实训基地微博：/u/1262858854QQ:66797490博客：/panpan_0315/blog/本章内容仅供个人学习之用，请勿用于其它用途。

1.2DAC数模转换模块1.7.1 DAC简介Kinetis10包含两个独立的12位数模转换模块，DAC0和DAC1，用于将数字转换成对应的模拟电压。

转换后的模拟电压可由外部引脚输出，也可以通过芯片内部连接输入到比较器模块、放大器模块、和模数转换模块。

DAC的参考电压可以二选一，一个来自外部或VREF模块的输出，默认连接到DACREF_1；另一个时VDDA，默认连接到DACREF_2。

如果选择VDDA，则DAC的参考电压为3.3V。

12位二进制的表示范围为0~4095的无符号数。

对应数据转换成模拟电压输出范围从VREF/4096~VREF。

以VREF为3.3V计算，则是约0.8mV~3.3V，数据每变化1，输出电压变化约0.8mV。

将数据放入DAC的数据寄存器（DACx_DATL中的DACDATA[11:0]位），即可将数据转换为模拟电压。

电压Vout= VREF * (1 + DACDAT0[11:0])/4096。

在大量数据转换的应用中，也可以将数据放入DAC的缓冲区，由触发源输入触发信号，在触发信号的触发下，自动挨个将缓冲区中的数据转换为模拟电压。

缓冲区大小为1~16可设置大小的以word为单位的区域，转换的时候，由读指针指向正在转换的数据，可通过访问读指针获知当前正在转换的缓冲区单元。

数据转换的次序为从顶部到底部依次转换，从顶部到底部之间，用户可设置位置标记（watermark）作为预警位置，当读指针指向缓冲区顶部、底部或位置标记处时，都有状态位可供查询，也可以发出中断请求。

触发信号可来自PDB模块的TRIG输出详细可查看PDB模块设置。

同时DAC模块也支持DMA操作，可通过DMA的方式向缓冲区中传递数据，大大提高了效率。

DAC基本架构I ：DAC串和温度计(完全解码) DAC

参考文献：
1. Peter I. Wold, "Signal-Receiving System," U.S. Patent 1,514,753, filed November 19, 1920, issued November 11, 1924. (thermometer DAC using relays and vacuum tubes). Clarence A. Sprague, "Selective System," U.S. Patent 1,593,993, filed November 10, 1921, issued July 27, 1926. (thermometer DAC using relays and vacuum tubes). Leland K. Swart, "Gas-Filled Tube and Circuit Therefor," U.S. Patent 2,032,514, filed June 1, 1935, issued March 3, 1936. (a thermometer DAC based on vacuum tube switches). Robert Adams, Khiem Nguyen, and Karl Sweetland, "A 113 dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling, " ISSCC Digest of Technical Papers, vol. 41, 1998, pp. 62, 63, 413. (describes a segmented audio DAC with data scrambling). Robert W. Adams and Tom W. Kwan, "Data-directed Scrambler for Multi-bit Noise-shaping D/A Converters," U.S. Patent 5,404,142, filed August 5, 1993, issued April 4, 1995. (describes a segmented audio DAC with data scrambling). Walt Kester, Analog-Digital Conversion, Analog Devices, 2004, ISBN 0-916550-27-3, Chapter 3. Also available as The Data Conversion Handbook, Elsevier/Newnes, 2005, ISBN 0-7506-7841-0, Chapter 3.

ADS1118IDGS中文资料

ADS1118IDGSADS1118IDGS是规格小，功耗低，具有SPI TM(串行外围接口)-兼容，16位AD转换，温度传感器的芯片。

特点：（1）小封装：2mm*1.5mm*0.4mm （2）外部电压范围：2v~5.5v （3）低电流消耗：连续模式：150ua 单发模式：自动关闭（4）可编程数据速率：8sps~860sps（5）单循环设置（6）内部低漂移参考电压（7）温度传感器：-0.5摄氏度最大误差（8）内部振荡器（9）内部可编程增益放大器（10）四个单端型或两个微分型输入应用：1：温度测量（1）热电偶测量（2）冷端补偿（3）热敏电阻测量2：便携式仪器3：工厂自动化和程序控制描述:ADS1118IDGS规模小，使用无引线或者超小塑料外形的10脚封装，具有16位极高分辨率的AD转化功能，DAS1118在应用中被设计着精确，功能强大，易操作，ADS1118的特点是它的板上参考和振荡器。

它使用SPI传递一系列数据。

单功率电源（2v~5.5v）给它供电，每秒采样速度可达到860sps。

ADS1118上的可编程增益需要提供输入+-256mv范围的电压，在这范围内可高精度测量大小信号，ADS1118输入选择器提供两个微分型和四个单端型输入，ADS1118也作为高精度温度传感器，可用作系统温度传感器检测盒冷锻补偿为热电偶。

ADS1118使用练习模式或者单发模式，再不工作时使用单发模式可以减少功耗，ADS1118温度为-40~125摄氏度。

绝对最大额定值：（1）VDD到GND:-0.3~5.5V（2）模拟输入电流：瞬时100MA（3）模拟输入电流：持续10MA（4）模拟输入电压：-0.3~0.3V（5）DIN,DOUT/DRDY,SCLK,CS电压-0.3~5.5V引脚配置：引脚1：SCLK 时钟输入引脚2：CS/ 片选低电平有效引脚3：GND 地引脚4：AIN0 差分1，正极性或单通道1输入引脚5：AIN1 差分1，负极性或单通道2输入引脚6：AIN2 差分2，正极性或单通道3输入引脚7：AIN3 差分2，负极性或单通道4输入引脚8：VDD 供电2V到5V引脚9：DOUT/DRDY 串行数据出于数据读，低电平有效引脚10：DIN 串行数据输入SPI时钟特性：概述：ADS1118是一个小体积，低电压，16位delta-sigma的AD转化器，它可以通过简单的配置和设计而应用在很多地方，支持高精度测量。

DAC7811中文资料

DAC7811 参考资料一：DAC7811简介12位的DAC。

使用一个有三线接口的双缓存器，合乎与SPI和大多数SDO接口标准。

当运用复合器件时，通过接口SDO可以菊花链式连接；通过SDO口，用户可以回读DAC register的值。

上电时，移位寄存器的值0，DAC输出从0开始。

外部输入参考电压决定电流的满额输出电流。

当连接外部放大器后，反馈电阻可以提供温度跟踪和满额电压输出。

dac7811是10脚封装二：引脚描述引脚功能：1脚IOUT1是DAC电流输出2脚IOUT2是DAC模拟地。

这个引脚通常被接在系统的模拟地3脚是地4脚串行时钟输入：默认情况下，当串行时钟的下降沿时，数据被存入16位的输入移位寄存器；作为选择，依靠串行控制位，可以设置当时钟线上升沿时把数据输入进输入移位寄存器。

5脚串行数据输入：在有效的串行输入时钟边沿，数据被存入16位的输入移位寄存器。

默认情况下，在上电复位时，数据在时钟下降沿时时存入输入移位寄存器；同时控制位允许用户改变为上升沿有效。

6脚SYNC 有效低控制输入：这是数据输入的帧同步信号。

当SYNC变低时，它对SCLK和SDIN器作用，同时使能输入移位寄存器。

在有效的边沿时钟线边沿（默认为下降沿），数据下载到输入移位寄存器。

IN STAND——alone 模式下，这个串行接口计算有效时钟的个数，同时数据在第16个有效时钟时，整个数据被存入输入移位寄存器。

7脚SDO 串行数据输出：这一位允许很多个部分被菊花链式连接起来。

默认情况下，数据在时钟下降沿时存入输入寄存器，在上升沿时经由SDO输出（？）。

数据总是被存入输入寄存器（在交替的时钟边沿）。

（通过串行数据）在输入寄存器中写入回读控制字，可以实现在SDO引脚读出DAC寄存器的内容。

8脚VDD：正电压输入端。

可以提供输入2.7V——2.5V的电压。

9脚VREF：DAC参考电压输入端10脚RFB：DAC反馈电阻引脚。

为DAC建立外部电压输出，通过连接外部放大（输出）器。

ADG731中文资料

ADG725/ADG731 =REV. PrD May 2002Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.One T echnology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. T el: 781/ Fax: 781/326-8703Analog Devices, Inc., 200216-/32- Channel, Serially Controlled 4 Ω1.8 V to 5.5 V, ±2.5 V, Analog Multiplexers Preliminary Technical DataPRELIMINARY TECHNICAL DATAFEATURES3-Wire SPI Serial Interface1.8 V to 5.5 V Single Supply±2.5 V Dual Supply Operation4 Ω On Resistance0.5 Ω On Resistance Flatness7mm x 7mm 48 lead Chip Scale Package (CSP)or 48 lead TQFP package.Rail to Rail OperationPower On ResetFast Switching TimesSingle 32 to 1 Channel MultiplexerDual/Differential 16 to 1 Channel MultiplexerTTL/CMOS Compatible InputsFor Functionally Equivalent devices with Parallel InterfaceSee ADG726/ADG732APPLICATIONSOptical ApplicationsData Acquisition SystemsCommunication SystemsRelay replacementAudio and Video SwitchingBattery Powered SystemsMedical InstrumentationAutomatic Test EquipmentGENERAL DESCRIPTIONThe ADG725/ADG731 are monolithic CMOS 32channel/dual 16 channel analog multiplexers with aserially controlled 3-wire interface. The ADG732 switchesone of thirty-two inputs (S1-S32) to a common output, D.The ADG725 can be configured as a dual mux switchingone of sixteen inputs to one output or a differential muxswitching one of sixteen inputs to a differential output.These mulitplexers utilize a 3-wire serial interface that iscompatible with SPI TM, QSPI TM, MICROWIRE TM and some DSP interface standards. On power-up, the internal shift register contains all zeros and all switch are in the OFF state.These multiplexers are designed on an enhanced submi-cron process that provides low power dissipation yet gives high switching speed, very low on resistance and leakage currents. They operate from single supply of 1.8V to 5.5V and ±2.5 V dual supply, making them ideally suited to a variety of applications. On resistance is in the region of a few Ohms and is closely matched between switches and very flat over the full signal range. These parts can operate equally well as either Multiplexers or De-Multiplexers PRODUCT HIGHLIGHTS1.3-Wire Serial Interface.2.+1.8 V to +5.5 V Single or ±2.5 V Dual Supplyoperation. These parts are specified and guaranteedwith +5 V ±10%, +3 V ±10% single supply and±2.5 V ±10% dual supply rails.3.On Resistance of 4 Ω.4.Guaranteed Break-Before-Make Switching Action.5.7mm x 7mm 48 lead Chip Scale Package (CSP)or 48 lead TQFP package.FUNCTIONAL BLOCK DIAGRAMSS1S32SCLK DIN SYNCDS1ADAS16AS1BS16BDBSCLK DIN SYNCand have an input signal range which extends to the sup-plies. In the OFF condition, signal levels up to the supplies are blocked. All channels exhibit break before make switching action preventing momentary shorting when switching channels.They are available in either 48 lead CSP or TQFP package.元器件交易网–2–REV. PrDADG725/ADG731–SPECIFICATIONS 1PRELIMINARY TECHNICAL DATAB Version–40°CParameter+25o C to +85°C Units Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V On-Resistance (R ON )4Ω typ V S = 0 V to V DD , I DS = 10 mA;5.56Ω max Test Circuit 1On-Resistance Match Between 0.3Ω typ V S = 0 V to V DD , I DS = 10 mA Channels (∆R ON )0.8Ω max On-Resistance Flatness (R FLAT(ON))0.5Ω typ V S = 0 V to V DD , I DS = 10 mA 1Ω max LEAKAGE CURRENTSV DD = 5.5 VSource OFF Leakage I S (OFF)±0.01nA typ V D = 4.5 V/1 V, V S = 1 V/4.5 V;±0.25±0.5nA max Test Circuit 2Drain OFF Leakage I D (OFF)±0.05nA typ V D = 4.5 V/1 V, V S = 1 V/4.5 V; ADG725±0.5±2.5nA max Test Circuit 3ADG731±1±5nA max Channel ON Leakage I D , I S (ON)±0.05nA typ V D = V S = 1 V, or 4.5V; ADG725±0.5±2.5nA max Test Circuit 4ADG726±1±5nA max DIGITAL INPUTSInput High Voltage, V INH 2.4V min Input Low Voltage, V INL 0.8V max Input Current I INL or I INH 0.005µA typ V IN = V INL or V INH±0.1µA max C IN , Digital Input Capacitance 5pF typ DYNAMIC CHARACTERISTICS 2t TRANSITION 40ns typ R L = 300 Ω, C L = 35 pF,Test Circuit 5;60ns max V S1 = 3 V/0 V, V S32 = 0 V/3V Break-Before-Make Time Delay, t D 30ns typ R L = 300 Ω, C L = 35 pF;1ns min V S = 3 V, Test Circuit 6Charge Injection ±5pC typ V S = 0 V, R S = 0 Ω, C L = 1 nF;Test Circuit 7Off Isolation-60dB typ R L = 50 Ω, C L = 5 pF, f = 100 kHz;Test Circuit 8Channel to Channel Crosstalk -60dB typ R L = 50 Ω, C L = 5 pF, f = 100 kHz;Test Circuit 9-3 dB Bandwidth ADG72534MHz typ R L = 50 Ω, C L = 5 pF, Test Circuit 10 ADG73118MHz typ C S (OFF)13pF typ f = 1 MHz C D (OFF) ADG725180pF typ f = 1 MHz ADG731360pF typ f = 1 MHz C D , C S (ON) ADG725200pF typ f = 1 MHz ADG731400pF typ f = 1 MHzPOWER REQUIREMENTS V DD = +5.5 VI DD10µA typ Digital Inputs = 0 V or +5.5 V20µA maxNOTES 1Temperature range is as follows: B Version: –40°C to +85°C.2Guaranteed by design, not subject to production test.Specifications subject to change without notice.(V DD= 5V ± 10%, V SS= 0V, GND = 0 V, unless otherwise noted)元器件交易网–3–REV. PrD ADG725/ADG731PRELIMINARY TECHNICAL DATAB Version–40°CParameter+25o C to +85°CUnits Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V On-Resistance (R ON )7Ω typ V S = 0 V to V DD , I DS = 10 mA;1112Ω max Test Circuit 1On-Resistance Match Between 0.4Ω typ V S = 0 V to V DD , I DS = 10 mA Channels (∆R ON )1Ω max On-Resistance Flatness (R FLAT(ON))3Ω max V S = 0 V to V DD , I DS = 10 mA LEAKAGE CURRENTSV DD = 3.3 VSource OFF Leakage I S (OFF)±0.01nA typ V S = 3 V/1 V, V D = 1 V/3 V;±0.25±0.5nA max Test Circuit 2Drain OFF Leakage I D (OFF)±0.05nA typ V S = 1 V/3 V, V D = 3 V/1 V; ADG725±0.5±2.5nA max Test Circuit 3ADG731±1±5nA max Channel ON Leakage I D , I S (ON)±0.05nA typ V S = V D = +1 V or +3 V; ADG725±0.5±2.5nA max Test Circuit 4ADG731±1±5nA max DIGITAL INPUTSInput High Voltage, V INH 2.0V min Input Low Voltage, V INL 0.8V max Input Current I INL or I INH 0.005µA typ V IN = V INL or V INH±0.1µA max C IN , Digital Input Capacitance 5pF typ DYNAMIC CHARACTERISTICS 2t TRANSITION 45ns typ R L = 300 Ω, C L = 35 pF Test Circuit 575ns max V S1 = 2 V/0 V, V S32 = 0 V/2 V Break-Before-Make Time Delay, t D 30ns typ R L = 300 Ω, C L = 35 pF;1ns min V S = 2 V,Test Circuit 6Charge Injection ±5pC typ V S = 0 V, R S = 0 Ω, C L = 1 nF;Test Circuit 7Off Isolation-60dB typ R L = 50 Ω, C L = 5 pF, f = 1 MHz;Test Circuit 8Channel to Channel Crosstalk -60dB typ R L = 50 Ω, C L = 5 pF, f = 1 MHz;Test Circuit 9-3 dB Bandwidth ADG72534MHz typ R L = 50 Ω, C L = 5 pF, Test Circuit 10 ADG73118MHz typ C S (OFF)13pF typ f = 1 MHz C D (OFF) ADG725180pF typ f = 1 MHz ADG731360pF typ f = 1 MHz C D , C S (ON) ADG725200pF typ f = 1 MHz ADG731400pF typ f = 1 MHzPOWER REQUIREMENTS V DD = +3.3 VI DD10µA typ Digital Inputs = 0 V or +3.3 V20µA maxNOTES 1Temperature ranges are as follows: B Version: –40°C to +85°C.2Guaranteed by design, not subject to production test.Specifications subject to change without notice.(V DD = 3V ± 10%, V SS = 0V, GND = 0 V, unless otherwise noted)SPECIFICATIONS1元器件交易网–4–REV. PrDADG725/ADG731–SPECIFICATIONS 1PRELIMINARY TECHNICAL DATAB Version–40°CParameter+25o C to +85°C Units Test Conditions/Comments ANALOG SWITCHAnalog Signal Range V SS to V DD V On-Resistance (R ON )4Ω typ V S = V SS to V DD , I DS = 10 mA;5.56Ω max Test Circuit 1On-Resistance Match Between 0.3Ω typ V S = V SS to V DD , I DS = 10 mA Channels (∆R ON )0.8Ω max On-Resistance Flatness (R FLAT(ON))0.5Ω typ V S = V SS to V DD , I DS = 10 mA1Ω max LEAKAGE CURRENTSV DD = +2.75 V, V SS = -2.75 VSource OFF Leakage I S (OFF)±0.01nA typ V S = +2.25 V/-1.25 V, V D = -1.25 V/+2.25 V;±0.25±0.5nA max Test Circuit 2Drain OFF Leakage I D (OFF)±0.05nA typ V S = +2.25 V/-1.25 V, V D = -1.25 V/+2.25 V;±0.5±2.5nA max Test Circuit 3±1±5nA max Channel ON Leakage I D , I S (ON)±0.01nA typ V S = V D = +2.25 V/-1.25 V, Test Circuit 4±0.5±2.5nA max ±1±5nA max DIGITAL INPUTSInput High Voltage, V INH 1.7V min Input Low Voltage, V INL 0.7V max Input Current I INL or I INH 0.005µA typ V IN = V INL or V INH±0.1µA max C IN , Digital Input Capacitance 5pF typ DYNAMIC CHARACTERISTICS 2t TRANSITION 40ns typ R L = 300 Ω, C L = 35 pF Test Circuit 560ns max V S1 = 1.5 V/0 V,V S32 = 0 V/1.5 V Break-Before-Make Time Delay, t D 15ns typ R L = 300 Ω, C L = 35 pF;1ns min V S = 1.5 V, Test Circuit 6Charge Injection ±8pC typ V S = 0 V, R S = 0 Ω, C L = 1 nF; Test 7Off Isolation-60dB typ R L = 50 Ω, C L = 5 pF, f = 1 MHz;Test Circuit 8Channel to Channel Crosstalk -60dB typ R L = 50 Ω, C L = 5 pF, f = 1 MHz;Test Circuit 9-3 dB Bandwidth ADG72534MHz typ R L = 50 Ω, C L = 5 pF, Test Circuit 10ADG73118MHz typ C S (OFF)13pF typ C D (OFF) ADG725180pF typ f = 1 MHz ADG731360pF typ f = 1 MHz C D , C S (ON) ADG725200pF typ f = 1 MHz ADG731400pF typ f = 1 MHzPOWER REQUIREMENTS V DD = +2.75 VI DD 10µA typ Digital Inputs = 0 V or +2.75 V 20µA max I SS10µA typ V SS = -2.75 V20µA maxDigital Inputs = 0 V or +2.75 VNOTES 1Temperature range is as follows: B Version: –40°C to +85°C.2Guaranteed by design, not subject to production test.Specifications subject to change without notice.(V DD= +2.5 V ±10%, V SS= -2.5 V ±10%, GND = 0 V, unless otherwise noted)Dual Supply 元器件交易网元器件交易网PRELIMINARY TECHNICAL DATAADG725/ADG731 TIMING C HARACTERISTICS1,2Parameter Limit at T MIN, T MAX Units Conditions/Commentst133ns min SCLK Cycle timet213ns min SCLK High Timet313ns min SCLK Low Timet413ns min SYNC to SCLK falling edge setup timet540ns min Minimum SYNC low timet65ns min Data Setup Timet7 4.5ns min Data Hold Timet833ns min Minimum SYNC high timeNOTES1See Figure 1.2All input signals are specified with tr =tf = 5ns (10% to 90% of V) and timed from a voltage level of (V IL + V IH)/2.DDSpecifications subject to change without notice.Figure 1.3-Wire Serial Interface Timing Diagram.REV. PrD–5––6–REV. PrDADG725/ADG731PRELIMINARY TECHNICAL DATAABSOLUTE MAXIMUM RATINGS 1(T A = +25°C unless otherwise noted)V DD to V SS +7 VV DD to GND –0.3 V to +7 V V SS to GND +0.3 V to -7 VAnalog Inputs 2V SS - 0.3 V to V DD +0.3 Vor 30 mA, Whichever Occurs FirstDigital Inputs 2-0.3V to V DD +0.3 V or30 mA, Whichever Occurs FirstPeak Current, S or D 60mA(Pulsed at 1 ms, 10% Duty Cycle max)Continuous Current, S or D 30mA Operating Temperature Range Industrial (B Version)–40°C to +85°CCAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.Although the ADG725/ADG731 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.Storage Temperature Range –65°C to +150°C Junction Temperature +150°C48 lead CSP θJA Thermal ImpedanceTBD°C/W 48 lead TQFP θJA Thermal Impedance TBD°C/W Lead Temperature, Soldering (10seconds)300°C IR Reflow, Peak Temperature +220°CNOTES 1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.2Overvoltages at SCLK, SYNC , DIN , RS , S or D will be clamped by internal diodes.Current should be limited to the maximum ratings given.ORDERING GUIDEModel Temperature Range Package Description Package Option ADG725BCP -40 o C to +85 o C Chip Scale Package (CSP)CP-48ADG725BSU -40 o C to +85 o C Thin Quad FlatpackSU-48ADG731BCP -40 o C to +85 o C Chip Scale Package (CSP)CP-48ADG731BSU-40 o C to +85 o CThin Quad FlatpackSU-48元器件交易网ADG725/ADG731–7–REV. PrDPRELIMINARY TECHNICAL DATAPIN FUNCTION DESCRIPTIONADG725ADG731Mnemonic Function SCLKSerial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. These devices can accomodate serial input rates of up to 30MHz.R S Active low control input that clears the input register and turns all switches to the OFF condition.DIN Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial clock input.SXX Source. May be an input or output.D X Drain. May be an input or output.V DD Power Supply Input. These parts can be operated from a supply of +1.8V to +5.5V and dual supply of +/-2.5V.G N D Ground reference.SYNCActive Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. An 8-bit counter is also enabled. Data is transferred on the falling edges of the following clocks. After 8 falling clock edges, switch conditions are automaticaly updated. SYNC may be used to frame the signal, or just pulled low for a short period of time to enable the counter and input buffers.PIN CONFIGURATIONSCSP & TQFPS28S27S26S25S24S23S22S12S11S10S9S8S7S6S5S4S3S2S21S20S19S18S1S17S 13S 14S 15S 16N CDN CN CS 32S 31S 30S 29V D DV D DN CN CS Y N CD I NS C L KN CN CN CG N DV S SS12B S11B S10B S9B S8B S7B S6B S12A S11AS10A S9A S8A S7A S6A S5A S4AS3A S2A S5B S4B S3B S2B S1A S1BS 13AS 14AS 15AS 16AN CD A N CD BS 16AS 15BS 14BS 13B元器件交易网–8–REV. PrDADG725/ADG731PRELIMINARY TECHNICAL DATATable 2. ADG731 Truth TableA4A3A2A1A0E N C S Switch Condition X X X X X X 1Retains previous switch condition X X X X X 11All Switches OFF 0000000100001002000100030001100400100005001010060011000700111008010000090100100100101000110101100120110000130110100140111000150111100161000000171000100181001000191001100201010000211010100221011000231011100241100000251100100261101000271101100281110000291110100301111000311111132X = Don’t CareTable 1. ADG725 Truth TableA3A2A1A0E N C S A C S B Switch ConditionX X X X X 11Retains previous switch condition X X X X 111All Switches OFF 0000000S1A - DA, S1B - DB 0001000S2A - DA, S2B - DB 0010000S3A - DA, S3B - DB 0011000S4A - DA, S4B - DB 0100000S5A - DA, S5B - DB 0101000S6A - DA, S6B - DB 0110000S7A - DA, S7B - DB 0111000S8A - DA, S8B - DB 1000000S9A - DA, S9B - DB 1001000S10A - DA, S10B - DB 1010000S11A - DA, S11B - DB 1011000S12A - DA, S12B - DB 1100000S13A - DA, S13B - DB 1101000S14A - DA, S14B - DB 1110000S15A - DA, S15B - DB 1111S16A - DA, S16B - DB元器件交易网ADG725/ADG731–9–REV. PrD PRELIMINARY TECHNICAL DATAV DD Most positive power supply potential.V SS Most Negative power supply in a dual supply application. In single supply applications, connect to GND.I DD Positive supply current.I SSNegative supply current.G N D Ground (0 V) reference.S Source terminal. May be an input or output.D Drain terminal. May be an input or output.I N Logic control input.V D (V S )Analog voltage on terminals D, S R ON Ohmic resistance between D and S.∆R ONOn resistance match between any two channels, i.e. R ON max - R ON minR FLAT(ON)Flatness is defined as the difference between the maximum and minimum value of on-resistance as mea sured over the specified analog signal range.I S (OFF)Source leakage current with the switch “OFF.”I D (OFF)Drain leakage current with the switch “OFF.”I D , I S (ON)Channel leakage current with the switch “ON.”V INL Maximum input voltage for logic “0”.V INHMinimum input voltage for logic “1”.I INL (I INH )Input current of the digital input.C S (OFF)“OFF” switch source capacitance. Measured with reference to ground.CD (OFF)“OFF” switch drain capacitance. Measured with reference to ground.C D ,C S (ON)“ON” switch capacitance. Measured with reference to ground.C INDigital input capacitance.t TRANSITION Delay time measured between the 50% and 90% points of the SYNC and the switch “ON” condi tion when switching from one address state to another.t OPEN“OFF” time measured between the 80% points of both switches when switching from one address state to another.Charge A measure of the glitch impulse transferred from the digital input to the analog output during switching.InjectionOff Isolation A measure of unwanted signal coupling through an “OFF” switch.Crosstalk A measure of unwanted signal is coupled through from one channel to another as a result of parasiticcapacitance.On Response The Frequency response of the “ON” switch.Insertion The loss due to the ON resistance of the switch.LossTERMINOLOGY元器件交易网ADG725/ADG731PRELIMINARY TECHNICAL DATA TYPICAL PERFORMANCE CHARACTERISTICSTBDTPC 1. On Resistance vs. V D(V S) for forSingle SupplyTBDTPC 2. On Resistance vs. V D(V S) forDual SupplyTBDTPC 3. On Resistance vs. V D(V S) forDifferent Temperatures, SingleSupplyTBDTPC 4. On Resistance vs. V D(V S) forDifferent Temperatures, SingleSupplyTBDTPC 5. On Resistance vs. V D(V S) forDifferent Temperatures, Dual SupplyTBDTPC 6. Leakage Currents vs. V D(V S)TBDTPC 7. Leakage Currents vs. V D(V S)TBDTPC 8. Leakage Currents vs. V D(V S)TBDTPC 9. Leakage Currents vs.Temperature元器件交易网–10–REV. PrDADG725/ADG731–11–REV. PrD PRELIMINARY TECHNICAL DATATBD TPC 10. Leakage Currents vs.Temperature TBD TPC 11. Supply Currents vs. InputSwitching FrequencyTBD TPC 12. Charge Injection vs. SourceVoltageTBD TPC 13. T ON /T OFF Times vs.TemperatureTBDTPC 14. Off Isolation vs. FrequencyTBDTPC 15. Crosstalk vs. FrequencyTBDTPC 16. On Response vs. Frequency元器件交易网元器件交易网PRELIMINARY TECHNICAL DATAADG725/ADG731GENERAL DESCRIPTIONThe ADG725 and ADG731 are serially controlled, 32channel and dual/differential 16 channel multiplexers re-spectively.POWER ON RESETOn power up of the device, all switches will be in theOFF condition and the internal shift register is filled withzeros and will remain so until a valid write takes place.SERIAL INTERFACEThe ADG725 and ADG731 have a three wire serial inter-face (SYNC, SCLK, and DIN), which is compatible withSPI, QSPI, MICROWIRE interface standards and mostDSP’s. Figure 1 shows the timing diagram of a typicalwrite sequence.Data is written to the 8-bit shift register via DIN underthe control of the SYNC and SCLK signals.When SYNC goes low, the input shift register is enabled.An 8-bit counter is also enabled. Data from DIN isclocked into the shift register on the falling edge ofSCLK. Figures 2 & 3 show the contents of the input shiftregisters for these devices. When the part has receivedeight clock cycles after SYNC has been pulled low, theswitches are automatically updated with the newconfiguration and the input shift register is disabled. WithSYNC held high, any further data or noise on the DINline will have no effect on the shift register.The ADG725 CSA and CSB data bits allow the user theflexibility to change the configuration of either or bothbanks of the multiplexer.–12–REV. PrDADG725/ADG731–13–REV. PrD PRELIMINARY TECHNICAL DATATest Circuit 1.On Resistance.Test Circuit 2.I S (OFF).D Test Circuit 4.I D (ON)Test Circuit 5.Switching Time of Multiplexer, t TRANSITION .Test Circuit 6.Break Before Make Delay, t OPEN .V V DVV DVV OUTTRANSITIONTRANSITIONSYNCV OUT* SIMILAR CONNECTION FOR ADG7250V V V V V V V OUTV 0VV S SYNC*SIMILAR CONNECTION FOR ADG725V 元器件交易网–14–REV. PrDADG725/ADG731PRELIMINARY TECHNICAL DATATest Circuit 7.Charge Injection.Test Circuit 8.OFF IsolationTest Circuit 9.Channel-to-Channel Crosstalk.V *SIMILAR CONNECTION FOR ADG725V*SIMILAR CONNECTION FOR ADG725OFF ISOLATION = 20 LOGOUT V SCHANNEL TO CHANNEL CROSSTALK=20LOG 10(V OUT /V S )*SIMILAR CONNECTION FOR ADG725Test Circuit 10. Bandwidth*SIMILAR CONNECTION FOR ADG725INSERTION LOSS = 20 LOG VOUT WITH SWITCHVOUT WITHOUT SWITCH元器件交易网ADG725/ADG731–15–REV. PrD PRELIMINARY TECHNICAL DATAOUTLINE DIMENSIONSDimensions shown in inches and (mm).48-Lead CSP (CP-48)48-Lead TQFP(SU-48)0.006 (0.17)BSC0.024 (0.60) 0.017 (0.42) 0.012 (0.30) 0.009 (0.23) BSC PIN 1CONTROLLING DIMENSIONS ARE IN MILLIMETERS0.035 (0.90) MAX 0.033 (0.85) NOMREF元器件交易网。

DAC7554IDGS中文资料

FEATURES DESCRIPTIONAPPLICATIONSSCLKSYNCDINOUT AOUT BOUT COUT DDAC7554SLAS399A–OCTOBER2004–REVISED NOVEMBER2004 12-BIT,QUAD,ULTRALOW GLITCH,VOLTAGE OUTPUTDIGITAL-TO-ANALOG CONVERTER• 2.7-V to5.5-V Single Supply The DAC7554is a quad-channel,voltage-output DACwith exceptional linearity and monotonicity.Its pro-•12-Bit Linearity and Monotonicityprietary architecture minimizes undesired transients •Rail-to-Rail Voltage Outputsuch as code to code glitch and channel to channel •Settling Time:5µs(Max)crosstalk.The low-power DAC7554operates from a •Ultralow Glitch Energy:0.1nVs single2.7-V to5.5-V supply.The DAC7554outputamplifiers can drive a2-kΩ,200-pF load rail-to-rail •Ultralow Crosstalk:–100dBwith5-µs settling time;the output range is set using •Low Power:880µA(Max)an external voltage reference.•Per-Channel Power Down:2µA(Max)The3-wire serial interface operates at clock rates up •Power-On Reset to Zero Scale to50MHz and is compatible with SPI,QSPI,•SPI-Compatible Serial Interface:Up to50MHz Microwire,and DSP interface standards.The outputsof all DACs may be updated simultaneously or •Simultaneous or Sequential Updatesequentially.The parts incorporate a power-on-reset •Specified Temperature Range:–40°C to105°C circuit to ensure that the DAC outputs power up to•Small10-Lead MSOP Package zero volts and remain there until a valid write cycle tothe device takes place.The parts contain apower-down feature that reduces the current con-sumption of the device to under1µA.•Portable Battery-Powered Instruments•Digital Gain and Offset Adjustment The small size and low-power operation makes theDAC7554ideally suited for battery-operated portable •Programmable Voltage and Current Sourcesapplications.The power consumption is typically3.5•Programmable AttenuatorsmW at5V,1.65mW at3V,and reduces to1µW in •Industrial Process Control power-down mode.The DAC7554is available in a10-lead MSOP pack-age and is specified over–40°C to105°C.FUNCTIONAL BLOCK DIAGRAMPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2004,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.ABSOLUTE MAXIMUM RATINGSDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.ORDERING INFORMATIONSPECIFIED PACKAGE PACKAGE ORDERING TRANSPORT PRODUCTPACKAGETEMPERATUREDESIGNATORMARKINGNUMBER MEDIA RANGE DAC7554IDGS80-piece Tube DAC755410MSOPDGS–40°C TO 105°CD754DAC7554IDGSR2500-piece Tapeand Reelover operating free-air temperature range (unless otherwise noted)(1)UNITV DD to GND–0.3V to 6V Digital input voltage to GND –0.3V to V DD +0.3V V out to GND–0.3V to V DD +0.3V Operating temperature range –40°C to 105°C Storage temperature range –65°C to 150°CJunction temperature (T J Max)150°C(1)Stresses above those listed under “Absolute Maximum Ratings”may cause permanent damage to the device.Exposure to absolute maximum conditions for extended periods may affect device reliability.2ELECTRICAL CHARACTERISTICSDAC7554 SLAS399A–OCTOBER2004–REVISED NOVEMBER2004V DD =2.7V to5.5V,REFIN=VDD,RL=2kΩto GND;CL=200pF to GND;all specifications–40°C to105°C,unlessotherwise specifiedPARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE(1)Resolution12Bits Relative accuracy±0.35±1LSB Differential nonlinearity Specified monotonic by design±0.08±0.5LSB Offset error±12mVZero-scale error All zeroes loaded to DAC register±12mVGain error±0.15%FSRFull-scale error±0.5%FSRZero-scale error drift7µV/°CGain temperature coefficient3ppm of FSR/°C PSRR V DD=5V0.75mV/V OUTPUT CHARACTERISTICS(2)Output voltage range0REFIN VOutput voltage settling time R L=2kΩ;0pF<C L<200pF5µsSlew rate1V/µs Capacitive load stability R L=∞470pFR L=2kΩ1000Digital-to-analog glitch impulse1LSB change around major carry0.1nV-s Channel-to-channel crosstalk1-kHz full-scale sine wave,outputs unloaded–100dBDigital feedthrough0.1nV-s Output noise density(10-kHz offset fre-70nV/rtHz quency)Total harmonic distortion F OUT=1kHz,F S=1MSPS,BW=20kHz–85dBDC output impedance1ΩShort-circuit current V DD=5V50mAV DD=3V20Power-up time Coming out of power-down mode,V DD=5V15µsComing out of power-down mode,V DD=3V15LOGIC INPUTS(2)Input current±1µAV IN_L,Input low voltage V DD=5V0.3V DD VV IN_H,Input high voltage V DD=3V0.7V DD VPin capacitance3pF POWER REQUIREMENTSV DD 2.7 5.5VI DD(normal operation)DAC active and excluding load currentV DD=3.6V to5.5V V IH=V DD and V IL=GND700880µAV DD=2.7V to3.6V550830I DD(all power-down modes)V DD=3.6V to5.5V V IH=V DD and V IL=GND0.22µAV DD=2.7V to3.6V0.052Reference input impedance25kΩPOWER EFFICIENCYI OUT/I DD I LOAD=2mA,V DD=5V93%(1)Linearity tested using a reduced code range of48to4048;output unloaded.(2)Specified by design and characterization,not production tested.3 TIMING CHARACTERISTICS(1)(2)SCLK SYNCD INDAC7554SLAS399A–OCTOBER2004–REVISED NOVEMBER2004V DD =2.7V to5.5V,RL=2kΩto GND;all specifications–40°C to105°C,unless otherwise specifiedPARAMETER TEST CONDITIONS MIN TYP MAX UNITSV DD=2.7V to3.6V20t1(3)SCLK cycle time nsV DD=3.6V to5.5V20V DD=2.7V to3.6V10t2SCLK HIGH time nsV DD=3.6V to5.5V10V DD=2.7V to3.6V10t3SCLK LOW time nsV DD=3.6V to5.5V10V DD=2.7V to3.6V4SYNC falling edge to SCLK falling edge setupt4ns time VDD=3.6V to5.5V4V DD=2.7V to3.6V5t5Data setup time nsV DD=3.6V to5.5V5V DD=2.7V to3.6V 4.5t6Data hold time nsV DD=3.6V to5.5V 4.5V DD=2.7V to3.6V0t7SCLK falling edge to SYNC rising edge nsV DD=3.6V to5.5V0V DD=2.7V to3.6V20t8Minimum SYNC HIGH time nsV DD=3.6V to5.5V20(1)All input signals are specified with t R=t F=1ns(10%to90%of V DD)and timed from a voltage level of(V IL+V IH)/2.(2)See Serial Write Operation timing diagram Figure1.(3)Maximum SCLK frequency is50MHz at V DD=2.7V to5.5V.Figure1.Serial Write Operation4PIN DESCRIPTIONV OUTV OUTV OUTV OUTDAC7554 SLAS399A–OCTOBER2004–REVISED NOVEMBER2004DGS Package(Top View)Terminal FunctionsTERMINAL DESCRIPTION1VOUTA Analog output voltage from DAC A2VOUTB Analog output voltage from DAC B3GND Ground4VOUTC Analog output voltage from DAC C5VOUTD Analog output voltage from DAC D6SCLK Serial clock input7DIN Serial data input8VDD Analog voltage supply input9SYNC Frame synchronization input.The falling edge of the FS pulse indicates the start of a serial data frame shifted out to the DAC755410REFIN Analog input.External reference5TYPICAL CHARACTERISTICSL i n e a r i t y E r r o r − L S BD i f f e r e n t i a l L i n e a r i t yE r r o r − L S BDigital Input Code05121024153620482560307235844096L i n e a r i t y E r r o r − L S BD i f f e r e n t i a l L i n e a r i t yE r r o r − L S BDigital Input CodeL i n e a r i t y E r r o r − L S BD i f f e r e n t i a l L i n e a r i t yE r r o r − L S BDigital Input CodeL i n e a r i t y E r r o r − L S BD i f f e r e n t i a l L i n e a r i t yE r r o r − L S BDigital Input CodeDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004LINEARITY ERROR ANDLINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORDIFFERENTIAL LINEARITY ERRORvsvsDIGITAL INPUT CODEDIGITAL INPUT CODEFigure 2.Figure 3.LINEARITY ERROR ANDLINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORDIFFERENTIAL LINEARITY ERRORvsvsDIGITAL INPUT CODEDIGITAL INPUT CODEFigure 4.Figure 5.6L i n e a r i t y E r r o r − L S BD i f f e r e n t i a l L i n e a r i t yE r r o r − L S BDigital Input CodeL i n e a r i t y E r r o r − L S BD i f f e r e n t i a l L i n e a r i t yE r r o r − L S BDigital Input CodeL i n e a r i t y E r r o r − L S BD i f f e r e n t i a l L i n e a r i t yE r r o r − L S BDigital Input CodeL i n e a r i t y E r r o r − L S BD i f f e r e n t i a l L i n e a r i t yE r r o r − L S BDigital Input CodeDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)LINEARITY ERROR ANDLINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORDIFFERENTIAL LINEARITY ERRORvsvsDIGITAL INPUT CODEDIGITAL INPUT CODEFigure 6.Figure 7.LINEARITY ERROR ANDLINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORDIFFERENTIAL LINEARITY ERRORvsvsDIGITAL INPUT CODEDIGITAL INPUT CODEFigure 8.Figure 9.7−50510−40−10205080Z e r o −S c a l e E r r o r − m VT A − Free-Air Temperature − °C−50510−40−10205080Z e r o −S c a l e E r r o r − m VT A − Free-Air Temperature − °C−10−55−40−10205080F u l l −S c a l e E r r o r − m VT A − Free-Air Temperature − °C−10−55−40−10205080F u l l −S c a l e E r r o r − m VT A − Free-Air Temperature − °CDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)ZERO-SCALE ERRORZERO-SCALE ERRORvsvsFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFigure 10.Figure 11.FULL-SCALE ERRORFULL-SCALE ERRORvsvsFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFigure 12.Figure 13.80.050.10.150.251015− O u t p u t V o l t a g e − VV O I SINK − Sink Current − mA5.205.305.405.5051015− O u t p u t V o l t a g e − VV O I SOURCE − Source Current − mA51015− O u t p u t V o l t a g e − VV O I SOURCE − Source Current − mA5121024153620482560307235844096Digital Input CodeD D I S u p p l y C u r r e n t − −AµDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)SINK CURRENT AT NEGATIVE RAILSOURCE CURRENT AT POSITIVE RAILFigure 14.Figure 15.SUPPLY CURRENTvsSOURCE CURRENT AT POSITIVE RAILDIGITAL INPUT CODEFigure 16.Figure 17.90100200300400500600700800−40−10205080110D D I S u p p l y C u r r e n t − −AµT A − Free-Air Temperature − °C400450500550600650700D D I S u p p l y C u r r e n t − −AµV DD − Supply Voltage − V200600100014001800220012345D D I S u p p l y C u r r e n t − −AµV LOGIC − Logic Input Voltage − V500100015002000f − F r e q u e n c y − H zI DD − Current Consumption −m ADAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)SUPPLY CURRENTSUPPLY CURRENTvsvsFREE-AIR TEMPERATURESUPPLY VOLTAGEFigure 18.Figure 19.SUPPLY CURRENTvsLOGIC INPUT VOLTAGEHISTOGRAM OF CURRENT CONSUMPTION -5.5VFigure 20.Figure 21.10−6−4−2024605121024153620482560307235844095T o t a l E r r o r - m VDigital Input Code500100015002000f − F r e q u e n c y − H zI DD − Current Consumption −m AT o t a l E r r o r - m VDigital Input Code12345− O u t p u t V o l t a g e − VV O t − Time − 4m s/divDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)HISTOGRAM OF CURRENT CONSUMPTION -2.7VTOTAL ERROR -5VFigure 22.Figure 23.TOTAL ERROR -2.7VEXITING POWER-DOWN MODEFigure 24.Figure 25.1112345− O u t p u t V o l t a g e − VV O t − Time − 5m s/div− O u t p u t V o l t a g e − VV O t − Time − 5m s/divTime - (400 nS/Div)Trigger PulseV O (5 m V /D i v )-Trigger PulseV O (5 m V /D i v )-Time - (400 nS/Div)DAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)LARGE-SIGNAL SETTLING TIME -5VLARGE-SIGNAL SETTLING TIME -2.7VFigure 26.Figure 27.MIDSCALE GLITCHWORST-CASE GLITCHFigure 28.Figure 29.12Time - (400 nS/Div)Trigger PulseV O (5 m V /D i v )-Time - (400 nS/Div)Trigger PulseV O (5 m V /D i v )-−100−90−80−70−60−50−40012345678910T H D − T o t a l H a r m o n i c D i s t o r t i o n − d BOutput Frequency (Tone) − kHzDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)CHANNEL-TO-CHANNEL CROSSTALKDIGITAL FEEDTHROUGH ERRORFOR A FULL-SCALE SWINGFigure 30.Figure 31.TOTAL HARMONIC DISTORTIONvsOUTPUT FREQUENCYFigure 32.133-Wire Serial InterfaceDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004The DAC7554digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface.Table 1.Serial Interface ProgrammingCONTROLDATA BITS DAC(s)FUNCTIONLD1LD0Sel1Sel0DB11-DB00000data A Input register updated 0001data B Input register updated 0010data C Input register updated 0011data D Input register updated0100data A DAC register updated,output updated 0101data B DAC register updated,output updated 0110data C DAC register updated,output updated 0111data D DAC register updated,output updated1000data A Input register and DAC register updated,output updated 1001data B Input register and DAC register updated,output updated 1010data C Input register and DAC register updated,output updated 1011data D Input register and DAC register updated,output updated 1100data A-D Input register updated1101data A-D DAC register updated,output updated1110data A-D Input register and DAC register updated,output updated 1111data--Power-Down Mode -See Table 2Sel1Sel0CHANNEL SELECT00Channel A 01Channel B 10Channel C 11Channel D LD1LD0FUNCTION00Single channel store.The selected input register is updated.01Single channel DAC update.The selected DAC register is updated with input register information.10Single channel update.The selected input and DAC register is updated.11Depends on the Sel1and Sel0Bits14POWER-DOWN MODEDAC7554 SLAS399A–OCTOBER2004–REVISED NOVEMBER2004In power-down mode,the DAC outputs are programmed to one of three output impedances,1kΩ,100kΩ,or floating.Table2.Power-Down Mode ControlEXTENDED CONTROL DATA BITSFUNCTION LD1LD0Sel1Sel0DB11DB10DB9DB8DB7DB6-DB0111100000X PWD Hi-Z(selected channel=A)111100001X PWD1kΩ(selected channel=A)111100010X PWD100kΩ(selected channel=A)111100011X PWD Hi-Z(selected channel=A)111100100X PWD Hi-Z(selected channel=B)111100101X PWD1kΩ(selected channel=B)111100110X PWD100kΩ(selected channel=B)111100111X PWD Hi-Z(selected channel=B)111101000X PWD Hi-Z(selected channel=C)111101001X PWD1kΩ(selected channel=C)111101010X PWD100kΩ(selected channel=C)111101011X PWD Hi-Z(selected channel=C)111101100X PWD Hi-Z(selected channel=D)111101101X PWD1kΩ(selected channel=D)111101110X PWD100kΩ(selected channel=D)111101111X PWD Hi-Z(selected channel=D)11111X X00X PWD Hi-Z(all channels)11111X X01X PWD1kΩ(all channels)11111X X10X PWD100kΩ(all channels)11111X X11X PWD Hi-Z(all channels)DB11ALL CHANNELS FLAG0See DB7–DB101DB10and DB9are Don't CareDB10DB9Channel Select00Channel A01Channel B10Channel C11Channel DDB8DB7Power-Down Mode00Power-down Hi-Z01Power-down1kΩ10Power-down100kΩ11Power-down Hi-Z15THEORY OF OPERATIONDAC External Reference InputD/A SECTIONPower-On ResetV OUTPowerDownTo Output AmplifierSERIAL INTERFACERESISTOR STRING16-Bit Word and Input Shift RegisterOUTPUT BUFFER AMPLIFIERSDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004There is a single reference input pin for the four The architecture of the DAC7554consists of a string DACs.The reference input is unbuffered.The user DAC followed by an output buffer amplifier.Figure 33can have a reference voltage as low as 0.25V and shows a generalized block diagram of the DAC as high as V DD because there is no restriction due to architecture.headroom and footroom of any reference amplifier.It is recommended to use a buffered reference in the external circuit (e.g.,REF3140).The input impedance is typically 25k Ω.On power up,all internal registers are cleared and all Figure 33.Typical DAC Architecturechannels are updated with zero-scale voltages.Until valid data is written,all DAC outputs remain in this state.This is particularly useful in applications where The input coding to the DAC7554is unsigned binary,it is important to know the state of the DAC outputs which gives the ideal output voltage as:while the device is powering up.In order not to turn V OUT =REFIN ×D/4096on ESD protection devices,V DD should be applied Where D =decimal equivalent of the binary code that before any other pin is brought high.is loaded to the DAC register which can range from 0to 4095.The DAC7554has a flexible power-down capability as described in Table 2.Individual channels could be powered down separately or all channels could be powered down simultaneously.During a power-down condition,the user has flexibility to select the output impedance of each channel.During power-down operation,each channel can have either 1-k Ω,100-k Ω,or Hi-Z output impedance to ground.Figure 34.Typical Resistor StringThe DAC7554is controlled over a versatile 3-wire serial interface,which operates at clock rates up to The resistor string section is shown in Figure 34.It is 50MHz and is compatible with SPI,QSPI,Microwire,simply a string of resistors,each of value R.The and DSP interface standards.digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier.The voltage is tapped off by closing one of the switches connecting the The input shift register is 16bits wide.DAC data is string to the amplifier.Because it is a string of loaded into the device as a 16-bit word under the resistors,it is specified monotonic.The DAC7554control of a serial clock input,SCLK,as shown in the architecture uses four separate resistor strings to Figure 1timing diagram.The 16-bit word,illustrated minimize channel-to-channel crosstalk.in Table 1,consists of four control bits followed by 12bits of DAC data.The data format is straight binary with all zeroes corresponding to 0-V output and all ones corresponding to full-scale output (V REF –1The output buffer amplifier is capable of generating LSB).Data is loaded MSB first (Bit 15)where the first rail-to-rail voltages on its output,which gives an two bits (LD1and LD0)determine if the input register,output range of 0V to V DD .It is capable of driving a DAC register,or both are updated with shift register load of 2k Ωin parallel with up to 1000pF to GND.input data.Bit 13and bit 12(Sel1and Sel0)The source and sink capabilities of the output ampli-determine whether the data is for DAC A,DAC B,fier can be seen in the typical curves.The slew rate is DAC C,DAC D,or all DACs.All channels are 1V/µs with a half-scale settling time of 3µs with the updated when bits 15and 14(LD1and LD0)are output unloaded.high.16Generating ±5-V,±10-V,and ±12-V Outputs For INTEGRAL AND DIFFERENTIAL LINEARITYGLITCH ENERGYCHANNEL-TO-CHANNEL CROSSTALKAPPLICATION INFORMATIONWaveform GenerationDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004The SYNC input is a level-triggered input that acts as can exceed 1MSPS if the waveform to be generated a frame synchronization signal and chip enable.Data consists of small voltage steps between consecutive can only be transferred into the device while SYNC is DAC updates.To obtain a high dynamic range,low.To start the serial data transfer,SYNC should be REF3140(4.096V)or REF02(5.0V)are rec-taken low,observing the minimum SYNC to SCLK ommended for reference voltage generation.falling edge setup time,t 4.After SYNC goes low,serial data is shifted into the device's input shift Precision Industrial Controlregister on the falling edges of SCLK for 16clock pulses.Any data and clock pulses after the sixteenth Industrial control applications can require multiple falling edge of SCLK are ignored.No further serial feedback loops consisting of sensors,ADCs,MCUs,data transfer occurs until SYNC is taken high and low DACs,and actuators.Loop accuracy and loop speed again.are the two important parameters of such control loops.SYNC may be taken high after the falling edge of the sixteenth SCLK pulse,observing the minimum SCLK Loop Accuracy:falling edge to SYNC rising edge time,t 7.In a control loop,the ADC has to be accurate.Offset,After the end of serial data transfer,data is automati-gain,and the integral linearity errors of the DAC are cally transferred from the input shift register to the not factors in determining the accuracy of the loop.input register of the selected DAC.If SYNC is taken As long as a voltage exists in the transfer curve of a high before the sixteenth falling edge of SCLK,the monotonic DAC,the loop can find it and settle to it.data transfer is aborted and the DAC input registers On the other hand,DAC resolution and differential are not updated.linearity do determine the loop accuracy,because each DAC step determines the minimum incremental change the loop can generate.A DNL error less than –1LSB (non-monotonicity)can create loop instability.The DAC7554uses precision thin-film resistors pro-A DNL error greater than +1LSB implies unnecess-viding exceptional linearity and monotonicity.Integral arily large voltage steps and missed voltage targets.linearity error is typically within (+/-)0.35LSBs,and With high DNL errors,the loop looses its stability,differential linearity error is typically within (+/-)0.08resolution,and accuracy.Offering 12-bit ensured LSBs.monotonicity and ±0.08LSB typical DNL error,755X DACs are great choices for precision control loops.Loop Speed:The DAC7554uses a proprietary architecture that minimizes glitch energy.The code-to-code glitches Many factors determine control loop speed.Typically,are so low,they are usually buried within the the ADC's conversion time,and the MCU's compu-wide-band noise and cannot be easily detected.The tation time are the two major factors that dominate DAC7554glitch is typically well under 0.1nV-s.Such the time constant of the loop.DAC settling time is low glitch energy provides more than 10X improve-rarely a dominant factor because ADC conversion ment over industry alternatives.times usually exceed DAC conversion times.DAC offset,gain,and linearity errors can slow the loop down only during the start-up.Once the loop reaches its steady-state operation,these errors do not affect The DAC7554architecture is designed to minimize loop speed any further.Depending on the ringing channel-to-channel crosstalk.The voltage change in characteristics of the loop's transfer function,DAC one channel does not affect the voltage output in glitches can also slow the loop down.With its 1another channel.The DC crosstalk is in the order of a MSPS (small-signal)maximum data update rate,few microvolts.AC crosstalk is also less than –100DAC7554can support high-speed control loops.dBs.This provides orders of magnitude improvement Ultra-low glitch energy of the DAC7554significantly over certain competing architectures.improves loop stability and loop settling time.Generating Industrial Voltage Ranges:For control loop applications,DAC gain and offset errors are not important parameters.This could be Due to its exceptional linearity,low glitch,and low exploited to lower trim and calibration costs in a crosstalk,the DAC7554is well suited for waveform high-voltage control circuit ing a quad generation (from DC to 10kHz).The DAC7554operational amplifier (OPA4130),and a voltage refer-large-signal settling time is 5µs,supporting an ence (REF3140),the DAC7554can generate the update rate of 200KSPS.However,the update rateswide voltage swings required by the control loop.17V out +V ref ǒR2R1)1ǓDin 4096*V tail R2R1(1)V OUTDAC7554SLAS399A–OCTOBER 2004–REVISED NOVEMBER 2004Fixed R1and R2resistors can be used to coarselyset the gain required in the first term of the equation.Once R2and R1set the gain to include some minimal over-range,a DAC7554channel could be used to set the required offset voltages.Residual errors are not an issue for loop accuracy because offset and gain errors could be tolerated.One DAC7554channel can provide the Vtail voltage,while the other three DAC7554channels can provide Vdac Figure 35.Low-cost,Wide-swing Voltage Gener-voltages to help generate three high-voltage outputs.ator for Control Loop Applications For ±5-V operation:R1=10k Ω,R2=15k Ω,Vtail =3.33V,Vref =4.096VThe output voltage of the configuration is given by:For ±10-V operation:R1=10k Ω,R2=39k Ω,Vtail =2.56V,Vref =4.096VFor ±12-V operation:R1=10k Ω,R2=49k Ω,Vtail =2.45V,Vref =4.096V18PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)DAC7554IDGS ACTIVE MSOP DGS 10100TBD CU NIPDAU Level-1-220C-UNLIM DAC7554IDGSRACTIVEMSOPDGS102500TBDCU NIPDAULevel-1-220C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS)or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing orchemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM30-Mar-2005Addendum-Page 1。

7815芯片

7815芯片
7815芯片是一款具有高性能和低功耗的集成电路芯片，广泛
应用于微电子领域。

下面是对7815芯片的详细介绍。

7815芯片采用了先进的工艺技术，具有较高的性能和可靠性。

它的主要特点包括：电压稳定、电流大、工作温度范围广、功耗低等。

7815芯片的电压稳定性非常好，可以提供一个稳定
的电平输出，能够满足各种电子设备的电源供应需求。

同时，它的电流输出能力很强，可以在较大负载情况下保持输出电流的稳定。

7815芯片的工作温度范围广，可以适应各种环境下的工作条件。

无论是在高温还是低温环境中，7815芯片都能够正常运行，并保持良好的性能。

这使得它适用于各种电子设备，包括工业控制系统、通信设备、医疗仪器等。

此外，7815芯片的功耗非常低，可以提供高效的电源供应，
并且节约能源。

这对于移动设备和便携式电子设备尤为重要，可以延长电池的使用时间，并提高设备的使用寿命。

7815芯片的应用非常广泛。

它可以用作线性稳压器，为各种
数字和模拟电路提供稳定的电源。

同时，它还可以用于电源管理系统、电源变换器、电源适配器、充电器等领域。

总结一下，7815芯片是一款具有高性能和低功耗的集成电路
芯片。

它具有电压稳定、电流大、工作温度范围广、功耗低等特点，并广泛应用于各种电子设备中。

未来随着科技的不断发
展，7815芯片有望在更多领域中得到应用，满足人们对于高性能和低功耗的需求。

AN7812R中文资料

4-pin SIL Plastic Package with Fin (SSIP004-P-0000)
s Block Diagram
1 Pass Tr Q1 Current Source Current Limiter Input
RSC 3 Output Reset
Starter
Voltage Reference
*1 Follow the derating curve. When Tj exceeds 150˚C, the internal circuit cuts off the output.
s Electrical Characteristics (Ta=25˚C)
AN7800R Series
· AN7805R (1A, 5V Type)
Parameter Output voltage Output voltage tolerance Line regulation Load regulation Bias current Input bias current fluctuation Load bias current fluctuation Output noise voltage Ripple rejection ratio Minimum input/output voltage difference Output impedance Output short circuit current Peak output current Output voltage temperature coefficient Output voltage at reset Reset input current Symbol VO VO REGIN REGL Ibias ∆Ibias (IN) ∆Ibias (L) Vno RR VDIF (min.) ZO IO (Short) IO (Peak) ∆VO/Ta VO (Reset) II (Reset) Condition Tj=25˚C VI=8 to 20V, IO=5mA to 1A, Tj=0 to 125˚C, PD < 15W = VI=7.5 to 25V, Tj=25˚C VI=8 to 12V, Tj=25˚C IO=5mA to 1.5A, Tj=25˚C IO=250 to 750mA, Tj=25˚C Tj=25˚C VI=7.5 to 25V, Tj=25˚C IO=5mA to 1A, Tj=25˚C f=10Hz to 100kHz VI=8 to 18V, IO=100mA, f=120Hz IO=1A, Tj=25˚C f=1kHz VI=35V, Tj=25˚C Tj=25˚C IO=5mA, Tj=0 to 125˚C Tj=25˚C, II (Reset)=1mA Tj=25˚C 62 2 17 700 2 – 0.3 1 1 40 min 4.8 4.75 3 1 15 5 3.9 typ 5 max 5.2 5.25 100 50 100 50 8 1.3 0.5 Unit V V mV mV mV mV mA mA mA µV dB V mΩ mA A mV/˚C V mA

LM7811I中文资料

3-TERMINAL 1A POSITIVE VOLTAGE REGULATORSThe LM78XX series of three-terminal positive regulators are available in the TO-220/D-PAK package and with several fixed output voltages, making them useful in a wide range of applications. Each type employs internal current limiting, thermal shut-down and safe area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents.FEATURES• Output Current up to 1A• Output Voltages of 5, 6, 8, 9, 10, 11, 12, 15, 18, 24V • Thermal Overload Protection • Short Circuit Protection• Output Transistor SOA ProtectionKA78XXCT ± 4%KA78XXAT ± 2%KA78XXIT TO-220 -40 ~ +125 °CKA78XXR KA78XXAR ± 2% KA78XXIR± 4%D-PAK -40 ~ +125 °C0 ~ +125°C0 ~ +125 °C 1: Input 2: GND 3: OutputBLOCK DIAGRAM1ORDERING INFORMATIONDevice Operating Temperature± 4%Output Voltage TolerancePackag e©1999 Fairchild Semiconductor CorporationRev. BABSOLUTE MAXIMUM RATINGS (T A = +25°C, unless otherwise specified )LM7805/I/R/RI ELECTRICAL CHARACTERISTICS(Refer to test circuit, T MIN < T J < T MAX , I O = 500mA, V I = 10V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)* T MIN <T J <T MAXLM78XXI/RI: T MIN = - 40 °C, T MAX = +125°CLM78XX/R: T MIN = 0 °C, T MAX = +125°C *Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.CharacteristicSymbol Value Unit Input Voltage (for V O = 5V to 18V) (for V O = 24V)V I V I 3540V V Thermal Resistance Junction-Cases R θJC 5°C/W Thermal Resistance Junction-AirR θJA 65°C/W Operating Temperature Range KA78XX/A/R/RA KA78XXI/RI T OPR 0 ~ +125-40 ~ +125°C °C Storage Temperature RangeT STG-65 ~ +150°CLM7805I LM7805Min Typ Max Min Typ Max T J =+25°C4.85.0 5.2 4.8 5.0 5.2Output VoltageV O5.0mA ≤ I O ≤1.0A, P O ≤ 15W V I = 7V to 20V V I = 8V to 20V4.755.0 5.254.755.0 5.25VV O = 7V to 25V4.0100 4.0100V I = 8V to 12V 1.650 1.650I O =5.0mA to1.5A 91009100I O =250mA to 750mA450450 Quiescent Current I Q T J =+25 °C5.085.08mA I O = 5mA to 1.0A 0.030.50.030.5 Quiescent Current Change ∆I Q V I = 7V to 25V 0.3 1.3mA V I = 8V to 25V 0.3 1.3Output Voltage Drift ∆V O /∆T I O = 5mA-0.8-0.8mV/°C Output Noise Voltage V N f = 10Hz to 100Khz, T A =+25°C 4242µV/Vo Ripple RejectionRR f = 120Hz V O = 8 to 18V62736273dB Dropout Voltage V O I O = 1A, T J =+25°C 22V Output Resistance R O f = 1KHz1515m Ω Short Circuit Current I SC V I = 35V, T A =+25°C 230230mA Peak CurrentI PKT J =+25°C2.22.2ACharacteristicSymbolTest ConditionsUnitLine Regulation ∆V O ∆V O Load Regulation T J =+25°CT J =+25°CmV mV(Refer to test circuit, T MIN <T J <T MAX , I O =500mA, V I = 11V C I = 0.33µF, C O = 0.1µF, unless otherwise specified)*T MIN <T J <T MAXLM78XXI/RI: T MIN = - 40 °C, T MAX = +125°CLM78XX/R: T MIN = 0 °C, T MAX = +125°C* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.LM7806ILM7806Min Typ Max MinTyp Max T J =+25°C5.756.0 6.255.756.0 6.25Output Voltage V O5.0mA ≤ I O ≤1.0A, P D ≤ 15W V I = 8.0V to 21V V I = 9.0V to 21V5.76.0 6.3 5.76.0 6.3VV I = 8V to 25V 51205120V I = 9V to 13V 1.560 1.560I O =5mA to 1.5A 91209120I O =250mA to750A 360360Quiescent Current I Q T J =+25°C 5.08 5.08mA I O = 5mA to 1A 0.50.5Quiescent Current Change ∆I Q V I = 8V to 25V 1.3mAV I = 9V to 25V 1.3Output Voltage Drift ∆V O /∆T I O = 5mA-0.8-0.8mV/°C Output Noise Voltage V N f = 10Hz to 100Khz, T A =+25°C 4545µV/V O Ripple RejectionRR f = 120HzV I = 9V to 19V 59755975dB Dropout Voltage V D I O = 1A, T J =+25°C 22V Output Resistance R D f = 1KHz1919m ΩShort Circuit Current I SC V I = 35V, T A =+25°C 250250mA Peak CurrentI PKT J =+25°C2.22.2ALine Regulation Load Regulation ∆V O ∆V O T J =+25°CT J =+25°CmV mV CharacteristicSymbolTest ConditionsUnit(Refer to test Circuit, T MIN <T J < T MAX , I O = 500mA, V I = 14V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)*T MIN <T J <T MAXLM78XXI/RI: T MIN = - 40 °C, T MAX = +125°CLM78XX/R: T MIN = 0 °C, T MAX = +125°C* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.LM7808I LM7808Min Typ Max Min Typ Max T J =+25°C7.78.08.37.78.08.3 Output Voltage V O5.0mA ≤ I O ≤ 1.0A, P O ≤ 15W V I = 10.5V to 23V V I = 11.5V to 23V7.68.08.47.68.08.4VV I = 10.5V to 25V5.0160 5.0160V I = 11.5V to 17V 2.080 2.080I O= 5.0mA to 1.5A1016010160I O = 250mA to 750mA 5.080 5.080 Quiescent Current I Q T J =+25°C5.08 5.08mA I O = 5mA to 1.0A 0.050.50.050.5 Quiescent Current Change ∆I Q V I = 10.5A to 25V 0.5 1.0mAV I = 11.5V to 25V 0.5 1.0Output Voltage Drift ∆V O /∆T I O = 5mA-0.8-0.8mV/°C Output Noise Voltage V N f = 10Hz to 100Khz, T A =+25°C 5252µV/Vo Ripple RejectionRR f = 120Hz, V I = 11.5V to 21.556735673dB Dropout Voltage V D I O = 1A, T J =+25°C 22V Output Resistance R O f = 1KHz1717m Ω Short Circuit Current I SC V I = 35V, T A =+25 °C 230230mA Peak CurrentI PKT J =+25°C2.22.2ACharacteristicSymbolTest ConditionsUnitLine Regulation Load Regulation ∆V O ∆V O T J =+ 25°C T J = +25°C mV mV(Refer to test circuit. T MIN < T J <T MAX , I O = 500mA, V I = 15V, C I = 0.33µF, C O = 0.1µF. unless otherwise specified)*T MIN <T J <T MAXLM78XXI/RI: T MIN = - 40 °C, T MAX = +125°CLM78XX/R: T MIN = 0 °C, T MAX = +125°C* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.LM7809I LM7809Min Typ Max Min Typ Max T J =+25°C8.6599.358.6599.35Output Voltage V O5.0mA ≤ I O ≤1.0A, P D ≤15W V I = 11.5V to 24V V I = 12.5V to 24V8.699.48.699.4VV I = 11.5V to 25V 61806180V I = 12V to 25v 290290I O = 5mA to 1.5A 1218012180I O = 250mA to 750mA 490490 Quiescent Current I Q T J =+25°C5.08 5.08mA I O = 5mA to 1.0A 0.50.5 Quiescent Current Change ∆I Q V I = 11.5V to 26V 1.3mA V I = 12.5V to 26V 1.3 Output Voltage Drift ∆V O /∆T I O = 5mA-1-1mV/°C Output Noise Voltage V N f = 10Hz to 100Khz, T A =+25°C 5858µV/V O Ripple RejectionRR f = 120HzV I = 13V to 23V 56715671dB Dropout Voltage V D I O = 1A, T J =+25 °C 22V Output Resistance R O f = 1KHz1717m Ω Short Circuit Current I SC V I = 35V, T A =+25°C 250250mA Peak CurrentI PKT J = +25°C2.22.2ACharacteristicSymbolTest ConditionsLine Regulation Load Regulation ∆V O ∆V O T J =+25°CT J =+25°CmV mV UnitLM7810/I/R/RI ELECTRICAL CHARACTERISTICS(Refer to test circuit, T MIN <T J <T MAX , I O = 500mA, V I =16V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)*T MIN <T J <T MAXLM78XXI/RI: T MIN = - 40 °C, T MAX = +125°CLM78XX/R: T MIN = 0 °C, T MAX = +125°C* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.LM7810I LM7810Min Typ Max Min Typ Max T J =+25°C9.61010.49.61010.4 Output Voltage V O5.0mA ≤ I O ≤1.0A, P D ≤15W V I = 12.5V to 25V V I = 13.5V to 25V9.51010.59.51010.5VV I = 12.5V to 25V1020010200V I = 13V to 25V 31003100I O= 5mA to 1.5A1220012200I O = 250mA to 750mA 44004400 Quiescent Current I Q T J =+25°C5.18 5.18mA I O = 5mA to 1.0A 0.50.5 Quiescent Current Change ∆I Q V I = 12.5V to 29V 1.0mAV I = 13.5V to 29V 1.0 Output Voltage Drift ∆V O /∆T I O = 5mA-1-1mV/°C Output Noise Voltage V N f = 10Hz to 100Khz, T A =+25°C 5858µV/Vo Ripple RejectionRR f = 120HzV I = 13V to 23V 56715671dB Dropout Voltage V D I O = 1A, T J =+25 °C 22V Output Resistance R O f = 1KHz1717m Ω Short Circuit Current I SC V I = 35V, T A =+25°C 250250mA Peak CurrentI PKT J =+25°C2.22.2AUnitLine Regulation ∆V O ∆V O T J =+25°CT J =+25°C Load Regulation CharacteristicSymbolTest ConditionsmV mVLM7811/I/R/RI ELECTRICAL CHARACTERISTICS(Refer to test circuit, T MIN <T J <T MAX , I O = 500mA, V I =18V, C I =0.33µF, C O = 0.I µF, unless otherwise specified)*T MIN <T J <T MAXLM78XXI/RI: T MIN = - 40 °C, T MAX = +125°CLM78XX/R: T MIN = 0 °C, T MAX = +125°C* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.LM7811I LM7811Min Typ Max Min Typ Max T J =+25°C10.61111.410.61111.4 Output Voltage V O5.0mA ≤ I O ≤1.0A, P D ≤15W V I = 13.5V to 26V V I = 14.5V to 26V10.51111.510.51111.5VV I= 13.5V to 25V1022010220V I = 14V to 21V 3.01103110I O= 5.0mA to 1.5A1222012220I O = 250mA to 750mA 41104110 Quiescent Current I Q T J =+25°C5.18 5.18mA I O = 5mA to 1.0A 0.50.5 Quiescent Current Change ∆I Q V I = 13.5V to 29V 1.0mA V I = 14.5V to 29V 1.0Output Voltage Drift ∆V O /∆T I O = 5mA-1-1mV/°C Output Noise Voltage V N f = 10Hz to 100Khz, T A =+25°C 7070µV/V O Ripple RejectionRR f = 120HzV I = 14V to 24V 55715571dB Dropout Voltage V D I O = 1A, T J =+25 °C 22V Output Resistance R O f = 1KHz1818m Ω Short Circuit Current I SC V I = 35V, T A =+25°C 250250mA Peak CurrentI PKT J =+25°C2.22.2AUnit Line Regulation ∆V O ∆V O T J =+25°C T J =+25°C Load Regulation CharacteristicSymbolTest ConditionsmV mVLM7812/I/R/RI ELECTRICAL CHARACTERISTICS(Refer to test circuit, T MIN <T J <T MAX , I O =500mA, V I =19V, C I = 0.33µF, C O = 0.1.µF, unless otherwise specified)T MIN <T J <T MAXLM78XXI/RI: T MIN = - 40 °C, T MAX = +125°CLM78XX/R: T MIN = 0 °C, T MAX = +125°C* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.LM7812I LM7812Min Typ Max Min Typ Max T J =+25°C11.51212.511.51212.5 Output Voltage V O5.0mA ≤ I O ≤1.0A, P D ≤15W V I = 14.5V to 27V V I = 15.5V to 27V11.41212.611.41212.6VV I = 14.5V to 30V1024010240V I = 16V to 22V 3.0120 3.0120I O= 5mA to 1.5A1124011240I O = 250mA to 750mA 5.0120 5.0120 Quiescent Current I Q T J =+25°C5.18 5.18mA I O = 5mA to 1.0A 0.10.50.10.5 Quiescent Current Change ∆I Q V I = 14.5V to 30V 0.5 1.0mAV I = 15V to 30V 1.0Output Voltage Drift ∆V O /∆T I O = 5mA0.5-1-1mV/°C Output Noise Voltage V N f = 10Hz to 100Khz, T A =+25°C 7676mV/V O Ripple RejectionRR f = 120HzV I = 15V to 25V 55715571dB Dropout Voltage V D I O = 1A, T J =+25 °C 22V Output Resistance R O f = 1KHz1818m Ω Short Circuit Current I SC V I = 35V, T A =+25°C 230230mA Peak CurrentI PKT J = +25°C2.22.2AUnitLine Regulation ∆V O ∆V O T J =+25°CT J =+25°C Load Regulation CharacteristicSymbolTest ConditionsmV mV(Refer to test circuit, T MIN <T J <T MAX , I O =500mA, V I =23V, C I =0.33µF, C O =0.1µF, unless otherwise specified)*T MIN <T J <T MAXLM78XXI/RI: T MIN = - 40 °C, T MAX = +125°CLM78XX/R: T MIN = 0 °C, T MAX = +125°C* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.LM7815I LM7815Min Typ Max Min Typ Max T J =+25°C14.41515.614.41515.6Output VoltageV O5.0mA ≤ I O ≤1.0A, P D ≤15WV I = 17.5V to 30VV I = 18.5V to 30V14.251515.7514.251515.75VV I= 17.5V to 30V1130011300V I = 20V to 26V 31503150I O = 5mA to 1.5A1230012300I O = 250mA to 750mA 41504150 Quiescent Current I Q T J =+25°C5.28 5.28mA I O = 5mA to 1.0A 0.50.5 Quiescent Current Change ∆I Q V I = 17.5V to 30V 1.0mAV I = 18.5V to 30V 1.0 Output Voltage Drift ∆V O /∆T I O = 5mA-1-1mV/°C Output Noise Voltage V N f = 10Hz to 100Khz, T A =+25°C 9090µV/V O Ripple RejectionRR f = 120HzV I = 18.5V to 28.5V 54705470dB Dropout Voltage V D I O = 1A, T J =+25 °C 22V Output Resistance R O f = 1KHz1919m Ω Short Circuit Current I SC V I = 35V, T A =+25°C 250250mA Peak CurrentI PKT J =+25°C2.22.2AUnitLine Regulation ∆V O ∆V O T J =+25°C T J =+25°C Load Regulation CharacteristicSymbolTest ConditionsmV mV(Refer to test circuit, T MIN <T J <T MAX , I O =500mA, V I =27V, C I =0.33µF, C O =0.1µF, unless otherwise specified )*T MIN <T J <T MAXLM78XXI/RI: T MIN = - 40 °C, T MAX = +125°CLM78XX/R: T MIN = 0 °C, T MAX = +125°C* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.LM7818I LM7818Min Typ Max Min Typ Max T J =+25°C17.31818.717.31818.7 Output Voltage V O5.0mA ≤ I O ≤1.0A, P D ≤15W V I = 21V to 33V V I = 22V to 33V17.11818.917.11818.9VV I = 21V to 33V1536015360V I = 24V to 30V 51805180I O = 5mA to 1.5A1536015360I O = 250mA to 750mA 5.0180 5.0180 Quiescent Current I Q T J =+25°C5.28 5.28mA I O = 5mA to 1.0A 0.50.5 Quiescent Current Change ∆I Q V I = 21V to 33V 1mAV I = 22V to 33V 1.0 Output Voltage Drift ∆V O /∆T I O = 5mA-1-1mV/°C Output Noise Voltage V N f = 10Hz to 100Khz, T A =+25°C 110110µV/V O Ripple RejectionRR f = 120HzV I = 22V to 32V 53695369dB Dropout Voltage V D I O = 1A, T J =+25°C 22V Output Resistance R O f = 1KHz2222m Ω Short Circuit Current I SC V I = 35V, T A =+25 °C 250250mA Peak CurrentI PKT J =+25°C2.22.2AUnitLine Regulation ∆V O ∆V O T J =+25°CT J =+25°CLoad Regulation CharacteristicSymbolTest ConditionsmV mV(Refer to test circuit, T MIN <T J <T MAX , I O = 500mA, V I = 33V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)*T MIN <T J <T MAXLM78XXI/RI: T MIN = - 40 °C, T MAX = +125°CLM78XX/R: T MIN = 0 °C, T MAX = +125°C* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.LM7824I LM7824Min Typ Max Min Typ Max T J =+25°C232425232425 Output Voltage V O5.0mA ≤ I O ≤ 1.0A, P D ≤ 15W V I = 27V to 38V V I = 28V to 38V22.82425.222.82425.25VV I = 27V to 38V1748017480V I = 30V to 36V 62406240I O= 5mA to 1.5A1548015480I O = 250mA to 750mA 5.0240 5.0240 Quiescent Current I Q T J =+25°C5.28 5.28mA I O = 5mA to 1.0A 0.10.50.10.5 Quiescent Current Change ∆I Q V I = 27V to 38V 0.51mAV I = 28V to 38V 0.51Output Voltage Drift ∆V O /∆T I O = 5mA-1.5-1.5mV/°C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25°C 16060µV/V O Ripple RejectionRR f = 120HzV I = 28V to 38V 50675067dB Dropout Voltage V D I O = 1A, T J =+25 °C 22V Output Resistance R O f = 1KHz2828m Ω Short Circuit Current I SC V I = 35V, T A =+25°C 230230mA Peak CurrentI PKT J =+25°C2.22.2AUnitLine Regulation ∆V O ∆V O T J =+25°CT J =+25°C Load Regulation CharacteristicSymbolTest ConditionsmV mV(Refer to the test circuits. T J = 0 to +I25°C, I O = 1A, V I = 10V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)*Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.CharacteristicSymbolTest ConditionsMin Typ Max Unit T J =+25°C4.955.1 Output VoltageV OI O = 5mA to 1A, P D ≤ 5W V I = 7.5 to 20V 4.85 5.2VV I = 7.5 to 25V I O = 500mA 550Line Regulation∆V OV I = 8V to 12V 350VV I = 7.3V to 25V 550V I = 8V to 12V1.525 T J =+25 °CI O = 5mA to 1.5A 9100 I O = 5mA to 1A 9100 I O = 250 to 750mA450 Quiescent Current I Q T J =+25°C 5.06mA I O = 5mA to 1A0.5 Quiescent Current Change∆I Q V I = 8 V to 25V, I O = 500mA 0.8mAV I = 7.5V to 20V, T J =+25°C0.8Output Voltage Drift -0.8mV/°C Output Noise Voltage V N f = 10Hz to 100KHzT A =+25°C10 Ripple Rejection RR f = 120Hz, I O = 500mA V I = 8V to 18V 68dB Dropout Voltage V D I O = 1A, T J =+25°C 2V Output Resistance R O f = 1KHz17m Ω Short Circuit Current I SC V I = 35V, T A =+25 °C 250mA Peak CurrentI PKT J = +25°C2.2ALoad Regulation ∆V OT J =+25°C∆V/∆T I O = 5mAµV/V O V(Refer to the test circuits. T J = 0 to+150°C, I O = 1A, V I = 11V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.CharacteristicSymbolTest ConditionsMin Typ Max Unit T J =+25°C5.5866.12 Output VoltageV OI O = 5mA to 1A, P D ≤ 15W V I = 8.6 to 21V 5.766 6.24VV I = 8.6 to 25V I O = 500mA 560Line Regulation∆V OV I = 9V to 13V 360mVV I = 8.3V to 21V 560V I = 9V to 13V1.530 T J =+25 °CI O = 5mA to 1.5A 9100 I O = 5mA to 1A 4100 I O = 250 to 750mA 5.050 Quiescent Current I Q T J =+25°C 4.36mA I O = 5mA to 1A0.5 Quiescent Current Change∆I Q V I = 9V to 25V, I O = 500mA 0.8mAV I = 8.5V to 21V, T J =+25°C 0.8Output Voltage Drift I O = 5mA-0.8mV/°C Output Noise Voltage V N f = 10Hz to 100KHzT A =+25°C10µ V/V O Ripple Rejection RR f = 120Hz, I O = 500mA V I = 9V to 19V 65dB Dropout Voltage V D I O = 1A, T J =+25°C 2V Output Resistance R O f = 1KHz17m Ω Short Circuit Current I SC V I = 35V, T A =+25 °C 250mA Peak CurrentI PKT J =+25°C2.2ALoad Regulation ∆V O T J =+25°C∆V/∆T mV(Refer to the test circuits. T J = 0 to+150°C, I O = 1A, V I = 14V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.CharacteristicSymbolTest ConditionsMin Typ Max Unit T J =+25°C7.8488.16 Output VoltageV OI O = 5mA to 1A, P D ≤15W V I = 8.6 to 21V 7.788.3VV I = 10.6 to 25V I O = 500mA 680Line Regulation∆V OV I = 11to 17V 380mVV I = 10.4V to 23V 680V I = 11V to 17V240 T J =+25 °CI O = 5mA to 1.5A 12100 I O = 5mA to 1A 12100 I O = 250 to 750mA550 Quiescent Current I Q T J =+25°C 5.06mA I O = 5mA to 1A0.5 Quiescent Current Change∆I Q V I = 11V to 25V, I O = 500mA 0.8mAV I = 10.6V to 23V, T J =+25°C0.8Output Voltage Drift I O = 5mA-0.8mV /°C Output Noise Voltage V N f = 10Hz to 100KHzT A =+25°C10µV/V O Ripple Rejection RR f = 120Hz, I O = 500mA V I = 11.5V to 21.5V 62dB Dropout Voltage V D I O = 1A, T J =+25°C 2V Output Resistance R O f = 1KHz18m Ω Short Circuit Current I SC V I = 35V, T A =+25°C 250mA Peak CurrentI PKT J =+25°C2.2ALoad Regulation ∆V O T J =+25°C∆V/∆T mV(Refer to the test circuits. T J = 0 to +125°C, I O = 1A, V I = 15V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.CharacteristicSymbolTest ConditionsMin Typ Max Unit T J =+25°C8.829.09.18 Output VoltageV OI O = 5mA to 1A, P D ≤15W V I = 11.2 to 24V 8.659.09.35VV I = 11.7 to 25V I O = 500mA 690Line Regulation∆V OV I = 12.5 to 19V 445mVV I = 11.5V to 24V 690 V I = 12.5V to 19V245 T J =+25 °CI O = 5mA to 1.0A 12100 I O = 5mA to 1.0A 12100 I O = 250 to 750mA 550 Quiescent Current I Q T J =+25°C5.06.0mA V I = 11.7V to 25V, T J =+25°C 0.8 Quiescent Current Change∆I Q V I = 12V to 25V, I O = 500mA 0.8mAI O = 5mA to 1.0A0.5Output Voltage Drift I O = 5mA-1.0mV/°C Output Noise Voltage V N f = 10Hz to 100KHzT A =+25°C10 Ripple Rejection RR f = 120Hz, I O = 500mA V I = 12V to 22V 62dB Dropout Voltage V D I O = 1A, T J =+25°C 2.0V Output Resistance R O f = 1KHz17m Ω Short Circuit Current I SC V I = 35V, T A =+25 °C 250mA Peak CurrentI PKT J =+25°C2.2ALoad Regulation ∆V O T J =+25°C∆V/∆T µV/VOmV(Refer to the test circuits. T J = 0 to+125°C, I O = 1A, V I = 16V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.CharacteristicSymbol Test ConditionsMin Typ Max Unit T J =+25°C9.81010.2 Output VoltageV OI O = 5mA to 1A, P D ≤ 15W V I =12.8 to 25V 9.61010.4VV I = 12.8 to 26V I O = 500mA 8100Line Regulation∆V OV I = 13to 20V 450mVV I = 12.5V to 25V 8100 V I = 13V to 20V350 T J =+25 °CI O = 5mA to 1.5A 12100 I O = 5mA to 1.0A 12100 I O = 250 to 750mA 550 Quiescent Current I Q T J =+25°C5.06.0mA V I = 13V to 26V, T J =+25°C 0.5 Quiescent Current Change∆I Q V I = 12.8V to 25V, I O = 500mA 0.8mA I O = 5mA to 1.0A0.5Output Voltage Drift I O = 5mA-1.0mV°C Output Noise Voltage V N f = 10Hz to 100KHzT A =+25°C10 Ripple Rejection RR f = 120Hz, I O = 500mA V I = 14V to 24V 62dB Dropout Voltage V D I O = 1A, T J =+25°C 2.0V Output Resistance R O f = 1KHz17m Ω Short Circuit Current I SC V I = 35V, T A =+25 °C 250mA Peak CurrentI PKT J =+25°C2.2ALoad Regulation∆V OT J =+25 °C∆V/∆T µV/V O mV(Refer to the test circuits. T J = 0 to +125°C, I O = 1A, V I = 18V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.CharacteristicSymbolTest ConditionsMin Typ Max Unit T J =+25°C10.811.011.2 Output VoltageV OI O = 5mA to 1A, P D ≤15W V I = 13.8 to 26V 10.611.011.4VV I = 12.8 to 26V I O = 500mA 10110Line Regulation∆V OV I = 15 to 21V455mVV I = 13.5V to 26V10110 V I = 15V to 21V355 T J =+25°CI O = 5mA to 1.5A 12100 I O = 5mA to 1.0A 12100 I O = 250 to 750mA 550 Quiescent Current I Q T J =+25°C5.16.0mA V I = 13.8V to 26V, T J =+25°C 0.8 Quiescent Current Change ∆I Q V I = 14V to 27V, I O = 500mA 0.8mA I O = 5mA to 1.0A 0.5Output Voltage Drift ∆V O /∆TI O = 5mA-1.0mV /°C Output Noise Voltage V N f = 10Hz to 100KHzT A =+25°C10 Ripple Rejection RR f = 120Hz, I O = 500mA V I = 14V to 24V 61dB Dropout Voltage V D I O = 1A, T J =+25°C 2.0V Output Resistance R O f = 1KHz18m Ω Short Circuit Current I SC V I = 35V, T A =+25 °C 250mA Peak CurrentI PKT J =+25°C2.2ALoad Regulation∆V O T J =+25°C µV/V O mV(Refer to the test circuits. T J = 0 to +125°C, I O = 1A, V I = 19V, C I = 0.33µF, C O = 0.1µF, unless otherwise specified)* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.CharacteristicSymbolTest ConditionsMin Typ Max Unit T J =+25°C11.751212.25 Output VoltageV OI O = 5mA to 1A, P D ≤15W V I = 14.8 to 27V 11.51212.5VV I = 14.8 to 30V I O = 500mA 10120Line Regulation∆V OV I = 16 to 22V 4120mVV I = 14.5V to 27V 10120 V I = 16V to 22V360 T J =+25°CI O = 5mA to 1.5A 12100 I O = 5mA to 1.0A 12100 I O = 250 to 750mA 550 Quiescent Current I Q T J =+25°C5.16.0mA V I = 15V to 30V, T J =+25°C 0.5 Quiescent Current Change ∆I Q V I = 14V to 27V, I O = 500mA 0.8mA I O = 5mA to 1.0A 0.8Output Voltage Drift ∆V O /∆TI O = 5mA-1.0mV/°C Output Noise Voltage V N f = 10Hz to 100KHzT A =+25°C10 Ripple Rejection RR f = 120Hz, I O = 500mA V I = 14V to 24V 60dB Dropout Voltage V D I O = 1A, T J =+25°C 2.0V Output Resistance R O f = 1KHz18m Ω Short Circuit Current I SC V I = 35V, T A =+25 °C 250mA Peak CurrentI PKT J =+25°C2.2ALoad Regulation ∆V OmVµV/V O T J =+25°C(Refer to the test circuits. T J = 0 to +150°C, I O =1A, V I =23V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)* Load and line regulation are specified at constant, junction temperature. Change in V O due to heating effects must be taken into account separately. Pulse testing with low duty is used.CharacteristicSymbolTest ConditionsMin Typ Max Unit T J =+25°C14.71515.3 Output VoltageV OI O = 5mA to 1A, P D ≤15W V I = 17.7 to 30V 14.41515.6VV I = 17.9 to 30V I O = 500mA 10150Line Regulation∆V OV I = 20 to 26V 5150mVV I = 17.5V to 30V 11150 V I = 20V to 26V375 T J =+25 °CI O = 5mA to 1.5A 12100 I O = 5mA to 1.0A 12100 I O = 250 to 750mA 550 Quiescent Current I Q T J =+25°C5.26.0mA V I = 17.5V to 30V, T J =+25°C 0.5 Quiescent Current Change ∆I Q V I = 17.5V to 30V, I O = 500mA 0.8mA I O = 5mA to 1.0A 0.8Output Voltage Drift ∆V O /∆TI O = 5mA-1.0mV/°C Output Noise Voltage V N f = 10Hz to 100KHzT A =+25°C10 Ripple Rejection RR f = 120Hz, I O = 500mA V I = 18.5V to 28.5V 58dB Dropout Voltage V D I O = 1A, T J =+25°C 2.0V Output Resistance R O f = 1KHz19m Ω Short Circuit Current I SC V I = 35V, T A =+25 °C 250mA Peak CurrentI PKT J =+25°C2.2ALoad Regulation ∆V O T J =+25°CµV/V O mV。

DAC7311中文资料

ABSOLUTE MAXIMUM RATINGS(1)
PARAMETER AVDD to GND Digital input voltage to GND AVOUT to GND Operating temperature range Storage temperature range Junction temperature (TJ max) Power dissipation θJA thermal impedance
PACKAGE/ORDERING INFORMATION(1)
PRODUCT DAC5311 DAC6311 DAC7311
MAXIMUM RELATIVE ACCURACY
(LSB)
±0.25
±0.5
±1
MAXIMUM DIFFERENTIAL NONLINEARITY
(LSB)
±0.25
±0.5
• microPower Operation: 80µA at 1.8V • Power-Down: 0.5µA at 5V, 0.1µA at 1.8V • Wide Power Supply: +1.8V to +5.5V • Power-On Reset to Zero Scale • Straight Binary Data Format • Low Power Serial Interface with
These devices are pin-compatible with the DAC8311 and DAC8411, offering an easy upgrade path from 8-, 10-, and 12-bit resolution to 14- and 16-bit. All devices are available in a small, 6-pin, SC70 package. This package offers a flexible, pin-compatible, and functionally-compatible drop-in solution within the family over an extended temperature range of –40°C to +125°C.

EW-7811UAC DAC安装指南说明书

EW-7811UAC/DACI.产品信息 (1)I-1. 包装内容 (1)I-2. LED指示灯 (1)I-3. 系统需求 (2)I-4. 安规说明 (2)II.安装 (3)III.Windows用户 (5)III-1. 安装驱动程序 (5)III-2. 卸除驱动程序 (8)III-2-1. Windows XP/Vista/7 用户 (8)III-2-2. Windows 8/8.1用户 (8)IV.Mac OS用户 (9)IV-1. 安装驱动程序 (9)IV-2. 卸除驱动程序 (15)V.卸除网络卡 (16)V-1. Windows XP用户 (16)VI-2. Windows Vista 用户 (16)VI-3. Windows 7用户 (17)VI-4. Windows 8/8.1用户 (18)VI-5. Mac用户 (19)VI.使用本产品 (20)VII-1. Windows用户 (20)VII-2. Mac: 联机至无线网络 (21)VII-3. Mac:无线联机工具程序 (23)VII-3-1. 联机状态 (23)VII-3-2. Profiles (23)VII-3-3. 可联机网络 (26)VII-3-4. WPS (27)VII-3-5. 信息 (30)VII-4. WPS设定 (30)M u l t i-L a n g u a g e Q u i c k I n s t a l l a t i o n G u i d e(Q I G)o n t h e C DČešt i n a: Českého průvodce rychlou instalací naleznete napřiloženém CD s ovladačiD e u t s c h:Finden Sie bitte das deutsche S.A.L. beiliegend in der Treiber CDE s p año l: Incluido en el CD el G.R.I. en Español.F r a nça i s: Veui llez trouver l’français G.I.R ci-joint dans le CDI t a l i a n o:Incluso nel CD il Q.I.G. in Italiano.M a g y a r:A magyar telepítési útmutató megtalálható a mellékeltCD-nN e d e r l a n d s: De nederlandse Q.I.G. treft u aan op de bijgesloten CD P o l s k i: Skrócona instruk cja instalacji w języku polskim znajduje się na załączonej płycie CDP o r t u g uês: Incluído no CD o G.I.R. em PortuguesРусский:Найдите Q.I.G. на pусскoмязыке на приложеном CDTür kçe: Ürün ile beraber gelen CD içinde Türkçe Hızlı KurulumKılavuzu'nu bulabilirsinizУкраїнська:Для швидкого налаштування Вашого пристрою, будь ласка, ознайомтесь з інструкцією на CDI.产品信息I-1. 包装内容EW-7811DAC 或EW-7811UAC 安装指南CD光盘USB延长底座I-2. LED指示灯I-3. 系统需求-Windows XP/Vista/7/8/8.1~, Mac OS X 10.7~-USB 2.0接埠-硬盘: 100MB-光驱I-4. 安规说明为确保您及本产品操作使用上的安全，请务必详读及遵照以下说明指示。

写给电子小白：ADC和DAC常用的56个技术术语

写给电子小白：ADC和DAC常用的56个技术术语采集时光
采集时光是从释放保持状态(由采样-保持输入执行)到采样稳定至新输入值的1 LSB范围之内所需要的时光。

采集时光(Tacq)的公式如下：
混叠
按照采样定理，超过奈奎斯特频率的输入信号频率为“混叠”频率。

也就是说，这些频率被“折叠”或复制到奈奎斯特频率附近的其它频谱位置。

为防止混叠，必需对全部有害信号举行足够的衰减，使得不对其举行数字化。

欠采样时，混叠可作为一种有利条件。

孔径延迟
ADC中的孔径延迟(tAD)是从时钟信号的采样沿(下图中为时钟信号的升高沿)到发生采样时之间的时光间隔。

当ADC的跟踪-保持切换到保持状态时，举行采样。

孔径颤动
孔径颤动 (tAJ) 是指采样与采样之间孔径延迟的变幻，所示。

典型的ADC孔径颤动值远远小于孔径延迟值。

二进制编码(单极性)
标准二进制是一种常用于单极性信号的编码办法。

二进制码(零至满幅)的范围为从全0 (00...000)到全1的正向满幅值(11...111)。

中间值由一个1 (MSB)后边跟全0 (10...000)表示。

该编码类似于偏移二进制编码，后者支持正和负双极性传递函数。

双极性输入
术语“双极性”表示信号在某个基准电平上、下摆动。

单端系统中，输入通常以模拟地为基准，所以双极性信号为在地电平上、下摆动的信号。

差分系统中，信号不以地为基准，而是正输入以负输入为参考，
第1页共10页。

DAC7811中文资料

P R O D U C T P R E V I EWFEATURESDESCRIPTIONAPPLICATIONSSYNC SCLK SDINR FB I OUT 1I OUT 2SDODAC7811SBAS337–APRIL 200512-Bit,Serial Input,Multiplying Digital-to-Analog Converter• 2.7V to 5.5V Supply Operation The DAC7811is a CMOS 12-bit current output digital-to-analog converter (DAC).This device •50MHz Serial Interfaceoperates from a 3.0V to 5.5V power supply,making •10MHz Multiplying Bandwidth it suitable to both battery-powered and many other •±10V Reference Input applications.•Low Glitch Energy:2nV-sThis DAC uses a double-buffered 3-wire serial •Extended Temperature Range:interface that is compatible with SPI™,QSPI,–40°C to +125°CMICROWIRE™,and most DSP interface standards.In addition,a serial data out pin (SDO)allows for •10-Lead SON Package daisy-chaining when multiple packages are used.•12-Bit MonotonicData readback allows the user to read the contents of •4-Quadrant Multiplicationthe DAC register via the SDO pin.On power-up,the internal shift register and latches are filled with zeroes •Power-On Reset with Brownout Detection and the DAC outputs are at zero scale.•Daisy-Chain Mode The DAC7811offers excellent 4-quadrant multipli-•Readback Functioncation characteristics,with large signal multiplying •Industry-Standard Pin Configurationbandwidth of 10MHz.The applied external reference input voltage (V REF )determines the full-scale output current.An integrated feedback resistor (R FB )pro-•Portable Battery-Powered Instruments vides temperature tracking and full-scale voltage output when combined with an external cur-•Waveform Generators rent-to-voltage precision amplifier.•Analog Processing•Programmable Amplifiers and Attenuators The DAC7811is available in a 10-lead MSOP pack-age as well as a small 10-lead SON package.•Digitally Controlled Calibration•Programmable Filters and Oscillators •Composite Video •UltrasoundPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI is a trademark of Motorola,Inc.MICROWIRE is a trademark of National Semiconductor.All trademarks are the property of their respective owners.PRODUCT PREVIEW information concerns products in the forma-Copyright ©2005,Texas Instruments Incorporatedtive or design phase of development.Characteristic data and other specifications are design goals.Texas Instruments reserves the right to change or discontinue these products without notice.PRODUCT PREVIEWABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICSDAC7811SBAS337–APRIL 2005This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.ORDERING INFORMATION (1)SPECIFIED PACKAGE PACKAGE ORDERING NUM-TRANSPORT MEDIA,PRODUCT PACKAGE TEMPERATUREDESIGNATORMARKING BER QUANTITY RANGE DAC781110-MSOP DGS –40°C to +125°C 7811DAC7811IDGST 250,Tape and Reel DAC7811IDGSR 2500,Tape and Reel DAC781110-SONDRC–40°C to +125°C7811DAC7811IDRCT 250,Tape and Reel DAC7811IDRCR2500,Tape and Reel(1)For the most current specifications and package information,see the Package Option Addendum located at the end of this data sheet or refer to our web site at .over operating free-air temperature range (unless otherwise noted)(1)DAC7811UNIT V DD to GND–0.3to +7.0V Digital input voltage to GND –0.3to V DD +0.3V V OUT to GND–0.3to V DD +0.3V Operating temperature range –40to +125°C Storage temperature range –65to +150°C Junction temperature (T J max)+150°C ESD Rating,HBM 1500V ESD Rating,CDM 1000V(1)Stresses above those listed under absolute maximum ratings may cause permanent damage to the device.Exposure to absolute maximum conditions for extended periods may affect device reliability.V DD =+2.7V to +5.5V;I OUT1=Virtual GND;I OUT2=0V;V REF =10V;T A =full operating temperature.All specifications –40°C to +125°C,unless otherwise noted.DAC7811PARAMETERCONDITIONSMINTYPMAXUNITSSTATIC PERFORMANCE (1)Resolution 12Bits Relative accuracy DAC7811±1LSB Differential nonlinearity ±1LSB Output leakage current Data =0000h,T A =+25°C ±5nA Output leakage current Data =0000h,T A =T MAX ±25nA Full-scale gain error All ones loaded to DAC register±5±10mV Full-scale tempco ±5ppm/°C Output capacitance Code dependent50pF(1)Linearity calculated by using a reduced code range of 48to 4047;output unloaded.2P R O D U C T P R E V I E WDAC7811SBAS337–APRIL 2005ELECTRICAL CHARACTERISTICS (continued)V DD =+2.7V to +5.5V;I OUT1=Virtual GND;I OUT2=0V;V REF =10V;T A =full operating temperature.All specifications –40°C to +125°C,unless otherwise noted.DAC7811PARAMETERCONDITIONSMINTYPMAXUNITSREFERENCE INPUT V REF range –1515V Input resistance 81012k ΩR FB resistance81012k ΩLOGIC INPUTS AND OUTPUT (2)Input low voltage V IL V DD =+2.7V 0.6V V IL V DD =+5V 0.8V Input high voltage V IH V DD =+2.7V 2.1V V IH V DD =+5V 2.4V Input leakage current I IL 10µA Input capacitance C IL 10pF INTERFACE TIMING Clock input frequencyf CLK50MHzClock pulse width high t CH 8ns Clock pulse width low t CC 8ns SYNC falling edge to SCLK t CSS 13ns active edge setup time SCLK active edge to SYNC t CST 5ns rising edge hold time Data setup time t DS 5ns Data hold time t DH 5nsSYNC high timet SH 30V DD =+2.7V 2535ns SYNC inactive edge to SDO t DDSvalidV DD =+5V2030ns POWER REQUIREMENTS V DD2.75.5V I DD (normal operation)Logic inputs =0V 5µA V DD =+4.5V to +5.5V V IH =V DD and V IL =GND 0.85µA V DD =+2.7V to +3.6V V IH =V DD and V IL =GND0.42.5µAAC CHARACTERISTICS Output voltage settling time 0.2µs Reference multiplying BW V REF =7V PP ,Data =FFFh 10MHz V REF =0V to 10V,DAC glitch impulse2nV-s Data =7FFh to 800h to 7FFh Feedthrough error V OUT /V REF Data =000h,V REF =100kHz–70dB Digital feedthrough 2nV-s Total harmonic distortion –105dB Output spot noise voltage 25nV/√Hz(2)Specified by design and characterization;not production tested.3PRODUCT PREVIEWPIN DESCRIPTIONSMSOP PACKAGEIOUTI OUTR FBV REFV DDSDOSYNC109876IOUT1I OUT2GNDSCLKSDIN12345SON PACKAGE3mm x3mm QFN(TOP VIEW)DAC7811SBAS337–APRIL2005Table1.TERMINAL FUNCTIONSTERMINALDESCRIPTION1I OUT1DAC Current Output2I OUT2DAC Analog Ground.This pin is normally tied to the analog ground of the system.3GND Ground pin.Serial Clock Input.By default,data is clocked into the input shift register on the falling edge of the serial clock input.4SCLK Alternatively,by means of the serial control bits,the device may be configured such that data is clocked into the shift register on the rising edge of SCLK.Serial Data Input.Data is clocked into the16-bit input register on the active edge of the serial clock input.By default, 5SDIN on power-up,data is clocked into the shift register on the falling edge of SCLK.The control bits allow the user to change the active edge to the rising edge.Active Low Control Input.This is the frame synchronization signal for the input data.When SYNC goes low,it powerson the SCLK and DIN buffers,and the input shift register is enabled.Data is loaded to the shift register on the active 6SYNCedge of the following clocks(power-on default is falling clock edge).In stand-alone mode,the serial interface countsthe clocks and data is latched to the shift register on the16th active clock edge.Serial Data Output.This allows a number of parts to be daisy-chained.By default,data is clocked into the shift registeron the falling edge and out via SDO on the rising edge of SCLK.Data will always be clocked out on the alternate edge 7SDOto loading data to the shift register.Writing the Readback control word to the shift register makes the DAC registercontents available for readback on the SDO pin,clocked out on the opposite edges to the active clock edge.8V DD Positive Power Supply Input.These parts can be operated from a supply of2.7V to5.5V.9V REF DAC Reference Voltage Input10R FB DAC Feedback Resistor pin.Establish voltage output for the DAC by connecting to external amplifier output.4P R O D U C T P R E V I E WTYPICAL CHARACTERISTICS:V DD =+5V1.00.80.60.40.20−0.2−0.4−0.6−0.8−1.05121024153620482560307235844096I N L (L S B )Digital Input Code1.00.80.60.40.20−0.2−0.4−0.6−0.8−1.05121024153620482560307235844096D N L (L S B )Digital Input Code1.00.80.60.40.20−0.2−0.4−0.6−0.8−1.05121024153620482560307235844096I N L (L S B )Digital Input Code1.00.80.60.40.20−0.2−0.4−0.6−0.8−1.05121024153620482560307235844096D N L (L S B )Digital Input Code1.00.80.60.40.20−0.2−0.4−0.6−0.8−1.05121024153620482560307235844096I N L (L S B )Digital Input Code1.00.80.60.40.20−0.2−0.4−0.6−0.8−1.05121024153620482560307235844096D N L (L S B )Digital Input CodeDAC7811SBAS337–APRIL 2005At T A =+25°C,+V DD =+5V,unless otherwise noted.LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODEvs DIGITAL INPUT CODEFigure 1.Figure 2.LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODEvs DIGITAL INPUT CODEFigure 3.Figure 4.LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODEvs DIGITAL INPUT CODEFigure 5.Figure 6.5PRODUCT PREVIEW1.61.41.21.00.80.60.40.200.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0SupplyCurrent(mA)Logic Input Voltage(V)6−6−12−18−24−30−36−42−48−54−60−66−72−78−84−90−96−102101001k10k100k1M10M100MAttenuation(dB)Bandwidth(Hz)Time(50ns/div)OutputVoltage(5mV/div)Time(50ns/div)OutputVoltage(5mV/div)Time(20ns/div)OutputVoltage(2mV/div)−0.2−0.4−0.6−0.8−1.0−1.2−1.4−1.6−1.8−2.0−40−20020406080100120GainError(mV)T emperature(_C)DAC7811SBAS337–APRIL2005TYPICAL CHARACTERISTICS:V DD=+5V(continued)At TA=+25°C,+VDD=+5V,unless otherwise noted.SUPPLY CURRENTvs LOGIC INPUT VOLTAGE REFERENCE MULTIPLYING BANDWIDTHFigure7.Figure8.MIDSCALE DAC GLITCH MIDSCALE DAC GLITCHFigure9.Figure10.GAIN ERRORDAC SETTLING TIME vs TEMPERATUREFigure11.Figure12.6P R O D U C T P R E V I E W2.01.81.61.41.21.00.80.60.40.20−40−2020406080100120Q u i e s c e n t C u r r e n t (µA )T emperature (_C)1.61.41.21.00.80.60.40.20−40−2020406080100120O u t p u t L e a k a g e (n A )Temperature (_C)TYPICAL CHARACTERISTICS:V DD =+3V1.00.80.60.40.20−0.2−0.4−0.6−0.8−1.05121024153620482560307235844096I N L (L S B )Digital Input Code1.00.80.60.40.20−0.2−0.4−0.6−0.8−1.05121024153620482560307235844096D N L (L S B )Digital Input CodeDAC7811SBAS337–APRIL 2005TYPICAL CHARACTERISTICS:V DD =+5V (continued)At T A =+25°C,+V DD =+5V,unless otherwise noted.SUPPLY CURRENT OUTPUT LEAKAGE vs TEMPERATUREvs TEMPERATUREFigure 13.Figure 14.At T A =+25°C,+V DD =+3V,unless otherwise noted.LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODEvs DIGITAL INPUT CODEFigure 15.Figure 16.7PRODUCT PREVIEW1.00.80.60.40.2−0.2−0.4−0.6−0.8−1.005121024153620482560307235844096INL(LSB)Digital Input Code1.00.80.60.40.2−0.2−0.4−0.6−0.8−1.005121024153620482560307235844096DNL(LSB)Digital Input Code1.00.80.60.40.2−0.2−0.4−0.6−0.8−1.005121024153620482560307235844096INL(LSB)Digital Input Code1.00.80.60.40.2−0.2−0.4−0.6−0.8−1.005121024153620482560307235844096DNL(LSB)Digital Input CodeTime(50ns/div)OutputVoltage(5mV/div)Time(50ns/div)OutputVoltage(5mV/div)DAC7811SBAS337–APRIL2005TYPICAL CHARACTERISTICS:V DD=+3V(continued)At TA=+25°C,+VDD=+3V,unless otherwise noted.LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE vs DIGITAL INPUT CODEFigure17.Figure18.LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE vs DIGITAL INPUT CODEFigure19.Figure20.MIDSCALE DAC GLITCH MIDSCALE DAC GLITCHFigure21.Figure22.8P R O D U C T P R E V I E W0−0.2−0.4−0.6−0.8−1.0−1.2−1.4−1.6−1.8−2.0−40−2020406080100120G a i n E r r o r (m V )T emperature (_C)1.61.41.21.00.80.60.40.20−40−2020406080100120O u t p u t L e a k a g e (n A )Temperature (_C)Theory of OperationI OUT2I OUT 1V DB0(LSB)DB9DB10DB11(MSB)V OUT +*V REF CODE4096(1)DAC7811SBAS337–APRIL 2005TYPICAL CHARACTERISTICS:V DD =+3V (continued)At T A =+25°C,+V DD =+3V,unless otherwise noted.GAIN ERROR OUTPUT LEAKAGE vs TEMPERATUREvs TEMPERATUREFigure 23.Figure 24.The DAC7811is a single channel current output,12-bit digital-to-analog converter (DAC).The architecture,illustrated in Figure 25,is an R-2R ladder configuration with the three MSBs segmented.Each 2R leg of the ladder is either switched to I OUT1or the I OUT2terminal.The I OUT1terminal of the DAC is held at a virtual GND potential by the use of an external I/V converter op amp.The R-2R ladder is connected to an external reference input V REF that determines the DAC full-scale current.The R-2R ladder presents a code independent load impedance to the external reference of 10k Ω±20%.The external reference voltage can vary in a range of –15V to +15V,thus providing bipolar I OUT current operation.By using an external I/V converter and the DAC7811R FB resistor,output voltage ranges of -V REF to V REF can be generated.Figure 25.Equivalent R-2R DAC CircuitWhen using an external I/V converter and the DAC7811R FB resistor,the DAC output voltage is given by Equation 1:Each DAC code determines the 2R leg switch position to either GND or I OUT .Because the DAC outputimpedance as seen looking into the I OUT1terminal changes versus code,the external I/V converter noise gain will also change.Because of this,the external I/V converter op amp must have a sufficiently low offset voltage such that the amplifier offset is not modulated by the DAC I OUT1terminal impedance change.External op amps with large offset voltages can produce INL errors in the transfer function of the DAC7811due to offset modulation versus DAC code.9PRODUCT PREVIEWOUTVV REFSerial InterfaceInput Shift RegisterDAC7811SBAS337–APRIL2005Theory of Operation(continued)For best linearity performance of the DAC7811,an op amp(OPA277)is recommended(see Figure26).This circuit allows V REF swinging from–10V to+10V.Figure26.Voltage Output ConfigurationTable2.Control Logic Truth Table(1)CLK SYNC SERIAL SHIFT REGISTER DAC REGISTERX H No effect Latched↑+L Shift register data advanced one bit LatchedX↑+In daisy-chain mode the function as determined by In daisy-chain mode the contents may chageC3-C0is executed.as determined by C3-C0.(1)↑+Positive logic transition;X=Do not care.The DAC7811has a three-wire serial interface(SYNC,SCLK,and SDIN),which is compatible with SPI,QSPI, and MICROWIRE interface standards as well as most Digital Signal Processor(DSP)devices.See the Serial Write Operation timing diagram for an example of a typical write sequence.The write sequence begins by bringing the SYNC line low.Data from the DIN line is clocked into the16-bit shift register on the falling edge of SCLK.The serial clock frequency can be as high as50MHz,making the DAC7811compatible with high-speed DSPs.The SDIN and SCLK input buffers are gated off while SYNC is high which minimizes the power dissipation of the digital interface.After SYNC goes low,the digital interface will respond to the SDIN and SCLK input signals and data can now be shifted into the device.If an inactive clock edge occurs after SYNC goes low, but before the first active clock edge,it will be ignored.If the SDO pin is being used then SYNC must remain low until after the inactive clock edge that follows the16th active clock edge.The input shift register is16bits wide,as shown in Figure27.The four MSBs are the control bits C3–C0;these bits determine which function will be executed at the rising edge of SYNC in daisy-chain mode or the16th active clock edge in stand-alone mode.The remaining12bits are the data bits.On a load and update command (C3–C0=0001)these12data bits will be transferred to the DAC register;otherwise,they have no effect.4CONTROL BITS12DATA BITSC3C2C1C0DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0MSB LSB DB15Figure27.Contents of the16-Bit Input Shift Register10P R O D U C T P R E V I E WSYNC InterruptDaisy-ChainSCLKSYNCSDINSDOControl Bits C3to C0DAC7811SBAS337–APRIL 2005In a normal write sequence,the SYNC line is kept low for at least 16falling edges of SCLK and the DAC is updated on the 16th falling edge.However,if SYNC is brought high before the 16th falling edge,this acts as an interrupt to the write sequence.The shift register is reset and the write sequence is seen as invalid.Neither an update of the DAC register contents or a change in the operating mode occurs.The DAC7811powers up in the daisy chain mode which must be used when 2or more devices are connected in tandem.The SCLK and SYNC signals are shared across all devices while the SDO output of the first device connects to the SDIN input of the following device,and so forth.In this configuration 16SCLK cycles for each DAC7811in the chain are required.Please refer to the timing diagram of Figure 28.For n devices in a daisy-chain configuration,16n SCLK cycles are required to shift in the entire input data stream.After 16n active SCLK edges are received following a falling SYNC,the data stream becomes complete,and SYNC can brought high to update n devices simultaneously.When SYNC is brought high,each device will execute the function defined by the four DAC control bits C3-C0in its input shift register.For example,C3-C0must be 0001for each DAC in the chain that is to be updated with new data,and C3-C0must be 0000for each DAC in the chain whose contents are to remain unchanged.A continuous stream containing the exact number of SCLK cycles may be sent first while the SYNC signal is held low,and then raise SYNC at a later time.Nothing happens until the rising edge of SYNC,and then each DAC7811in the chain will execute the function defined by the four DAC control bits C3-C0in its input shift register.Figure 28.DAC7811Timing DiagramControl Bits C3to C0allow control of various functions of the DAC;see Table 3.Default settings of the DAC on powering up are as follows:Data clocked into shift register on falling clock edges;daisy-chain mode is enabled.Device powers on with zero-scale loaded into the DAC register and IOUT lines.The DAC control bits allow the user to adjust certain features as part of an initialization sequence,for example,daisy-chaining may be disabled if not in use,active clock edge may be changed to rising edge,and DAC output may be cleared to either zero or midscale.The user may also initiate a readback of the DAC register contents for verification purposes.11PRODUCT PREVIEWAPPLICATION INFORMATIONStability CircuitOUTV V REFPositive Voltage Output CircuitDAC7811SBAS337–APRIL 2005Table 3.Serial Input Register Data Format,Data Loaded MSB FirstC3C2C1C0FUNCTION IMPLEMENTED0000No operation (power-on default)0001Load and update 0010Initiate readback 0011Reserved 0100Reserved 0101Reserved 0110Reserved 0111Reserved 1000Reserved1001Daisy-chain disable1010Clock data to shift register on rising edge 1011Clear DAC output to 01100Clear DAC output to midscale 1101Reserved 1110Reserved 1111ReservedFor a current-to-voltage design (see Figure 29),the DAC7811current output (I OUT )and the connection with the inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)layout design.For each code change,there is a step function.If the gain bandwidth product (GBP)of the op amp is limited and parasitic capacitance is excessive at the inverting node,then gain peaking is possible.Therefore,for circuit stability,a compensation capacitor C1(4pF to 20pF typ)can be added to the design,as shown in Figure 29.Figure 29.Gain Peaking Prevention Circuit with Compensation CapacitorAs Figure 30illustrates,in order to generate a positive voltage output,a negative reference is input to the DAC7811.This design is suggested instead of using an inverting amp to invert the output as a result of resistor tolerance errors.For a negative reference,V OUT and GND of the reference are level-shifted to a virtual ground and a –2.5V input to the DAC7811with an op amp.12P R O D U C T P R E V I E WOUTBipolar Output SectionV OUT +ǒD0.5 2N*1ǓV REF(2)OUTProgrammable Current Source CircuitI L +(R2)R3)ńR1R3 V REF D(3)DAC7811SBAS337–APRIL 2005APPLICATION INFORMATION (continued)Figure 30.Positive Voltage Output CircuitThe DAC7811,as a 2-quadrant multiplying DAC,can be used to generate a unipolar output.The polarity of the full-scale output I OUT is the inverse of the input reference voltage at V REF .Some applications require full 4-quadrant multiplying capabilities or bipolar output swing.As shown in Figure 31,external op amp U4is added as a summing amp and has a gain of 2X that widens the output span to 5V.A 4-quadrant multiplying circuit is implemented by using a 2.5V offset of the reference voltage to bias U4.According to the circuit transfer equation given in Equation 2,input data (D)from code 0to full-scale produces output voltages of V OUT =–2.5V to V OUT =+2.5V.External resistance mismatching is the significant error in Figure 31.Figure 31.Bipolar Output CircuitA DAC7811can be integrated into the circuit in Figure 32to implement an improved Howland current pump for precise voltage to current conversions.Bidirectional current flow and high voltage compliance are two features of the circuit.With a matched resistor network,the load current of the circuit is shown by Equation 3:13PRODUCT PREVIEW ZO+R1ȀR3(R1)R2)R1(R2Ȁ)R3Ȁ)*R1Ȁ(R2)R3)(4)R2′V REFOUTCross-ReferenceDAC7811SBAS337–APRIL2005APPLICATION INFORMATION(continued)The value of R3in the previous equation can be reduced to increase the output current drive of U3.U3can drive ±20mA in both directions with voltage compliance limited up to15V by the U3voltage supply.Elimination of the circuit compensation capacitor C1in the circuit is not suggested as a result of the change in the output impedance Z O,according to Equation4:As shown in Equation4,with matched resistors,Z O is infinite and the circuit is optimum for use as a current source.However,if unmatched resistors are used,Z O is positive or negative with negative output impedance being a potential cause of oscillation.Therefore,by incorporating C1into the circuit,possible oscillation problems are eliminated.The value of C1can be determined for critical applications;for most applications,however,a value of several pF is suggested.Figure32.Programmable Bidirectional Current Source CircuitThe DAC7811has an industry-standard pinout.Table4provides the cross-reference information.Table4.Cross-ReferenceSPECIFIEDTEMPERATURE PACKAGE PACKAGE CROSS-PRODUCT INL(LSB)DNL(LSB)RANGE DESCRIPTION OPTION REFERENCE PART DAC7811±1±1–40°C to+125°C10-Lead MicroSOIC MSOP-10AD5443YRM14PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)DAC7811IDGSR PREVIEW MSOP DGS 102500TBD Call TI Call TI DAC7811IDGST PREVIEW MSOP DGS 10250TBD Call TI Call TI DAC7811IDRCR PREVIEW SON DRC 103000TBD Call TI Call TI DAC7811IDRCTPREVIEWSONDRC10250TBDCall TICall TI(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS)or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation orwarranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM6-Apr-2005Addendum-Page 1。

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DAC7811IDGSR芯片资料一.特征：·2.7~5.5V的电源供电·50MHz的串行接口·带宽10MHz的乘法·±10V的参考电压输入·低毛刺能源：2nV—S·拓展级温度范围：-40℃~+125℃·10引脚的SON封装·12位单调·四象限乘法·上电复位和掉电检测·菊花链模式·回读功能·工业标准引脚配置二.应用：·便携式供电仪表·波形发生器·模拟处理·可编程放大器和衰减器·数字控制校准·可编程的滤波器和振荡器·合成视频信号·超声波三.芯片描述：DAC7811 CMOS 12位电流输出数字到模拟转换器(DAC)。

这个设备从2.5 V至5.5 V电源,它适用于电池供电的和许多其他的应用。

该DAC使用双缓冲3-wire系列接口SPI™、QSPI，导电带™,大多数DSP接口标准。

此外,当运用复合器件时，一个串行数据输出引脚(SDO)允许菊花链连接。

回读数据允许用户阅读的内容DAC寄存器通过SDO引脚。

上电时,内部移位寄存器和锁存器充满了0规模和DAC输出为零。

DAC7811提供优秀的四象限乘法特性,大信号相乘10 MHz的带宽。

外加外部参考输入电压(Vref)确定满量程的输出电流。

一个集成反馈电阻器(Rfb),提供温度跟踪和满量程电压输出时，结合外部电流-电压高精密放大器。

DAC7811可用在10引脚MSOP封装，也可用小的10引脚SON封装。

四.引脚描述：·1脚：IOUT1是DAC电流输出·2脚：IOUT2是DAC模拟地。

这个引脚通常被接在系统的模拟地·3脚：接地·4脚：串行时钟输入, 默认情况下，当串行时钟的下降沿时，数据被存入16位的输入移位寄存器；作为选择，依靠串行控制位，可以设置当时钟线上升沿时把数据输入进输入移位寄存器。

·5脚：串行数据输入,在有效的串行输入时钟边沿，数据被存入16位的输入移位寄存器。

默认情况下，在上电复位时，数据在时钟下降沿时时存入输入移位寄存器；同时控制位允许用户改变为上升沿有效。

·6脚：SYNC 低电平控制输入，这是数据输入的帧同步信号。

当SYNC变低时，它对SCLK 和DIN器作用，同时使能输入移位寄存器。

在有效的边沿时钟线边沿（默认为下降沿），数据锁存到输入移位寄存器。

单机模式下，这个串行接口计算有效时钟的个数，同时数据在第16个有效时钟时，整个数据被存入输入移位寄存器。

·7脚：SDO 串行数据输出，这一位允许很多个部分被菊花链式连接起来。

默认情况下，数据在时钟下降沿时存入输入寄存器，在上升沿时经由SDO输出。

数据总是被存入输入寄存器（在交替的时钟边沿）。

（通过串行数据）在输入寄存器中写入回读控制字，可以实现在SDO引脚读出DAC 寄存器的内容。

·8脚: VDD：正电压输入端。

可以提供输入2.7V——2.5V的电压。

·9脚: VREF：DAC参考电压输入端·10脚:RFB：DAC反馈电阻引脚。

为DAC建立外部电压输出，通过连接外部放大（输出）器。

五.DAC 工作原理：DAC7811 是一个串行通道的电流输出的，12 位的数模准换器。

有一个 R—2R 的梯形结构，有三个分离的 MSBS。

每一个 2R 引脚被连接到 Iout1 或者 Iout2末端。

这个 R——2R 结构连接一个外部参考输入 VREF，可以用来实现 DAC 的满额电流。

这个 R_2R 结构可以外部连接一个 10K 左右的（反馈）电阻，这个外部参考电压能够在-15V——+15V 变化，所以实现两极性的电流输出。

通过运用外部 I/V 转换和 DAC7811 反馈电阻，输出电压可以实现在 VREF——0 之间的变化。

当运用 I/V 转换和反馈电阻后，这个 DAC 输出电压计算公式为每一个 DAC 代码决定着 2R 引脚是指向 GND 还是 Iout, 因为 DAC 的输出阻抗随着代码而变化，则外部的 I/V 转换噪声增益也会改变。

出于这些因素，外部放大器必须有一个足够低的偏移电压，最终确定这一级的电路如下图所示：（其中允许参考电压 VREF 变化从-10V——+10V）。

控制逻辑真值表：·SCLK （随便）、SYNC 为高时：串行移位寄存器不起作用； DAC 寄存器锁存。

·SCLK（负逻辑过度，下降沿）、SYNC 为低时：shift Register data advanced one bit( 移位寄存器数据提前移 1位)；DAC 寄存器锁存。

·SCLK（随便）、SYNC 为正逻辑上升沿：对于串行移位寄存器，在菊花链式模式中，由 C3_C0 决定的功能开始执行；对于 DAC 寄存器，在菊花链式模式中，它的内容可改变、更新（由 C3_C0决定）。

六：串行接口（Serial Interface）：DAC7811 有一个三线串行接口（SYNC、SCLK、 SDIN），可以连接 SPI、QSPI 和MICROWIRE 标准接口，同大多数数字信号处理设备（DSP）。

查看串行写操作时序图，是一个典型的写序列例子。

这个写序列的开始通过把 SYNC 线变低。

在时钟线下降沿时，数据通过 SDIN 而锁存入 16 位的移位寄存器。

这个时钟频率可以高达 50M 赫兹，可以实现高速数字信号处理。

当 SYNC 变高时，SDIN 和 SCLK 的输入缓存寄存器被关闭。

在 SYNC 再次变低之后，这个数据接口将响应 SDIN 和 SCLK 的输入信号，同时数据能被转移进入设备。

如果在 SYNC 变低之后出现了一个无效的时钟沿（这个时钟沿出现在有效时钟出现之前），这个时钟将被忽略。

如果 SDO 引脚被用到的话，必须保持 SYNC 为低直到第 16 个有效时钟沿之后的无效时钟之后。

七：输入移位寄存器（Input Shift Register）：它是 16 位的寄存器。

这个寄存器的高四位（C3_C0）是控制位，这些位决定在SYNC 的上升沿时选择实现哪一种功能（在菊花链式模式或者说是单机模式中的第 16 个有效时钟沿）；剩下的 12 位是数据位。

当在一个“加载和更新”命令（C3_C0）之后，这 12 位的数据将被转到 DAC 寄存器，否则没有任何响应。

八： SYNC 中断（SYNC Interrupt）：在一个正规写入序列中，SYNC 应保持低至少经过 16 个时钟下降沿，同时数据在第 16 个下降沿时更新。

但是，如果在第 16 个下降沿之前，SYNC 变高了，这对写入序列而言就相当于一个中断，移位寄存器复位，写序列无效； DAC 寄存器的内容不会改变，工作模式也不会改变。

九：菊花链模式（Daisy-Chain）：菊花链模式必须用在两个或者两个以上的串连式模式中。

这种模式中，对所有设备而言，SCLK 与 SYNC 是公用的，但是，对于第一个设备的 SDO 是下一个设备的 SDIN，接下来也一样。

在这种模式结构中， 16SCLK 被用在每一个DAC7811 设备中。

（参阅时序图）即对于 N 个设备的菊花链式结构来说，就需要 16*N 个时钟来转换全部的数据流。

在 SYNC 保持低的情况下，经过 16*N 个有效时钟之后，这个数据流完全转换完，与此同时 SYNC 变换成高来更新 N 个（DAC7811）设备。

当 SYNC 变高时，每个设备将执行输入移位寄存器中 4 位控制位（C3_C0）定义的命令的功能。

例如，如果 C3_C0 对于菊花链式中的每个设备而言都是 0001，那么将会更新新数据；如果是 0000 的话，这个设备的内容将不会改变（不更新）。

当 SYNC 信号保持低的时候，一个连续的包含准确数目时钟信号首先被发送，到最后的时候，升高 SYNC。

直到 SYNC 变成上升的时候，菊花链路中的各个设备将执行输入移位寄存器中高四位代表的控制命令。

时序图如下：十：控制位 C3_C0:C3_C0 控制 DAC 的多种功能，在默认设置情况下：数据在时钟下降沿时被锁入移位寄存器，菊花链式模式是使能的，设备上电复位时，DAC 寄存器的内容是 0，电流输出线（额度）是 0。

这四位控制位允许用户调整某些初始化参数，例如，在不使用菊花链路模式情况下不使能菊花链式功能，改变有效时钟沿为上升沿有效，而且 DAC 输出可以 clear to 0 OR midscale。

用户也可以回读 DAC 寄存器的内容来验证结果。

控制位组合代表的命令：十一.典型电路：*******************************************************1.稳定电路（Stability Circuit）2.正电压输出电路（Positive Voltage Output Circuit）3.双极输出部分电路（Bipolar Output Section）4.可编程的电流源电路（Programmable Current Source Circuit）。