An uplink power control algorithm using traditional iterative model for cognitive radio network

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REF615中文版3.0

615 系列保护测控装置支持多种通信协议，包括 IEC 61850（支持 GOOSE 通信）、IEC 60870-5-103以及 Modbus® 。
2. 标准配置
馈线保护测控装置 REF615 有九种可选择的标准配置。标准配置可通过保护测控装置管理工具 PCM600 中的矩阵或应用配置功能进行更改。此外，PCM600 中的应用配置功能支持创建多层逻辑，可以使用包括定时器和触发器在内的多种不同逻辑元件。应用丰富的逻辑模块组合不同的功能模块，可满足用户不同的应用需求。
ABB
1YZA000042 版本：F/2010.07.02
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Relion® 615 ဣଚ
ઍ၍ԍࢺ֪੦ጎዃREF615 ׂ೗ኸళ
馈线保护测控装置 REF615 产品版本：3.0
目录
1. 概述 .............................................................3 2. 标准配置 ......................................................3 3. 保护功能 ......................................................7 4. 应用 ...........................................................14 5. ABB 配电自动化解决方案 .........................17 6. 控制功能 ....................................................19 7. 测量功能 ....................................................19 8. 故障录波 ....................................................19 9. 事件记录 ....................................................20 10. 故障数据记录 .............................................20 11. 断路器监视 .................................................20 12. 跳合闸回路监视 .........................................20 13. 自检功能 ....................................................20 14. VT 熔丝断线监视 .......................................21 15. 电流回路监视 .............................................21

WCDMA射频指标测试--HSDPA篇

WCDMA射频指标测试--HSDPA篇前言：本文档主要介绍根据3GPP 34.121，使用Agilent 8960进行HSDPA测试的方法及测试步骤。

1.概述 (1)2.HSDPA信道结构 (1)2.1HS-PDSCH 高速物理下行链路共享信道 (1)2.2HS-SCCH 高速共享控制信道 (1)2.3HS-DPCCH 上行链路高速专用物理控制信道 (2)3.测试项目 (2)4.测试设置 (3)4.1常规设置 (3)4.2HSDPA 设置 (3)4.334.121 Preset Call Configurations参数配置 (4)5.HS-DPCCH的最大输出功率 (8)6.HS-DPCCH的频谱发射模版 (10)7.HS-DPCCH的邻道泄漏抑制比（ACLR） (10)8.HS-DPCCH (11)9.HS-DPCCH的矢量幅度误差（EVM） (16)10.Maximum Input Level for HS-PDSCH Reception (16QAM) (18)1.概述HSDPA （High Speed Downlink Packet Access）高速下行分组接入技术,WCDAM R99版本可以提供384kb/s的数据速率，但许多对流量要求较高的数据业务（如视频、流媒体和高速下载等业务）对下行数据速率提出了更高的要求。

3GPP在R5协议中提出了HSDPA，它可以在不改变已经建设的WCDMA 系统网络结构的基础上，大大提高用户下行数据业务速率，理论最大值可达到14.4Mb/s。

2.HSDPA信道结构HSDPA引入了一个新的传输信道，即高速下行链路共享信道（HS-DSCH），以承载用户数据，用户共享下行码资源和功率资源，进行时分和码分复用。

为实现HSDPA的功能特性，在3GPP的物理层规范中引入三个新的物理信道：2.1HS-PDSCH 高速物理下行链路共享信道承载下行链路用户数据，扩频因子采用16。

LTE信令-paging

RRC: MasterInformationBlockMessage type: BCCH_BCHDirection: DownlinkFrame No: 141Subframe No: 4Computer Timestamp:10:55:17.187BCCH-BCH-Messagemessagedl-Bandwidth :n100phich-Configphich-Duration : normalphich-Resource : halfsystemFrameNumber : 0x23spare : 0x0000A4 8C 00 00RRC: SysInfoType1Message type: BCCH_SCHDirection: DownlinkFrame No: 142Subframe No: 7Computer Timestamp:10:55:17.187BCCH-DL-SCH-Messagemessagec1systemInformationBlockType1cellAccessRelatedInfoplmn-IdentityListPLMN-IdentityInfoplmn-IdentitymccMCC-MNC-Digit : 4MCC-MNC-Digit : 6MCC-MNC-Digit : 0mncMCC-MNC-Digit : 0MCC-MNC-Digit : 8cellReservedForOperatorUse : notReservedtrackingAreaCode : 0x0002cellIdentity : 0xB243E010cellBarred : notBarredintraFreqReselection : allowedcsg-Indication : falsecellSelectionInfoq-RxLevMin : -60freqBandIndicator : 38schedulingInfoListSchedulingInfosi-Periodicity : rf16sib-MappingInfoSchedulingInfosi-Periodicity : rf16sib-MappingInfo : sibType3SchedulingInfosi-Periodicity : rf128sib-MappingInfo : sibType4tdd-ConfigsubframeAssignment : sa1specialSubframePatterns : ssp7si-WindowLength : ms20systemInfoValueTag : 2650 51 80 11 00 02 B2 43 E0 182A 51 10 10 82 04 25 EE 80 0000 00 64RRC: PagingMessage type: PCCHDirection: DownlinkFrame No: 752Subframe No: 2Computer Timestamp:10:55:23.343PCCH-Messagemessagec1pagingpagingRecordListPagingRecordue-Identitys-TMSImmec : 0x01m-TMSI : 0xC24006E4cn-Domain : ps40 00 1C 24 00 6E 40 00Service RequestMessage type: EPS MMDirection: UplinkComputer Timestamp:10:55:23.343Frame No: 752Subframe No: 4Service RequestSecurity header type: (12) Security header for the SERVICE REQUEST messageprotocol_discriminator : EPS Mobility Managementkey set identifier: 7Sequence number (short): 0Message authentication code (short): 0x0C7 E0 00 00RRC: RRCConnectionRequestMessage type: CCCH_ULDirection: UplinkFrame No: 753Subframe No: 3Computer Timestamp:10:55:23.343UL-CCCH-Messagemessagec1rrcConnectionRequestcriticalExtensionsrrcConnectionRequest-r8ue-Identitys-TMSImmec : 0x01m-TMSI : 0xC24006E4establishmentCause : mt-Accessspare : 0x0040 1C 24 00 6E 44 00RRC: RRCConnectionSetupMessage type: CCCH_DLDirection: DownlinkFrame No: 759Subframe No: 6Computer Timestamp:10:55:23.343DL-CCCH-Messagemessagec1rrcConnectionSetuprrc-TransactionIdentifier : 2criticalExtensionsc1rrcConnectionSetup-r8radioResourceConfigDedicatedsrb-ToAddModListSRB-ToAddModsrb-Identity : 1rlc-ConfigexplicitValueamul-AM-RLCt-PollRetransmit : ms100pollPDU : pInfinitypollByte : kBinfinitymaxRetxThreshold :t16dl-AM-RLCt-Reordering : ms50t-StatusProhibit : ms0logicalChannelConfig : defaultValuemac-MainConfigexplicitValueul-SCH-ConfigmaxHARQ-Tx : n4periodicBSR-Timer : infinityretxBSR-Timer : sf2560ttiBundling : falsetimeAlignmentTimerDedicated : sf10240physicalConfigDedicatedpdsch-ConfigDedicatedp-a : dB0pucch-ConfigDedicatedackNackRepetition : releasetdd-AckNackFeedbackMode : bundlingpusch-ConfigDedicatedbetaOffset-ACK-Index : 10betaOffset-RI-Index : 3betaOffset-CQI-Index :8uplinkPowerControlDedicatedp0-UE-PUSCH : 0deltaMCS-Enabled : en1accumulationEnabled : truep0-UE-PUCCH : 0pSRS-Offset : 7filterCoefficient : fc4cqi-ReportConfigcqi-ReportModeAperiodic : rm30nomPDSCH-RS-EPRE-Offset : 0cqi-ReportPeriodicsetupcqi-PUCCH-ResourceIndex : 2cqi-pmi-ConfigIndex : 28cqi-FormatIndicatorPeriodic : widebandCQIsimultaneousAckNackAndCQI : falsesoundingRS-UL-ConfigDedicatedsetupsrs-Bandwidth : bw3srs-HoppingBandwidth : hbw3freqDomainPosition :19duration : truesrs-ConfigIndex : 36transmissionComb : 0cyclicShift : cs3schedulingRequestConfigsetupsr-PUCCH-ResourceIndex : 13sr-ConfigIndex : 13dsr-TransMax : n6470 12 98 13 FD 94 04 99 F3 679B 25 1C 23 87 D9 80 10 38 7E70 90 E0 34 36 00 0DRRC: RRCConnectionSetupCompleteMessage type: DCCH_ULDirection: UplinkFrame No: 760Subframe No: 4Computer Timestamp:10:55:23.343UL-DCCH-Messagemessagec1rrcConnectionSetupCompleterrc-TransactionIdentifier : 2criticalExtensionsc1rrcConnectionSetupComplete-r8selectedPLMN-Identity : 1dedicatedInfoNAS : 0xC7E00000Service RequestSecurity header type: (12) Security header for the SERVICE REQUEST messageprotocol_discriminator : EPS Mobility Managementkey set identifier: 7Sequence number (short): 0Message authentication code (short): 0x024 00 09 8F C0 00 00 04RRC: SecurityModeCommandMessage type: DCCH_DLDirection: DownlinkFrame No: 766Subframe No: 6Computer Timestamp:10:55:23.437DL-DCCH-Messagemessagec1securityModeCommandrrc-TransactionIdentifier : 2criticalExtensionsc1securityModeCommand-r8securityConfigSMCsecurityAlgorithmConfigcipheringAlgorithm : eea0integrityProtAlgorithm : spare134 00 70 00 00 00 00 00RRC: SecurityModeCompleteMessage type: DCCH_ULDirection: UplinkFrame No: 766Subframe No: 9Computer Timestamp:10:55:23.437UL-DCCH-Messagemessagec1securityModeCompleterrc-TransactionIdentifier : 2criticalExtensions : securityModeComplete-r82C 00 00RRC: RRCConnectionReconfigurationMessage type: DCCH_DLDirection: DownlinkFrame No: 767Subframe No: 2Computer Timestamp:10:55:23.437DL-DCCH-Messagemessagec1rrcConnectionReconfigurationrrc-TransactionIdentifier : 1criticalExtensionsc1rrcConnectionReconfiguration-r8measConfigmeasObjectToAddModListMeasObjectToAddModmeasObjectId : 1measObjectmeasObjectEUTRAcarrierFreq : 38050allowedMeasBandwidth : mbw100presenceAntennaPort1 : trueneighCellConfig : 0x00offsetFreq : dB0cellsToAddModListCellsToAddModcellIndex : 1physCellId : 25cellIndividualOffset : dB0CellsToAddModcellIndex : 2physCellId : 26cellIndividualOffset : dB0CellsToAddModcellIndex : 3physCellId : 40cellIndividualOffset : dB0CellsToAddModcellIndex : 4physCellId : 64cellIndividualOffset : dB0CellsToAddModcellIndex : 5physCellId : 65cellIndividualOffset : dB0CellsToAddModcellIndex : 6physCellId : 108cellIndividualOffset : dB0 reportConfigToAddModListReportConfigToAddModreportConfigId : 1reportConfigreportConfigEUTRAtriggerTypeeventeventIdeventA3a3-Offset : 4reportOnLeave : falsehysteresis : 0timeToTrigger :ms320triggerQuantity : rsrpreportQuantity : sameAsTriggerQuantitymaxReportCells : 8reportInterval : ms1024reportAmount : infinityReportConfigToAddModreportConfigId : 2reportConfigreportConfigEUTRAtriggerTypeeventeventIdeventA5a5-Threshold1threshold-RSRP :40a5-Threshold2threshold-RSRP :43hysteresis : 0timeToTrigger :ms480triggerQuantity : rsrpreportQuantity : sameAsTriggerQuantitymaxReportCells : 8reportInterval : ms240reportAmount : infinitymeasIdToAddModListMeasIdToAddModmeasId : 1measObjectId : 1reportConfigId : 1MeasIdToAddModmeasId : 2measObjectId : 1reportConfigId : 2quantityConfigquantityConfigEUTRAfilterCoefficientRSRP : fc4filterCoefficientRSRQ : fc4measGapConfig : releases-Measure : 90speedStateParssetupmobilityStateParameterst-Evaluation : s180t-HystNormal : s180n-CellChangeMedium : 8n-CellChangeHigh : 8timeToTrigger-SFsf-Medium : oDot5sf-High : oDot5radioResourceConfigDedicatedsrb-ToAddModListSRB-ToAddModsrb-Identity : 2rlc-ConfigexplicitValueamul-AM-RLCt-PollRetransmit : ms100pollPDU : pInfinitypollByte : kBinfinitymaxRetxThreshold :t16dl-AM-RLCt-Reordering : ms50t-StatusProhibit : ms0logicalChannelConfig : defaultValuedrb-ToAddModListDRB-ToAddModeps-BearerIdentity : 5drb-Identity : 4pdcp-ConfigdiscardTimer : ms1500rlc-AMstatusReportRequired : trueheaderCompression : notUsedrlc-Configamul-AM-RLCt-PollRetransmit : ms250pollPDU : p16pollByte : kB500maxRetxThreshold :t16dl-AM-RLCt-Reordering : ms50t-StatusProhibit : ms50logicalChannelIdentity : 4logicalChannelConfigul-SpecificParameterspriority : 10prioritisedBitRate : infinitybucketSizeDuration : ms100logicalChannelGroup : 2mac-MainConfigexplicitValueul-SCH-ConfigperiodicBSR-Timer : sf10retxBSR-Timer : sf320ttiBundling : falsetimeAlignmentTimerDedicated : sf10240phr-ConfigsetupperiodicPHR-Timer : sf200prohibitPHR-Timer : sf100dl-PathlossChange : dB6physicalConfigDedicatedcqi-ReportConfigcqi-ReportModeAperiodic : rm30nomPDSCH-RS-EPRE-Offset : 0cqi-ReportPeriodicsetupcqi-PUCCH-ResourceIndex : 2cqi-pmi-ConfigIndex : 28cqi-FormatIndicatorPeriodic : widebandCQIsimultaneousAckNackAndCQI : truesoundingRS-UL-ConfigDedicatedsetupsrs-Bandwidth : bw3srs-HoppingBandwidth : hbw3freqDomainPosition :19duration : truesrs-ConfigIndex : 36transmissionComb : 0cyclicShift : cs3antennaInfoexplicitValuetransmissionMode : tm7ue-TransmitAntennaSelection : release22 12 15 E8 00 04 4A 51 58 5006 5E 10 D3 C4 28 78 C8 0F 2105 E5 36 3C 20 05 10 10 74 E108 50 56 09 38 F0 80 00 08 0281 6A DB BA B5 38 27 FB 28 083E A3 6D 0C 53 E5 14 5C B9 8A88 6C 90 0E D9 80 10 38 FE 7090 CC 00RRC: RRCConnectionReconfigurationCompleteMessage type: DCCH_ULDirection: UplinkFrame No: 768Subframe No: 1Computer Timestamp:10:55:23.453UL-DCCH-Messagemessagec1rrcConnectionReconfigurationCompleterrc-TransactionIdentifier : 1criticalExtensions :rrcConnectionReconfigurationComplete-r812 00 00RRC: RRCConnectionReconfigurationMessage type: DCCH_DLDirection: DownlinkFrame No: 772Subframe No: 1Computer Timestamp:10:55:23.546DL-DCCH-Messagemessagec1rrcConnectionReconfigurationrrc-TransactionIdentifier : 1criticalExtensionsc1rrcConnectionReconfiguration-r8radioResourceConfigDedicatedphysicalConfigDedicatedcqi-ReportConfigcqi-ReportModeAperiodic : rm30nomPDSCH-RS-EPRE-Offset : 0cqi-ReportPeriodicsetupcqi-PUCCH-ResourceIndex : 2cqi-pmi-ConfigIndex : 28cqi-FormatIndicatorPeriodic : widebandCQIri-ConfigIndex : 161simultaneousAckNackAndCQI : truesoundingRS-UL-ConfigDedicatedsetupsrs-Bandwidth : bw3srs-HoppingBandwidth : hbw3freqDomainPosition :19duration : truesrs-ConfigIndex : 36transmissionComb : 0cyclicShift : cs3antennaInfoexplicitValuetransmissionMode : tm3codebookSubsetRestrictionn2TxAntenna-tm3 : 0xC0ue-TransmitAntennaSelection : release22 02 01 01 DB 38 02 07 05 0FF3 84 86 A1 80 00RRC: RRCConnectionReconfigurationCompleteMessage type: DCCH_ULDirection: UplinkFrame No: 772Subframe No: 6Computer Timestamp:10:55:23.546UL-DCCH-Messagemessagec1rrcConnectionReconfigurationCompleterrc-TransactionIdentifier : 1criticalExtensions :rrcConnectionReconfigurationComplete-r812 00 00RRC: RRCConnectionReleaseMessage type: DCCH_DLDirection: DownlinkFrame No: 207Subframe No: 8Computer Timestamp:10:55:58.765DL-DCCH-Messagemessagec1rrcConnectionReleaserrc-TransactionIdentifier : 3criticalExtensionsc1rrcConnectionRelease-r8releaseCause : other2E 02 00RRC: MasterInformationBlockMessage type: BCCH_BCHDirection: DownlinkFrame No: 223Subframe No: 4Computer Timestamp:10:55:58.968BCCH-BCH-Messagemessagedl-Bandwidth :n100phich-Configphich-Duration : normalphich-Resource : halfsystemFrameNumber : 0x37spare : 0x0000A4 DC 00 00RRC: SysInfoType1Message type: BCCH_SCHDirection: DownlinkFrame No: 224Subframe No: 7Computer Timestamp:10:55:58.968BCCH-DL-SCH-Messagemessagec1systemInformationBlockType1cellAccessRelatedInfoplmn-IdentityListPLMN-IdentityInfoplmn-IdentitymccMCC-MNC-Digit : 4MCC-MNC-Digit : 6MCC-MNC-Digit : 0mncMCC-MNC-Digit : 0MCC-MNC-Digit : 8cellReservedForOperatorUse : notReservedtrackingAreaCode : 0x0002cellIdentity : 0xB243E010cellBarred : notBarredintraFreqReselection : allowedcsg-Indication : falsecellSelectionInfoq-RxLevMin : -60freqBandIndicator : 38schedulingInfoListSchedulingInfosi-Periodicity : rf16sib-MappingInfoSchedulingInfosi-Periodicity : rf16sib-MappingInfo : sibType3SchedulingInfosi-Periodicity : rf128sib-MappingInfo : sibType4tdd-ConfigsubframeAssignment : sa1specialSubframePatterns : ssp7si-WindowLength : ms20systemInfoValueTag : 2650 51 80 11 00 02 B2 43 E0 182A 51 10 10 82 04 25 EE 80 0000 00 60。

power control

11. System Model
In this section we describe the system model and some relevant results needed for the analysis. We discuss power control for the uplink (from terminal to base) only. For the downlink (from base to terminal) all the results in this paper are valid with appropriate changes in the notation. We consider a cellular radio system with a finite channel set of size N (where a channel could be a frequency or time slot). The number of terminals using the same channel is denoted by M. We assume that the channels are orthogonal i.e. terminals on different channels do not interfere with each other. We denote the transmitter power of the ith terminal communicating with the ith base station by Pi. The gain on the radio link from terminal j to base i is denoted by G i j . All the Gij’s are positive and can take values in the range (0,1]. U , denotes the receiver noise at the ith base. The link quality is measured by the carrier to interference ratio(C1R). The CIR of the ith terminal a t its base is given by

中兴交换机配置

一、系统的启动过程如下。

， Ltd.System Booting..。

.。

CPU: S3C45010 ARM7TDMIBSP version: 1.2/0Creation date: Feb 11 2004， 09：37：01Press any key to stop auto-boot。

..72、出现上述信息后，等待大约7 秒，用户可以在这段时间内按任意键进入boot 状态,修改启动参数.当系统在规定时间未检测到用户输入时，系统便开始自动加载版本，并提示下列信息：auto—booting。

..boot device ： secEndunit number ： 0processor number ： 0host name ： tigerfile name : vxWorksinet on ethernet (e) ： 10.40.92。

106host inet （h) : 10。

40.92.105flags (f） : 0x80Attaching to TFFS.。

done。

Loading version：/kernel.。

.1459932 + 75292 + 6358852Starting at 0x1656e0...Attaching interface lo0。

.。

done（省略)Welcome ！ZTE Corporation。

二、配置开始工作1．打开超级终端，输入连接的名称，如ZXR10，并选择一个图标。

38.300-无线接入网（NG-RAN）概述和总体描述英文原版

38.300-⽆线接⼊⽹（NG-RAN）概述和总体描述英⽂原版3GPP TS38.300V15.5.0(2019-03)Technical Specification3rd Generation Partnership Project;Technical Specification Group Radio Access Network;NR;NR and NG-RAN Overall Description;Stage2(Release15)The present document has been developed within the3rd Generation Partnership Project(3GPP TM)and may be further elaborated for the purposes of3GPP. The present document has not been subject to any approval process by the3GPP Organizational Partners and shall not be implemented.This Specification is provided for future development work within3GPP only.The Organizational Partners accept no liability for any use of this Specification. Specifications and Reports for implementation of the3GPP TM system should be obtained via the3GPP Organizational Partners'Publications Offices.3GPPPostal address3GPP support office address650Route des Lucioles-Sophia AntipolisValbonne-FRANCETel.:+33492944200Fax:+33493654716Internet/doc/2e6bf4e527c52cc58bd63186bceb19e8b8f6ecf2.htmlCopyright NotificationNo part may be reproduced except as authorized by written permission.The copyright and the foregoing restriction extend to reproduction in all media.2019,3GPP Organizational Partners(ARIB,ATIS,CCSA,ETSI,TSDSI,TTA,TTC).All rights reserved.UMTS?is a Trade Mark of ETSI registered for the benefit of its members3GPP?is a Trade Mark of ETSI registered for the benefit of its Members and of the3GPP Organizational Partners LTE?is a Trade Mark of ETSI registered for the benefit of its Members and of the3GPP Organizational Partners GSM?and the GSM logo are registered and owned by the GSM AssociationContentsForeword (7)1Scope (8)2References (8)3Abbreviations and Definitions (9)3.1Abbreviations (9)3.2Definitions (11)4Overall Architecture and Functional Split (11)4.1Overall Architecture (11)4.2Functional Split (12)4.3Network Interfaces (14)4.3.1.1NG User Plane (14)4.3.1.2NG Control Plane (14)4.3.2Xn Interface (15)4.3.2.1Xn User Plane (15)4.3.2.2Xn Control Plane (16)4.4Radio Protocol Architecture (16)4.4.1User Plane (16)4.4.2Control Plane (17)4.5Multi-Radio Dual Connectivity (17)5Physical Layer (17)5.1Waveform,numerology and frame structure (17)5.2Downlink (18)5.2.1Downlink transmission scheme (18)5.2.2Physical-layer processing for physical downlink shared channel (18) 5.2.3Physical downlink control channels (19)5.2.4Synchronization signal and PBCH block (20)5.2.5Physical layer procedures (20)5.2.5.1Link adaptation (20)5.2.5.2Power Control (21)5.2.5.3Cell search (21)5.2.5.4HARQ (21)5.2.5.5Reception of SIB1 (21)5.3Uplink (21)5.3.1Uplink transmission scheme (21)5.3.2Physical-layer processing for physical uplink shared channel (22) 5.3.3Physical uplink control channel (22)5.3.4Random access (23)5.3.5Physical layer procedures (23)5.3.5.1Link adaptation (23)5.3.5.2Uplink Power control (23)5.3.5.3Uplink timing control (23)5.3.5.4HARQ (24)5.4Carrier aggregation (24)5.4.1Carrier aggregation (24)5.4.2Supplementary Uplink (24)5.5Transport Channels (24)6Layer2 (25)6.1Overview (25)6.2MAC Sublayer (27)6.2.1Services and Functions (27)6.2.2Logical Channels (27)6.2.3Mapping to Transport Channels (27)6.3RLC Sublayer (28)6.3.1Transmission Modes (28)6.3.2Services and Functions (28)6.3.3ARQ (28)6.4PDCP Sublayer (29)6.4.1Services and Functions (29)6.5SDAP Sublayer (29)6.6L2Data Flow (29)6.7Carrier Aggregation (30)6.8Dual Connectivity (31)6.9Supplementary Uplink (31)6.10Bandwidth Adaptation (31)7RRC (32)7.1Services and Functions (32)7.3System Information Handling (33)7.3.1Overview (33)7.3.2Scheduling (35)7.3.3SI Modification (35)7.4Access Control (35)7.5UE Capability Retrieval framework (35)7.6Transport of NAS Messages (36)7.7Carrier Aggregation (36)7.8Bandwidth Adaptation (36)7.9UE Assistance Information (36)8NG Identities (36)8.1UE Identities (36)8.2Network Identities (37)9Mobility and State Transitions (37)9.1Overview (37)9.2Intra-NR (38)9.2.1Mobility in RRC_IDLE (38)9.2.1.1Cell Selection (38)9.2.1.2Cell Reselection (39)9.2.1.3State Transitions (39)9.2.2Mobility in RRC_INACTIVE (41)9.2.2.1Overview (41)9.2.2.2Cell Reselection (42)9.2.2.3RAN-Based Notification Area (42)9.2.2.4State Transitions (42)9.2.2.4.1UE triggered transition from RRC_INACTIVE to RRC_CONNECTED (42)9.2.2.4.2Network triggered transition from RRC_INACTIVE to RRC_CONNECTED (44) 9.2.2.5RNA update (45)9.2.3Mobility in RRC_CONNECTED (47)9.2.3.1Overview (47)9.2.3.2Handover (48)9.2.3.2.1C-Plane Handling (48)9.2.3.2.2U-Plane Handling (50)9.2.3.2.3Data Forwarding (52)9.2.3.3Re-establishment procedure (53)9.2.4Measurements (53)9.2.5Paging (56)9.2.6Random Access Procedure (56)9.2.7Radio Link Failure (57)9.2.8Beam failure detection and recovery (58)9.3Inter RAT (58)9.3.1Intra5GC (58)9.3.1.1Cell Reselection (58)9.3.1.2Handover (58)9.3.2From5GC to EPC (59)9.3.2.1Cell Reselection (59)9.3.2.2Handover and redirection (59)9.3.2.3Measurements (59)9.3.2.4Data Forwarding for the Control Plane (59)9.3.2.5Data Forwarding for the User Plane (60)9.3.3From EPC to5GC (60)9.3.3.1Data Forwarding for the Control Plane (60)9.3.3.2Data Forwarding for the User Plane (60)9.4Roaming and Access Restrictions (61)10Scheduling (61)10.1Basic Scheduler Operation (61)10.2Downlink Scheduling (61)10.3Uplink Scheduling (62)10.4Measurements to Support Scheduler Operation (62)10.5Rate Control (63)10.5.1Downlink (63)10.5.2Uplink (63)10.6Activation/Deactivation Mechanism (63)10.7E-UTRA-NR Cell Resource Coordination (64)11UE Power Saving (64)12QoS (65)12.1Overview (65)12.2Explicit Congestion Notification (67)13Security (67)13.1Overview and Principles (67)13.2Security Termination Points (69)13.3State Transitions and Mobility (70)14UE Capabilities (70)15Self-Configuration and Self-Optimisation (70)15.1Definitions (70)15.2Void (70)15.3Self-configuration (70)15.3.1Dynamic configuration of the NG-C interface (70)15.3.1.1Prerequisites (70)15.3.1.2SCTP initialization (71)15.3.1.3Application layer initialization (71)15.3.2Dynamic Configuration of the Xn interface (71)15.3.2.1Prerequisites (71)15.3.2.2SCTP initialization (71)15.3.2.3Application layer initialization (71)15.3.3Automatic Neighbour Cell Relation Function (72)15.3.3.1General (72)15.3.3.2Intra-system Automatic Neighbour Cell Relation Function (72) 15.3.3.3Void (73)15.3.3.4Void (73)15.3.3.5Inter-system Automatic Neighbour Cell Relation Function (73) 15.3.4Xn-C TNL address discovery (74)15.4Support for Energy Saving (75)15.4.1General (75)15.4.2Solution description (75)15.4.3O&M requirements (75)16Verticals Support (76)16.1URLLC (76)16.1.1Overview (76)16.1.2LCP Restrictions (76)16.2IMS Voice (77)16.2.0Support for IMS voice (77)16.2.1Support for MMTEL IMS voice and video enhancements (77) 16.2.1.1RAN-assisted codec adaptation (77)16.2.1.2MMTEL voice quality/coverage enhancements (78)16.3Network Slicing (78)16.3.1General Principles and Requirements (78)16.3.2AMF and NW Slice Selection (80)16.3.2.1CN-RAN interaction and internal RAN aspects (80)16.3.2.2Radio Interface Aspects (80)16.3.3Resource Isolation and Management (80)16.3.4Signalling Aspects (80)16.3.4.1General (80)16.3.4.2AMF and NW Slice Selection (80)16.3.4.3UE Context Handling (81)16.3.4.4PDU Session Setup Handling (81)16.3.4.5Mobility (82)16.4Public Warning System (83)16.5Emergency Services (83)16.5.1Overview (83)16.5.2IMS Emergency call (83)16.5.3eCall over IMS (84)16.5.4Fallback (84)Annex A(informative):QoS Handling in RAN (85)A.1PDU Session Establishment (85)A.2New QoS Flow with RQoS (85)A.3New QoS Flow with Explicit RRC Signalling (86)A.4New QoS Flow with Explicit NAS Signalling (87)A.5Release of QoS Flow with Explicit Signalling (88)A.6UE Initiated UL QoS Flow (88)Annex B(informative):Deployment Scenarios (90)B.1Supplementary Uplink (90)B.2Multiple SSBs in a carrier (90)Annex C(informative):I-RNTI Reference Profiles (92)Annex D(informative):SPID ranges and mapping of SPID values to cell reselection andinter-RAT/inter frequency handover priorities (93)Annex E(informative):Change history (94)ForewordThis Technical Specification has been produced by the3rd Generation Partnership Project(3GPP).The contents of the present document are subject to continuing work within the TSG and may change following formal TSG approval.Should the TSG modify the contents of the present document,it will be re-released by the TSG with an identifying change of release date and an increase in version number as follows:Version x.y.zwhere:x the first digit:1presented to TSG for information;2presented to TSG for approval;3or greater indicates TSG approved document under change control.y the second digit is incremented for all changes of substance,i.e.technical enhancements,corrections, updates,etc.z the third digit is incremented when editorial only changes have been incorporated in the document.1ScopeThe present document provides an overview and overall description of the NG-RAN and focuses on the radio interface protocol architecture of NR connected to5GC(E-UTRA connected to5GC is covered in the36series).Details of the radio interface protocols are specified in companion specifications of the38series.2ReferencesThe following documents contain provisions which,through reference in this text,constitute provisions of the present document.-References are either specific(identified by date of publication,edition number,version number,etc.)or non-specific.-For a specific reference,subsequent revisions do not apply.-For a non-specific reference,the latest version applies.In the case of a reference to a3GPP document(includinga GSM document),a non-specific reference implicitly refers to the latest version of that document in the sameRelease as the present document.[1]3GPP TR21.905:"Vocabulary for3GPP Specifications".[2]3GPP TS36.300:"Evolved Universal Terrestrial Radio Access(E-UTRA)and Evolved UniversalTerrestrial Radio Access Network(E-UTRAN);Overall description;Stage2".[3]3GPP TS23.501:"System Architecture for the5G System;Stage2".[4]3GPP TS38.401:"NG-RAN;Architecture description".[5]3GPP TS33.501:"Security Architecture and Procedures for5G System".[6]3GPP TS38.321:"NR;Medium Access Control(MAC)protocol specification".[7]3GPP TS38.322:"NR;Radio Link Control(RLC)protocol specification".[8]3GPP TS38.323:"NR;Packet Data Convergence Protocol(PDCP)specification".[9]3GPP TS37.324:"NR;Service Data Protocol(SDAP)specification".[10]3GPP TS38.304:"NR;User Equipment(UE)procedures in idle mode".[11]3GPP TS38.306:"NR;User Equipment(UE)radio access capabilities".[12]3GPP TS38.331:"NR;Radio Resource Control(RRC);Protocol specification".[13]3GPP TS38.133:"NR;Requirements for support of radio resource management".[14]3GPP TS22.168:"Earthquake and Tsunami Warning System(ETWS)requirements;Stage1".[15]3GPP TS22.268:"Public Warning System(PWS)Requirements".[16]3GPP TS38.410:"NG-RAN;NG general aspects and principles".[17]3GPP TS38.420:"NG-RAN;Xn general aspects and principles".[18]3GPP TS38.101:"NR;User Equipment(UE)radio transmission and reception".[19]3GPP TS22.261:"Service requirements for next generation new services and markets".[20]3GPP TS38.202:"NR;Physical layer services provided by the physical layer"[21]3GPP TS37.340:"NR;Multi-connectivity;Overall description;Stage-2".[22]3GPP TS23.502:"Procedures for the5G System;Stage2".[23]IETF RFC4960(2007-09):"Stream Control Transmission Protocol".[24]3GPP TS26.114:"Technical Specification Group Services and System Aspects;IP MultimediaSubsystem(IMS);Multimedia Telephony;Media handling and interaction".[25]Void.[26]3GPP TS38.413:"NG-RAN;NG Application Protocol(NGAP)".[27]IETF RFC3168(09/2001):"The Addition of Explicit Congestion Notification(ECN)to IP".[28]3GPP TS24.501:"NR;Non-Access-Stratum(NAS)protocol for5G System(5GS)".[29]3GPP TS36.331:"Evolved Universal Terrestrial Radio Access(E-UTRA);Radio ResourceControl(RRC);Protocol specification".3Abbreviations and Definitions3.1AbbreviationsFor the purposes of the present document,the abbreviations given in TR21.905[1],in TS36.300[2]and the following apply.An abbreviation defined in the present document takes precedence over the definition of the same abbreviation,if any,in TR21.905[1]and TS36.300[2].5GC5G Core Network5QI5G QoS IdentifierA-CSI Aperiodic CSIAKA Authentication and Key AgreementAMBR Aggregate Maximum Bit RateAMC Adaptive Modulation and CodingAMF Access and Mobility Management FunctionARP Allocation and Retention PriorityBA Bandwidth AdaptationBCH Broadcast ChannelBPSK Binary Phase Shift KeyingC-RNTI Cell RNTICBRA Contention Based Random AccessCCE Control Channel ElementCD-SSB Cell Defining SSBCFRA Contention Free Random AccessCMAS Commercial Mobile Alert ServiceCORESET Control Resource SetDFT Discrete Fourier TransformDCI Downlink Control InformationDL-SCH Downlink Shared ChannelDMRS Demodulation Reference SignalDRX Discontinuous ReceptionETWS Earthquake and Tsunami Warning SystemGFBR Guaranteed Flow Bit RateI-RNTI Inactive RNTIINT-RNTI Interruption RNTILDPC Low Density Parity CheckMDBV Maximum Data Burst VolumeMIB Master Information BlockMICO Mobile Initiated Connection OnlyMFBR Maximum Flow Bit RateMMTEL Multimedia telephonyMNO Mobile Network OperatorMU-MIMO Multi User MIMONCGI NR Cell Global IdentifierNCR Neighbour Cell RelationNCRT Neighbour Cell Relation TableNGAP NG Application ProtocolNR NR Radio AccessP-RNTI Paging RNTIPCH Paging ChannelPCI Physical Cell IdentifierPDCCH Physical Downlink Control ChannelPDSCH Physical Downlink Shared ChannelPO Paging OccasionPRACH Physical Random Access ChannelPRB Physical Resource BlockPRG Precoding Resource block GroupPSS Primary Synchronisation SignalPUCCH Physical Uplink Control ChannelPUSCH Physical Uplink Shared ChannelPWS Public Warning SystemQAM Quadrature Amplitude ModulationQFI QoS Flow IDQPSK Quadrature Phase Shift KeyingRA-RNTI Random Access RNTIRACH Random Access ChannelRANAC RAN-based Notification Area CodeREG Resource Element GroupRMSI Remaining Minimum SIRNA RAN-based Notification AreaRNAU RAN-based Notification Area UpdateRNTI Radio Network Temporary IdentifierRQA Reflective QoS AttributeRQoS Reflective Quality of ServiceRS Reference SignalRSRP Reference Signal Received PowerRSRQ Reference Signal Received QualitySD Slice DifferentiatorSDAP Service Data Adaptation ProtocolSFI-RNTI Slot Format Indication RNTISIB System Information BlockSI-RNTI System Information RNTISLA Service Level AgreementSMC Security Mode CommandSMF Session Management FunctionS-NSSAI Single Network Slice Selection Assistance Information SPS Semi-Persistent Scheduling SR Scheduling RequestSRS Sounding Reference SignalSS Synchronization SignalSSB SS/PBCH blockSSS Secondary Synchronisation SignalSST Slice/Service TypeSU-MIMO Single User MIMOSUL Supplementary UplinkTA Timing AdvanceTPC Transmit Power ControlUCI Uplink Control InformationUL-SCH Uplink Shared ChannelUPF User Plane FunctionURLLC Ultra-Reliable and Low Latency CommunicationsXn-C Xn-Control planeXn-U Xn-User planeXnAP Xn Application Protocol3.2DefinitionsFor the purposes of the present document,the terms and definitions given in TR21.905[1],in TS36.300[2]and the following apply.A term defined in the present document takes precedence over the definition of the same term,if any, in TR21.905[1]and TS36.300[2].Cell-Defining SSB:an SSB with an RMSI associated.CORESET#0:the control resource set for at least SIB1scheduling,can be configured either via MIB or via dedicated RRC signalling.gNB:node providing NR user plane and control plane protocol terminations towards the UE,and connected via the NG interface to the5GC.Intra-system Handover:Handover that does not involve a CN change(EPC or5GC).Inter-system Handover:Handover that involves a CN change(EPC or5GC).MSG1:preamble transmission of the random access procedure.MSG3:first scheduled transmission of the random access procedure.ng-eNB:node providing E-UTRA user plane and control plane protocol terminations towards the UE,and connected via the NG interface to the5GC.NG-C:control plane interface between NG-RAN and5GC.NG-U:user plane interface between NG-RAN and5GC.NG-RAN node:either a gNB or an ng-eNB.Numerology:corresponds to one subcarrier spacing in the frequency domain.By scaling a reference subcarrier spacing by an integer N,different numerologies can be defined.Xn:network interface between NG-RAN nodes.4Overall Architecture and Functional Split4.1Overall ArchitectureAn NG-RAN node is either:-a gNB,providing NR user plane and control plane protocol terminations towards the UE;or-an ng-eNB,providing E-UTRA user plane and control plane protocol terminations towards the UE.The gNBs and ng-eNBs are interconnected with each other by means of the Xn interface.The gNBs and ng-eNBs are also connected by means of the NG interfaces to the5GC,more specifically to the AMF(Access and Mobility Management Function)by means of the NG-C interface and to the UPF(User Plane Function)by means of the NG-U interface(see TS23.501[3]).NOTE:The architecture and the F1interface for a functional split are defined in TS38.401[4].The NG-RAN architecture is illustrated in Figure4.1-1below.Figure4.1-1:Overall Architecture4.2Functional SplitThe gNB and ng-eNB host the following functions:-Functions for Radio Resource Management:Radio Bearer Control,Radio Admission Control,Connection Mobility Control,Dynamic allocation of resources to UEs in both uplink anddownlink(scheduling);-IP header compression,encryption and integrity protection of data;-Selection of an AMF at UE attachment when no routing to an AMF can be determined from the information provided by the UE;-Routing of User Plane data towards UPF(s);-Routing of Control Plane information towards AMF;-Connection setup and release;-Scheduling and transmission of paging messages;-Scheduling and transmission of system broadcast information(originated from the AMF or OAM);-Measurement and measurement reporting configuration for mobility and scheduling;-Transport level packet marking in the uplink;-Session Management;-Support of Network Slicing;-QoS Flow management and mapping to data radio bearers;-Support of UEs in RRC_INACTIVE state;-Distribution function for NAS messages;-Radio access network sharing;-Dual Connectivity;-Tight interworking between NR and E-UTRA.The AMF hosts the following main functions(see TS23.501[3]):-NAS signalling termination;-NAS signalling security;-AS Security control;-Inter CN node signalling for mobility between3GPP access networks;-Idle mode UE Reachability(including control and execution of paging retransmission);-Registration Area management;-Support of intra-system and inter-system mobility;-Access Authentication;-Access Authorization including check of roaming rights;-Mobility management control(subscription and policies);-Support of Network Slicing;-SMF selection.The UPF hosts the following main functions(see TS23.501[3]):-Anchor point for Intra-/Inter-RAT mobility(when applicable);-External PDU session point of interconnect to Data Network;-Packet routing&forwarding-Packet inspection and User plane part of Policy rule enforcement;-Traffic usage reporting;-Uplink classifier to support routing traffic flows to a data network;-Branching point to support multi-homed PDU session;-QoS handling for user plane,e.g.packet filtering,gating,UL/DL rate enforcement;-Uplink Traffic verification(SDF to QoS flow mapping);-Downlink packet buffering and downlink data notification triggering.The Session Management function(SMF)hosts the following main functions(see TS23.501[3]): -Session Management;-UE IP address allocation and management;-Selection and control of UP function;-Configures traffic steering at UPF to route traffic to proper destination;-Control part of policy enforcement and QoS;-Downlink Data Notification.This is summarized on the figure below where yellow boxes depict the logical nodes and white boxes depict the main functions.Figure4.2-1:Functional Split between NG-RAN and5GC4.3Network Interfaces4.3.1NG Interface4.3.1.1NG User PlaneThe NG user plane interface(NG-U)is defined between the NG-RAN node and the UPF.The user plane protocol stack of the NG interface is shown on Figure4.3.1.1-1.The transport network layer is built on IP transport and GTP-U is used on top of UDP/IP to carry the user plane PDUs between the NG-RAN node and the UPF.Figure4.3.1.1-1:NG-U Protocol StackNG-U provides non-guaranteed delivery of user plane PDUs between the NG-RAN node and the UPF.Further details of NG-U can be found in TS38.410[16].4.3.1.2NG Control PlaneThe NG control plane interface(NG-C)is defined between the NG-RAN node and the AMF.The control plane protocol stack of the NG interface is shown on Figure4.3.1.2-1.The transport network layer is built on IP transport.For the reliable transport of signalling messages,SCTP is added on top of IP.The application layer signalling protocol is referred to as NGAP(NG Application Protocol).The SCTP layer provides guaranteed delivery of application layer messages.In the transport,IP layer point-to-point transmission is used to deliver the signalling PDUs.Figure4.3.1.2-1:NG-C Protocol StackNG-C provides the following functions:-NG interface management;-UE context management;-UE mobility management;-Transport of NAS messages;-Paging;-PDU Session Management;-Configuration Transfer;-Warning Message Transmission.Further details of NG-C can be found in TS38.410[16].4.3.2Xn Interface4.3.2.1Xn User PlaneThe Xn User plane(Xn-U)interface is defined between two NG-RAN nodes.The user plane protocol stack on the Xn interface is shown in Figure4.3.2.1-1.The transport network layer is built on IP transport and GTP-U is used on top of UDP/IP to carry the user plane PDUs.Figure4.3.2.1-1:Xn-U Protocol StackXn-U provides non-guaranteed delivery of user plane PDUs and supports the following functions: -Data forwarding;-Flow control.Further details of Xn-U can be found in TS38.420[17].4.3.2.2Xn Control PlaneThe Xn control plane interface(Xn-C)is defined between two NG-RAN nodes.The control plane protocol stack of the Xn interface is shown on Figure4.3.2.2-1.The transport network layer is built on SCTP on top of IP.The application layer signalling protocol is referred to as XnAP(Xn Application Protocol).The SCTP layer provides the guaranteed delivery of application layer messages.In the transport IP layer point-to-point transmission is used to deliver the signalling PDUs.Figure4.3.2.2-1:Xn-C Protocol StackThe Xn-C interface supports the following functions:-Xn interface management;-UE mobility management,including context transfer and RAN paging;-Dual connectivity.Further details of Xn-C can be found in TS38.420[17].4.4Radio Protocol Architecture4.4.1User PlaneThe figure below shows the protocol stack for the user plane,where SDAP,PDCP,RLC and MAC sublayers (terminated in gNB on the network side)perform the functions listed in subclause6.Figure4.4.1-1:User Plane Protocol Stack4.4.2Control PlaneThe figure below shows the protocol stack for the control plane,where:-PDCP,RLC and MAC sublayers(terminated in gNB on the network side)perform the functions listed in subclause6;-RRC(terminated in gNB on the network side)performs the functions listed in subclause7;-NAS control protocol(terminated in AMF on the network side)performs the functions listed in TS23.501[3]), for instance:authentication,mobility management,security control…Figure4.4.2-1:Control Plane Protocol Stack4.5Multi-Radio Dual ConnectivityNG-RAN supports Multi-Radio Dual Connectivity(MR-DC)operation whereby a UE in RRC_CONNECTED is configured to utilise radio resources provided by two distinct schedulers,located in two different NG-RAN nodes connected via a non-ideal backhaul,one providing NR access and the other one providing either E-UTRA or NR access. Further details of MR-DC operation can be found in TS37.340[21].5Physical Layer5.1Waveform,numerology and frame structureThe downlink transmission waveform is conventional OFDM using a cyclic prefix.The uplink transmission waveform is conventional OFDM using a cyclic prefix with a transform precoding function performing DFT spreading that can be disabled or enabled.Figure5.1-1:Transmitter block diagram for CP-OFDM with optional DFT-spreadingThe numerology is based on exponentially scalable sub-carrier spacing f=2µ×15kHz withµ={0,1,3,4}for PSS,SSS and PBCH andµ={0,1,2,3}for other channels.Normal CP is supported for all sub-carrier spacings,Extended CP is supported forµ=2.12consecutive sub-carriers form a Physical Resource Block(PRB).Up to275PRBs are supported on a carrier.Table5.1-1:Supported transmission numerologies.µ[kHz]f Cyclic prefix Supported for data Supported for synchµ=2?15015Normal Yes Yes130Normal Yes Yes260Normal,Extended Yes No3120Normal Yes Yes4240Normal No YesThe UE may be configured with one or more bandwidth parts on a given component carrier,of which only one can be active at a time,as described in subclauses7.8and6.10respectively.The active bandwidth part defines the UE's operating bandwidth within the cell's operating bandwidth.For initial access,and until the UE's configuration in a cell is received,initial bandwidth part detected from system information is used.Downlink and uplink transmissions are organized into frames with10ms duration,consisting of ten1ms subframes. Each frame is divided into two equally-sized half-frames of five subframes each.The slot duration is14symbols with Normal CP and12symbols with Extended CP,and scales in time as a function of the used sub-carrier spacing so that there is always an integer number of slots in a subframe. Timing Advance TA is used to adjust the uplink frame timing relative to the downlink frame timing.Figure5.1-2:Uplink-downlink timing relationOperation on both paired and unpaired spectrum is supported.5.2Downlink5.2.1Downlink transmission schemeA closed loop Demodulation Reference Signal(DMRS)based spatial multiplexing is supported for Physical Downlink Shared Channel(PDSCH).Up to8and12orthogonal DL DMRS ports are supported for type1and type2DMRS respectively.Up to8orthogonal DL DMRS ports per UE are supported for SU-MIMO and up to4orthogonal DL DMRS ports per UE are supported for MU-MIMO.The number of SU-MIMO code words is one for1-4layer transmissions and two for5-8layer transmissions.The DMRS and corresponding PDSCH are transmitted using the same precoding matrix and the UE does not need to know the precoding matrix to demodulate the transmission.The transmitter may use different precoder matrix for different parts of the transmission bandwidth,resulting in frequency selective precoding.The UE may also assume that the same precoding matrix is used across a set of Physical Resource Blocks(PRBs)denoted Precoding Resource Block Group(PRG).Transmission durations from2to14symbols in a slot is supported.Aggregation of multiple slots with Transport Block(TB)repetition is supported.5.2.2Physical-layer processing for physical downlink shared channelThe downlink physical-layer processing of transport channels consists of the following steps:-Transport block CRC attachment;-Code block segmentation and code block CRC attachment;-Channel coding:LDPC coding;-Physical-layer hybrid-ARQ processing;-Rate matching;-Scrambling;-Modulation:QPSK,16QAM,64QAM and256QAM;-Layer mapping;-Mapping to assigned resources and antenna ports.The UE may assume that at least one symbol with demodulation reference signal is present on each layer in which PDSCH is transmitted to a UE,and up to3additional DMRS can be configured by higher layers.Phase Tracking RS may be transmitted on additional symbols to aid receiver phase tracking.The DL-SCH physical layer model is described in TS38.202[20].5.2.3Physical downlink control channelsThe Physical Downlink Control Channel(PDCCH)can be used to schedule DL transmissions on PDSCH and UL transmissions on PUSCH,where the Downlink Control Information(DCI)on PDCCH includes: -Downlink assignments containing at least modulation and coding format,resource allocation,and hybrid-ARQ information related to DL-SCH;-Uplink scheduling grants containing at least modulation and coding format,resource allocation,and hybrid-ARQ information related to UL-SCH.In addition to scheduling,PDCCH can be used to for-Activation and deactivation of configured PUSCH transmission with configured grant;-Activation and deactivation of PDSCH semi-persistent transmission;。

CY7C63723-PC中文资料

元器件交易网CY7C63743CY7C63722/23CY7C63743enCoRe™ USBCombination Low-Speed USB & PS/2Peripheral ControllerTABLE OF CONTENTS1.0 FEATURES (5)2.0 FUNCTIONAL OVERVIEW (6)2.1 enCoRe USB - The New USB Standard (6)3.0 LOGIC BLOCK DIAGRAM (7)4.0 PIN CONFIGURATIONS (7)5.0 PIN ASSIGNMENTS (7)6.0 PROGRAMMING MODEL (8)6.1 Program Counter (PC) (8)6.2 8-bit Accumulator (A) (8)6.3 8-bit Index Register (X) (8)6.4 8-bit Program Stack Pointer (PSP) (8)6.5 8-bit Data Stack Pointer (DSP) (9)6.6 Address Modes (9)6.6.1 Data (9)6.6.2 Direct (9)6.6.3 Indexed (9)7.0 INSTRUCTION SET SUMMARY (10)8.0 MEMORY ORGANIZATION (11)8.1 Program Memory Organization (11)8.2 Data Memory Organization (12)8.3 I/O Register Summary (13)9.0 CLOCKING (14)9.1 Internal/External Oscillator Operation (15)9.2 External Oscillator (16)10.0 RESET (16)10.1 Low-voltage Reset (LVR) (16)10.2 Brown Out Reset (BOR) (16)10.3 Watchdog Reset (WDR) (17)11.0 SUSPEND MODE (17)11.1 Clocking Mode on Wake-up from Suspend (18)11.2 Wake-up Timer (18)12.0 GENERAL PURPOSE I/O PORTS (18)12.1 Auxiliary Input Port (21)13.0 USB SERIAL INTERFACE ENGINE (SIE) (22)13.1 USB Enumeration (22)13.2 USB Port Status and Control (22)14.0 USB DEVICE (24)14.1 USB Address Register (24)14.2 USB Control Endpoint (24)14.3 USB Non-control Endpoints (25)14.4 USB Endpoint Counter Registers (26)15.0 USB REGULATOR OUTPUT (27)16.0 PS/2 OPERATION (27)17.0 SERIAL PERIPHERAL INTERFACE (SPI) (28)17.1 Operation as an SPI Master (29)17.2 Master SCK Selection (29)17.3 Operation as an SPI Slave (29)17.4 SPI Status and Control (30)17.5 SPI Interrupt (31)17.6 SPI Modes for GPIO Pins (31)18.0 12-BIT FREE-RUNNING TIMER (31)19.0 TIMER CAPTURE REGISTERS (32)20.0 PROCESSOR STATUS AND CONTROL REGISTER (35)21.0 INTERRUPTS (36)21.1 Interrupt Vectors (37)21.2 Interrupt Latency (37)21.3 Interrupt Sources (37)22.0 USB MODE TABLES (42)23.0 REGISTER SUMMARY (47)24.0 ABSOLUTE MAXIMUM RATINGS (48)25.0 DC CHARACTERISTICS (48)26.0 SWITCHING CHARACTERISTICS (50)27.0 ORDERING INFORMATION (55)28.0 PACKAGE DIAGRAMS (55)LIST OF FIGURESFigure 8-1. Program Memory Space with Interrupt Vector Table (11)Figure 8-2. Data Memory Organization (12)Figure 9-1. Clock Oscillator On-chip Circuit (14)Figure 9-2. Clock Configuration Register (Address 0xF8) (14)Figure 10-1. Watchdog Reset (WDR, Address 0x26) (17)Figure 12-1. Block Diagram of GPIO Port (one pin shown) (19)Figure 12-2. Port 0 Data (Address 0x00) (19)Figure 12-3. Port 1 Data (Address 0x01) (19)Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A) (20)Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B) (20)Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C) (20)Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D) (20)Figure 12-8. Port 2 Data Register (Address 0x02) (21)Figure 13-1. USB Status and Control Register (Address 0x1F) (23)Figure 14-1. USB Device Address Register (Address 0x10) (24)Figure 14-2. Endpoint 0 Mode Register (Address 0x12) (25)Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14 and 0x16) (26)Figure 14-4. Endpoint 0,1,2 Counter Registers (Addresses 0x11, 0x13 and 0x15) (26)Figure 17-1. SPI Block Diagram (28)Figure 16-1. Diagram of USB-PS/2 System Connections (28)Figure 17-2. SPI Data Register (Address 0x60) (29)Figure 17-3. SPI Control Register (Address 0x61) (30)Figure 17-4. SPI Data Timing (31)Figure 18-1. Timer LSB Register (Address 0x24) (31)Figure 18-2. Timer MSB Register (Address 0x25) (32)Figure 18-3. Timer Block Diagram (32)Figure 19-1. Capture Timers Block Diagram (33)Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40) (33)Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41) (34)Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42) (34)Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43) (34)Figure 19-6. Capture Timer Status Register (Address 0x45) (34)Figure 19-7. Capture Timer Configuration Register (Address 0x44) (34)Figure 20-1. Processor Status and Control Register (Address 0xFF) (35)Figure 21-1. Global Interrupt Enable Register (Address 0x20) (38)Figure 21-2. Endpoint Interrupt Enable Register (Address 0x21) (39)Figure 21-3. Interrupt Controller Logic Block Diagram (40)Figure 21-4. Port 0 Interrupt Enable Register (Address 0x04) (40)Figure 21-5. Port 1 Interrupt Enable Register (Address 0x05) (40)Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06) (41)Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07) (41)Figure 21-8. GPIO Interrupt Diagram (41)Figure 26-1. Clock Timing (51)Figure 26-2. USB Data Signal Timing (51)Figure 26-3. Receiver Jitter Tolerance (52)Figure 26-4. Differential to EOP Transition Skew and EOP Width (52)Figure 26-5. Differential Data Jitter (52)Figure 26-7. SPI Slave Timing, CPHA = 0 (53)Figure 26-6. SPI Master Timing, CPHA = 0 (53)Figure 26-8. SPI Master Timing, CPHA = 1 (54)Figure 26-9. SPI Slave Timing, CPHA = 1 (54)LIST OF TABLESTable 8-1. I/O Register Summary (13)Table 11-1. Wake-up Timer Adjust Settings (18)Table 12-1. Ports 0 and 1 Output Control Truth Table (21)Table 13-1. Control Modes to Force D+/D– Outputs (24)Table 17-1. SPI Pin Assignments (31)Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) (35)Table 21-1. Interrupt Vector Assignments (37)Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints (42)Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions” (44)Table 22-3. Details of Modes for Differing Traffic Conditions (45)Table 28-1. CY7C63722-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) (57)1.0 Features•enCoRe™ USB - enhanced Component Reduction—Internal oscillator eliminates the need for an external crystal or resonator—Interface can auto-configure to operate as PS/2 or USB without the need for external components to switch between modes (no GPIO pins needed to manage dual mode capability)—Internal 3.3V regulator for USB pull-up resistor—Configurable GPIO for real-world interface without external components•Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads, joysticks, and many others.•USB Specification Compliance—Conforms to USB Specification, Version 2.0—Conforms to USB HID Specification, Version 1.1—Supports 1 Low-Speed USB device address and 3 data endpoints—Integrated USB transceiver—3.3V regulated output for USB pull-up resistor•8-bit RISC microcontroller—Harvard architecture—6-MHz external ceramic resonator or internal clock mode—12-MHz internal CPU clock—Internal memory—256 bytes of RAM—8 Kbytes of EPROM—Interface can auto-configure to operate as PS/2 or USB—No external components for switching between PS/2 and USB modes—No GPIO pins needed to manage dual mode capability•I/O ports—Up to 16 versatile General Purpose I/O (GPIO) pins, individually configurable—High current drive on any GPIO pin: 50 mA/pin current sink—Each GPIO pin supports high-impedance inputs, internal pull-ups, open drain outputs or traditional CMOS outputs —Maskable interrupts on all I/O pins•SPI serial communication block—Master or slave operation—2 Mbit/s transfers•Four 8-bit Input Capture registers—Two registers each for two input pins—Capture timer setting with 5 prescaler settings—Separate registers for rising and falling edge capture—Simplifies interface to RF inputs for wireless applications•Internal low-power wake-up timer during suspend mode—Periodic wake-up with no external components•Optional 6-MHz internal oscillator mode—Allows fast start-up from suspend mode•Watchdog Reset (WDR)•Low-voltage Reset at 3.75V•Internal brown-out reset for suspend mode•Improved output drivers to reduce EMI•Operating voltage from 4.0V to 5.5VDC•Operating temperature from 0 to 70 degrees Celsius•CY7C63723 available in 18-pin SOIC, 18-pin PDIP•CY7C63743 available in 24-pin SOIC, 24-pin PDIP•CY7C63722 available in DIE form•Industry standard programmer support2.0 Functional Overview2.1enCoRe USB - The New USB StandardCypress has re-invented its leadership position in the low-speed USB market with a new family of innovative microcontrollers. Introducing...enCoRe USB—“enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to create a new family of low-speed USB microcontrollers that enables peripheral developers to design new products with a minimum number of components. At the heart of the enCoRe USB technology is the breakthrough design of a crystal-less oscillator. By integrating the oscillator into our chip, an external crystal or resonator is no longer needed. We have also integrated other external components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a 3.3V regulator. All of this adds up to a lower system cost.The CY7C637xx is an 8-bit RISC One Time Programmable (OTP) microcontroller. The instruction set has been optimized specif-ically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications. The CY7C637xx features up to 16 general purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins are grouped into two ports (Port 0 to 1) where each pin can be individually configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs with programmable drive strength of up to 50 mA output drive. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector. The CY7C637xx microcontrollers feature an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (6 MHz ±1.5%). Optionally, an external 6-MHz ceramic resonator can be used to provide a higher precision reference for USB operation. This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller.The CY7C637xx has 8 Kbytes of EPROM and 256 bytes of data RAM for stack space, user variables, and USB FIFOs.These parts include low-voltage reset logic, a watchdog timer, a vectored interrupt controller, a 12-bit free-running timer, and capture timers. The low-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000. LVR will also reset the part when V CC drops below the operating voltage range. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, two capture timers, an internal wake-up timer and the GPIO ports. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after USB transactions complete on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. The GPIO ports have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be either rising or falling edge.The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 µs and 1.024 ms). The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event, and subtracting the two values. The four capture timers save a programmable 8 bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.0, P0.1).The CY7C637xx includes an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. A 3.3V regulated output pin provides a pull-up source for the external USB resistor on the D– pin.The USB D+ and D– USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and SDATA, the ability to disable the regulator output pin, and an interrupt to signal the start of PS/2 activity. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge rates operate in both modes to reduce EMI.3.0 Logic Block Diagram4.0 Pin Configurations5.0 Pin AssignmentsNameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-Pad D–/SDATA,D+/SCLK I/O 121315161617USB differential data lines (D– and D+), or PS/2 clock and data signals (SDATA and SCLK)P0[7:0]I/O1, 2, 3, 4,15, 16, 17, 181, 2, 3, 4,21, 22, 23, 241, 2, 3, 4,22, 23, 24, 25GPIO Port 0 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current.Can also source 2 mA current, provide a resistive pull-up, or serve as a high-impedance input. P0.0 and P0.1 provide inputs to Capture Timers A and B, respec-tively.P1[7:0]I/O5, 145, 6, 7, 8,17, 18, 19, 205, 6, 7, 8,18, 19, 20, 21IO Port 1 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current. Can alsosource 2 mA current, provide a resistive pull-up, or serve as a high-impedance input.Wake-Up 12-bit Timer USB &D+,D–P1.0–P1.7Interrupt ControllerPort 0P0.0–P0.7GPIO8-bit RISC Xtal RAM 256 Byte EPROM 8K ByteCoreBrown-out Reset XcvrWatch Timer Dog 3.3V Port 1GPIO Capture TimersUSB Engine PS/2Internal Oscillator Oscillator Low ResetVoltage RegulatorTimerSPIXTALOUTXTALIN/P2.1VREG/P2.01234569111516171819202221P0.0P0.1P0.2P0.3P1.0P1.2VSS VREG/P2.0P0.6P1.5P1.1P1.3D+/SCLK P1.7D–/SDATA VCC14P0.710VPPXTALIN/P2.1XTALOUT121378P1.4P1.62423P0.4P0.524-pin SOIC/PDIPCY7C6374312346781011121315161817P0.0P0.1P0.2P0.3VSS VREG/P2.0P0.4P0.6P0.7D+/SCLK D–/SDATA VCC18-pin SOIC/PDIPP0.59VPPXTALIN/P2.1XTALOUTCY7C63723514P1.0P1.1Top View4 5 6 7 8 93 P 0.21 P 0.0 2 P 0.125 P 0.4 24 P 0.523 P 0.622 21 20 19 1811121314151617P0.3P1.0P1.2P1.4P1.6 VSS VSS V P P X T A L I N /P 2.1V R E G X T A L O U T V C C D -/S D A T A D+/SCLK P0.7P1.1P1.3P1.5P1.7CY7C63722-XCDIE106.0 Programming ModelRefer to the CYASM Assembler User’s Guide for more details on firmware operation with the CY7C637xx microcontrollers.6.1Program Counter (PC)The 14-bit program counter (PC) allows access for up to 8 Kbytes of EPROM using the CY7C637xx architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This instruction is typically a jump instruction to a reset handler that initializes the application.The lower 8 bits of the program counter are incremented as instructions are loaded and executed. The upper 6 bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page”of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will cause the assembler to insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution.The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack only during a RETI instruction.Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.6.28-bit Accumulator (A)The accumulator is the general-purpose, do everything register in the architecture where results are usually calculated.6.38-bit Index Register (X)The index register “X” is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform indexed operations by loading an index value into X.6.48-bit Program Stack Pointer (PSP)During a reset, the program stack pointer (PSP) is set to zero. This means the program “stack” starts at RAM address 0x00 and “grows” upward from there. Note that the program stack pointer is directly addressable under firmware control, using the MOV PSP ,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control.During an interrupt acknowledge, interrupts are disabled and the program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented.The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again. The net effect is to store the program counter and flags on the program “stack” and increment the program stack pointer by two.The return from interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory addressed by the PSP . The program stack pointer is decremented again and the first byte is restored from memory addressed by the PSP . After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to restore the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.The call subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.XTALIN/P2.1IN 912136-MHz ceramic resonator or external clock input, or P2.1 inputXTALOUT OUT1013146-MHz ceramic resonator return pin or internal oscillator outputV PP 71011Programming voltage supply, ground for normal operation V CC111415Voltage supplyVREG/P2.0 81112Voltage supply for 1.3-k Ω USB pull-up resistor (3.3V nominal). Also serves as P2.0 input.V SS699, 10Ground5.0 Pin Assignments (continued)NameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-PadThe return from subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decrements the PSP by two.Note that there are restrictions in using the JMP, CALL, and INDEX instructions across the 4-KB boundary of the program memory. Refer to the CYASM Assembler User’s Guide for a detailed description.6.58-bit Data Stack Pointer (DSP)The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction will pre-decrement the DSP, then write data to the memory location addressed by the DSP. A POP instruction will read data from the memory location addressed by the DSP, then post-increment the DSP.During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equals zero will write data at the top of the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB applications, this works fine and is not a problem.For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are shown in Section 8.2. For example, assembly instructions to set the DSP to 20h (giving 32 bytes for program and data stack combined) are shown below:MOV A,20h; Move 20 hex into Accumulator (must be D8h or less to avoid USB FIFOs)SWAP A,DSP; swap accumulator value into DSP register6.6Address ModesThe CY7C637xx microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed.6.6.1DataThe “Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0x30:•MOV A, 30hThis instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the second byte. The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:•DSPINIT: EQU 30h•MOV A,DSPINIT6.6.2Direct“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10h:•MOV A, [10h]In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above:•buttons: EQU 10h•MOV A,[buttons]6.6.3Indexed“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the “base” address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed:•array: EQU 10h•MOV X,3•MOV A,[x+array]This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth element would be at address 0x13h.7.0 Instruction Set SummaryRefer to the CYASM Assembler User’s Guide for detailed information on these instructions. Note that conditional jump instructions (i.e., JC, JNC, JZ, JNZ) take 5 cycles if jump is taken, 4 cycles if no jump.MNEMONIC Operand Opcode Cycles MNEMONIC Operand Opcode Cycles HALT 007NOP 204ADD A,expr data014INC A acc214ADD A,[expr] direct026INC X x224ADD A,[X+expr] index037INC [expr] direct237ADC A,expr data044INC [X+expr] index248ADC A,[expr] direct056DEC A acc254ADC A,[X+expr] index067DEC X x264SUB A,expr data074DEC [expr] direct277SUB A,[expr] direct086DEC [X+expr] index288SUB A,[X+expr] index097IORD expr address295SBB A,expr data0A4IOWR expr address2A5SBB A,[expr] direct0B6POP A2B4SBB A,[X+expr] index0C7POP X2C4OR A,expr data0D4PUSH A2D5OR A,[expr] direct0E6PUSH X2E5OR A,[X+expr] index0F7SWAP A,X2F5AND A,expr data104SWAP A,DSP305AND A,[expr] direct116MOV [expr],A direct315AND A,[X+expr] index127MOV [X+expr],A index326XOR A,expr data134OR [expr],A direct337XOR A,[expr] direct146OR [X+expr],A index348XOR A,[X+expr] index157AND [expr],A direct357CMP A,expr data165AND [X+expr],A index368CMP A,[expr] direct177XOR [expr],A direct377CMP A,[X+expr] index188XOR [X+expr],A index388MOV A,expr data194IOWX [X+expr] index396MOV A,[expr] direct1A5CPL 3A4MOV A,[X+expr] index1B6ASL 3B4MOV X,expr data1C4ASR 3C4MOV X,[expr] direct1D5RLC 3D4reserved 1E RRC 3E4XPAGE 1F4RET 3F8MOV A,X404DI 704MOV X,A414EI 724MOV PSP,A604RETI 738CALL addr50 - 5F10JMP addr80-8F5JC addr C0-CF 5 (or 4) CALL addr90-9F10JNC addr D0-DF 5 (or 4)JZ addr A0-AF 5 (or 4)JACC addr E0-EF7JNZ addr B0-BF 5 (or 4)INDEX addr F0-FF148.0 Memory Organization8.1Program Memory Organization[1]After reset Address14 -bit PC0x0000Program execution begins here after a reset.0x0002USB Bus Reset interrupt vector0x0004128-µs timer interrupt vector0x0006 1.024-ms timer interrupt vector0x0008USB endpoint 0 interrupt vector0x000A USB endpoint 1 interrupt vector0x000C USB endpoint 2 interrupt vector0x000E SPI interrupt vector0x0010Capture timer A interrupt Vector0x0012Capture timer B interrupt vector0x0014GPIO interrupt vector0x0016Wake-up interrupt vector0x0018Program Memory begins here0x1FDF8 KB PROM ends here (8K - 32 bytes). See Note below Figure 8-1. Program Memory Space with Interrupt Vector TableNote:1.The upper 32 bytes of the 8K PROM are reserved. Therefore, the user’s program must not overwrite this space.8.2Data Memory OrganizationThe CY7C637xx microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below:After reset Address8-bit DSP8-bit PSP0x00Program Stack Growth(User’s firmware movesDSP)8-bit DSP User Selected Data Stack GrowthUser Variables0xE8USB FIFO for Address A endpoint 20xF0USB FIFO for Address A endpoint 10xF8USB FIFO for Address A endpoint 0Top of RAM Memory0xFFFigure 8-2. Data Memory Organization8.3I/O Register SummaryI/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.Note:All bits of all registers are cleared to all zeros on reset, except the Processor Status and Control Register (Figure20-1). All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always be written as 0 and be treated as undefined by reads.Table 8-1. I/O Register SummaryRegister Name I/O Address Read/Write Function Fig. Port 0 Data0x00R/W GPIO Port 012-2 Port 1 Data0x01R/W GPIO Port 112-3 Port 2 Data0x02R Auxiliary input register for D+, D–, VREG, XTALIN 12-8 Port 0 Interrupt Enable0x04W Interrupt enable for pins in Port 021-4 Port 1 Interrupt Enable0x05W Interrupt enable for pins in Port 121-5 Port 0 Interrupt Polarity 0x06W Interrupt polarity for pins in Port 021-6 Port 1 Interrupt Polarity 0x07W Interrupt polarity for pins in Port 121-7 Port 0 Mode0 0x0A W Controls output configuration for Port 012-4 Port 0 Mode10x0B W12-5 Port 1 Mode00x0C W Controls output configuration for Port 112-6 Port 1 Mode10x0D W12-7 USB Device Address0x10R/W USB Device Address register14-1 EP0 Counter Register0x11R/W USB Endpoint 0 counter register14-4 EP0 Mode Register0x12R/W USB Endpoint 0 configuration register14-2 EP1 Counter Register0x13R/W USB Endpoint 1 counter register14-4 EP1 Mode Register0x14R/W USB Endpoint 1 configuration register14-3 EP2 Counter Register0x15R/W USB Endpoint 2 counter register14-4 EP2 Mode Register0x16R/W USB Endpoint 2 configuration register14-3 USB Status & Control0x1F R/W USB status and control register13-1 Global Interrupt Enable0x20R/W Global interrupt enable register21-1 Endpoint Interrupt Enable0x21R/W USB endpoint interrupt enables21-2 Timer (LSB)0x24R Lower 8 bits of free-running timer (1 MHz)18-1 Timer (MSB)0x25R Upper 4 bits of free-running timer18-2 WDR Clear0x26W Watchdog Reset clear-Capture Timer A Rising0x40R Rising edge Capture Timer A data register19-2 Capture Timer A Falling0x41R Falling edge Capture Timer A data register19-3 Capture Timer B Rising0x42R Rising edge Capture Timer B data register19-4 Capture Timer B Falling0x43R Falling edge Capture Timer B data register19-5 Capture TImer Configuration0x44R/W Capture Timer configuration register19-7 Capture Timer Status0x45R Capture Timer status register19-6 SPI Data0x60R/W SPI read and write data register17-2 SPI Control0x61R/W SPI status and control register17-3 Clock Configuration0xF8R/W Internal / External Clock configuration register9-2 Processor Status & Control0xFF R/W Processor status and control20-1。

STM32固件库使用手册_v3.5版本

1.3.1 变量 ................................................................................................................................................ 28 1.3.2 布尔型 ............................................................................................................................................ 28 1.3.3 标志位状态类型 ........................................................................................................................... 29 1.3.4 功能状态类型 ............................................................................................................................... 29 1.3.5 错误状态类型 ............................................................................................................................... 29 1.3.6 外设 .............................................................

综测仪测试NBIoT射频指标手册

1文档综述1.1前言本文适用于使用综测仪对NB-iot 进行与模拟小区的连接及射频测试，当前版本。

1.2版本更新信息Signaling中添加DAU链接以及用户自定义调度。

Measurement添加RX测试功能。

可以建立NB-iot小区，并在Measurement中进行TX测试。

2 NB-iot Signaling2.1信令界面NB-iot SignalingNB-iot Signaling小区模拟界面需要License KS300才能打开，打开后界面如下图所示。

（打开方式，仪表面板上的SIGNAL GEN按键，选择NB-iot Signaling1）2.1.1连接状态Connection Status小区指示Cell，小区打开后会亮起数据包开关Packet Switched，小区打开后显示Cell on，终端进行小区搜索的时候显示Signaling in Progress，终端注册成功后显示Attached。

无线资源管理状态RRC state，终端未注册时显示Idle，终端注册成功后显示Connected。

2.1.2日志显示Event Log终端与仪表的信令交互情况，会显示在这个区域，如图中所示。

蓝色信息都是正常的提示，黄色信息为失败消息，红色信息为仪表出现错误。

终端信息UE Info及其他，暂未添加。

2.1.3小区设置Cell频带和双工方式选择，目前只支持FDD，后续版本将会支持TDD信道及频率选择Channel/Frequency，信道和频点有对应关系，设置一个参数的数值会相应变化。

窄带参考符号每资源元素功率NRS EPRE（Narrow Reference Symbol Energy per Resource Element），通过这个参数，可以设置仪表发射给终端的信号强度。

上行功率Uplink nominal power，设置终端上行的目标功率。

2.1.4连接Connection在Configuration中详解。

GSM无线参数详细介绍

无线参数介绍GSM网络中的无线参数是指与无线设备和无线资源有关的参数，这些参数对网络中小区的覆盖、信令流量的分布、网络的业务性能等具有至关重要的影响，因此合理调整无线参数是GSM网络优化的重要组成部分。

本章对网络优化过程中常用的一部分参数（以北电为例）进行简单介绍。

第一节参数体系按参数控制实体可分为：BSC参数、BSM（btsSiteManager）参数、BTS参数、TRX参数、Channel参数、OMC参数、md参数等等。

按参数可变性可分为：动态参数、内部参数、固定参数、静态参数等。

按其实际优化应用可分为：工程参数、优化参数等。

第二节常用无线参数介绍由于无线优化参数对于实际的无线网络优化工作有着及其重要的作用，所以本节所涉及的均为常用无线优化参数。

2.1 BSC参数：hoTraffic（话务切换）描述：本BSC是否允许进行话务原因的切换。

取值：enabled，disabled作用：当hoTrffic设置为enabled时，本BSC内的BTS允许进行话务原因的切换（需将相应BTS的hoTraffic设置为enable）；当hoTraffic设置为disabled时，本BSC内的BTS不允许进行话务原因的切换（无论相应BTS 的hoTrffic是否设置为enabled）。

interBscDerectedRetry（BSC间定向重试）描述：本BSC是否允许与相邻BSC间的定向重试。

取值：enabled，disabled作用：当interBscDerectedRetry设置为enabled时，本BSC内的BTS允许与相邻BSC的BTS进行定向重试（需相应BTS参数配合）；当interBscDerectedRetry设置为disabled时，本BSC内的BTS不允许与相邻BSC的BTS进行定向重试（无论相应BTS参数如何设置）。

intraBscDerectedRetry（BSC内定向重试）描述：本BSC是否允许BSC内的定向重试。

Power Control WCDMA

Serving RNC
Open loop power control of PRACH
NBAP Start RX description 3. Radio Link Setup Response NBAP
NBAP
NBAP
4. ALCAP Iub Data Transport Bearer Setup 5. Downlink Synchronisation 6. Uplink Synchronisation
RRC
Page 7
Open loop power control of DL DPCCH
Application scenarios
UE
Node B Serving RNS
1. CCCH : RRC Connection Request RRC RRC Allocate RNTI Select L1 and L2 parameters 2. Radio Link Setup Request NBAP Start RX description 3. Radio Link Setup Response NBAP NBAP NBAP
Chapter 2 Power Control Algorithm
2.1 Open loop power control 2.2 Inner-loop power control 2.3 Outer loop power control
Page 4
Open Loop Power Control Overview
DCH - FP
Start TX description
DCH - FP
RRC
7. CCCH : RRC Connection Set up

d2d通信中的资源分配算法研究

摘要摘要作为第五代移动通信系统的关键技术之一，设备到设备（Device-to-Device, D2D）技术允许近距离的两个或多个终端设备彼此间不经过基站而进行直接通信。

它能够很好的改善蜂窝通信系统的能量效率和频谱效率，缓解频谱资源的紧缺和电池容量的不足。

但D2D通信给蜂窝网络带来巨大改善的同时，也为其带来了复杂的同频干扰问题。

如何最大限度地降低干扰带来的有害影响，进而提高D2D通信的能量效率，已引起学术界和产业界的广泛关注。

另一方面，当考虑到蜂窝用户设备（Cellular User Equipment, CUE）的物理层安全问题时，这种干扰可以作为一种友好干扰，来混淆窃听者，恶化窃听信道，增强CUE的保密性能。

如何选择合适的干扰源及设置它们的发射功率，来最大化CUE的保密速率是一个值得研究的问题。

围绕上述提出的两个问题，本文进行了如下深入的研究：第一，提出了多个D2D对共用相同无线资源的模型。

该模型能够在满足最小频谱效率的要求下，实现最大化D2D通信系统能量效率的目标。

为此，设计了一个新颖的无线资源管理算法：首先，使用分簇算法完成对D2D用户设备（D2D User Equipment, DUE）的分组来简化干扰模型；然后，利用广义分式规划理论将优化问题由分式形式等价转换为减式形式；最后，通过一个高效的功率控制和子载波分配迭代算法完成对这个减式形式的优化问题的求解。

仿真结果显示，该算法可以显著增加D2D网络的能量效率，并且拥有良好的收敛性能。

第二，将D2D通信引入到CUE保密容量的问题中，通过优化CUE和DUE的资源共享，来提高CUE的安全速率和DUE的传输速率。

为了最大化具有优先级的CUE 的保密速率，提出了一个最佳协作D2D对选择策略。

同时，为保证DUE和CUE在合作中的公平性，进一步提出一个功率控制策略来最大化所选中的D2D链路集合的传输速率。

仿真结果表明，将DUE作为CUE的友好干扰源，不仅可以很好地改善CUE的保密速率，同时也能够极大的提高D2D网络的传输速率。

综测仪测试nb-iot-射频指标手册.doc

1文档综述前言本文适用于使用综测仪对NB-iot进行与模拟小区的连接及射频测试，当前版本。

版本更新信息中添加 DAU链接以及用户自定义调度。

添加 RX测试功能。

可以建立NB-iot小区，并在Measurement 中进行 TX 测试。

2 NB-iot Signaling信令界面 NB-iot SignalingNB-iot Signaling 小区模拟界面需要License KS300 才能打开，打开后界面如下图所示。

NB-iot Signaling1 ）（打开方式，仪表面板上的SIGNAL GEN按键，选择连接状态 Connection Status小区指示Cell ，小区打开后会亮起数据包开关Packet Switched ，小区打开后显示Cell on，终端进行小区搜索的时候显示Signaling in Progress ，终端注册成功后显示Attached 。

无线资源管理状态RRC state ，终端未注册时显示Idle ，终端注册成功后显示Connected 。

日志显示 Event Log终端与仪表的信令交互情况，会显示在这个区域，如图中所示。

蓝色信息都是正常的提示，黄色信息为失败消息，红色信息为仪表出现错误。

终端信息UE Info及其他，暂未添加。

小区设置 Cell频带和双工方式选择，目前只支持FDD，后续版本将会支持TDD信道及频率选择Channel/Frequency，信道和频点有对应关系，设置一个参数的数值会相应变化。

窄带参考符号每资源元素功率NRS EPRE（ Narrow Reference Symbol Energy per Resource Element），通过这个参数，可以设置仪表发射给终端的信号强度。

上行功率Uplink nominal power，设置终端上行的目标功率。

连接 Connection在 Configuration中详解。

配置 Configuration测试场景 Scenario目前仅支持标准小区Standard Cell的建立。

ds-cdm570-L_570-L-IP

G.703 Clock Extension
Cellular networks require precise synchronization of base stations, which is a challenge when using IP backhaul. Most operators are forced to use GPS-based external equipment for site synchronization. CDM-570/L-IP offers a G.703 clock extension option that propagates a high stability reference from hub to the remote. This process does not require additional bandwidth.

Management
The modems support SNMP, web-based and command line interfaces for management. The modems can also be configured and monitored from the front panel, or through the remote M&C port (for non-IP mode of operation). Ten complete RF configurations may be stored in the modem. An event log stores alarm and status information in non-volatile RAM, while the link statistics log stores link performance (Eb/No and AUPC performance) for monitoring and reporting purposes.

Uplink power control optimization for a switched b

专利名称：Uplink power control optimization for aswitched beam wireless transmit/receive unit发明人：Ana Lucia Iacono申请号：US11216817申请日：20050831公开号：US20060270434A1公开日：20061130专利内容由知识产权出版社提供专利附图：摘要：The present invention is a method for adjusting the uplink transmission power of a WTRU utilizing a switched beam antenna. The method measures the received power of a pilot channel beacon in order to estimate the path loss associated with eachdirectional antenna beam. A beam correction function is calculated based on an estimated gain difference between the beam which is currently used for transmission and the beam to which the WTRU will switch. The transmission power of the WTRU is adjusted according to the beam correction function at the time of beam switching. The beam correction function is equivalent to the response of the WTRU's averaging function to the estimated gain difference, offset by the same estimated gain difference.申请人：Ana Lucia Iacono地址：Garden City NY US国籍：US更多信息请下载全文后查看。

Uplink (UL) power control apparatus and method in

专利名称：Uplink (UL) power control apparatus andmethod in broadband wirelesscommunication system发明人：Hwa-Sun You,Ji-Ho Jang,Jae-Ho Jeon,Seung-Joo Maeng申请号：US12816937申请日：20100616公开号：US07899486B2公开日：20110301专利内容由知识产权出版社提供专利附图：摘要：An uplink (UL) power control apparatus and method in a broadband wirelesscommunication system are provided. The Mobile Station (MS) includes a power controller for calculating a power compensation value using a last transmit power in a previous closed loop power control when a power control mode is changed to an open loop power control, and determining a transmit power according to the open loop power control using the power compensation value; and a transmitter for adjusting and transmitting the transmit power of a UL signal under control of the power controller.申请人：Hwa-Sun You,Ji-Ho Jang,Jae-Ho Jeon,Seung-Joo Maeng地址：Suwon-si KR,Yongin-si KR,Seongnam-si KR,Seongnam-si KR国籍：KR,KR,KR,KR代理机构：The Farrell Law Firm, P.C.更多信息请下载全文后查看。

nv 40系电源管理模式bug

nv 40系电源管理模式bug下载温馨提示：该文档是我店铺精心编制而成，希望大家下载以后，能够帮助大家解决实际的问题。

文档下载后可定制随意修改，请根据实际需要进行相应的调整和使用，谢谢!并且，本店铺为大家提供各种各样类型的实用资料，如教育随笔、日记赏析、句子摘抄、古诗大全、经典美文、话题作文、工作总结、词语解析、文案摘录、其他资料等等，如想了解不同资料格式和写法，敬请关注!Download tips: This document is carefully compiled by the editor. I hope that after you download them, they can help you solve practical problems. The document can be customized and modified after downloading, please adjust and use it according to actual needs, thank you!In addition, our shop provides you with various types of practical materials, such as educational essays, diary appreciation, sentence excerpts, ancient poems, classic articles, topic composition, work summary, word parsing, copy excerpts, other materials and so on, want to know different data formats and writing methods, please pay attention!nv40系列电源管理模式bug随着科技的不断发展，电源管理模式在现代计算机系统中扮演着至关重要的角色。

database参数

## Software Release : 1.6.0.0equip 0 SITEbtsno(定义基站站号)LCFLcfid [哪一块LCF控制这个基站（link control function ; GPROC Ⅱ的一种功能）]equip btsno CAB181 （定义第一个机柜）equip btsno CAB119 （定义第二个机柜）1equip btsno CAB219 （定义第三个机柜）1equip btsno CAB3191 （定义第四个机柜）chg_element ber_loss_daily 6 btsnochg_element ber_loss_hourly 4 btsnochg_element remote_loss_daily 20 btsnochg_element remote_loss_hourly 16 btsnochg_element remote_loss_oos 511 btsnochg_element remote_loss_restore 600 btsnochg_element remote_time_oos 10000 btsnochg_element remote_time_restore 600 btsnochg_element slip_loss_daily 24 btsnochg_element slip_loss_hourly 24 btsnochg_element slip_loss_oos 255 btsnochg_element slip_loss_restore 600 btsnochg_element sync_loss_daily 20 btsnochg_element sync_loss_hourly 16 btsnochg_element sync_loss_oos 511 btsnochg_element sync_loss_restore 600 btsnochg_element sync_time_oos 10000 btsnochg_element sync_time_restore 600 btsno（设置传输中断、恢复门限）add_cell 4 6 0 0 0 lac cellid1 btsnofrequency_type = 1 （pgsm频段，即信道代号为1-124）bsic = bsic1bsic由NCC、BCC组成，换算方法BSIC(D) > BSIC(H) > BSIC(B)1、先将十进制BSIC转换成16进制，然后每位按8421码转化成二进制。

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